From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: redhat.com, ip: 209.132.183.28, mailfrom: lersek@redhat.com) Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) by groups.io with SMTP; Mon, 12 Aug 2019 07:07:46 -0700 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 1035A3005628; Mon, 12 Aug 2019 14:07:46 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-116-247.ams2.redhat.com [10.36.116.247]) by smtp.corp.redhat.com (Postfix) with ESMTP id 0C5857CD94; Mon, 12 Aug 2019 14:07:44 +0000 (UTC) Subject: Re: [Patch v2 2/6] UefiCpuPkg/PiSmmCpuDxeSmm: Combine CR read/write action in one function. To: Eric Dong , devel@edk2.groups.io Cc: Ray Ni References: <20190812103152.35164-1-eric.dong@intel.com> <20190812103152.35164-3-eric.dong@intel.com> From: "Laszlo Ersek" Message-ID: <48642653-7404-156b-9f72-a62a88e3fa4f@redhat.com> Date: Mon, 12 Aug 2019 16:07:44 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 MIME-Version: 1.0 In-Reply-To: <20190812103152.35164-3-eric.dong@intel.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.44]); Mon, 12 Aug 2019 14:07:46 +0000 (UTC) Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit On 08/12/19 12:31, Eric Dong wrote: > Signed-off-by: Eric Dong > Cc: Ray Ni > Cc: Laszlo Ersek > --- > UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 106 ++++++++++++++++++------------ > 1 file changed, 63 insertions(+), 43 deletions(-) > > diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c > index d8c6b19ead..b20992d5ab 100644 > --- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c > +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c > @@ -159,6 +159,58 @@ S3WaitForSemaphore ( > ) != Value); > } > > +/** > + Read / write CR value. > + > + @param[in] CrIndex The CR index which need to read/write. > + @param[in] Read Read or write. TRUE is read. > + @param[in,out] CrValue CR value. > + > + @retval EFI_SUCCESS means read/write success, else return EFI_UNSUPPORTED. > +**/ > +UINTN > +ReadWriteCr ( > + IN UINT32 CrIndex, > + IN BOOLEAN Read, > + IN OUT UINTN *CrValue > + ) > +{ > + switch (CrIndex) { > + case 0: > + if (Read) { > + *CrValue = AsmReadCr0 (); > + } else { > + AsmWriteCr0 (*CrValue); > + } > + break; > + case 2: > + if (Read) { > + *CrValue = AsmReadCr2 (); > + } else { > + AsmWriteCr2 (*CrValue); > + } > + break; > + case 3: > + if (Read) { > + *CrValue = AsmReadCr3 (); > + } else { > + AsmWriteCr3 (*CrValue); > + } > + break; > + case 4: > + if (Read) { > + *CrValue = AsmReadCr4 (); > + } else { > + AsmWriteCr4 (*CrValue); > + } > + break; > + default: > + return EFI_UNSUPPORTED;; > + } > + > + return EFI_SUCCESS; > +} > + > /** > Initialize the CPU registers from a register table. > > @@ -188,6 +240,7 @@ ProgramProcessorRegister ( > UINTN ProcessorIndex; > UINTN ValidThreadCount; > UINT32 *ValidCoreCountPerPackage; > + EFI_STATUS Status; > > // > // Traverse Register Table of this logical processor > @@ -206,50 +259,17 @@ ProgramProcessorRegister ( > // The specified register is Control Register > // > case ControlRegister: > - switch (RegisterTableEntry->Index) { > - case 0: > - Value = AsmReadCr0 (); > - Value = (UINTN) BitFieldWrite64 ( > - Value, > - RegisterTableEntry->ValidBitStart, > - RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1, > - (UINTN) RegisterTableEntry->Value > - ); > - AsmWriteCr0 (Value); > - break; > - case 2: > - Value = AsmReadCr2 (); > - Value = (UINTN) BitFieldWrite64 ( > - Value, > - RegisterTableEntry->ValidBitStart, > - RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1, > - (UINTN) RegisterTableEntry->Value > - ); > - AsmWriteCr2 (Value); > - break; > - case 3: > - Value = AsmReadCr3 (); > - Value = (UINTN) BitFieldWrite64 ( > - Value, > - RegisterTableEntry->ValidBitStart, > - RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1, > - (UINTN) RegisterTableEntry->Value > - ); > - AsmWriteCr3 (Value); > - break; > - case 4: > - Value = AsmReadCr4 (); > - Value = (UINTN) BitFieldWrite64 ( > - Value, > - RegisterTableEntry->ValidBitStart, > - RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1, > - (UINTN) RegisterTableEntry->Value > - ); > - AsmWriteCr4 (Value); > - break; > - default: > - break; > + Status = ReadWriteCr (RegisterTableEntry->Index, TRUE, &Value); > + if (EFI_ERROR (Status)) { > + continue; > } > + Value = (UINTN) BitFieldWrite64 ( > + Value, > + RegisterTableEntry->ValidBitStart, > + RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1, > + RegisterTableEntry->Value > + ); > + ReadWriteCr (RegisterTableEntry->Index, FALSE, &Value); > break; > // > // The specified register is Model Specific Register > Using a "break" rather than a "continue" would be more consistent with the current code, and it would have the same effect. But, there's no need to repost just because of that. Reviewed-by: Laszlo Ersek