From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.136; helo=mga12.intel.com; envelope-from=michael.a.kubacki@intel.com; receiver=edk2-devel@lists.01.org Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 25C42211B5A5E for ; Tue, 15 Jan 2019 00:11:50 -0800 (PST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 15 Jan 2019 00:11:49 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,481,1539673200"; d="scan'208";a="114772267" Received: from orsmsx110.amr.corp.intel.com ([10.22.240.8]) by fmsmga007.fm.intel.com with ESMTP; 15 Jan 2019 00:11:49 -0800 Received: from orsmsx121.amr.corp.intel.com ([169.254.10.77]) by ORSMSX110.amr.corp.intel.com ([169.254.10.158]) with mapi id 14.03.0415.000; Tue, 15 Jan 2019 00:11:49 -0800 From: "Kubacki, Michael A" To: "Chiu, Chasel" , "edk2-devel@lists.01.org" CC: "Desimone, Nathaniel L" , "Zeng, Star" Thread-Topic: [PATCH] MinPlatformPkg: Support TCO base locked by FSP Thread-Index: AQHUrIftsldI2E6/R0ucKQj3sJoeb6WvuFtQgAAyD0A= Date: Tue, 15 Jan 2019 08:11:48 +0000 Message-ID: <49AB4ACB9627B8468F29D589A27B74558449A4FA@ORSMSX121.amr.corp.intel.com> References: <20190115040727.2452-1-chasel.chiu@intel.com> <3C3EFB470A303B4AB093197B6777CCEC502302CD@PGSMSX111.gar.corp.intel.com> In-Reply-To: <3C3EFB470A303B4AB093197B6777CCEC502302CD@PGSMSX111.gar.corp.intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiMGI0OGM4YjUtN2ZkNy00M2VjLWI3YTUtMzI1ZGFmYjZhNTBiIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiM1M3bWdDSU9Rb2FoNzc4K1Nra1VUbDBEZnV3enppK21jeTdhZ2hFbUVmbG9waXJCbFg5SkpDMW1yeXAxMWVOKyJ9 x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.400.15 dlp-reaction: no-action x-originating-ip: [10.22.254.138] MIME-Version: 1.0 Subject: Re: [PATCH] MinPlatformPkg: Support TCO base locked by FSP X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 15 Jan 2019 08:11:50 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable According to the function description, PchTcoBaseSet ( ) should ensure the = following steps are done before returning success: 1. set Smbus PCI offset 54h [8] to enable TCO base address. 2. program Smbus PCI offset 50h [15:5] to TCO base address. 3. set Smbus PCI offset 54h [8] to enable TCO base address. 4. program "TCO Base Address" PCR[DMI] + 2778h[15:5, 1] to [Smbus PCI off= set 50h[15:5], 1]. Currently the patch updates PchTcoBaseSet ( ) to return EFI_SUCCESS if it f= inds the TCOCTL lock is already set, however, it doesn't test the other con= ditions are met. This is different from returning EFI_SUCCESS if the lock i= s not already set. The lock could have erroneously been set by HW/SW and th= is would return that the PCH TCO base address was successfully set when it = may not be. What about adding a PchTcoIsLocked () that checks if the lock is set and th= e caller not call PchTcoBaseSet () if PchTcoIsLocked () returns true? Then = PchTcoBaseSet () can continue to return an error if it cannot update the ba= se address.=20 Regards, Michael > -----Original Message----- > From: Chiu, Chasel > Sent: Monday, January 14, 2019 8:15 PM > To: edk2-devel@lists.01.org > Cc: Desimone, Nathaniel L ; Zeng, Star > ; Kubacki, Michael A > Subject: RE: [PATCH] MinPlatformPkg: Support TCO base locked by FSP >=20 >=20 > + Michael to review this too. >=20 > Thanks! > Chasel >=20 >=20 > > -----Original Message----- > > From: Chiu, Chasel > > Sent: Tuesday, January 15, 2019 12:07 PM > > To: edk2-devel@lists.01.org > > Cc: Desimone, Nathaniel L ; Zeng, Star > > ; Chiu, Chasel > > Subject: [PATCH] MinPlatformPkg: Support TCO base locked by FSP > > > > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1457 > > > > Per security recommendation TCO Base should be initialized and locked > > by FSP and MinPlatform should support both TCO Base locked and not lock= ed > scenarios. > > > > Cc: Nate DeSimone > > Cc: Star Zeng > > Contributed-under: TianoCore Contribution Agreement 1.1 > > Signed-off-by: Chasel Chiu > > --- > > > > Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDecoding > > Lib /PchCycleDecodingLib.c | 17 +++++++++-------- > > 1 file changed, 9 insertions(+), 8 deletions(-) > > > > diff --git > > a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDecodi > > ngLi > > b/PchCycleDecodingLib.c > > b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDecodi > > ngL > > ib/PchCycleDecodingLib.c > > index 68b0b5dd4b..e135ef1f3e 100644 > > --- > > a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDecodi > > ngLi > > b/PchCycleDecodingLib.c > > +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDe > > +++ co > > +++ dingLib/PchCycleDecodingLib.c > > @@ -1,7 +1,7 @@ > > /** @file > > PCH cycle deocding configuration and query library. > > > > -Copyright (c) 2017, Intel Corporation. All rights reserved.
> > +Copyright (c) 2017 - 2019, Intel Corporation. All rights > > +reserved.
> > This program and the accompanying materials are licensed and made > > available under the terms and conditions of the BSD License that > > accompanies this distribution. > > The full text of the license may be found at @@ -352,17 +352,18 @@ > > PchTcoBaseSet ( > > } > > // > > // Verify TCO base is not locked. > > + // If it is locked already, skip following steps. > > // > > if ((MmioRead8 (SmbusBase + R_PCH_SMBUS_TCOCTL) & > > B_PCH_SMBUS_TCOCTL_TCO_BASE_LOCK) !=3D 0) { > > - ASSERT (FALSE); > > - return EFI_DEVICE_ERROR; > > + return EFI_SUCCESS; > > } > > // > > // Disable TCO in SMBUS Device first before changing base address. > > + // Byte access to not touch the TCO_BASE_LOCK bit > > // > > - MmioAnd16 ( > > - SmbusBase + R_PCH_SMBUS_TCOCTL, > > - (UINT16) ~B_PCH_SMBUS_TCOCTL_TCO_BASE_EN > > + MmioAnd8 ( > > + SmbusBase + R_PCH_SMBUS_TCOCTL + 1, > > + (UINT8) ~(B_PCH_SMBUS_TCOCTL_TCO_BASE_EN >> 8) > > ); > > // > > // Program TCO in SMBUS Device > > @@ -373,11 +374,11 @@ PchTcoBaseSet ( > > Address > > ); > > // > > - // Enable TCO in SMBUS Device > > + // Enable TCO in SMBUS Device and lock TCO BASE > > // > > MmioOr16 ( > > SmbusBase + R_PCH_SMBUS_TCOCTL, > > - B_PCH_SMBUS_TCOCTL_TCO_BASE_EN > > + B_PCH_SMBUS_TCOCTL_TCO_BASE_EN | > > B_PCH_SMBUS_TCOCTL_TCO_BASE_LOCK > > ); > > // > > // Program "TCO Base Address" PCR[DMI] + 2778h[15:5, 1] to [SMBUS > > PCI offset 50h[15:5], 1]. > > -- > > 2.13.3.windows.1