From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.20; helo=mga02.intel.com; envelope-from=michael.a.kubacki@intel.com; receiver=edk2-devel@lists.01.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9EEF221B02822 for ; Thu, 24 Jan 2019 17:45:06 -0800 (PST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Jan 2019 17:45:06 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,519,1539673200"; d="scan'208";a="121142458" Received: from orsmsx103.amr.corp.intel.com ([10.22.225.130]) by orsmga003.jf.intel.com with ESMTP; 24 Jan 2019 17:45:06 -0800 Received: from orsmsx121.amr.corp.intel.com ([169.254.10.212]) by ORSMSX103.amr.corp.intel.com ([169.254.5.210]) with mapi id 14.03.0415.000; Thu, 24 Jan 2019 17:45:05 -0800 From: "Kubacki, Michael A" To: "Chiu, Chasel" , "edk2-devel@lists.01.org" CC: "Yao, Jiewen" Thread-Topic: [PATCH v2] MinPlatformPkg: Support TCO base locked by FSP Thread-Index: AQHUrjSjS42xGP9E3Umzxkm3PIKQsaW/QqaQ Date: Fri, 25 Jan 2019 01:45:05 +0000 Message-ID: <49AB4ACB9627B8468F29D589A27B7455844AD6D3@ORSMSX121.amr.corp.intel.com> References: <20190117071608.6604-1-chasel.chiu@intel.com> In-Reply-To: <20190117071608.6604-1-chasel.chiu@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiNGQyOTcyNTktMWZkZi00ZDI2LThkYWYtYTJhZTVjNDAyN2U0IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiXC9nTzF0Q1RmRUlNYnlRV1NzaU9aM1V2aGYxYWtLVmpVTkt4dHU1ekF2WlJFV0J0WWx5cmdcL2JvbG1SbW1LVndhIn0= x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.400.15 dlp-reaction: no-action x-originating-ip: [10.22.254.139] MIME-Version: 1.0 Subject: Re: [PATCH v2] MinPlatformPkg: Support TCO base locked by FSP X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 25 Jan 2019 01:45:06 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Michael Kubacki =20 > -----Original Message----- > From: Chiu, Chasel > Sent: Wednesday, January 16, 2019 11:16 PM > To: edk2-devel@lists.01.org > Cc: Kubacki, Michael A ; Yao, Jiewen > ; Chiu, Chasel > Subject: [PATCH v2] MinPlatformPkg: Support TCO base locked by FSP >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1457 >=20 > Per security recommendation TCO Base should be initialized and locked by > FSP and MinPlatform should support both TCO Base locked and not locked > scenarios. >=20 > Cc: Michael A Kubacki > Cc: Jiewen Yao > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Chasel Chiu > --- > Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/SiliconInitPreMe= m.c > | 8 +++++--- >=20 > Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDecodingLi > b/PchCycleDecodingLib.c | 48 > ++++++++++++++++++++++++++++++++++++++++-------- > Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchCycleDecodingLib= .h > | 18 +++++++++++++++++- > 3 files changed, 62 insertions(+), 12 deletions(-) >=20 > diff --git > a/Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/SiliconInitPreM= em.c > b/Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/SiliconInitPreM= em.c > index 616584ffe7..bb21872e1e 100644 > --- > a/Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/SiliconInitPreM= em.c > +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/SiliconIni > +++ tPreMem.c > @@ -1,7 +1,7 @@ > /** @file > Source code file for Platform Init Pre-Memory PEI module >=20 > -Copyright (c) 2017, Intel Corporation. All rights reserved.
> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
> This program and the accompanying materials are licensed and made > available under the terms and conditions of the BSD License that > accompanies this distribution. > The full text of the license may be found at @@ -80,9 +80,11 @@ > EarlySiliconInit ( > PchPwrmBaseSet (PCH_PWRM_BASE_ADDRESS); >=20 > /// > - /// Program TCO BASE > + /// Program TCO BASE if it is present and not locked > /// > - PchTcoBaseSet (PcdGet16 (PcdTcoBaseAddress)); > + if (PchIsTcoBaseSetValid ()) { > + PchTcoBaseSet (PcdGet16 (PcdTcoBaseAddress)); } >=20 > /// > /// LPC I/O Configuration > diff --git > a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDecodin > gLib/PchCycleDecodingLib.c > b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDecodin > gLib/PchCycleDecodingLib.c > index 68b0b5dd4b..d7e91f947b 100644 > --- > a/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDecodin > gLib/PchCycleDecodingLib.c > +++ > b/Silicon/Intel/KabylakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDeco > +++ dingLib/PchCycleDecodingLib.c > @@ -1,7 +1,7 @@ > /** @file > PCH cycle deocding configuration and query library. >=20 > -Copyright (c) 2017, Intel Corporation. All rights reserved.
> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
> This program and the accompanying materials are licensed and made > available under the terms and conditions of the BSD License that > accompanies this distribution. > The full text of the license may be found at @@ -306,6 +306,36 @@ > PchPwrmBaseGet ( } >=20 > /** > + Check if TCO Base register is present and unlocked. > + This should be called before calling PchTcoBaseSet () > + > + @retval BOOLEAN FALSE =3D Either TCO base is loc= ked or Smbus > not present > + TRUE =3D TCO base is not locked > + > +**/ > +BOOLEAN > +EFIAPI > +PchIsTcoBaseSetValid ( > + VOID > + ) > +{ > + UINTN SmbusBase; > + > + SmbusBase =3D MmPciBase ( > + DEFAULT_PCI_BUS_NUMBER_PCH, > + PCI_DEVICE_NUMBER_PCH_SMBUS, > + PCI_FUNCTION_NUMBER_PCH_SMBUS > + ); > + if (MmioRead16 (SmbusBase) =3D=3D 0xFFFF) { > + return FALSE; > + } > + // > + // Verify TCO base is not locked. > + // > + return ((MmioRead8 (SmbusBase + R_PCH_SMBUS_TCOCTL) & > +B_PCH_SMBUS_TCOCTL_TCO_BASE_LOCK) =3D=3D 0); } > + > +/** > Set PCH TCO base address. > This cycle decoding is allowed to set when DMIC.SRL is 0. > Programming steps: > @@ -318,7 +348,8 @@ PchPwrmBaseGet ( >=20 > @retval EFI_SUCCESS Successfully completed. > @retval EFI_INVALID_PARAMETER Invalid base address passed. > - @retval EFI_UNSUPPORTED DMIC.SRL is set. > + @retval EFI_UNSUPPORTED DMIC.SRL is set, or Smbus device= not > present > + @retval EFI_DEVICE_ERROR TCO Base register is locked alre= ady > **/ > EFI_STATUS > EFIAPI > @@ -353,16 +384,17 @@ PchTcoBaseSet ( > // > // Verify TCO base is not locked. > // > - if ((MmioRead8 (SmbusBase + R_PCH_SMBUS_TCOCTL) & > B_PCH_SMBUS_TCOCTL_TCO_BASE_LOCK) !=3D 0) { > + if (!PchIsTcoBaseSetValid ()) { > ASSERT (FALSE); > return EFI_DEVICE_ERROR; > } > // > // Disable TCO in SMBUS Device first before changing base address. > + // Byte access to not touch the TCO_BASE_LOCK bit > // > - MmioAnd16 ( > - SmbusBase + R_PCH_SMBUS_TCOCTL, > - (UINT16) ~B_PCH_SMBUS_TCOCTL_TCO_BASE_EN > + MmioAnd8 ( > + SmbusBase + R_PCH_SMBUS_TCOCTL + 1, > + (UINT8) ~(B_PCH_SMBUS_TCOCTL_TCO_BASE_EN >> 8) > ); > // > // Program TCO in SMBUS Device > @@ -373,11 +405,11 @@ PchTcoBaseSet ( > Address > ); > // > - // Enable TCO in SMBUS Device > + // Enable TCO in SMBUS Device and lock TCO BASE > // > MmioOr16 ( > SmbusBase + R_PCH_SMBUS_TCOCTL, > - B_PCH_SMBUS_TCOCTL_TCO_BASE_EN > + B_PCH_SMBUS_TCOCTL_TCO_BASE_EN | > B_PCH_SMBUS_TCOCTL_TCO_BASE_LOCK > ); > // > // Program "TCO Base Address" PCR[DMI] + 2778h[15:5, 1] to [SMBUS PCI > offset 50h[15:5], 1]. > diff --git > a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchCycleDecodingLi= b. > h > b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchCycleDecodingLi= b > .h > index 30ad2713b5..830fdf5abf 100644 > --- > a/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchCycleDecodingLi= b. > h > +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/Include/Library/PchCycleDecod > +++ ingLib.h > @@ -1,7 +1,7 @@ > /** @file > Header file for PchCycleDecodingLib. >=20 > -Copyright (c) 2017, Intel Corporation. All rights reserved.
> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
> This program and the accompanying materials are licensed and made > available under the terms and conditions of the BSD License that > accompanies this distribution. > The full text of the license may be found at @@ -87,6 +87,20 @@ > PchPwrmBaseGet ( > ); >=20 > /** > + Check if TCO Base register is present and unlocked. > + This should be called before calling PchTcoBaseSet () > + > + @retval BOOLEAN FALSE =3D Either TCO base is loc= ked or Smbus > not present > + TRUE =3D TCO base is not locked > + > +**/ > +BOOLEAN > +EFIAPI > +PchIsTcoBaseSetValid ( > + VOID > + ); > + > +/** > Set PCH TCO base address. > This cycle decoding is allowed to set when DMIC.SRL is 0. > Programming steps: > @@ -99,6 +113,8 @@ PchPwrmBaseGet ( >=20 > @retval EFI_SUCCESS Successfully completed. > @retval EFI_INVALID_PARAMETER Invalid base address passed. > + @retval EFI_UNSUPPORTED DMIC.SRL is set, or Smbus device= not > present > + @retval EFI_DEVICE_ERROR TCO Base register is locked alre= ady > **/ > EFI_STATUS > EFIAPI > -- > 2.13.3.windows.1