From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.24, mailfrom: michael.a.kubacki@intel.com) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by groups.io with SMTP; Mon, 13 May 2019 14:24:21 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 13 May 2019 14:24:21 -0700 X-ExtLoop1: 1 Received: from orsmsx109.amr.corp.intel.com ([10.22.240.7]) by fmsmga007.fm.intel.com with ESMTP; 13 May 2019 14:24:20 -0700 Received: from orsmsx157.amr.corp.intel.com (10.22.240.23) by ORSMSX109.amr.corp.intel.com (10.22.240.7) with Microsoft SMTP Server (TLS) id 14.3.408.0; Mon, 13 May 2019 14:24:20 -0700 Received: from orsmsx121.amr.corp.intel.com ([169.254.10.70]) by ORSMSX157.amr.corp.intel.com ([169.254.9.37]) with mapi id 14.03.0415.000; Mon, 13 May 2019 14:24:20 -0700 From: "Kubacki, Michael A" To: "Chen, Marc W" , "devel@edk2.groups.io" CC: "Chaganty, Rangasai V" Subject: Re: [PATCH] MinPlatformPkg: Add multiple segment support for PciHostBridgeLib Thread-Topic: [PATCH] MinPlatformPkg: Add multiple segment support for PciHostBridgeLib Thread-Index: AQHVCXDoUBUu3FBgsEadVC33Ajps1aZpj7/QgAABljA= Date: Mon, 13 May 2019 21:24:20 +0000 Message-ID: <49AB4ACB9627B8468F29D589A27B74558893B564@ORSMSX121.amr.corp.intel.com> References: <20190513094655.90868-1-marc.w.chen@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiMWFkNTY5ZmMtOWQzNS00NDAzLTkyZTItODNlN2QxMzUwN2E5IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiUkJxWDd1T2tiUDdmdFNrQmhUdlkyUmdQTEd3TnBnbUdTMGd3R0RVMzBES1dOWkFQb3FHU0h6c1dtZUFaMktPRyJ9 x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.0.600.7 dlp-reaction: no-action x-originating-ip: [10.22.254.139] MIME-Version: 1.0 Return-Path: michael.a.kubacki@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Actually run PatchCheck.py against the patch there's a few errors that need= to be fixed. > -----Original Message----- > From: Kubacki, Michael A > Sent: Monday, May 13, 2019 2:22 PM > To: Chen, Marc W ; devel@edk2.groups.io > Cc: Chaganty, Rangasai V > Subject: RE: [PATCH] MinPlatformPkg: Add multiple segment support for > PciHostBridgeLib >=20 > Please update the copyright years. The other changes look fine. >=20 > Thanks, > Michael >=20 > > -----Original Message----- > > From: Chen, Marc W > > Sent: Monday, May 13, 2019 2:47 AM > > To: devel@edk2.groups.io > > Cc: Chen, Marc W ; Kubacki, Michael A > > ; Chaganty, Rangasai V > > > > Subject: [PATCH] MinPlatformPkg: Add multiple segment support for > > PciHostBridgeLib > > > > https://bugzilla.tianocore.org/show_bug.cgi?id=3D1799 > > > > Add PcdPciSegmentCount PCD in MinPlatformPkg.dec and set default to 1, > > then base on PciHostBridge related PCDs to Initialize RootBridges. > > > > Contributed-under: TianoCore Contribution Agreement 1.1 > > Signed-off-by: Marc Chen > > Cc: Michael Kubacki > > Cc: Sai Chaganty > > --- > > Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec | 1 + > > .../PciHostBridgeLibSimple.c | 71 ++++++++++++++= +------- > > .../PciHostBridgeLibSimple.inf | 2 +- > > 3 files changed, 51 insertions(+), 23 deletions(-) > > > > diff --git a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec > > b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec > > index 3185776ac3..09701bd004 100644 > > --- a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec > > +++ b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec > > @@ -223,6 +223,7 @@ > > > gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicEnable|0x0|UINT32|0x90000 > > 019 > > gMinPlatformPkgTokenSpaceGuid.PcdPciDmaAbove4G > > |FALSE|BOOLEAN|0x4001004B > > gMinPlatformPkgTokenSpaceGuid.PcdPciNoExtendedConfigSpace > > |FALSE|BOOLEAN|0x4001004C > > gMinPlatformPkgTokenSpaceGuid.PcdPciResourceAssigned > > |FALSE|BOOLEAN|0x4001004D > > + gMinPlatformPkgTokenSpaceGuid.PcdPciSegmentCount |0x1 > > |UINT8|0x4001004E > > > > > > > gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1AEventBlockAddress|0x1800| > > UINT16|0x00010035 > > > > > gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1BEventBlockAddress|0x0000| > > UINT16|0x00010036 > > diff --git > > a/Platform/Intel/MinPlatformPkg/Pci/Library/PciHostBridgeLibSimple/Pci > > Ho > > stBridgeLibSimple.c > > b/Platform/Intel/MinPlatformPkg/Pci/Library/PciHostBridgeLibSimple/Pci > > Ho > > stBridgeLibSimple.c > > index 557ac2a5b3..aafadc598b 100644 > > --- > > a/Platform/Intel/MinPlatformPkg/Pci/Library/PciHostBridgeLibSimple/Pci > > Ho > > stBridgeLibSimple.c > > +++ b/Platform/Intel/MinPlatformPkg/Pci/Library/PciHostBridgeLibSimple > > +++ /P > > +++ ciHostBridgeLibSimple.c > > @@ -15,6 +15,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF > ANY KIND, > > EITHER EXPRESS OR IMPLIED. > > #include > > #include > > #include > > +#include > > #include > > #include #include > > @@ > > -28,7 +29,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY > KIND, > > EITHER EXPRESS OR IMPLIED. > > GLOBAL_REMOVE_IF_UNREFERENCED CHAR16 > > *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] =3D { > > L"Mem", L"I/O", L"Bus" > > }; > > -ACPI_HID_DEVICE_PATH mRootBridgeDeviceNode =3D { > > +ACPI_HID_DEVICE_PATH mRootBridgeDeviceNodeTemplate =3D { > > { > > ACPI_DEVICE_PATH, > > ACPI_DP, > > @@ -41,7 +42,7 @@ ACPI_HID_DEVICE_PATH mRootBridgeDeviceNode =3D > { > > 0 > > }; > > > > -PCI_ROOT_BRIDGE mRootBridge =3D { > > +PCI_ROOT_BRIDGE mRootBridgeTemplate =3D { > > 0, > > EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO | > > EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO | > > @@ -66,41 +67,67 @@ PCI_ROOT_BRIDGE mRootBridge =3D { > > NULL // DevicePath; > > }; > > > > +/** > > + Return all the root bridge instances. > > + > > + @param Count Return the count of root bridge instances. > > + > > + @return All the root bridge instances, it will be NULL if system > > + has > > insufficient memory > > + resources available and count will be zero. > > +**/ > > + > > PCI_ROOT_BRIDGE * > > EFIAPI > > PciHostBridgeGetRootBridges ( > > UINTN *Count > > ) > > { > > - mRootBridge.Mem.Base =3D PcdGet32 (PcdPciReservedMemBase); > > + UINT8 Index; > > + PCI_ROOT_BRIDGE *RootBridge; > > + > > + RootBridge =3D AllocateZeroPool (sizeof (PCI_ROOT_BRIDGE) * PcdGet8 > > + (PcdPciSegmentCount)); if (RootBridge =3D=3D NULL) { > > + DEBUG ((EFI_D_ERROR, "PciHostBridge: Out of resource\n")); > > + *Count =3D 0; > > + return RootBridge; > > + } > > + > > + mRootBridgeTemplate.Mem.Base =3D PcdGet32 > (PcdPciReservedMemBase); > > if (PcdGet32(PcdPciReservedMemLimit) !=3D 0) { > > - mRootBridge.Mem.Limit =3D PcdGet32 (PcdPciReservedMemLimit); > > + mRootBridgeTemplate.Mem.Limit =3D PcdGet32 > > (PcdPciReservedMemLimit); > > } else { > > - mRootBridge.Mem.Limit =3D (UINT32)PcdGet64 > > (PcdPciExpressBaseAddress); > > + mRootBridgeTemplate.Mem.Limit =3D (UINT32) PcdGet64 > > + (PcdPciExpressBaseAddress); > > } > > > > - mRootBridge.MemAbove4G.Base =3D PcdGet64 > > (PcdPciReservedMemAbove4GBBase); > > - mRootBridge.MemAbove4G.Limit =3D PcdGet64 > > (PcdPciReservedMemAbove4GBLimit); > > + mRootBridgeTemplate.MemAbove4G.Base =3D PcdGet64 > > + (PcdPciReservedMemAbove4GBBase); > > mRootBridgeTemplate.MemAbove4G.Limit > > + =3D PcdGet64 (PcdPciReservedMemAbove4GBLimit); > > > > - mRootBridge.PMem.Base =3D PcdGet32 (PcdPciReservedPMemBase); > > - mRootBridge.PMem.Limit =3D PcdGet32 (PcdPciReservedPMemLimit); > > - mRootBridge.PMemAbove4G.Base =3D PcdGet64 > > (PcdPciReservedPMemAbove4GBBase); > > - mRootBridge.PMemAbove4G.Limit =3D PcdGet64 > > (PcdPciReservedPMemAbove4GBLimit); > > + mRootBridgeTemplate.PMem.Base =3D PcdGet32 > > (PcdPciReservedPMemBase); > > + mRootBridgeTemplate.PMem.Limit =3D PcdGet32 > > (PcdPciReservedPMemLimit); > > + mRootBridgeTemplate.PMemAbove4G.Base =3D PcdGet64 > > + (PcdPciReservedPMemAbove4GBBase); > > + mRootBridgeTemplate.PMemAbove4G.Limit =3D PcdGet64 > > + (PcdPciReservedPMemAbove4GBLimit); > > > > - if (mRootBridge.MemAbove4G.Base < mRootBridge.MemAbove4G.Limit) > { > > - mRootBridge.AllocationAttributes |=3D > > EFI_PCI_HOST_BRIDGE_MEM64_DECODE; > > + if (mRootBridgeTemplate.MemAbove4G.Base < > > mRootBridgeTemplate.MemAbove4G.Limit) { > > + mRootBridgeTemplate.AllocationAttributes |=3D > > + EFI_PCI_HOST_BRIDGE_MEM64_DECODE; > > } > > > > - mRootBridge.Io.Base =3D PcdGet16 (PcdPciReservedIobase); > > - mRootBridge.Io.Limit =3D PcdGet16 (PcdPciReservedIoLimit); > > + mRootBridgeTemplate.Io.Base =3D PcdGet16 (PcdPciReservedIobase); > > + mRootBridgeTemplate.Io.Limit =3D PcdGet16 (PcdPciReservedIoLimit); > > > > - mRootBridge.DmaAbove4G =3D PcdGetBool (PcdPciDmaAbove4G); > > - mRootBridge.NoExtendedConfigSpace =3D PcdGetBool > > (PcdPciNoExtendedConfigSpace); > > - mRootBridge.ResourceAssigned =3D PcdGetBool (PcdPciResourceAssigned)= ; > > + mRootBridgeTemplate.DmaAbove4G =3D PcdGetBool > (PcdPciDmaAbove4G); > > + mRootBridgeTemplate.NoExtendedConfigSpace =3D PcdGetBool > > + (PcdPciNoExtendedConfigSpace); > > mRootBridgeTemplate.ResourceAssigned =3D > > + PcdGetBool (PcdPciResourceAssigned); > > + > > + for (Index =3D 0; Index < PcdGet8 (PcdPciSegmentCount); Index ++) { > > + mRootBridgeDeviceNodeTemplate.UID =3D Index; > > + mRootBridgeTemplate.Segment =3D Index; > > + mRootBridgeTemplate.DevicePath =3D NULL; > > + mRootBridgeTemplate.DevicePath =3D AppendDevicePathNode (NULL, > > &mRootBridgeDeviceNodeTemplate.Header); > > + CopyMem (RootBridge + Index, &mRootBridgeTemplate, sizeof > > + (PCI_ROOT_BRIDGE)); } > > > > - mRootBridge.DevicePath =3D AppendDevicePathNode (NULL, > > &mRootBridgeDeviceNode.Header); > > - *Count =3D 1; > > - return &mRootBridge; > > + *Count =3D PcdGet8 (PcdPciSegmentCount); return RootBridge; > > } > > > > VOID > > @@ -110,7 +137,7 @@ PciHostBridgeFreeRootBridges ( > > UINTN Count > > ) > > { > > - ASSERT (Count =3D=3D 1); > > + ASSERT (Count <=3D PcdGet8 (PcdPciSegmentCount)); > > FreePool (Bridges->DevicePath); > > } > > > > diff --git > > a/Platform/Intel/MinPlatformPkg/Pci/Library/PciHostBridgeLibSimple/Pci > > Ho > > stBridgeLibSimple.inf > > b/Platform/Intel/MinPlatformPkg/Pci/Library/PciHostBridgeLibSimple/Pci > > Ho > > stBridgeLibSimple.inf > > index f9a769155b..e5c0ca2774 100644 > > --- > > a/Platform/Intel/MinPlatformPkg/Pci/Library/PciHostBridgeLibSimple/Pci > > Ho > > stBridgeLibSimple.inf > > +++ > > b/Platform/Intel/MinPlatformPkg/Pci/Library/PciHostBridgeLibSimple/Pci > > Ho > > stBridgeLibSimple.inf > > @@ -56,4 +56,4 @@ > > gMinPlatformPkgTokenSpaceGuid.PcdPciDmaAbove4G > > gMinPlatformPkgTokenSpaceGuid.PcdPciNoExtendedConfigSpace > > gMinPlatformPkgTokenSpaceGuid.PcdPciResourceAssigned > > - > > + gMinPlatformPkgTokenSpaceGuid.PcdPciSegmentCount > > -- > > 2.16.2.windows.1