* [edk2-platforms] [PATCH v2 0/5] Added GCC5 build support
@ 2019-05-21 3:08 Agyeman, Prince
2019-05-21 3:08 ` [edk2-platforms] [PATCH v2 1/5] MinPlatformPkg: " Agyeman, Prince
` (4 more replies)
0 siblings, 5 replies; 18+ messages in thread
From: Agyeman, Prince @ 2019-05-21 3:08 UTC (permalink / raw)
To: devel; +Cc: chasel.chiu, Prince Agyeman
From: Prince Agyeman <prince.agyeman@intel.com>
This patch series adds GCC 5 build support to
ClevoOpenBoardPkg and KabylakeOpenBoardPkg
Changes in v2:
- Updated Readme.md
- Updated python path in build_bios.py
- Fixed spelling error in Stack.nasm
- Fixed copyright data in SecFspWrapperPlatformSecLib
- Removed TE Rule from RuleInclude.fdf, updated PE32 alignment to 64
Prince Agyeman (5):
MinPlatformPkg: Added GCC5 build support
KabylakeSiliconPkg: Casting functions to EFIAPI
KabylakeOpenBoardPkg: Added GCC5 build support
ClevoOpenBoardPkg: Added GCC5 build support
Intel/Readme.md: Updated readme with linux build instructions
.../N1xxWU/OpenBoardPkgBuildOption.dsc | 2 +
Platform/Intel/ClevoOpenBoardPkg/OpenBoardPkg.dec | 4 +-
.../KabylakeRvp3/OpenBoardPkgBuildOption.dsc | 4 +-
.../Intel/KabylakeOpenBoardPkg/OpenBoardPkg.dec | 6 +-
.../Ia32/PeiCoreEntry.S | 117 -------
.../Ia32/{PeiCoreEntry.asm => PeiCoreEntry.nasm} | 46 +--
.../SecFspWrapperPlatformSecLib/Ia32/SecEntry.S | 342 ---------------------
.../Ia32/{SecEntry.asm => SecEntry.nasm} | 132 ++++----
.../SecFspWrapperPlatformSecLib/Ia32/Stack.S | 67 ----
.../Ia32/{Stack.asm => Stack.nasm} | 39 ++-
.../SecFspWrapperPlatformSecLib.inf | 12 +-
.../MinPlatformPkg/Include/Fdf/RuleInclude.fdf | 6 +-
.../Tools/Fsp/RebaseAndPatchFspBinBaseAddress.py | 2 +-
.../MinPlatformPkg/Tools/PatchFv/PatchBinFv.py | 8 +-
.../MinPlatformPkg/Tools/PatchFv/RebaseBinFv.py | 15 +-
Platform/Intel/Readme.md | 42 +--
Platform/Intel/build_bios.py | 28 +-
.../Pch/PchInit/Smm/PchInitSmm.h | 3 +-
.../Pch/PchInit/Smm/PchPcieSmm.c | 3 +-
.../Pch/PchSmiDispatcher/Smm/PchSmm.h | 4 +-
.../Pch/PchSmiDispatcher/Smm/PchSmmCore.c | 4 +-
21 files changed, 187 insertions(+), 699 deletions(-)
delete mode 100644 Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/PeiCoreEntry.S
rename Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/{PeiCoreEntry.asm => PeiCoreEntry.nasm} (66%)
delete mode 100644 Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.S
rename Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/{SecEntry.asm => SecEntry.nasm} (72%)
delete mode 100644 Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Stack.S
rename Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/{Stack.asm => Stack.nasm} (59%)
--
2.7.4
^ permalink raw reply [flat|nested] 18+ messages in thread
* [edk2-platforms] [PATCH v2 1/5] MinPlatformPkg: Added GCC5 build support
2019-05-21 3:08 [edk2-platforms] [PATCH v2 0/5] Added GCC5 build support Agyeman, Prince
@ 2019-05-21 3:08 ` Agyeman, Prince
2019-05-22 19:08 ` Kubacki, Michael A
2019-05-22 19:11 ` Nate DeSimone
2019-05-21 3:08 ` [edk2-platforms] [PATCH v2 2/5] KabylakeSiliconPkg: Casting functions to EFIAPI Agyeman, Prince
` (3 subsequent siblings)
4 siblings, 2 replies; 18+ messages in thread
From: Agyeman, Prince @ 2019-05-21 3:08 UTC (permalink / raw)
To: devel
Cc: chasel.chiu, Prince Agyeman, Michael Kubacki, Michael D Kinney,
Nate DeSimone, Liming Gao, Ankit Sinha
From: Prince Agyeman <prince.agyeman@intel.com>
Fixes:
* Replacing .asm and .S with nasm in SecFspWrapperPlatformSecLib
for cross-platform build support
* Modified RuleInclude.fdf
* Modified python files to be OS independent
Gcc build was tested on Ubuntu 16.04.5 LTS with gcc version 5.4.0,
nasm version 2.11.08
Cc: Michael Kubacki <michael.a.kubacki@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Ankit Sinha <ankit.sinha@intel.com>
Signed-off-by: Prince Agyeman <prince.agyeman@intel.com>
---
.../Ia32/PeiCoreEntry.S | 117 -------
.../Ia32/{PeiCoreEntry.asm => PeiCoreEntry.nasm} | 46 +--
.../SecFspWrapperPlatformSecLib/Ia32/SecEntry.S | 342 ---------------------
.../Ia32/{SecEntry.asm => SecEntry.nasm} | 132 ++++----
.../SecFspWrapperPlatformSecLib/Ia32/Stack.S | 67 ----
.../Ia32/{Stack.asm => Stack.nasm} | 39 ++-
.../SecFspWrapperPlatformSecLib.inf | 12 +-
.../MinPlatformPkg/Include/Fdf/RuleInclude.fdf | 6 +-
.../Tools/Fsp/RebaseAndPatchFspBinBaseAddress.py | 2 +-
.../MinPlatformPkg/Tools/PatchFv/PatchBinFv.py | 8 +-
.../MinPlatformPkg/Tools/PatchFv/RebaseBinFv.py | 15 +-
Platform/Intel/build_bios.py | 28 +-
12 files changed, 143 insertions(+), 671 deletions(-)
delete mode 100644 Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/PeiCoreEntry.S
rename Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/{PeiCoreEntry.asm => PeiCoreEntry.nasm} (66%)
delete mode 100644 Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.S
rename Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/{SecEntry.asm => SecEntry.nasm} (72%)
delete mode 100644 Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Stack.S
rename Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/{Stack.asm => Stack.nasm} (59%)
diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/PeiCoreEntry.S b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/PeiCoreEntry.S
deleted file mode 100644
index 8c8356f..0000000
--- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/PeiCoreEntry.S
+++ /dev/null
@@ -1,117 +0,0 @@
-## @file
-# Find and call SecStartup
-#
-# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
-# SPDX-License-Identifier: BSD-2-Clause-Patent
-#
-##
-
-ASM_GLOBAL ASM_PFX(CallPeiCoreEntryPoint)
-ASM_PFX(CallPeiCoreEntryPoint):
- #
- # Obtain the hob list pointer
- #
- movl 0x4(%esp), %eax
- #
- # Obtain the stack information
- # ECX: start of range
- # EDX: end of range
- #
- movl 0x8(%esp), %ecx
- movl 0xC(%esp), %edx
-
- #
- # Platform init
- #
- pushal
- pushl %edx
- pushl %ecx
- pushl %eax
- call ASM_PFX(PlatformInit)
- popl %eax
- popl %eax
- popl %eax
- popal
-
- #
- # Set stack top pointer
- #
- movl %edx, %esp
-
- #
- # Push the hob list pointer
- #
- pushl %eax
-
- #
- # Save the value
- # ECX: start of range
- # EDX: end of range
- #
- movl %esp, %ebp
- pushl %ecx
- pushl %edx
-
- #
- # Push processor count to stack first, then BIST status (AP then BSP)
- #
- movl $1, %eax
- cpuid
- shr $16, %ebx
- andl $0x000000FF, %ebx
- cmp $1, %bl
- jae PushProcessorCount
-
- #
- # Some processors report 0 logical processors. Effectively 0 = 1.
- # So we fix up the processor count
- #
- inc %ebx
-
-PushProcessorCount:
- pushl %ebx
-
- #
- # We need to implement a long-term solution for BIST capture. For now, we just copy BSP BIST
- # for all processor threads
- #
- xorl %ecx, %ecx
- movb %bl, %cl
-PushBist:
- movd %mm0, %eax
- pushl %eax
- loop PushBist
-
- # Save Time-Stamp Counter
- movd %mm5, %eax
- pushl %eax
-
- movd %mm6, %eax
- pushl %eax
-
- #
- # Pass entry point of the PEI core
- #
- movl $0xFFFFFFE0, %edi
- pushl %ds:(%edi)
-
- #
- # Pass BFV into the PEI Core
- #
- movl $0xFFFFFFFC, %edi
- pushl %ds:(%edi)
-
- #
- # Pass stack size into the PEI Core
- #
- movl -4(%ebp), %ecx
- movl -8(%ebp), %edx
- pushl %ecx # RamBase
-
- subl %ecx, %edx
- pushl %edx # RamSize
-
- #
- # Pass Control into the PEI Core
- #
- call ASM_PFX(SecStartup)
diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/PeiCoreEntry.asm b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/PeiCoreEntry.nasm
similarity index 66%
rename from Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/PeiCoreEntry.asm
rename to Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/PeiCoreEntry.nasm
index c854067..5c5b788 100644
--- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/PeiCoreEntry.asm
+++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/PeiCoreEntry.nasm
@@ -1,21 +1,25 @@
-;; @file
-; Find and call SecStartup
+;------------------------------------------------------------------------------
;
-; Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
-;;
-
+; Module Name:
+;
+; PeiCoreEntry.nasm
+;
+; Abstract:
+;
+; Find and call SecStartup
+;
+;------------------------------------------------------------------------------
-.686p
-.xmm
-.model flat, c
-.code
+SECTION .text
-EXTRN SecStartup:NEAR
-EXTRN PlatformInit:NEAR
+extern ASM_PFX(SecStartup)
+extern ASM_PFX(PlatformInit)
-CallPeiCoreEntryPoint PROC PUBLIC
+global ASM_PFX(CallPeiCoreEntryPoint)
+ASM_PFX(CallPeiCoreEntryPoint):
;
; Obtain the hob list pointer
;
@@ -26,7 +30,7 @@ CallPeiCoreEntryPoint PROC PUBLIC
; EDX: end of range
;
mov ecx, [esp+8]
- mov edx, [esp+0Ch]
+ mov edx, [esp+0xC]
;
; Platform init
@@ -35,7 +39,7 @@ CallPeiCoreEntryPoint PROC PUBLIC
push edx
push ecx
push eax
- call PlatformInit
+ call ASM_PFX(PlatformInit)
pop eax
pop eax
pop eax
@@ -66,7 +70,7 @@ CallPeiCoreEntryPoint PROC PUBLIC
mov eax, 1
cpuid
shr ebx, 16
- and ebx, 0000000FFh
+ and ebx, 0xFF
cmp bl, 1
jae PushProcessorCount
@@ -100,14 +104,14 @@ PushBist:
;
; Pass entry point of the PEI core
;
- mov edi, 0FFFFFFE0h
- push DWORD PTR ds:[edi]
+ mov edi, 0xFFFFFFE0
+ push DWORD [edi]
;
; Pass BFV into the PEI Core
;
- mov edi, 0FFFFFFFCh
- push DWORD PTR ds:[edi]
+ mov edi, 0xFFFFFFFC
+ push DWORD [edi]
;
; Pass stack size into the PEI Core
@@ -122,7 +126,5 @@ PushBist:
;
; Pass Control into the PEI Core
;
- call SecStartup
-CallPeiCoreEntryPoint ENDP
+ call ASM_PFX(SecStartup)
-END
diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.S b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.S
deleted file mode 100644
index 63c420a..0000000
--- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.S
+++ /dev/null
@@ -1,342 +0,0 @@
-## @file
-# This is the code that goes from real-mode to protected mode.
-# It consumes the reset vector, calls TempRamInit API from FSP binary.
-#
-# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
-# SPDX-License-Identifier: BSD-2-Clause-Patent
-#
-##
-
-#include "Fsp.h"
-
-ASM_GLOBAL ASM_PFX(_gPcd_FixedAtBuild_PcdFsptBaseAddress)
-ASM_GLOBAL ASM_PFX(_gPcd_FixedAtBuild_PcdFspTemporaryRamSize)
-
-ASM_GLOBAL ASM_PFX(_TEXT_REALMODE)
-ASM_PFX(_TEXT_REALMODE):
-#----------------------------------------------------------------------------
-#
-# Procedure: _ModuleEntryPoint
-#
-# Input: None
-#
-# Output: None
-#
-# Destroys: Assume all registers
-#
-# Description:
-#
-# Transition to non-paged flat-model protected mode from a
-# hard-coded GDT that provides exactly two descriptors.
-# This is a bare bones transition to protected mode only
-# used for a while in PEI and possibly DXE.
-#
-# After enabling protected mode, a far jump is executed to
-# transfer to PEI using the newly loaded GDT.
-#
-# Return: None
-#
-# MMX Usage:
-# MM0 = BIST State
-# MM5 = Save time-stamp counter value high32bit
-# MM6 = Save time-stamp counter value low32bit.
-#
-#----------------------------------------------------------------------------
-
-ASM_GLOBAL ASM_PFX(_ModuleEntryPoint)
-ASM_PFX(_ModuleEntryPoint):
- fninit # clear any pending Floating point exceptions
- #
- # Store the BIST value in mm0
- #
- movd %eax, %mm0
- cli
-
- #
- # Check INIT# is asserted by port 0xCF9
- #
- mov $0x0CF9, %dx
- in %dx, %al
- cmp $0x04, %al
- jnz NotWarmStart
-
- #
- # @note Issue warm reset, since if CPU only reset is issued not all MSRs are restored to their defaults
- #
- movw $0x0CF9, %dx
- movb $0x06, %al
- out %al, %dx
-
- #
- # Save time-stamp counter value
- # rdtsc load 64bit time-stamp counter to EDX:EAX
- #
- rdtsc
- movd %edx, %mm5
- movd %ecx, %mm6
-
- #
- # Load the GDT table in GdtDesc
- #
- movl $GdtDesc, %esi
- .byte 0x66
- lgdt %cs:(%si)
-
- #
- # Transition to 16 bit protected mode
- #
- movl %cr0, %eax # Get control register 0
- orl $0x00000003, %eax # Set PE bit (bit #0) & MP bit (bit #1)
- movl %eax, %cr0 # Activate protected mode
-
- movl %cr4, %eax # Get control register 4
- orl $0x00000600, %eax # Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10)
- movl %eax, %cr4
-
- #
- # Now we're in 16 bit protected mode
- # Set up the selectors for 32 bit protected mode entry
- #
- mov $SYS_DATA_SEL, %ax
- mov %ax, %ds
- mov %ax, %es
- mov %ax, %fs
- mov %ax, %gs
- mov %ax, %ss
-
- #
- # Transition to Flat 32 bit protected mode
- # The jump to a far pointer causes the transition to 32 bit mode
- #
- movl $ProtectedModeEntryLinearAddress, %esi
- jmp *%cs:(%si)
-
-ASM_GLOBAL ASM_PFX(_TEXT_PROTECTED_MODE)
-ASM_PFX(_TEXT_PROTECTED_MODE):
-
-#----------------------------------------------------------------------------
-#
-# Procedure: ProtectedModeEntryPoint
-#
-# Input: None
-#
-# Output: None
-#
-# Destroys: Assume all registers
-#
-# Description:
-#
-# This function handles:
-# Call two basic APIs from FSP binary
-# Initializes stack with some early data (BIST, PEI entry, etc)
-#
-# Return: None
-#
-#----------------------------------------------------------------------------
-
-ASM_GLOBAL ASM_PFX(ProtectedModeEntryPoint)
-ASM_PFX(ProtectedModeEntryPoint):
-
- # Find the fsp info header
- movl PcdGet32(PcdFsptBaseAddress), %edi
-
- movl FVH_SIGINATURE_OFFSET(%edi), %eax
- cmp $FVH_SIGINATURE_VALID_VALUE, %eax
- jnz FspHeaderNotFound
-
- xorl %eax, %eax
- movw FVH_EXTHEADER_OFFSET_OFFSET(%edi), %ax
- cmp $0x00, %ax
- jnz FspFvExtHeaderExist
-
- xorl %eax, %eax
- movw FVH_HEADER_LENGTH_OFFSET(%edi), %ax # Bypass Fv Header
- addl %eax, %edi
- jmp FspCheckFfsHeader
-
-FspFvExtHeaderExist:
- addl %eax, %edi
- movl FVH_EXTHEADER_SIZE_OFFSET(%edi), %eax # Bypass Ext Fv Header
- addl %eax, %edi
-
- # Round up to 8 byte alignment
- movl %edi, %eax
- andb $0x07, %al
- jz FspCheckFfsHeader
-
- and $0xFFFFFFF8, %edi
- add $0x08, %edi
-
-FspCheckFfsHeader:
- # Check the ffs guid
- movl (%edi), %eax
- cmp $FSP_HEADER_GUID_DWORD1, %eax
- jnz FspHeaderNotFound
-
- movl 0x4(%edi), %eax
- cmp $FSP_HEADER_GUID_DWORD2, %eax
- jnz FspHeaderNotFound
-
- movl 0x08(%edi), %eax
- cmp $FSP_HEADER_GUID_DWORD3, %eax
- jnz FspHeaderNotFound
-
- movl 0x0c(%edi), %eax
- cmp $FSP_HEADER_GUID_DWORD4, %eax
- jnz FspHeaderNotFound
-
- add $FFS_HEADER_SIZE_VALUE, %edi # Bypass the ffs header
-
- # Check the section type as raw section
- movb SECTION_HEADER_TYPE_OFFSET(%edi), %al
- cmp $0x19, %al
- jnz FspHeaderNotFound
-
- addl $RAW_SECTION_HEADER_SIZE_VALUE, %edi # Bypass the section header
- jmp FspHeaderFound
-
-FspHeaderNotFound:
- jmp .
-
-FspHeaderFound:
- # Get the fsp TempRamInit Api address
- movl FSP_HEADER_IMAGEBASE_OFFSET(%edi), %eax
- addl FSP_HEADER_TEMPRAMINIT_OFFSET(%edi), %eax
-
- # Setup the hardcode stack
- movl $TempRamInitStack, %esp
-
- # Call the fsp TempRamInit Api
- jmp *%eax
-
-TempRamInitDone:
- cmp $0x8000000E, %eax #Check if EFI_NOT_FOUND returned. Error code for Microcode Update not found.
- je CallSecFspInit #If microcode not found, don't hang, but continue.
-
- cmp $0x0, %eax
- jnz FspApiFailed
-
- # ECX: start of range
- # EDX: end of range
-CallSecFspInit:
- subl PcdGet32 (PcdFspTemporaryRamSize), %edx # TemporaryRam for FSP
- xorl %eax, %eax
- movl %edx, %esp
-
- # Align the stack at DWORD
- addl $3, %esp
- andl $0xFFFFFFFC, %esp
-
- pushl %edx
- pushl %ecx
- pushl %eax # zero - no hob list yet
- call ASM_PFX(CallPeiCoreEntryPoint)
-
-FspApiFailed:
- jmp .
-
-.align 0x10
-TempRamInitStack:
- .long TempRamInitDone
- .long FsptUpdDataPtr
-
-#
-# ROM-based Global-Descriptor Table for the Tiano PEI Phase
-#
-.align 0x10
-
-#
-# GDT[0]: 0x00: Null entry, never used.
-#
-.equ NULL_SEL, . - GdtBase # Selector [0]
-GdtBase:
-BootGdtTable:
- .long 0
- .long 0
-
-#
-# Linear data segment descriptor
-#
-.equ LINEAR_SEL, . - GdtBase # Selector [0x8]
- .word 0xFFFF # limit 0xFFFFF
- .word 0 # base 0
- .byte 0
- .byte 0x92 # present, ring 0, data, expand-up, writable
- .byte 0xCF # page-granular, 32-bit
- .byte 0
-
-#
-# Linear code segment descriptor
-#
-.equ LINEAR_CODE_SEL, . - GdtBase # Selector [0x10]
- .word 0xFFFF # limit 0xFFFFF
- .word 0 # base 0
- .byte 0
- .byte 0x9B # present, ring 0, data, expand-up, not-writable
- .byte 0xCF # page-granular, 32-bit
- .byte 0
-#
-# System data segment descriptor
-#
-.equ SYS_DATA_SEL, . - GdtBase # Selector [0x18]
- .word 0xFFFF # limit 0xFFFFF
- .word 0 # base 0
- .byte 0
- .byte 0x93 # present, ring 0, data, expand-up, not-writable
- .byte 0xCF # page-granular, 32-bit
- .byte 0
-
-#
-# System code segment descriptor
-#
-.equ SYS_CODE_SEL, . - GdtBase # Selector [0x20]
- .word 0xFFFF # limit 0xFFFFF
- .word 0 # base 0
- .byte 0
- .byte 0x9A # present, ring 0, data, expand-up, writable
- .byte 0xCF # page-granular, 32-bit
- .byte 0
-#
-# Spare segment descriptor
-#
-.equ SYS16_CODE_SEL, . - GdtBase # Selector [0x28]
- .word 0xFFFF # limit 0xFFFFF
- .word 0 # base 0
- .byte 0x0E # Changed from F000 to E000.
- .byte 0x9B # present, ring 0, code, expand-up, writable
- .byte 0x00 # byte-granular, 16-bit
- .byte 0
-#
-# Spare segment descriptor
-#
-.equ SYS16_DATA_SEL, . - GdtBase # Selector [0x30]
- .word 0xFFFF # limit 0xFFFF
- .word 0 # base 0
- .byte 0
- .byte 0x93 # present, ring 0, data, expand-up, not-writable
- .byte 0x00 # byte-granular, 16-bit
- .byte 0
-
-#
-# Spare segment descriptor
-#
-.equ SPARE5_SEL, . - GdtBase # Selector [0x38]
- .word 0 # limit 0
- .word 0 # base 0
- .byte 0
- .byte 0 # present, ring 0, data, expand-up, writable
- .byte 0 # page-granular, 32-bit
- .byte 0
-.equ GDT_SIZE, . - BootGdtTable # Size, in bytes
-
-#
-# GDT Descriptor
-#
-GdtDesc: # GDT descriptor
- .word GDT_SIZE - 1 # GDT limit
- .long BootGdtTable # GDT base address
-
-ASM_PFX(ProtectedModeEntryLinearAddress):
-ProtectedModeEntryLinearOffset:
- .long ProtectedModeEntryPoint # Offset of our 32 bit code
- .word LINEAR_CODE_SEL
diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.asm b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
similarity index 72%
rename from Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.asm
rename to Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
index 2886a37..7f6d771 100644
--- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.asm
+++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
@@ -1,28 +1,28 @@
-;; @file
-; This is the code that goes from real-mode to protected mode.
-; It consumes the reset vector, calls TempRamInit API from FSP binary.
+;------------------------------------------------------------------------------
;
-; Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
+; Module Name:
;
-;;
+; SecEntry.nasm
+;
+; Abstract:
+;
+; This is the code that goes from real-mode to protected mode.
+; It consumes the reset vector, calls TempRamInit API from FSP binary.
+;
+;------------------------------------------------------------------------------
#include "Fsp.h"
-.686p
-.xmm
-.model small, c
-
-EXTRN CallPeiCoreEntryPoint:NEAR
-EXTRN BoardBeforeTempRamInit:NEAR
-EXTRN FsptUpdDataPtr:FAR
+SECTION .text
+extern ASM_PFX(CallPeiCoreEntryPoint)
+extern ASM_PFX(FsptUpdDataPtr)
+extern ASM_PFX(BoardBeforeTempRamInit)
; Pcds
-EXTRN PcdGet32 (PcdFsptBaseAddress):DWORD
-EXTRN PcdGet32(PcdFspTemporaryRamSize):DWORD
-
-_TEXT_REALMODE SEGMENT PARA PUBLIC USE16 'CODE'
- ASSUME CS:_TEXT_REALMODE, DS:_TEXT_REALMODE
+extern ASM_PFX(PcdGet32 (PcdFspTemporaryRamSize))
+extern ASM_PFX(PcdGet32 (PcdFsptBaseAddress))
;----------------------------------------------------------------------------
;
@@ -53,8 +53,10 @@ _TEXT_REALMODE SEGMENT PARA PUBLIC USE16 'CODE'
;
;----------------------------------------------------------------------------
+BITS 16
align 4
-_ModuleEntryPoint PROC NEAR C PUBLIC
+global ASM_PFX(_ModuleEntryPoint)
+ASM_PFX(_ModuleEntryPoint):
fninit ; clear any pending Floating point exceptions
;
; Store the BIST value in mm0
@@ -70,6 +72,7 @@ _ModuleEntryPoint PROC NEAR C PUBLIC
cmp al, 04h
jnz NotWarmStart
+
;
; @note Issue warm reset, since if CPU only reset is issued not all MSRs are restored to their defaults
;
@@ -78,7 +81,6 @@ _ModuleEntryPoint PROC NEAR C PUBLIC
out dx, al
NotWarmStart:
-
;
; Save time-stamp counter value
; rdtsc load 64bit time-stamp counter to EDX:EAX
@@ -90,9 +92,9 @@ NotWarmStart:
;
; Load the GDT table in GdtDesc
;
- mov esi, OFFSET GdtDesc
+ mov esi, GdtDesc
DB 66h
- lgdt fword ptr cs:[si]
+ lgdt [cs:si]
;
; Transition to 16 bit protected mode
@@ -120,14 +122,8 @@ NotWarmStart:
; Transition to Flat 32 bit protected mode
; The jump to a far pointer causes the transition to 32 bit mode
;
- mov esi, offset ProtectedModeEntryLinearAddress
- jmp fword ptr cs:[si]
-
-_ModuleEntryPoint ENDP
-_TEXT_REALMODE ENDS
-
-_TEXT_PROTECTED_MODE SEGMENT PARA PUBLIC USE32 'CODE'
- ASSUME CS:_TEXT_PROTECTED_MODE, DS:_TEXT_PROTECTED_MODE
+ mov esi, ProtectedModeEntryLinearAddress
+ jmp dword far [cs:si]
;----------------------------------------------------------------------------
;
@@ -149,69 +145,69 @@ _TEXT_PROTECTED_MODE SEGMENT PARA PUBLIC USE32 'CODE'
;
;----------------------------------------------------------------------------
+BITS 32
align 4
-ProtectedModeEntryPoint PROC NEAR PUBLIC
-
- ;
- ; Early board hooks
- ;
- mov esp, BoardBeforeTempRamInitRet
- jmp BoardBeforeTempRamInit
+ProtectedModeEntryPoint:
+ ;
+ ; Early board hooks
+ ;
+ mov esp, BoardBeforeTempRamInitRet
+ jmp ASM_PFX(BoardBeforeTempRamInit)
BoardBeforeTempRamInitRet:
; Find the fsp info header
- mov edi, PcdGet32 (PcdFsptBaseAddress)
+ mov edi, [ASM_PFX(PcdGet32 (PcdFsptBaseAddress))]
- mov eax, dword ptr [edi + FVH_SIGINATURE_OFFSET]
+ mov eax, dword [edi + FVH_SIGINATURE_OFFSET]
cmp eax, FVH_SIGINATURE_VALID_VALUE
jnz FspHeaderNotFound
xor eax, eax
- mov ax, word ptr [edi + FVH_EXTHEADER_OFFSET_OFFSET]
+ mov ax, word [edi + FVH_EXTHEADER_OFFSET_OFFSET]
cmp ax, 0
jnz FspFvExtHeaderExist
xor eax, eax
- mov ax, word ptr [edi + FVH_HEADER_LENGTH_OFFSET] ; Bypass Fv Header
+ mov ax, word [edi + FVH_HEADER_LENGTH_OFFSET] ; Bypass Fv Header
add edi, eax
jmp FspCheckFfsHeader
FspFvExtHeaderExist:
add edi, eax
- mov eax, dword ptr [edi + FVH_EXTHEADER_SIZE_OFFSET] ; Bypass Ext Fv Header
+ mov eax, dword [edi + FVH_EXTHEADER_SIZE_OFFSET] ; Bypass Ext Fv Header
add edi, eax
; Round up to 8 byte alignment
mov eax, edi
and al, 07h
- jz FspCheckFfsHeader
+ jz FspCheckFfsHeader
and edi, 0FFFFFFF8h
add edi, 08h
FspCheckFfsHeader:
; Check the ffs guid
- mov eax, dword ptr [edi]
+ mov eax, dword [edi]
cmp eax, FSP_HEADER_GUID_DWORD1
- jnz FspHeaderNotFound
+ jnz FspHeaderNotFound
- mov eax, dword ptr [edi + 4]
+ mov eax, dword [edi + 4]
cmp eax, FSP_HEADER_GUID_DWORD2
- jnz FspHeaderNotFound
+ jnz FspHeaderNotFound
- mov eax, dword ptr [edi + 8]
+ mov eax, dword [edi + 8]
cmp eax, FSP_HEADER_GUID_DWORD3
- jnz FspHeaderNotFound
+ jnz FspHeaderNotFound
- mov eax, dword ptr [edi + 0Ch]
+ mov eax, dword [edi + 0Ch]
cmp eax, FSP_HEADER_GUID_DWORD4
- jnz FspHeaderNotFound
+ jnz FspHeaderNotFound
add edi, FFS_HEADER_SIZE_VALUE ; Bypass the ffs header
; Check the section type as raw section
- mov al, byte ptr [edi + SECTION_HEADER_TYPE_OFFSET]
+ mov al, byte [edi + SECTION_HEADER_TYPE_OFFSET]
cmp al, 019h
jnz FspHeaderNotFound
@@ -223,11 +219,11 @@ FspHeaderNotFound:
FspHeaderFound:
; Get the fsp TempRamInit Api address
- mov eax, dword ptr [edi + FSP_HEADER_IMAGEBASE_OFFSET]
- add eax, dword ptr [edi + FSP_HEADER_TEMPRAMINIT_OFFSET]
+ mov eax, dword [edi + FSP_HEADER_IMAGEBASE_OFFSET]
+ add eax, dword [edi + FSP_HEADER_TEMPRAMINIT_OFFSET]
; Setup the hardcode stack
- mov esp, OFFSET TempRamInitStack
+ mov esp, TempRamInitStack
; Call the fsp TempRamInit Api
jmp eax
@@ -242,7 +238,7 @@ TempRamInitDone:
; ECX: start of range
; EDX: end of range
CallSecFspInit:
- sub edx, PcdGet32 (PcdFspTemporaryRamSize) ; TemporaryRam for FSP
+ sub edx, [ASM_PFX(PcdGet32 (PcdFspTemporaryRamSize))] ; TemporaryRam for FSP
xor eax, eax
mov esp, edx
@@ -253,30 +249,29 @@ CallSecFspInit:
push edx
push ecx
push eax ; zero - no hob list yet
- call CallPeiCoreEntryPoint
+ call ASM_PFX(CallPeiCoreEntryPoint)
FspApiFailed:
jmp $
align 10h
TempRamInitStack:
- DD OFFSET TempRamInitDone
- DD OFFSET FsptUpdDataPtr ; TempRamInitParams
-
-ProtectedModeEntryPoint ENDP
+ DD TempRamInitDone
+ DD ASM_PFX(FsptUpdDataPtr); TempRamInitParams
;
; ROM-based Global-Descriptor Table for the Tiano PEI Phase
;
align 16
-PUBLIC BootGdtTable
+global ASM_PFX(BootGdtTable)
;
; GDT[0]: 0x00: Null entry, never used.
;
NULL_SEL EQU $ - GDT_BASE ; Selector [0]
GDT_BASE:
-BootGdtTable DD 0
+ASM_PFX(BootGdtTable):
+ DD 0
DD 0
;
; Linear data segment descriptor
@@ -350,20 +345,17 @@ SPARE5_SEL EQU $ - GDT_BASE ; Selector [0x38]
DB 0 ; present, ring 0, data, expand-up, writable
DB 0 ; page-granular, 32-bit
DB 0
-GDT_SIZE EQU $ - BootGdtTable ; Size, in bytes
+GDT_SIZE EQU $ - GDT_BASE ; Size, in bytes
;
; GDT Descriptor
;
GdtDesc: ; GDT descriptor
DW GDT_SIZE - 1 ; GDT limit
- DD OFFSET BootGdtTable ; GDT base address
+ DD GDT_BASE ; GDT base address
-ProtectedModeEntryLinearAddress LABEL FWORD
-ProtectedModeEntryLinearOffset LABEL DWORD
- DD OFFSET ProtectedModeEntryPoint ; Offset of our 32 bit code
+ProtectedModeEntryLinearAddress:
+ProtectedModeEntryLinear:
+ DD ProtectedModeEntryPoint ; Offset of our 32 bit code
DW LINEAR_CODE_SEL
-
-_TEXT_PROTECTED_MODE ENDS
-END
diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Stack.S b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Stack.S
deleted file mode 100644
index 9953daa..0000000
--- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Stack.S
+++ /dev/null
@@ -1,67 +0,0 @@
-## @file
-# Switch the stack from temporary memory to permenent memory.
-#
-# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
-# SPDX-License-Identifier: BSD-2-Clause-Patent
-#
-##
-
-#------------------------------------------------------------------------------
-# VOID
-# EFIAPI
-# SecSwitchStack (
-# UINT32 TemporaryMemoryBase,
-# UINT32 PermanentMemoryBase
-# )
-#------------------------------------------------------------------------------
-ASM_GLOBAL ASM_PFX (SecSwitchStack)
-ASM_PFX(SecSwitchStack):
- #
- # Save standard registers so they can be used to change stack
- #
- pushl %eax
- pushl %ebx
- pushl %ecx
- pushl %edx
-
- #
- # !!CAUTION!! this function address's is pushed into stack after
- # migration of whole temporary memory, so need save it to permanent
- # memory at first!
- #
- movl 20(%esp), %ebx # Save the first parameter
- movl 24(%esp), %ecx # Save the second parameter
-
- #
- # Save this function's return address into permanent memory at first.
- # Then, Fixup the esp point to permanent memory
- #
- movl %esp, %eax
- subl %ebx, %eax
- addl %ecx, %eax
- movl 0(%esp), %edx # copy pushed register's value to permanent memory
- movl %edx, 0(%eax)
- movl 4(%esp), %edx
- movl %edx, 4(%eax)
- movl 8(%esp), %edx
- movl %edx, 8(%eax)
- movl 12(%esp), %edx
- movl %edx, 12(%eax)
- movl 16(%esp), %edx # Update this function's return address into permanent memory
- movl %edx, 16(%eax)
- movl %eax, %esp # From now, esp is pointed to permanent memory
-
- #
- # Fixup the ebp point to permanent memory
- #
- movl %ebp, %eax
- subl %ebx, %eax
- addl %ecx, %eax
- movl %eax, %ebp # From now, ebp is pointed to permanent memory
-
- popl %edx
- popl %ecx
- popl %ebx
- popl %eax
- ret
-
diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Stack.asm b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Stack.nasm
similarity index 59%
rename from Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Stack.asm
rename to Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Stack.nasm
index 1830240..47db32d 100644
--- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Stack.asm
+++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Stack.nasm
@@ -1,14 +1,14 @@
-;; @file
-; Switch the stack from temporary memory to permenent memory.
+;------------------------------------------------------------------------------
;
-; Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
+; Abstract:
+;
+; Switch the stack from temporary memory to permanent memory.
;
-;;
+;------------------------------------------------------------------------------
- .586p
- .model flat,C
- .code
+ SECTION .text
;------------------------------------------------------------------------------
; VOID
@@ -18,7 +18,8 @@
; UINT32 PermanentMemoryBase
; );
;------------------------------------------------------------------------------
-SecSwitchStack PROC
+global ASM_PFX(SecSwitchStack)
+ASM_PFX(SecSwitchStack):
;
; Save three register: eax, ebx, ecx
;
@@ -43,16 +44,16 @@ SecSwitchStack PROC
mov eax, esp
sub eax, ebx
add eax, ecx
- mov edx, dword ptr [esp] ; copy pushed register's value to permanent memory
- mov dword ptr [eax], edx
- mov edx, dword ptr [esp + 4]
- mov dword ptr [eax + 4], edx
- mov edx, dword ptr [esp + 8]
- mov dword ptr [eax + 8], edx
- mov edx, dword ptr [esp + 12]
- mov dword ptr [eax + 12], edx
- mov edx, dword ptr [esp + 16] ; Update this function's return address into permanent memory
- mov dword ptr [eax + 16], edx
+ mov edx, dword [esp] ; copy pushed register's value to permanent memory
+ mov dword [eax], edx
+ mov edx, dword [esp + 4]
+ mov dword [eax + 4], edx
+ mov edx, dword [esp + 8]
+ mov dword [eax + 8], edx
+ mov edx, dword [esp + 12]
+ mov dword [eax + 12], edx
+ mov edx, dword [esp + 16] ; Update this function's return address into permanent memory
+ mov dword [eax + 16], edx
mov esp, eax ; From now, esp is pointed to permanent memory
;
@@ -68,6 +69,4 @@ SecSwitchStack PROC
pop ebx
pop eax
ret
-SecSwitchStack ENDP
- END
diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
index 6f2c95a..5d77e9e 100644
--- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
+++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
@@ -1,10 +1,11 @@
## @file
# Provide FSP wrapper platform sec related function.
#
-# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
+#
##
################################################################################
@@ -42,13 +43,10 @@
PlatformInit.c
[Sources.IA32]
- Ia32/SecEntry.asm
- Ia32/PeiCoreEntry.asm
- Ia32/Stack.asm
+ Ia32/SecEntry.nasm
+ Ia32/PeiCoreEntry.nasm
+ Ia32/Stack.nasm
Ia32/Fsp.h
- Ia32/SecEntry.S
- Ia32/PeiCoreEntry.S
- Ia32/Stack.S
################################################################################
#
diff --git a/Platform/Intel/MinPlatformPkg/Include/Fdf/RuleInclude.fdf b/Platform/Intel/MinPlatformPkg/Include/Fdf/RuleInclude.fdf
index c4c4315..a1a8964 100644
--- a/Platform/Intel/MinPlatformPkg/Include/Fdf/RuleInclude.fdf
+++ b/Platform/Intel/MinPlatformPkg/Include/Fdf/RuleInclude.fdf
@@ -1,7 +1,7 @@
## @file
# FDF file of Platform.
#
-# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -25,7 +25,7 @@
[Rule.Common.PEI_CORE]
FILE PEI_CORE = $(NAMED_GUID) {
- PE32 PE32 Align = 32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ PE32 PE32 Align = 64 $(INF_OUTPUT)/$(MODULE_NAME).efi
UI STRING="$(MODULE_NAME)" Optional
VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
}
@@ -40,7 +40,7 @@
[Rule.Common.PEIM]
FILE PEIM = $(NAMED_GUID) {
PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
- PE32 PE32 Align = 32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ PE32 PE32 Align = 64 $(INF_OUTPUT)/$(MODULE_NAME).efi
UI STRING="$(MODULE_NAME)" Optional
VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
}
diff --git a/Platform/Intel/MinPlatformPkg/Tools/Fsp/RebaseAndPatchFspBinBaseAddress.py b/Platform/Intel/MinPlatformPkg/Tools/Fsp/RebaseAndPatchFspBinBaseAddress.py
index 496b977..167a0e0 100644
--- a/Platform/Intel/MinPlatformPkg/Tools/Fsp/RebaseAndPatchFspBinBaseAddress.py
+++ b/Platform/Intel/MinPlatformPkg/Tools/Fsp/RebaseAndPatchFspBinBaseAddress.py
@@ -76,7 +76,7 @@ file.close()
pythontool = 'python'
if 'PYTHON_HOME' in os.environ:
pythontool = os.environ['PYTHON_HOME'] + os.sep + 'python'
-Process = subprocess.Popen(pythontool + " " + splitFspBinPath + " info -f" + fspBinFilePath, stdout=subprocess.PIPE)
+Process = subprocess.Popen([pythontool, splitFspBinPath, "info","-f",fspBinFilePath], stdout=subprocess.PIPE)
Output = Process.communicate()[0]
FsptInfo = Output.rsplit("FSP_M", 1);
for line in FsptInfo[1].split("\n"):
diff --git a/Platform/Intel/MinPlatformPkg/Tools/PatchFv/PatchBinFv.py b/Platform/Intel/MinPlatformPkg/Tools/PatchFv/PatchBinFv.py
index 5b49b6b..b98c951 100644
--- a/Platform/Intel/MinPlatformPkg/Tools/PatchFv/PatchBinFv.py
+++ b/Platform/Intel/MinPlatformPkg/Tools/PatchFv/PatchBinFv.py
@@ -1,6 +1,6 @@
## @ PatchBinFv.py
#
-# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
@@ -107,7 +107,7 @@ class FileChecker:
return
def ProcessFvInf(self, fvName):
- sourceFileName = os.path.join(self.sourceRoot,fvName+"\\"+self.target+"\\"+fvName+".inf")
+ sourceFileName = os.path.join(self.sourceRoot,fvName,self.target,fvName+".inf")
print "\nprocessing - " + sourceFileName
fileGuid = self.GetInfFileGuid (sourceFileName)
print "FV NAME GUID - " + fileGuid
@@ -137,7 +137,7 @@ class FileChecker:
self.PrintPcdList(self.InfPcdList)
def PatchFv(self, fvName):
- sourceFileName = os.path.join(self.sourceRoot,fvName+"\\"+self.target+"\\"+fvName+".fv")
+ sourceFileName = os.path.join(self.sourceRoot,fvName,self.target,fvName+".Fv")
print "patching - " + sourceFileName
try :
@@ -161,7 +161,7 @@ class FileChecker:
print " [" + hex(offset) + "] " + binascii.hexlify(data[offset:offset+2]) + " <= " + binascii.hexlify(h)
data[offset:offset+2] = h
elif (cmp (pcd[4], "UINT32") == 0):
- l = struct.pack("L", int(pcd[3],16))
+ l = struct.pack("I", int(pcd[3],16))
print " [" + hex(offset) + "] " + binascii.hexlify(data[offset:offset+4]) + " <= " + binascii.hexlify(l)
data[offset:offset+4] = l
elif (cmp (pcd[4], "UINT64") == 0):
diff --git a/Platform/Intel/MinPlatformPkg/Tools/PatchFv/RebaseBinFv.py b/Platform/Intel/MinPlatformPkg/Tools/PatchFv/RebaseBinFv.py
index 321f7c5..149630e 100644
--- a/Platform/Intel/MinPlatformPkg/Tools/PatchFv/RebaseBinFv.py
+++ b/Platform/Intel/MinPlatformPkg/Tools/PatchFv/RebaseBinFv.py
@@ -1,9 +1,8 @@
## @ PatchBinFv.py
#
-# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
-##
import os
import re
@@ -541,7 +540,7 @@ class FileChecker:
print "PCD: " + pcd[0] + "|" + pcd[3] + " <== " + pcd[1] + "(" + pcd[2] + ")"
def RebaseFv(self, fvName, rebasePcd):
- sourceFileName = os.path.join(self.sourceRoot,fvName+"\\"+self.target+"\\"+fvName+".fv")
+ sourceFileName = os.path.join(self.sourceRoot,fvName,self.target,fvName+".Fv")
print "rebasing(FV) - " + sourceFileName
try :
@@ -617,7 +616,7 @@ class FileChecker:
if not line:
break
- newline = line[:-1]
+ newline = line[:-1].replace('\r','')
if (cmp (newline, TargetPkg) == 0):
FoundPkg = True
@@ -645,7 +644,7 @@ class FileChecker:
def GetOldFvBase (self, fvName, PcdName):
ParseBase = False
Value = ""
- fileName = os.path.join(self.sourceRoot,fvName+"\\"+self.target+"\\"+fvName+".inf")
+ fileName = os.path.join(self.sourceRoot,fvName,self.target,fvName+".inf")
try :
file = open(fileName)
except Exception:
@@ -657,7 +656,7 @@ class FileChecker:
if not line:
break
- newline = line[:-1]
+ newline = line[:-1].replace('\r','')
if cmp (newline, "") == 0:
continue
@@ -681,7 +680,7 @@ class FileChecker:
return Value
def SetNewFvBase (self, fvName, PcdName, OldFvBase, NewFvBase):
- fileName = os.path.join(self.sourceRoot,fvName+"\\"+self.target+"\\"+fvName+".inf")
+ fileName = os.path.join(self.sourceRoot,fvName,self.target,fvName+".inf")
print "update - " + fileName
try :
file = open(fileName, "r")
@@ -698,7 +697,7 @@ class FileChecker:
if not line:
break
- newline = line[:-1]
+ newline = line[:-1].strip()
if cmp (newline, "") == 0:
continue
diff --git a/Platform/Intel/build_bios.py b/Platform/Intel/build_bios.py
index a4ea093..9effefc 100644
--- a/Platform/Intel/build_bios.py
+++ b/Platform/Intel/build_bios.py
@@ -135,12 +135,16 @@ def pre_build(build_config, build_type="DEBUG", silent=False, toolchain=None):
# get the python path
if os.environ.get("PYTHON_HOME") is None:
- config["PYTHON_HOME"] = None
if os.environ.get("PYTHONPATH") is not None:
config["PYTHON_HOME"] = os.environ.get("PYTHONPATH")
else:
- print("PYTHONPATH environment variable is not found")
- sys.exit(1)
+ config["PYTHON_HOME"] = os.path.dirname(sys.executable)
+ config["PYTHONPATH"] = config["PYTHON_HOME"]
+
+ if config.get("PYTHON_HOME") is None or \
+ not os.path.exists(config.get("PYTHON_HOME")):
+ print("PYTHON_HOME environment variable is not found")
+ sys.exit(1)
# if python is installed, disable the binary base tools.
# python is installed if this code is running :)
@@ -151,18 +155,18 @@ def pre_build(build_config, build_type="DEBUG", silent=False, toolchain=None):
# Run edk setup and update config
if os.name == 'nt':
edk2_setup_cmd = [os.path.join(config["EFI_SOURCE"], "edksetup"),
- "Rebuild"]
+ "Rebuild"]
if config.get("EDK_SETUP_OPTION") and \
- config["EDK_SETUP_OPTION"] != " ":
+ config["EDK_SETUP_OPTION"] != " ":
edk2_setup_cmd.append(config["EDK_SETUP_OPTION"])
_, _, result, return_code = execute_script(edk2_setup_cmd,
- config,
- collect_env=True,
- shell=True)
+ config,
+ collect_env=True,
+ shell=True)
if return_code == 0 and result is not None and isinstance(result,
- dict):
+ dict):
config.update(result)
# nmake BaseTools source
@@ -355,7 +359,11 @@ def build(config):
command.append("-D")
command.append("MAX_SOCKET=" + config["MAX_SOCKET"])
- _, _, _, exit_code = execute_script(command, config)
+ shell = True
+ if os.name == "posix":
+ shell = False
+
+ _, _, _, exit_code = execute_script(command, config, shell=shell)
if exit_code != 0:
build_failed(config)
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [edk2-platforms] [PATCH v2 2/5] KabylakeSiliconPkg: Casting functions to EFIAPI
2019-05-21 3:08 [edk2-platforms] [PATCH v2 0/5] Added GCC5 build support Agyeman, Prince
2019-05-21 3:08 ` [edk2-platforms] [PATCH v2 1/5] MinPlatformPkg: " Agyeman, Prince
@ 2019-05-21 3:08 ` Agyeman, Prince
2019-05-22 19:08 ` [edk2-devel] " Kubacki, Michael A
` (2 more replies)
2019-05-21 3:08 ` [edk2-platforms] [PATCH v2 3/5] KabylakeOpenBoardPkg: Added GCC5 build support Agyeman, Prince
` (2 subsequent siblings)
4 siblings, 3 replies; 18+ messages in thread
From: Agyeman, Prince @ 2019-05-21 3:08 UTC (permalink / raw)
To: devel
Cc: chasel.chiu, Prince Agyeman, Michael Kubacki, Michael D Kinney,
Nate DeSimone, Liming Gao, Ankit Sinha
From: Prince Agyeman <prince.agyeman@intel.com>
This fixes the calling convension issues in gcc
Gcc build was tested on Ubuntu 16.04.5 LTS
with gcc version 5.4.0, nasm version 2.11.08
Cc: Michael Kubacki <michael.a.kubacki@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Ankit Sinha <ankit.sinha@intel.com>
Signed-off-by: Prince Agyeman <prince.agyeman@intel.com>
---
Silicon/Intel/KabylakeSiliconPkg/Pch/PchInit/Smm/PchInitSmm.h | 3 ++-
Silicon/Intel/KabylakeSiliconPkg/Pch/PchInit/Smm/PchPcieSmm.c | 3 ++-
Silicon/Intel/KabylakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmm.h | 4 +++-
.../Intel/KabylakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmmCore.c | 4 +++-
4 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/PchInit/Smm/PchInitSmm.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/PchInit/Smm/PchInitSmm.h
index 44f151c..666340e 100644
--- a/Silicon/Intel/KabylakeSiliconPkg/Pch/PchInit/Smm/PchInitSmm.h
+++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/PchInit/Smm/PchInitSmm.h
@@ -1,7 +1,7 @@
/** @file
Header file for PCH Init SMM Handler
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -205,6 +205,7 @@ PchPcieLinkEqHandlerFunction (
**/
VOID
+EFIAPI
PchPcieIoTrapSmiCallback (
IN EFI_HANDLE DispatchHandle,
IN EFI_SMM_IO_TRAP_CONTEXT *CallbackContext,
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/PchInit/Smm/PchPcieSmm.c b/Silicon/Intel/KabylakeSiliconPkg/Pch/PchInit/Smm/PchPcieSmm.c
index aed33bb..847fbfb 100644
--- a/Silicon/Intel/KabylakeSiliconPkg/Pch/PchInit/Smm/PchPcieSmm.c
+++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/PchInit/Smm/PchPcieSmm.c
@@ -1,7 +1,7 @@
/** @file
PCH Pcie SMM Driver Entry
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -238,6 +238,7 @@ PchPciePmIoTrapSmiCallback (
**/
VOID
+EFIAPI
PchPcieIoTrapSmiCallback (
IN EFI_HANDLE DispatchHandle,
IN EFI_SMM_IO_TRAP_CONTEXT *CallbackContext,
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmm.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmm.h
index 508832e..a9f0664 100644
--- a/Silicon/Intel/KabylakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmm.h
+++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmm.h
@@ -1,7 +1,7 @@
/** @file
Prototypes and defines for the PCH SMM Dispatcher.
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -510,6 +510,7 @@ typedef struct {
registered and the SMI source has been enabled.
**/
EFI_STATUS
+EFIAPI
PchSmmCoreRegister (
IN PCH_SMM_GENERIC_PROTOCOL *This,
IN EFI_SMM_HANDLER_ENTRY_POINT2 DispatchFunction,
@@ -530,6 +531,7 @@ PchSmmCoreRegister (
@retval EFI_INVALID_PARAMETER Handle is invalid.
**/
EFI_STATUS
+EFIAPI
PchSmmCoreUnRegister (
IN PCH_SMM_GENERIC_PROTOCOL *This,
IN EFI_HANDLE *DispatchHandle
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmmCore.c b/Silicon/Intel/KabylakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmmCore.c
index 0c494bf..cb3bfba 100644
--- a/Silicon/Intel/KabylakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmmCore.c
+++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmmCore.c
@@ -2,7 +2,7 @@
This driver is responsible for the registration of child drivers
and the abstraction of the PCH SMI sources.
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -325,6 +325,7 @@ SmiInputValueDuplicateCheck (
registered and the SMI source has been enabled.
**/
EFI_STATUS
+EFIAPI
PchSmmCoreRegister (
IN PCH_SMM_GENERIC_PROTOCOL *This,
IN EFI_SMM_HANDLER_ENTRY_POINT2 DispatchFunction,
@@ -596,6 +597,7 @@ Error:
@retval EFI_INVALID_PARAMETER Handle is invalid.
**/
EFI_STATUS
+EFIAPI
PchSmmCoreUnRegister (
IN PCH_SMM_GENERIC_PROTOCOL *This,
IN EFI_HANDLE *DispatchHandle
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [edk2-platforms] [PATCH v2 3/5] KabylakeOpenBoardPkg: Added GCC5 build support
2019-05-21 3:08 [edk2-platforms] [PATCH v2 0/5] Added GCC5 build support Agyeman, Prince
2019-05-21 3:08 ` [edk2-platforms] [PATCH v2 1/5] MinPlatformPkg: " Agyeman, Prince
2019-05-21 3:08 ` [edk2-platforms] [PATCH v2 2/5] KabylakeSiliconPkg: Casting functions to EFIAPI Agyeman, Prince
@ 2019-05-21 3:08 ` Agyeman, Prince
2019-05-22 19:11 ` [edk2-devel] " Nate DeSimone
2019-05-23 0:19 ` Chiu, Chasel
2019-05-21 3:08 ` [edk2-platforms] [PATCH v2 4/5] ClevoOpenBoardPkg: " Agyeman, Prince
2019-05-21 3:08 ` [edk2-platforms] [PATCH v2 5/5] Intel/Readme.md: Updated readme with linux build instructions Agyeman, Prince
4 siblings, 2 replies; 18+ messages in thread
From: Agyeman, Prince @ 2019-05-21 3:08 UTC (permalink / raw)
To: devel; +Cc: chasel.chiu, Prince Agyeman
From: Prince Agyeman <prince.agyeman@intel.com>
Fixed:
* Include file paths in dec
* Gcc build options
Gcc build was tested on Ubuntu 16.04.5 LTS
with gcc version 5.4.0, nasm version 2.11.08
Signed-off-by: Prince Agyeman <prince.agyeman@intel.com>
---
.../KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgBuildOption.dsc | 4 +++-
Platform/Intel/KabylakeOpenBoardPkg/OpenBoardPkg.dec | 6 +++---
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgBuildOption.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgBuildOption.dsc
index 04c5786..8e885cc 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgBuildOption.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgBuildOption.dsc
@@ -1,7 +1,7 @@
## @file
# platform build option configuration file.
#
-# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -102,6 +102,7 @@ DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(
# For IA32 Specific Build Flag
#
GCC: *_*_IA32_PP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+GCC: *_*_IA32_CC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015 -DASF_PEI -Wno-unused -Wl,--allow-multiple-definition
MSFT: *_*_IA32_ASM_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
MSFT: *_*_IA32_CC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015 -DASF_PEI
MSFT: *_*_IA32_VFRPP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
@@ -124,6 +125,7 @@ MSFT: *_*_IA32_ASLCC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_D
# For X64 Specific Build Flag
#
GCC: *_*_X64_PP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+GCC: *_*_X64_CC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015 -Wno-unused -Wl,--allow-multiple-definition
MSFT: *_*_X64_ASM_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
MSFT: *_*_X64_CC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015
MSFT: *_*_X64_VFRPP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/OpenBoardPkg.dec b/Platform/Intel/KabylakeOpenBoardPkg/OpenBoardPkg.dec
index e326598..68977d0 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/OpenBoardPkg.dec
+++ b/Platform/Intel/KabylakeOpenBoardPkg/OpenBoardPkg.dec
@@ -5,7 +5,7 @@
# INF files to generate AutoGen.c and AutoGen.h files
# for the build infrastructure.
#
-# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -20,8 +20,8 @@ PACKAGE_GUID = 0A8BA6E8-C8AC-4AC1-87AC-52772FA6AE5E
[Includes]
Include
-KabylakeRvp3\Include
-Features\Tbt\Include
+KabylakeRvp3/Include
+Features/Tbt/Include
[Guids]
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [edk2-platforms] [PATCH v2 4/5] ClevoOpenBoardPkg: Added GCC5 build support
2019-05-21 3:08 [edk2-platforms] [PATCH v2 0/5] Added GCC5 build support Agyeman, Prince
` (2 preceding siblings ...)
2019-05-21 3:08 ` [edk2-platforms] [PATCH v2 3/5] KabylakeOpenBoardPkg: Added GCC5 build support Agyeman, Prince
@ 2019-05-21 3:08 ` Agyeman, Prince
2019-05-22 19:11 ` [edk2-devel] " Nate DeSimone
2019-05-21 3:08 ` [edk2-platforms] [PATCH v2 5/5] Intel/Readme.md: Updated readme with linux build instructions Agyeman, Prince
4 siblings, 1 reply; 18+ messages in thread
From: Agyeman, Prince @ 2019-05-21 3:08 UTC (permalink / raw)
To: devel; +Cc: chasel.chiu, Prince Agyeman
From: Prince Agyeman <prince.agyeman@intel.com>
Fixes:
* include file paths
* gcc build options
Gcc build was tested on Ubuntu 16.04.5 LTS
with gcc version 5.4.0, nasm version 2.11.08
Signed-off-by: Prince Agyeman <prince.agyeman@intel.com>
---
Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgBuildOption.dsc | 2 ++
Platform/Intel/ClevoOpenBoardPkg/OpenBoardPkg.dec | 4 ++--
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgBuildOption.dsc b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgBuildOption.dsc
index 2cfcfdf..31e7f41 100644
--- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgBuildOption.dsc
+++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgBuildOption.dsc
@@ -102,6 +102,7 @@ DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(
# For IA32 Specific Build Flag
#
GCC: *_*_IA32_PP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+GCC: *_*_IA32_CC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015 -Wno-unused -Wl,--allow-multiple-definition
MSFT: *_*_IA32_ASM_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
MSFT: *_*_IA32_CC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015 -DASF_PEI
MSFT: *_*_IA32_VFRPP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
@@ -124,6 +125,7 @@ MSFT: *_*_IA32_ASLCC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_D
# For X64 Specific Build Flag
#
GCC: *_*_X64_PP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+GCC: *_*_X64_CC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015 -Wno-unused -Wl,--allow-multiple-definition
MSFT: *_*_X64_ASM_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
MSFT: *_*_X64_CC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015
MSFT: *_*_X64_VFRPP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
diff --git a/Platform/Intel/ClevoOpenBoardPkg/OpenBoardPkg.dec b/Platform/Intel/ClevoOpenBoardPkg/OpenBoardPkg.dec
index 29816e3..28aedfe 100644
--- a/Platform/Intel/ClevoOpenBoardPkg/OpenBoardPkg.dec
+++ b/Platform/Intel/ClevoOpenBoardPkg/OpenBoardPkg.dec
@@ -18,8 +18,8 @@ PACKAGE_GUID = D04CCA80-5F71-478D-9A26-72BC751D0106
[Includes]
Include
-N1xxWU\Include
-Features\Tbt\Include
+N1xxWU/Include
+Features/Tbt/Include
[Guids]
gBoardModuleTokenSpaceGuid = {0x72d1fff7, 0xa42a, 0x4219, {0xb9, 0x95, 0x5a, 0x67, 0x53, 0x6e, 0xa4, 0x2a}}
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [edk2-platforms] [PATCH v2 5/5] Intel/Readme.md: Updated readme with linux build instructions
2019-05-21 3:08 [edk2-platforms] [PATCH v2 0/5] Added GCC5 build support Agyeman, Prince
` (3 preceding siblings ...)
2019-05-21 3:08 ` [edk2-platforms] [PATCH v2 4/5] ClevoOpenBoardPkg: " Agyeman, Prince
@ 2019-05-21 3:08 ` Agyeman, Prince
2019-05-21 3:20 ` Chiu, Chasel
` (2 more replies)
4 siblings, 3 replies; 18+ messages in thread
From: Agyeman, Prince @ 2019-05-21 3:08 UTC (permalink / raw)
To: devel; +Cc: chasel.chiu, Prince Agyeman
From: Prince Agyeman <prince.agyeman@intel.com>
Signed-off-by: Prince Agyeman <prince.agyeman@intel.com>
---
Platform/Intel/Readme.md | 42 ++++++++++++++++++++++++------------------
1 file changed, 24 insertions(+), 18 deletions(-)
diff --git a/Platform/Intel/Readme.md b/Platform/Intel/Readme.md
index 1da5d0a..443fb40 100644
--- a/Platform/Intel/Readme.md
+++ b/Platform/Intel/Readme.md
@@ -107,9 +107,13 @@ return back to the minimum platform caller.
**Building with the python script**
-1. Open command window, go to the workspace directory, e.g. c:\Kabylake.
-2. Type "cd edk2-platforms\Platform\Intel
-3. Type "python build_bios.py -p REPLACE_WITH_BOARD_NAME"
+1. Open command window, go to the workspace directory, e.g. c:\Kabylake or ~/Kabylake in the case of a linux OS
+2. If using a linux OS
+ * Type "cd edk2"
+ * Type "source edksetup.sh"
+ * Type "cd ../" to go back to the workspace directory
+3. Type "cd edk2-platforms/Platform/Intel
+4. Type "python build_bios.py -p REPLACE_WITH_BOARD_NAME"
* build_bios.py arguments:
@@ -132,18 +136,19 @@ return back to the minimum platform caller.
| |
* For more information on build options
- * ``Type "python build_bios.py -h"``
+ * Type "python build_bios.py -h"
* Note
- * ``Python 2.7.16 and Python 3.7.3 compatible``
- * ``These python build scripts have been tested on Windows due to`` [cross-platform limitations](#Known-limitations)
+ * Python 2.7.16 and Python 3.7.3 compatible
+ * This python build script has been tested on Windows 10 and Ubuntu 16.04.5 LTS
+ * See [cross-platform limitations](#Known-limitations)
* Configuration Files
- * ``The edk2-platforms\Platform\Intel\build.cfg file contains the default settings used by build_bios.py``
- * ``The default settings are under the DEFAULT_CONFIG section``
- * ``Each board can have a settings file that will override the edk2-platforms\Platform\Intel\build.cfg settings``
- * ``An example of a board specific settings:``
- * ``edk2-platforms\Platform\Intel\KabylakeOpenBoardPkg\KabylakeRvp3\build_config.cfg``
+ * The edk2-platforms\Platform\Intel\build.cfg file contains the default settings used by build_bios.py
+ * The default settings are under the DEFAULT_CONFIG section
+ * Each board can have a settings file that will override the edk2-platforms\Platform\Intel\build.cfg settings
+ * An example of a board specific settings:
+ * edk2-platforms\Platform\Intel\KabylakeOpenBoardPkg\KabylakeRvp3\build_config.cfg
* Workspace view of the build scripts
* <pre>
@@ -212,14 +217,13 @@ Users can also flash the UEFI firmware image to the highest area of the flash re
### **Known limitations**
-* All firmware projects can only build on Windows with the validated configuration below.
- * Cross-platform build support is work-in-progress.
-
**KabylakeOpenBoardPkg**
1. This firmware project has only been tested on the Intel KabylakeRvp3 board.
2. This firmware project has only been tested booting to Microsoft Windows 10 x64 with AHCI mode and Integrated Graphic
Device.
-3. This firmware project build has only been tested using the Microsoft Visual Studio 2015 compiler.
+3. The Windows build was tested on Windows 10 with Microsoft Visual Studio 2015.
+4. The Linux build was tested on Ubuntu 16.04.5 LTS with GCC version 5.4.0.
+5. The build was tested with NASM version 2.11.08.
**PurleyOpenBoardPkg**
1. This firmware project has only been tested on the Microsoft MtOlympus board.
@@ -228,9 +232,11 @@ Users can also flash the UEFI firmware image to the highest area of the flash re
**ClevoOpenBoardPkg**
1. Currently, support is only being added for the N1xxWU series of boards.
-2. The firmware project build has only been tested using the Microsoft Visual Studio 2015 compiler.
-3. The firmware project has not been tested on an actual board, it *should not* be expected to boot.
-4. The firmware project applies to all Clevo supported board configurations but is only being tested on System 76 Galago
+2. The Windows build was tested on Windows 10 with Microsoft Visual Studio 2015 compiler.
+3. The Linux build was tested on Ubuntu 16.04.5 LTS with GCC version 5.4.0.
+4. The build was tested with NASM version 2.11.08.
+5. The firmware project has not been tested on an actual board, it *should not* be expected to boot.
+6. The firmware project applies to all Clevo supported board configurations but is only being tested on System 76 Galago
Pro devices.
### **Planned Activities**
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [edk2-platforms] [PATCH v2 5/5] Intel/Readme.md: Updated readme with linux build instructions
2019-05-21 3:08 ` [edk2-platforms] [PATCH v2 5/5] Intel/Readme.md: Updated readme with linux build instructions Agyeman, Prince
@ 2019-05-21 3:20 ` Chiu, Chasel
2019-05-22 19:06 ` [edk2-devel] " Kubacki, Michael A
2019-05-22 19:12 ` Nate DeSimone
2 siblings, 0 replies; 18+ messages in thread
From: Chiu, Chasel @ 2019-05-21 3:20 UTC (permalink / raw)
To: Agyeman, Prince, devel@edk2.groups.io
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
> -----Original Message-----
> From: Agyeman, Prince
> Sent: Tuesday, May 21, 2019 11:08 AM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel <chasel.chiu@intel.com>; Agyeman, Prince
> <prince.agyeman@intel.com>
> Subject: [edk2-platforms] [PATCH v2 5/5] Intel/Readme.md: Updated readme
> with linux build instructions
>
> From: Prince Agyeman <prince.agyeman@intel.com>
>
> Signed-off-by: Prince Agyeman <prince.agyeman@intel.com>
> ---
> Platform/Intel/Readme.md | 42 ++++++++++++++++++++++++------------------
> 1 file changed, 24 insertions(+), 18 deletions(-)
>
> diff --git a/Platform/Intel/Readme.md b/Platform/Intel/Readme.md index
> 1da5d0a..443fb40 100644
> --- a/Platform/Intel/Readme.md
> +++ b/Platform/Intel/Readme.md
> @@ -107,9 +107,13 @@ return back to the minimum platform caller.
>
> **Building with the python script**
>
> -1. Open command window, go to the workspace directory, e.g. c:\Kabylake.
> -2. Type "cd edk2-platforms\Platform\Intel -3. Type "python build_bios.py -p
> REPLACE_WITH_BOARD_NAME"
> +1. Open command window, go to the workspace directory, e.g. c:\Kabylake
> +or ~/Kabylake in the case of a linux OS 2. If using a linux OS
> + * Type "cd edk2"
> + * Type "source edksetup.sh"
> + * Type "cd ../" to go back to the workspace directory 3. Type "cd
> +edk2-platforms/Platform/Intel 4. Type "python build_bios.py -p
> +REPLACE_WITH_BOARD_NAME"
>
> * build_bios.py arguments:
>
> @@ -132,18 +136,19 @@ return back to the minimum platform caller.
> | |
>
> * For more information on build options
> - * ``Type "python build_bios.py -h"``
> + * Type "python build_bios.py -h"
>
> * Note
> - * ``Python 2.7.16 and Python 3.7.3 compatible``
> - * ``These python build scripts have been tested on Windows due to``
> [cross-platform limitations](#Known-limitations)
> + * Python 2.7.16 and Python 3.7.3 compatible
> + * This python build script has been tested on Windows 10 and Ubuntu
> + 16.04.5 LTS
> + * See [cross-platform limitations](#Known-limitations)
>
> * Configuration Files
> - * ``The edk2-platforms\Platform\Intel\build.cfg file contains the default
> settings used by build_bios.py``
> - * ``The default settings are under the DEFAULT_CONFIG section``
> - * ``Each board can have a settings file that will override the
> edk2-platforms\Platform\Intel\build.cfg settings``
> - * ``An example of a board specific settings:``
> - *
> ``edk2-platforms\Platform\Intel\KabylakeOpenBoardPkg\KabylakeRvp3\build_
> config.cfg``
> + * The edk2-platforms\Platform\Intel\build.cfg file contains the
> + default settings used by build_bios.py
> + * The default settings are under the DEFAULT_CONFIG section
> + * Each board can have a settings file that will override the
> + edk2-platforms\Platform\Intel\build.cfg settings
> + * An example of a board specific settings:
> + *
> +
> edk2-platforms\Platform\Intel\KabylakeOpenBoardPkg\KabylakeRvp3\build_
> + config.cfg
>
> * Workspace view of the build scripts
> * <pre>
> @@ -212,14 +217,13 @@ Users can also flash the UEFI firmware image to the
> highest area of the flash re
>
> ### **Known limitations**
>
> -* All firmware projects can only build on Windows with the validated
> configuration below.
> - * Cross-platform build support is work-in-progress.
> -
> **KabylakeOpenBoardPkg**
> 1. This firmware project has only been tested on the Intel KabylakeRvp3 board.
> 2. This firmware project has only been tested booting to Microsoft Windows 10
> x64 with AHCI mode and Integrated Graphic
> Device.
> -3. This firmware project build has only been tested using the Microsoft Visual
> Studio 2015 compiler.
> +3. The Windows build was tested on Windows 10 with Microsoft Visual Studio
> 2015.
> +4. The Linux build was tested on Ubuntu 16.04.5 LTS with GCC version 5.4.0.
> +5. The build was tested with NASM version 2.11.08.
>
> **PurleyOpenBoardPkg**
> 1. This firmware project has only been tested on the Microsoft MtOlympus
> board.
> @@ -228,9 +232,11 @@ Users can also flash the UEFI firmware image to the
> highest area of the flash re
>
> **ClevoOpenBoardPkg**
> 1. Currently, support is only being added for the N1xxWU series of boards.
> -2. The firmware project build has only been tested using the Microsoft Visual
> Studio 2015 compiler.
> -3. The firmware project has not been tested on an actual board, it *should not*
> be expected to boot.
> -4. The firmware project applies to all Clevo supported board configurations but
> is only being tested on System 76 Galago
> +2. The Windows build was tested on Windows 10 with Microsoft Visual Studio
> 2015 compiler.
> +3. The Linux build was tested on Ubuntu 16.04.5 LTS with GCC version 5.4.0.
> +4. The build was tested with NASM version 2.11.08.
> +5. The firmware project has not been tested on an actual board, it *should not*
> be expected to boot.
> +6. The firmware project applies to all Clevo supported board
> +configurations but is only being tested on System 76 Galago
> Pro devices.
>
> ### **Planned Activities**
> --
> 2.7.4
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [edk2-devel] [edk2-platforms] [PATCH v2 5/5] Intel/Readme.md: Updated readme with linux build instructions
2019-05-21 3:08 ` [edk2-platforms] [PATCH v2 5/5] Intel/Readme.md: Updated readme with linux build instructions Agyeman, Prince
2019-05-21 3:20 ` Chiu, Chasel
@ 2019-05-22 19:06 ` Kubacki, Michael A
2019-05-22 19:12 ` Nate DeSimone
2 siblings, 0 replies; 18+ messages in thread
From: Kubacki, Michael A @ 2019-05-22 19:06 UTC (permalink / raw)
To: devel@edk2.groups.io, Agyeman, Prince; +Cc: Chiu, Chasel
Reviewed-by: Michael Kubacki <michael.a.kubacki@intel.com>
> -----Original Message-----
> From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> Agyeman, Prince
> Sent: Monday, May 20, 2019 8:08 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel <chasel.chiu@intel.com>; Agyeman, Prince
> <prince.agyeman@intel.com>
> Subject: [edk2-devel] [edk2-platforms] [PATCH v2 5/5] Intel/Readme.md:
> Updated readme with linux build instructions
>
> From: Prince Agyeman <prince.agyeman@intel.com>
>
> Signed-off-by: Prince Agyeman <prince.agyeman@intel.com>
> ---
> Platform/Intel/Readme.md | 42 ++++++++++++++++++++++++------------------
> 1 file changed, 24 insertions(+), 18 deletions(-)
>
> diff --git a/Platform/Intel/Readme.md b/Platform/Intel/Readme.md index
> 1da5d0a..443fb40 100644
> --- a/Platform/Intel/Readme.md
> +++ b/Platform/Intel/Readme.md
> @@ -107,9 +107,13 @@ return back to the minimum platform caller.
>
> **Building with the python script**
>
> -1. Open command window, go to the workspace directory, e.g. c:\Kabylake.
> -2. Type "cd edk2-platforms\Platform\Intel -3. Type "python build_bios.py -p
> REPLACE_WITH_BOARD_NAME"
> +1. Open command window, go to the workspace directory, e.g. c:\Kabylake
> +or ~/Kabylake in the case of a linux OS 2. If using a linux OS
> + * Type "cd edk2"
> + * Type "source edksetup.sh"
> + * Type "cd ../" to go back to the workspace directory 3. Type "cd
> +edk2-platforms/Platform/Intel 4. Type "python build_bios.py -p
> +REPLACE_WITH_BOARD_NAME"
>
> * build_bios.py arguments:
>
> @@ -132,18 +136,19 @@ return back to the minimum platform caller.
> | |
>
> * For more information on build options
> - * ``Type "python build_bios.py -h"``
> + * Type "python build_bios.py -h"
>
> * Note
> - * ``Python 2.7.16 and Python 3.7.3 compatible``
> - * ``These python build scripts have been tested on Windows due to``
> [cross-platform limitations](#Known-limitations)
> + * Python 2.7.16 and Python 3.7.3 compatible
> + * This python build script has been tested on Windows 10 and Ubuntu
> + 16.04.5 LTS
> + * See [cross-platform limitations](#Known-limitations)
>
> * Configuration Files
> - * ``The edk2-platforms\Platform\Intel\build.cfg file contains the default
> settings used by build_bios.py``
> - * ``The default settings are under the DEFAULT_CONFIG section``
> - * ``Each board can have a settings file that will override the edk2-
> platforms\Platform\Intel\build.cfg settings``
> - * ``An example of a board specific settings:``
> - * ``edk2-
> platforms\Platform\Intel\KabylakeOpenBoardPkg\KabylakeRvp3\build_confi
> g.cfg``
> + * The edk2-platforms\Platform\Intel\build.cfg file contains the
> + default settings used by build_bios.py
> + * The default settings are under the DEFAULT_CONFIG section
> + * Each board can have a settings file that will override the
> + edk2-platforms\Platform\Intel\build.cfg settings
> + * An example of a board specific settings:
> + *
> + edk2-
> platforms\Platform\Intel\KabylakeOpenBoardPkg\KabylakeRvp3\build_
> + config.cfg
>
> * Workspace view of the build scripts
> * <pre>
> @@ -212,14 +217,13 @@ Users can also flash the UEFI firmware image to
> the highest area of the flash re
>
> ### **Known limitations**
>
> -* All firmware projects can only build on Windows with the validated
> configuration below.
> - * Cross-platform build support is work-in-progress.
> -
> **KabylakeOpenBoardPkg**
> 1. This firmware project has only been tested on the Intel KabylakeRvp3
> board.
> 2. This firmware project has only been tested booting to Microsoft Windows
> 10 x64 with AHCI mode and Integrated Graphic
> Device.
> -3. This firmware project build has only been tested using the Microsoft
> Visual Studio 2015 compiler.
> +3. The Windows build was tested on Windows 10 with Microsoft Visual
> Studio 2015.
> +4. The Linux build was tested on Ubuntu 16.04.5 LTS with GCC version 5.4.0.
> +5. The build was tested with NASM version 2.11.08.
>
> **PurleyOpenBoardPkg**
> 1. This firmware project has only been tested on the Microsoft MtOlympus
> board.
> @@ -228,9 +232,11 @@ Users can also flash the UEFI firmware image to the
> highest area of the flash re
>
> **ClevoOpenBoardPkg**
> 1. Currently, support is only being added for the N1xxWU series of boards.
> -2. The firmware project build has only been tested using the Microsoft
> Visual Studio 2015 compiler.
> -3. The firmware project has not been tested on an actual board, it *should
> not* be expected to boot.
> -4. The firmware project applies to all Clevo supported board configurations
> but is only being tested on System 76 Galago
> +2. The Windows build was tested on Windows 10 with Microsoft Visual
> Studio 2015 compiler.
> +3. The Linux build was tested on Ubuntu 16.04.5 LTS with GCC version 5.4.0.
> +4. The build was tested with NASM version 2.11.08.
> +5. The firmware project has not been tested on an actual board, it *should
> not* be expected to boot.
> +6. The firmware project applies to all Clevo supported board
> +configurations but is only being tested on System 76 Galago
> Pro devices.
>
> ### **Planned Activities**
> --
> 2.7.4
>
>
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [edk2-platforms] [PATCH v2 1/5] MinPlatformPkg: Added GCC5 build support
2019-05-21 3:08 ` [edk2-platforms] [PATCH v2 1/5] MinPlatformPkg: " Agyeman, Prince
@ 2019-05-22 19:08 ` Kubacki, Michael A
2019-05-22 19:11 ` Nate DeSimone
1 sibling, 0 replies; 18+ messages in thread
From: Kubacki, Michael A @ 2019-05-22 19:08 UTC (permalink / raw)
To: Agyeman, Prince, devel@edk2.groups.io
Cc: Chiu, Chasel, Kinney, Michael D, Desimone, Nathaniel L,
Gao, Liming, Sinha, Ankit
Reviewed-by: Michael Kubacki <michael.a.kubacki@intel.com>
> -----Original Message-----
> From: Agyeman, Prince
> Sent: Monday, May 20, 2019 8:08 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel <chasel.chiu@intel.com>; Agyeman, Prince
> <prince.agyeman@intel.com>; Kubacki, Michael A
> <michael.a.kubacki@intel.com>; Kinney, Michael D
> <michael.d.kinney@intel.com>; Desimone, Nathaniel L
> <nathaniel.l.desimone@intel.com>; Gao, Liming <liming.gao@intel.com>;
> Sinha, Ankit <ankit.sinha@intel.com>
> Subject: [edk2-platforms] [PATCH v2 1/5] MinPlatformPkg: Added GCC5 build
> support
>
> From: Prince Agyeman <prince.agyeman@intel.com>
>
> Fixes:
> * Replacing .asm and .S with nasm in SecFspWrapperPlatformSecLib for
> cross-platform build support
> * Modified RuleInclude.fdf
> * Modified python files to be OS independent
>
> Gcc build was tested on Ubuntu 16.04.5 LTS with gcc version 5.4.0, nasm
> version 2.11.08
>
> Cc: Michael Kubacki <michael.a.kubacki@intel.com>
> Cc: Michael D Kinney <michael.d.kinney@intel.com>
> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
> Cc: Liming Gao <liming.gao@intel.com>
> Cc: Ankit Sinha <ankit.sinha@intel.com>
>
> Signed-off-by: Prince Agyeman <prince.agyeman@intel.com>
> ---
> .../Ia32/PeiCoreEntry.S | 117 -------
> .../Ia32/{PeiCoreEntry.asm => PeiCoreEntry.nasm} | 46 +--
> .../SecFspWrapperPlatformSecLib/Ia32/SecEntry.S | 342 ---------------------
> .../Ia32/{SecEntry.asm => SecEntry.nasm} | 132 ++++----
> .../SecFspWrapperPlatformSecLib/Ia32/Stack.S | 67 ----
> .../Ia32/{Stack.asm => Stack.nasm} | 39 ++-
> .../SecFspWrapperPlatformSecLib.inf | 12 +-
> .../MinPlatformPkg/Include/Fdf/RuleInclude.fdf | 6 +-
> .../Tools/Fsp/RebaseAndPatchFspBinBaseAddress.py | 2 +-
> .../MinPlatformPkg/Tools/PatchFv/PatchBinFv.py | 8 +-
> .../MinPlatformPkg/Tools/PatchFv/RebaseBinFv.py | 15 +-
> Platform/Intel/build_bios.py | 28 +-
> 12 files changed, 143 insertions(+), 671 deletions(-) delete mode 100644
> Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/Ia32/PeiCoreEntry.S
> rename
> Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/Ia32/{PeiCoreEntry.asm => PeiCoreEntry.nasm} (66%) delete mode
> 100644
> Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/Ia32/SecEntry.S
> rename
> Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/Ia32/{SecEntry.asm => SecEntry.nasm} (72%) delete mode 100644
> Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/Ia32/Stack.S
> rename
> Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/Ia32/{Stack.asm => Stack.nasm} (59%)
>
> diff --git
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo
> rmSecLib/Ia32/PeiCoreEntry.S
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo
> rmSecLib/Ia32/PeiCoreEntry.S
> deleted file mode 100644
> index 8c8356f..0000000
> ---
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo
> rmSecLib/Ia32/PeiCoreEntry.S
> +++ /dev/null
> @@ -1,117 +0,0 @@
> -## @file
> -# Find and call SecStartup
> -#
> -# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> -# SPDX-
> License-Identifier: BSD-2-Clause-Patent -# -##
> -
> -ASM_GLOBAL ASM_PFX(CallPeiCoreEntryPoint)
> -ASM_PFX(CallPeiCoreEntryPoint):
> - #
> - # Obtain the hob list pointer
> - #
> - movl 0x4(%esp), %eax
> - #
> - # Obtain the stack information
> - # ECX: start of range
> - # EDX: end of range
> - #
> - movl 0x8(%esp), %ecx
> - movl 0xC(%esp), %edx
> -
> - #
> - # Platform init
> - #
> - pushal
> - pushl %edx
> - pushl %ecx
> - pushl %eax
> - call ASM_PFX(PlatformInit)
> - popl %eax
> - popl %eax
> - popl %eax
> - popal
> -
> - #
> - # Set stack top pointer
> - #
> - movl %edx, %esp
> -
> - #
> - # Push the hob list pointer
> - #
> - pushl %eax
> -
> - #
> - # Save the value
> - # ECX: start of range
> - # EDX: end of range
> - #
> - movl %esp, %ebp
> - pushl %ecx
> - pushl %edx
> -
> - #
> - # Push processor count to stack first, then BIST status (AP then BSP)
> - #
> - movl $1, %eax
> - cpuid
> - shr $16, %ebx
> - andl $0x000000FF, %ebx
> - cmp $1, %bl
> - jae PushProcessorCount
> -
> - #
> - # Some processors report 0 logical processors. Effectively 0 = 1.
> - # So we fix up the processor count
> - #
> - inc %ebx
> -
> -PushProcessorCount:
> - pushl %ebx
> -
> - #
> - # We need to implement a long-term solution for BIST capture. For now,
> we just copy BSP BIST
> - # for all processor threads
> - #
> - xorl %ecx, %ecx
> - movb %bl, %cl
> -PushBist:
> - movd %mm0, %eax
> - pushl %eax
> - loop PushBist
> -
> - # Save Time-Stamp Counter
> - movd %mm5, %eax
> - pushl %eax
> -
> - movd %mm6, %eax
> - pushl %eax
> -
> - #
> - # Pass entry point of the PEI core
> - #
> - movl $0xFFFFFFE0, %edi
> - pushl %ds:(%edi)
> -
> - #
> - # Pass BFV into the PEI Core
> - #
> - movl $0xFFFFFFFC, %edi
> - pushl %ds:(%edi)
> -
> - #
> - # Pass stack size into the PEI Core
> - #
> - movl -4(%ebp), %ecx
> - movl -8(%ebp), %edx
> - pushl %ecx # RamBase
> -
> - subl %ecx, %edx
> - pushl %edx # RamSize
> -
> - #
> - # Pass Control into the PEI Core
> - #
> - call ASM_PFX(SecStartup)
> diff --git
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo
> rmSecLib/Ia32/PeiCoreEntry.asm
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo
> rmSecLib/Ia32/PeiCoreEntry.nasm
> similarity index 66%
> rename from
> Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/Ia32/PeiCoreEntry.asm
> rename to
> Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/Ia32/PeiCoreEntry.nasm
> index c854067..5c5b788 100644
> ---
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo
> rmSecLib/Ia32/PeiCoreEntry.asm
> +++
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat
> +++ formSecLib/Ia32/PeiCoreEntry.nasm
> @@ -1,21 +1,25 @@
> -;; @file
> -; Find and call SecStartup
> +;----------------------------------------------------------------------
> +--------
> ;
> -; Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> +; Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; -;;
> -
> +; Module Name:
> +;
> +; PeiCoreEntry.nasm
> +;
> +; Abstract:
> +;
> +; Find and call SecStartup
> +;
> +;----------------------------------------------------------------------
> +--------
>
> -.686p
> -.xmm
> -.model flat, c
> -.code
> +SECTION .text
>
> -EXTRN SecStartup:NEAR
> -EXTRN PlatformInit:NEAR
> +extern ASM_PFX(SecStartup)
> +extern ASM_PFX(PlatformInit)
>
> -CallPeiCoreEntryPoint PROC PUBLIC
> +global ASM_PFX(CallPeiCoreEntryPoint)
> +ASM_PFX(CallPeiCoreEntryPoint):
> ;
> ; Obtain the hob list pointer
> ;
> @@ -26,7 +30,7 @@ CallPeiCoreEntryPoint PROC PUBLIC
> ; EDX: end of range
> ;
> mov ecx, [esp+8]
> - mov edx, [esp+0Ch]
> + mov edx, [esp+0xC]
>
> ;
> ; Platform init
> @@ -35,7 +39,7 @@ CallPeiCoreEntryPoint PROC PUBLIC
> push edx
> push ecx
> push eax
> - call PlatformInit
> + call ASM_PFX(PlatformInit)
> pop eax
> pop eax
> pop eax
> @@ -66,7 +70,7 @@ CallPeiCoreEntryPoint PROC PUBLIC
> mov eax, 1
> cpuid
> shr ebx, 16
> - and ebx, 0000000FFh
> + and ebx, 0xFF
> cmp bl, 1
> jae PushProcessorCount
>
> @@ -100,14 +104,14 @@ PushBist:
> ;
> ; Pass entry point of the PEI core
> ;
> - mov edi, 0FFFFFFE0h
> - push DWORD PTR ds:[edi]
> + mov edi, 0xFFFFFFE0
> + push DWORD [edi]
>
> ;
> ; Pass BFV into the PEI Core
> ;
> - mov edi, 0FFFFFFFCh
> - push DWORD PTR ds:[edi]
> + mov edi, 0xFFFFFFFC
> + push DWORD [edi]
>
> ;
> ; Pass stack size into the PEI Core
> @@ -122,7 +126,5 @@ PushBist:
> ;
> ; Pass Control into the PEI Core
> ;
> - call SecStartup
> -CallPeiCoreEntryPoint ENDP
> + call ASM_PFX(SecStartup)
>
> -END
> diff --git
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo
> rmSecLib/Ia32/SecEntry.S
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo
> rmSecLib/Ia32/SecEntry.S
> deleted file mode 100644
> index 63c420a..0000000
> ---
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo
> rmSecLib/Ia32/SecEntry.S
> +++ /dev/null
> @@ -1,342 +0,0 @@
> -## @file
> -# This is the code that goes from real-mode to protected mode.
> -# It consumes the reset vector, calls TempRamInit API from FSP binary.
> -#
> -# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> -# SPDX-
> License-Identifier: BSD-2-Clause-Patent -# -##
> -
> -#include "Fsp.h"
> -
> -ASM_GLOBAL ASM_PFX(_gPcd_FixedAtBuild_PcdFsptBaseAddress)
> -ASM_GLOBAL ASM_PFX(_gPcd_FixedAtBuild_PcdFspTemporaryRamSize)
> -
> -ASM_GLOBAL ASM_PFX(_TEXT_REALMODE)
> -ASM_PFX(_TEXT_REALMODE):
> -#----------------------------------------------------------------------------
> -#
> -# Procedure: _ModuleEntryPoint
> -#
> -# Input: None
> -#
> -# Output: None
> -#
> -# Destroys: Assume all registers
> -#
> -# Description:
> -#
> -# Transition to non-paged flat-model protected mode from a
> -# hard-coded GDT that provides exactly two descriptors.
> -# This is a bare bones transition to protected mode only
> -# used for a while in PEI and possibly DXE.
> -#
> -# After enabling protected mode, a far jump is executed to
> -# transfer to PEI using the newly loaded GDT.
> -#
> -# Return: None
> -#
> -# MMX Usage:
> -# MM0 = BIST State
> -# MM5 = Save time-stamp counter value high32bit
> -# MM6 = Save time-stamp counter value low32bit.
> -#
> -#----------------------------------------------------------------------------
> -
> -ASM_GLOBAL ASM_PFX(_ModuleEntryPoint)
> -ASM_PFX(_ModuleEntryPoint):
> - fninit # clear any pending Floating point exceptions
> - #
> - # Store the BIST value in mm0
> - #
> - movd %eax, %mm0
> - cli
> -
> - #
> - # Check INIT# is asserted by port 0xCF9
> - #
> - mov $0x0CF9, %dx
> - in %dx, %al
> - cmp $0x04, %al
> - jnz NotWarmStart
> -
> - #
> - # @note Issue warm reset, since if CPU only reset is issued not all MSRs are
> restored to their defaults
> - #
> - movw $0x0CF9, %dx
> - movb $0x06, %al
> - out %al, %dx
> -
> - #
> - # Save time-stamp counter value
> - # rdtsc load 64bit time-stamp counter to EDX:EAX
> - #
> - rdtsc
> - movd %edx, %mm5
> - movd %ecx, %mm6
> -
> - #
> - # Load the GDT table in GdtDesc
> - #
> - movl $GdtDesc, %esi
> - .byte 0x66
> - lgdt %cs:(%si)
> -
> - #
> - # Transition to 16 bit protected mode
> - #
> - movl %cr0, %eax # Get control register 0
> - orl $0x00000003, %eax # Set PE bit (bit #0) & MP bit (bit #1)
> - movl %eax, %cr0 # Activate protected mode
> -
> - movl %cr4, %eax # Get control register 4
> - orl $0x00000600, %eax # Set OSFXSR bit (bit #9) & OSXMMEXCPT bit
> (bit #10)
> - movl %eax, %cr4
> -
> - #
> - # Now we're in 16 bit protected mode
> - # Set up the selectors for 32 bit protected mode entry
> - #
> - mov $SYS_DATA_SEL, %ax
> - mov %ax, %ds
> - mov %ax, %es
> - mov %ax, %fs
> - mov %ax, %gs
> - mov %ax, %ss
> -
> - #
> - # Transition to Flat 32 bit protected mode
> - # The jump to a far pointer causes the transition to 32 bit mode
> - #
> - movl $ProtectedModeEntryLinearAddress, %esi
> - jmp *%cs:(%si)
> -
> -ASM_GLOBAL ASM_PFX(_TEXT_PROTECTED_MODE)
> -ASM_PFX(_TEXT_PROTECTED_MODE):
> -
> -#----------------------------------------------------------------------------
> -#
> -# Procedure: ProtectedModeEntryPoint
> -#
> -# Input: None
> -#
> -# Output: None
> -#
> -# Destroys: Assume all registers
> -#
> -# Description:
> -#
> -# This function handles:
> -# Call two basic APIs from FSP binary
> -# Initializes stack with some early data (BIST, PEI entry, etc)
> -#
> -# Return: None
> -#
> -#----------------------------------------------------------------------------
> -
> -ASM_GLOBAL ASM_PFX(ProtectedModeEntryPoint)
> -ASM_PFX(ProtectedModeEntryPoint):
> -
> - # Find the fsp info header
> - movl PcdGet32(PcdFsptBaseAddress), %edi
> -
> - movl FVH_SIGINATURE_OFFSET(%edi), %eax
> - cmp $FVH_SIGINATURE_VALID_VALUE, %eax
> - jnz FspHeaderNotFound
> -
> - xorl %eax, %eax
> - movw FVH_EXTHEADER_OFFSET_OFFSET(%edi), %ax
> - cmp $0x00, %ax
> - jnz FspFvExtHeaderExist
> -
> - xorl %eax, %eax
> - movw FVH_HEADER_LENGTH_OFFSET(%edi), %ax # Bypass Fv Header
> - addl %eax, %edi
> - jmp FspCheckFfsHeader
> -
> -FspFvExtHeaderExist:
> - addl %eax, %edi
> - movl FVH_EXTHEADER_SIZE_OFFSET(%edi), %eax # Bypass Ext Fv Header
> - addl %eax, %edi
> -
> - # Round up to 8 byte alignment
> - movl %edi, %eax
> - andb $0x07, %al
> - jz FspCheckFfsHeader
> -
> - and $0xFFFFFFF8, %edi
> - add $0x08, %edi
> -
> -FspCheckFfsHeader:
> - # Check the ffs guid
> - movl (%edi), %eax
> - cmp $FSP_HEADER_GUID_DWORD1, %eax
> - jnz FspHeaderNotFound
> -
> - movl 0x4(%edi), %eax
> - cmp $FSP_HEADER_GUID_DWORD2, %eax
> - jnz FspHeaderNotFound
> -
> - movl 0x08(%edi), %eax
> - cmp $FSP_HEADER_GUID_DWORD3, %eax
> - jnz FspHeaderNotFound
> -
> - movl 0x0c(%edi), %eax
> - cmp $FSP_HEADER_GUID_DWORD4, %eax
> - jnz FspHeaderNotFound
> -
> - add $FFS_HEADER_SIZE_VALUE, %edi # Bypass the ffs header
> -
> - # Check the section type as raw section
> - movb SECTION_HEADER_TYPE_OFFSET(%edi), %al
> - cmp $0x19, %al
> - jnz FspHeaderNotFound
> -
> - addl $RAW_SECTION_HEADER_SIZE_VALUE, %edi # Bypass the section
> header
> - jmp FspHeaderFound
> -
> -FspHeaderNotFound:
> - jmp .
> -
> -FspHeaderFound:
> - # Get the fsp TempRamInit Api address
> - movl FSP_HEADER_IMAGEBASE_OFFSET(%edi), %eax
> - addl FSP_HEADER_TEMPRAMINIT_OFFSET(%edi), %eax
> -
> - # Setup the hardcode stack
> - movl $TempRamInitStack, %esp
> -
> - # Call the fsp TempRamInit Api
> - jmp *%eax
> -
> -TempRamInitDone:
> - cmp $0x8000000E, %eax #Check if EFI_NOT_FOUND returned. Error code
> for Microcode Update not found.
> - je CallSecFspInit #If microcode not found, don't hang, but continue.
> -
> - cmp $0x0, %eax
> - jnz FspApiFailed
> -
> - # ECX: start of range
> - # EDX: end of range
> -CallSecFspInit:
> - subl PcdGet32 (PcdFspTemporaryRamSize), %edx # TemporaryRam for
> FSP
> - xorl %eax, %eax
> - movl %edx, %esp
> -
> - # Align the stack at DWORD
> - addl $3, %esp
> - andl $0xFFFFFFFC, %esp
> -
> - pushl %edx
> - pushl %ecx
> - pushl %eax # zero - no hob list yet
> - call ASM_PFX(CallPeiCoreEntryPoint)
> -
> -FspApiFailed:
> - jmp .
> -
> -.align 0x10
> -TempRamInitStack:
> - .long TempRamInitDone
> - .long FsptUpdDataPtr
> -
> -#
> -# ROM-based Global-Descriptor Table for the Tiano PEI Phase -# -.align 0x10
> -
> -#
> -# GDT[0]: 0x00: Null entry, never used.
> -#
> -.equ NULL_SEL, . - GdtBase # Selector [0]
> -GdtBase:
> -BootGdtTable:
> - .long 0
> - .long 0
> -
> -#
> -# Linear data segment descriptor
> -#
> -.equ LINEAR_SEL, . - GdtBase # Selector [0x8]
> - .word 0xFFFF # limit 0xFFFFF
> - .word 0 # base 0
> - .byte 0
> - .byte 0x92 # present, ring 0, data, expand-up, writable
> - .byte 0xCF # page-granular, 32-bit
> - .byte 0
> -
> -#
> -# Linear code segment descriptor
> -#
> -.equ LINEAR_CODE_SEL, . - GdtBase # Selector [0x10]
> - .word 0xFFFF # limit 0xFFFFF
> - .word 0 # base 0
> - .byte 0
> - .byte 0x9B # present, ring 0, data, expand-up, not-writable
> - .byte 0xCF # page-granular, 32-bit
> - .byte 0
> -#
> -# System data segment descriptor
> -#
> -.equ SYS_DATA_SEL, . - GdtBase # Selector [0x18]
> - .word 0xFFFF # limit 0xFFFFF
> - .word 0 # base 0
> - .byte 0
> - .byte 0x93 # present, ring 0, data, expand-up, not-writable
> - .byte 0xCF # page-granular, 32-bit
> - .byte 0
> -
> -#
> -# System code segment descriptor
> -#
> -.equ SYS_CODE_SEL, . - GdtBase # Selector [0x20]
> - .word 0xFFFF # limit 0xFFFFF
> - .word 0 # base 0
> - .byte 0
> - .byte 0x9A # present, ring 0, data, expand-up, writable
> - .byte 0xCF # page-granular, 32-bit
> - .byte 0
> -#
> -# Spare segment descriptor
> -#
> -.equ SYS16_CODE_SEL, . - GdtBase # Selector [0x28]
> - .word 0xFFFF # limit 0xFFFFF
> - .word 0 # base 0
> - .byte 0x0E # Changed from F000 to E000.
> - .byte 0x9B # present, ring 0, code, expand-up, writable
> - .byte 0x00 # byte-granular, 16-bit
> - .byte 0
> -#
> -# Spare segment descriptor
> -#
> -.equ SYS16_DATA_SEL, . - GdtBase # Selector [0x30]
> - .word 0xFFFF # limit 0xFFFF
> - .word 0 # base 0
> - .byte 0
> - .byte 0x93 # present, ring 0, data, expand-up, not-writable
> - .byte 0x00 # byte-granular, 16-bit
> - .byte 0
> -
> -#
> -# Spare segment descriptor
> -#
> -.equ SPARE5_SEL, . - GdtBase # Selector [0x38]
> - .word 0 # limit 0
> - .word 0 # base 0
> - .byte 0
> - .byte 0 # present, ring 0, data, expand-up, writable
> - .byte 0 # page-granular, 32-bit
> - .byte 0
> -.equ GDT_SIZE, . - BootGdtTable # Size, in bytes
> -
> -#
> -# GDT Descriptor
> -#
> -GdtDesc: # GDT descriptor
> - .word GDT_SIZE - 1 # GDT limit
> - .long BootGdtTable # GDT base address
> -
> -ASM_PFX(ProtectedModeEntryLinearAddress):
> -ProtectedModeEntryLinearOffset:
> - .long ProtectedModeEntryPoint # Offset of our 32 bit code
> - .word LINEAR_CODE_SEL
> diff --git
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo
> rmSecLib/Ia32/SecEntry.asm
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo
> rmSecLib/Ia32/SecEntry.nasm
> similarity index 72%
> rename from
> Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/Ia32/SecEntry.asm
> rename to
> Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/Ia32/SecEntry.nasm
> index 2886a37..7f6d771 100644
> ---
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo
> rmSecLib/Ia32/SecEntry.asm
> +++
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat
> +++ formSecLib/Ia32/SecEntry.nasm
> @@ -1,28 +1,28 @@
> -;; @file
> -; This is the code that goes from real-mode to protected mode.
> -; It consumes the reset vector, calls TempRamInit API from FSP binary.
> +;----------------------------------------------------------------------
> +--------
> ;
> -; Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> +; Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> ; SPDX-License-Identifier: BSD-2-Clause-Patent
> +; Module Name:
> ;
> -;;
> +; SecEntry.nasm
> +;
> +; Abstract:
> +;
> +; This is the code that goes from real-mode to protected mode.
> +; It consumes the reset vector, calls TempRamInit API from FSP binary.
> +;
> +;----------------------------------------------------------------------
> +--------
>
> #include "Fsp.h"
>
> -.686p
> -.xmm
> -.model small, c
> -
> -EXTRN CallPeiCoreEntryPoint:NEAR
> -EXTRN BoardBeforeTempRamInit:NEAR
> -EXTRN FsptUpdDataPtr:FAR
> +SECTION .text
>
> +extern ASM_PFX(CallPeiCoreEntryPoint)
> +extern ASM_PFX(FsptUpdDataPtr)
> +extern ASM_PFX(BoardBeforeTempRamInit)
> ; Pcds
> -EXTRN PcdGet32 (PcdFsptBaseAddress):DWORD
> -EXTRN PcdGet32(PcdFspTemporaryRamSize):DWORD
> -
> -_TEXT_REALMODE SEGMENT PARA PUBLIC USE16 'CODE'
> - ASSUME CS:_TEXT_REALMODE, DS:_TEXT_REALMODE
> +extern ASM_PFX(PcdGet32 (PcdFspTemporaryRamSize))
> +extern ASM_PFX(PcdGet32 (PcdFsptBaseAddress))
>
> ;----------------------------------------------------------------------------
> ;
> @@ -53,8 +53,10 @@ _TEXT_REALMODE SEGMENT PARA PUBLIC USE16
> 'CODE'
> ;
> ;----------------------------------------------------------------------------
>
> +BITS 16
> align 4
> -_ModuleEntryPoint PROC NEAR C PUBLIC
> +global ASM_PFX(_ModuleEntryPoint)
> +ASM_PFX(_ModuleEntryPoint):
> fninit ; clear any pending Floating point exceptions
> ;
> ; Store the BIST value in mm0
> @@ -70,6 +72,7 @@ _ModuleEntryPoint PROC NEAR C PUBLIC
> cmp al, 04h
> jnz NotWarmStart
>
> +
> ;
> ; @note Issue warm reset, since if CPU only reset is issued not all MSRs are
> restored to their defaults
> ;
> @@ -78,7 +81,6 @@ _ModuleEntryPoint PROC NEAR C PUBLIC
> out dx, al
>
> NotWarmStart:
> -
> ;
> ; Save time-stamp counter value
> ; rdtsc load 64bit time-stamp counter to EDX:EAX @@ -90,9 +92,9 @@
> NotWarmStart:
> ;
> ; Load the GDT table in GdtDesc
> ;
> - mov esi, OFFSET GdtDesc
> + mov esi, GdtDesc
> DB 66h
> - lgdt fword ptr cs:[si]
> + lgdt [cs:si]
>
> ;
> ; Transition to 16 bit protected mode @@ -120,14 +122,8 @@
> NotWarmStart:
> ; Transition to Flat 32 bit protected mode
> ; The jump to a far pointer causes the transition to 32 bit mode
> ;
> - mov esi, offset ProtectedModeEntryLinearAddress
> - jmp fword ptr cs:[si]
> -
> -_ModuleEntryPoint ENDP
> -_TEXT_REALMODE ENDS
> -
> -_TEXT_PROTECTED_MODE SEGMENT PARA PUBLIC USE32 'CODE'
> - ASSUME CS:_TEXT_PROTECTED_MODE,
> DS:_TEXT_PROTECTED_MODE
> + mov esi, ProtectedModeEntryLinearAddress
> + jmp dword far [cs:si]
>
> ;----------------------------------------------------------------------------
> ;
> @@ -149,69 +145,69 @@ _TEXT_PROTECTED_MODE SEGMENT PARA
> PUBLIC USE32 'CODE'
> ;
> ;----------------------------------------------------------------------------
>
> +BITS 32
> align 4
> -ProtectedModeEntryPoint PROC NEAR PUBLIC
> -
> - ;
> - ; Early board hooks
> - ;
> - mov esp, BoardBeforeTempRamInitRet
> - jmp BoardBeforeTempRamInit
> +ProtectedModeEntryPoint:
> + ;
> + ; Early board hooks
> + ;
> + mov esp, BoardBeforeTempRamInitRet
> + jmp ASM_PFX(BoardBeforeTempRamInit)
>
> BoardBeforeTempRamInitRet:
>
> ; Find the fsp info header
> - mov edi, PcdGet32 (PcdFsptBaseAddress)
> + mov edi, [ASM_PFX(PcdGet32 (PcdFsptBaseAddress))]
>
> - mov eax, dword ptr [edi + FVH_SIGINATURE_OFFSET]
> + mov eax, dword [edi + FVH_SIGINATURE_OFFSET]
> cmp eax, FVH_SIGINATURE_VALID_VALUE
> jnz FspHeaderNotFound
>
> xor eax, eax
> - mov ax, word ptr [edi + FVH_EXTHEADER_OFFSET_OFFSET]
> + mov ax, word [edi + FVH_EXTHEADER_OFFSET_OFFSET]
> cmp ax, 0
> jnz FspFvExtHeaderExist
>
> xor eax, eax
> - mov ax, word ptr [edi + FVH_HEADER_LENGTH_OFFSET] ; Bypass Fv
> Header
> + mov ax, word [edi + FVH_HEADER_LENGTH_OFFSET] ; Bypass Fv Header
> add edi, eax
> jmp FspCheckFfsHeader
>
> FspFvExtHeaderExist:
> add edi, eax
> - mov eax, dword ptr [edi + FVH_EXTHEADER_SIZE_OFFSET] ; Bypass Ext Fv
> Header
> + mov eax, dword [edi + FVH_EXTHEADER_SIZE_OFFSET] ; Bypass Ext Fv
> + Header
> add edi, eax
>
> ; Round up to 8 byte alignment
> mov eax, edi
> and al, 07h
> - jz FspCheckFfsHeader
> + jz FspCheckFfsHeader
>
> and edi, 0FFFFFFF8h
> add edi, 08h
>
> FspCheckFfsHeader:
> ; Check the ffs guid
> - mov eax, dword ptr [edi]
> + mov eax, dword [edi]
> cmp eax, FSP_HEADER_GUID_DWORD1
> - jnz FspHeaderNotFound
> + jnz FspHeaderNotFound
>
> - mov eax, dword ptr [edi + 4]
> + mov eax, dword [edi + 4]
> cmp eax, FSP_HEADER_GUID_DWORD2
> - jnz FspHeaderNotFound
> + jnz FspHeaderNotFound
>
> - mov eax, dword ptr [edi + 8]
> + mov eax, dword [edi + 8]
> cmp eax, FSP_HEADER_GUID_DWORD3
> - jnz FspHeaderNotFound
> + jnz FspHeaderNotFound
>
> - mov eax, dword ptr [edi + 0Ch]
> + mov eax, dword [edi + 0Ch]
> cmp eax, FSP_HEADER_GUID_DWORD4
> - jnz FspHeaderNotFound
> + jnz FspHeaderNotFound
>
> add edi, FFS_HEADER_SIZE_VALUE ; Bypass the ffs header
>
> ; Check the section type as raw section
> - mov al, byte ptr [edi + SECTION_HEADER_TYPE_OFFSET]
> + mov al, byte [edi + SECTION_HEADER_TYPE_OFFSET]
> cmp al, 019h
> jnz FspHeaderNotFound
>
> @@ -223,11 +219,11 @@ FspHeaderNotFound:
>
> FspHeaderFound:
> ; Get the fsp TempRamInit Api address
> - mov eax, dword ptr [edi + FSP_HEADER_IMAGEBASE_OFFSET]
> - add eax, dword ptr [edi + FSP_HEADER_TEMPRAMINIT_OFFSET]
> + mov eax, dword [edi + FSP_HEADER_IMAGEBASE_OFFSET] add eax, dword
> + [edi + FSP_HEADER_TEMPRAMINIT_OFFSET]
>
> ; Setup the hardcode stack
> - mov esp, OFFSET TempRamInitStack
> + mov esp, TempRamInitStack
>
> ; Call the fsp TempRamInit Api
> jmp eax
> @@ -242,7 +238,7 @@ TempRamInitDone:
> ; ECX: start of range
> ; EDX: end of range
> CallSecFspInit:
> - sub edx, PcdGet32 (PcdFspTemporaryRamSize) ; TemporaryRam for FSP
> + sub edx, [ASM_PFX(PcdGet32 (PcdFspTemporaryRamSize))] ;
> TemporaryRam for FSP
> xor eax, eax
> mov esp, edx
>
> @@ -253,30 +249,29 @@ CallSecFspInit:
> push edx
> push ecx
> push eax ; zero - no hob list yet
> - call CallPeiCoreEntryPoint
> + call ASM_PFX(CallPeiCoreEntryPoint)
>
> FspApiFailed:
> jmp $
>
> align 10h
> TempRamInitStack:
> - DD OFFSET TempRamInitDone
> - DD OFFSET FsptUpdDataPtr ; TempRamInitParams
> -
> -ProtectedModeEntryPoint ENDP
> + DD TempRamInitDone
> + DD ASM_PFX(FsptUpdDataPtr); TempRamInitParams
>
> ;
> ; ROM-based Global-Descriptor Table for the Tiano PEI Phase ; align 16 -
> PUBLIC BootGdtTable
> +global ASM_PFX(BootGdtTable)
>
> ;
> ; GDT[0]: 0x00: Null entry, never used.
> ;
> NULL_SEL EQU $ - GDT_BASE ; Selector [0]
> GDT_BASE:
> -BootGdtTable DD 0
> +ASM_PFX(BootGdtTable):
> + DD 0
> DD 0
> ;
> ; Linear data segment descriptor
> @@ -350,20 +345,17 @@ SPARE5_SEL EQU $ - GDT_BASE ; Selector
> [0x38]
> DB 0 ; present, ring 0, data, expand-up, writable
> DB 0 ; page-granular, 32-bit
> DB 0
> -GDT_SIZE EQU $ - BootGdtTable ; Size, in bytes
> +GDT_SIZE EQU $ - GDT_BASE ; Size, in bytes
>
> ;
> ; GDT Descriptor
> ;
> GdtDesc: ; GDT descriptor
> DW GDT_SIZE - 1 ; GDT limit
> - DD OFFSET BootGdtTable ; GDT base address
> + DD GDT_BASE ; GDT base address
>
>
> -ProtectedModeEntryLinearAddress LABEL FWORD
> -ProtectedModeEntryLinearOffset LABEL DWORD
> - DD OFFSET ProtectedModeEntryPoint ; Offset of our 32 bit code
> +ProtectedModeEntryLinearAddress:
> +ProtectedModeEntryLinear:
> + DD ProtectedModeEntryPoint ; Offset of our 32 bit code
> DW LINEAR_CODE_SEL
> -
> -_TEXT_PROTECTED_MODE ENDS
> -END
> diff --git
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo
> rmSecLib/Ia32/Stack.S
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo
> rmSecLib/Ia32/Stack.S
> deleted file mode 100644
> index 9953daa..0000000
> ---
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo
> rmSecLib/Ia32/Stack.S
> +++ /dev/null
> @@ -1,67 +0,0 @@
> -## @file
> -# Switch the stack from temporary memory to permenent memory.
> -#
> -# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> -# SPDX-
> License-Identifier: BSD-2-Clause-Patent -# -##
> -
> -#------------------------------------------------------------------------------
> -# VOID
> -# EFIAPI
> -# SecSwitchStack (
> -# UINT32 TemporaryMemoryBase,
> -# UINT32 PermanentMemoryBase
> -# )
> -#------------------------------------------------------------------------------
> -ASM_GLOBAL ASM_PFX (SecSwitchStack)
> -ASM_PFX(SecSwitchStack):
> - #
> - # Save standard registers so they can be used to change stack
> - #
> - pushl %eax
> - pushl %ebx
> - pushl %ecx
> - pushl %edx
> -
> - #
> - # !!CAUTION!! this function address's is pushed into stack after
> - # migration of whole temporary memory, so need save it to permanent
> - # memory at first!
> - #
> - movl 20(%esp), %ebx # Save the first parameter
> - movl 24(%esp), %ecx # Save the second parameter
> -
> - #
> - # Save this function's return address into permanent memory at first.
> - # Then, Fixup the esp point to permanent memory
> - #
> - movl %esp, %eax
> - subl %ebx, %eax
> - addl %ecx, %eax
> - movl 0(%esp), %edx # copy pushed register's value to permanent
> memory
> - movl %edx, 0(%eax)
> - movl 4(%esp), %edx
> - movl %edx, 4(%eax)
> - movl 8(%esp), %edx
> - movl %edx, 8(%eax)
> - movl 12(%esp), %edx
> - movl %edx, 12(%eax)
> - movl 16(%esp), %edx # Update this function's return address into
> permanent memory
> - movl %edx, 16(%eax)
> - movl %eax, %esp # From now, esp is pointed to permanent
> memory
> -
> - #
> - # Fixup the ebp point to permanent memory
> - #
> - movl %ebp, %eax
> - subl %ebx, %eax
> - addl %ecx, %eax
> - movl %eax, %ebp # From now, ebp is pointed to permanent
> memory
> -
> - popl %edx
> - popl %ecx
> - popl %ebx
> - popl %eax
> - ret
> -
> diff --git
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo
> rmSecLib/Ia32/Stack.asm
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo
> rmSecLib/Ia32/Stack.nasm
> similarity index 59%
> rename from
> Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/Ia32/Stack.asm
> rename to
> Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/Ia32/Stack.nasm
> index 1830240..47db32d 100644
> ---
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo
> rmSecLib/Ia32/Stack.asm
> +++
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat
> +++ formSecLib/Ia32/Stack.nasm
> @@ -1,14 +1,14 @@
> -;; @file
> -; Switch the stack from temporary memory to permenent memory.
> +;----------------------------------------------------------------------
> +--------
> ;
> -; Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> +; Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> ; SPDX-License-Identifier: BSD-2-Clause-Patent
> +; Abstract:
> +;
> +; Switch the stack from temporary memory to permanent memory.
> ;
> -;;
> +;----------------------------------------------------------------------
> +--------
>
> - .586p
> - .model flat,C
> - .code
> + SECTION .text
>
> ;------------------------------------------------------------------------------
> ; VOID
> @@ -18,7 +18,8 @@
> ; UINT32 PermanentMemoryBase
> ; );
> ;------------------------------------------------------------------------------
> -SecSwitchStack PROC
> +global ASM_PFX(SecSwitchStack)
> +ASM_PFX(SecSwitchStack):
> ;
> ; Save three register: eax, ebx, ecx
> ;
> @@ -43,16 +44,16 @@ SecSwitchStack PROC
> mov eax, esp
> sub eax, ebx
> add eax, ecx
> - mov edx, dword ptr [esp] ; copy pushed register's value to
> permanent memory
> - mov dword ptr [eax], edx
> - mov edx, dword ptr [esp + 4]
> - mov dword ptr [eax + 4], edx
> - mov edx, dword ptr [esp + 8]
> - mov dword ptr [eax + 8], edx
> - mov edx, dword ptr [esp + 12]
> - mov dword ptr [eax + 12], edx
> - mov edx, dword ptr [esp + 16] ; Update this function's return address
> into permanent memory
> - mov dword ptr [eax + 16], edx
> + mov edx, dword [esp] ; copy pushed register's value to permanent
> memory
> + mov dword [eax], edx
> + mov edx, dword [esp + 4]
> + mov dword [eax + 4], edx
> + mov edx, dword [esp + 8]
> + mov dword [eax + 8], edx
> + mov edx, dword [esp + 12]
> + mov dword [eax + 12], edx
> + mov edx, dword [esp + 16] ; Update this function's return address into
> permanent memory
> + mov dword [eax + 16], edx
> mov esp, eax ; From now, esp is pointed to permanent
> memory
>
> ;
> @@ -68,6 +69,4 @@ SecSwitchStack PROC
> pop ebx
> pop eax
> ret
> -SecSwitchStack ENDP
>
> - END
> diff --git
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo
> rmSecLib/SecFspWrapperPlatformSecLib.inf
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo
> rmSecLib/SecFspWrapperPlatformSecLib.inf
> index 6f2c95a..5d77e9e 100644
> ---
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfo
> rmSecLib/SecFspWrapperPlatformSecLib.inf
> +++
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat
> +++ formSecLib/SecFspWrapperPlatformSecLib.inf
> @@ -1,10 +1,11 @@
> ## @file
> # Provide FSP wrapper platform sec related function.
> #
> -# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> +# Copyright (c) 2017 - 2019, Intel Corporation. All rights
> +reserved.<BR>
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent #
> +#
> ##
>
>
> ################################################################
> ################
> @@ -42,13 +43,10 @@
> PlatformInit.c
>
> [Sources.IA32]
> - Ia32/SecEntry.asm
> - Ia32/PeiCoreEntry.asm
> - Ia32/Stack.asm
> + Ia32/SecEntry.nasm
> + Ia32/PeiCoreEntry.nasm
> + Ia32/Stack.nasm
> Ia32/Fsp.h
> - Ia32/SecEntry.S
> - Ia32/PeiCoreEntry.S
> - Ia32/Stack.S
>
>
> ################################################################
> ################
> #
> diff --git a/Platform/Intel/MinPlatformPkg/Include/Fdf/RuleInclude.fdf
> b/Platform/Intel/MinPlatformPkg/Include/Fdf/RuleInclude.fdf
> index c4c4315..a1a8964 100644
> --- a/Platform/Intel/MinPlatformPkg/Include/Fdf/RuleInclude.fdf
> +++ b/Platform/Intel/MinPlatformPkg/Include/Fdf/RuleInclude.fdf
> @@ -1,7 +1,7 @@
> ## @file
> # FDF file of Platform.
> #
> -# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> +# Copyright (c) 2017 - 2019, Intel Corporation. All rights
> +reserved.<BR>
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -25,7 +25,7 @@
>
> [Rule.Common.PEI_CORE]
> FILE PEI_CORE = $(NAMED_GUID) {
> - PE32 PE32 Align = 32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + PE32 PE32 Align = 64 $(INF_OUTPUT)/$(MODULE_NAME).efi
> UI STRING="$(MODULE_NAME)" Optional
> VERSION STRING="$(INF_VERSION)" Optional
> BUILD_NUM=$(BUILD_NUMBER)
> }
> @@ -40,7 +40,7 @@
> [Rule.Common.PEIM]
> FILE PEIM = $(NAMED_GUID) {
> PEI_DEPEX PEI_DEPEX Optional
> $(INF_OUTPUT)/$(MODULE_NAME).depex
> - PE32 PE32 Align = 32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + PE32 PE32 Align = 64 $(INF_OUTPUT)/$(MODULE_NAME).efi
> UI STRING="$(MODULE_NAME)" Optional
> VERSION STRING="$(INF_VERSION)" Optional
> BUILD_NUM=$(BUILD_NUMBER)
> }
> diff --git
> a/Platform/Intel/MinPlatformPkg/Tools/Fsp/RebaseAndPatchFspBinBaseAdd
> ress.py
> b/Platform/Intel/MinPlatformPkg/Tools/Fsp/RebaseAndPatchFspBinBaseAdd
> ress.py
> index 496b977..167a0e0 100644
> ---
> a/Platform/Intel/MinPlatformPkg/Tools/Fsp/RebaseAndPatchFspBinBaseAdd
> ress.py
> +++
> b/Platform/Intel/MinPlatformPkg/Tools/Fsp/RebaseAndPatchFspBinBaseAd
> +++ dress.py
> @@ -76,7 +76,7 @@ file.close()
> pythontool = 'python'
> if 'PYTHON_HOME' in os.environ:
> pythontool = os.environ['PYTHON_HOME'] + os.sep + 'python'
> -Process = subprocess.Popen(pythontool + " " + splitFspBinPath + " info -f" +
> fspBinFilePath, stdout=subprocess.PIPE)
> +Process = subprocess.Popen([pythontool, splitFspBinPath,
> +"info","-f",fspBinFilePath], stdout=subprocess.PIPE)
> Output = Process.communicate()[0]
> FsptInfo = Output.rsplit("FSP_M", 1);
> for line in FsptInfo[1].split("\n"):
> diff --git a/Platform/Intel/MinPlatformPkg/Tools/PatchFv/PatchBinFv.py
> b/Platform/Intel/MinPlatformPkg/Tools/PatchFv/PatchBinFv.py
> index 5b49b6b..b98c951 100644
> --- a/Platform/Intel/MinPlatformPkg/Tools/PatchFv/PatchBinFv.py
> +++ b/Platform/Intel/MinPlatformPkg/Tools/PatchFv/PatchBinFv.py
> @@ -1,6 +1,6 @@
> ## @ PatchBinFv.py
> #
> -# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> +# Copyright (c) 2017 - 2019, Intel Corporation. All rights
> +reserved.<BR>
> # SPDX-License-Identifier: BSD-2-Clause-Patent # ## @@ -107,7 +107,7 @@
> class FileChecker:
> return
>
> def ProcessFvInf(self, fvName):
> - sourceFileName =
> os.path.join(self.sourceRoot,fvName+"\\"+self.target+"\\"+fvName+".inf")
> + sourceFileName =
> + os.path.join(self.sourceRoot,fvName,self.target,fvName+".inf")
> print "\nprocessing - " + sourceFileName
> fileGuid = self.GetInfFileGuid (sourceFileName)
> print "FV NAME GUID - " + fileGuid @@ -137,7 +137,7 @@ class
> FileChecker:
> self.PrintPcdList(self.InfPcdList)
>
> def PatchFv(self, fvName):
> - sourceFileName =
> os.path.join(self.sourceRoot,fvName+"\\"+self.target+"\\"+fvName+".fv")
> + sourceFileName =
> + os.path.join(self.sourceRoot,fvName,self.target,fvName+".Fv")
> print "patching - " + sourceFileName
>
> try :
> @@ -161,7 +161,7 @@ class FileChecker:
> print " [" + hex(offset) + "] " +
> binascii.hexlify(data[offset:offset+2]) + " <= " + binascii.hexlify(h)
> data[offset:offset+2] = h
> elif (cmp (pcd[4], "UINT32") == 0):
> - l = struct.pack("L", int(pcd[3],16))
> + l = struct.pack("I", int(pcd[3],16))
> print " [" + hex(offset) + "] " +
> binascii.hexlify(data[offset:offset+4]) + " <= " + binascii.hexlify(l)
> data[offset:offset+4] = l
> elif (cmp (pcd[4], "UINT64") == 0):
> diff --git a/Platform/Intel/MinPlatformPkg/Tools/PatchFv/RebaseBinFv.py
> b/Platform/Intel/MinPlatformPkg/Tools/PatchFv/RebaseBinFv.py
> index 321f7c5..149630e 100644
> --- a/Platform/Intel/MinPlatformPkg/Tools/PatchFv/RebaseBinFv.py
> +++ b/Platform/Intel/MinPlatformPkg/Tools/PatchFv/RebaseBinFv.py
> @@ -1,9 +1,8 @@
> ## @ PatchBinFv.py
> #
> -# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> +# Copyright (c) 2017 - 2019, Intel Corporation. All rights
> +reserved.<BR>
> # SPDX-License-Identifier: BSD-2-Clause-Patent # -##
>
> import os
> import re
> @@ -541,7 +540,7 @@ class FileChecker:
> print "PCD: " + pcd[0] + "|" + pcd[3] + " <== " + pcd[1] + "(" + pcd[2] + ")"
>
> def RebaseFv(self, fvName, rebasePcd):
> - sourceFileName =
> os.path.join(self.sourceRoot,fvName+"\\"+self.target+"\\"+fvName+".fv")
> + sourceFileName =
> + os.path.join(self.sourceRoot,fvName,self.target,fvName+".Fv")
> print "rebasing(FV) - " + sourceFileName
>
> try :
> @@ -617,7 +616,7 @@ class FileChecker:
> if not line:
> break
>
> - newline = line[:-1]
> + newline = line[:-1].replace('\r','')
>
> if (cmp (newline, TargetPkg) == 0):
> FoundPkg = True
> @@ -645,7 +644,7 @@ class FileChecker:
> def GetOldFvBase (self, fvName, PcdName):
> ParseBase = False
> Value = ""
> - fileName =
> os.path.join(self.sourceRoot,fvName+"\\"+self.target+"\\"+fvName+".inf")
> + fileName =
> + os.path.join(self.sourceRoot,fvName,self.target,fvName+".inf")
> try :
> file = open(fileName)
> except Exception:
> @@ -657,7 +656,7 @@ class FileChecker:
> if not line:
> break
>
> - newline = line[:-1]
> + newline = line[:-1].replace('\r','')
>
> if cmp (newline, "") == 0:
> continue
> @@ -681,7 +680,7 @@ class FileChecker:
> return Value
>
> def SetNewFvBase (self, fvName, PcdName, OldFvBase, NewFvBase):
> - fileName =
> os.path.join(self.sourceRoot,fvName+"\\"+self.target+"\\"+fvName+".inf")
> + fileName =
> + os.path.join(self.sourceRoot,fvName,self.target,fvName+".inf")
> print "update - " + fileName
> try :
> file = open(fileName, "r")
> @@ -698,7 +697,7 @@ class FileChecker:
> if not line:
> break
>
> - newline = line[:-1]
> + newline = line[:-1].strip()
>
> if cmp (newline, "") == 0:
> continue
> diff --git a/Platform/Intel/build_bios.py b/Platform/Intel/build_bios.py index
> a4ea093..9effefc 100644
> --- a/Platform/Intel/build_bios.py
> +++ b/Platform/Intel/build_bios.py
> @@ -135,12 +135,16 @@ def pre_build(build_config, build_type="DEBUG",
> silent=False, toolchain=None):
>
> # get the python path
> if os.environ.get("PYTHON_HOME") is None:
> - config["PYTHON_HOME"] = None
> if os.environ.get("PYTHONPATH") is not None:
> config["PYTHON_HOME"] = os.environ.get("PYTHONPATH")
> else:
> - print("PYTHONPATH environment variable is not found")
> - sys.exit(1)
> + config["PYTHON_HOME"] = os.path.dirname(sys.executable)
> + config["PYTHONPATH"] = config["PYTHON_HOME"]
> +
> + if config.get("PYTHON_HOME") is None or \
> + not os.path.exists(config.get("PYTHON_HOME")):
> + print("PYTHON_HOME environment variable is not found")
> + sys.exit(1)
>
> # if python is installed, disable the binary base tools.
> # python is installed if this code is running :) @@ -151,18 +155,18 @@ def
> pre_build(build_config, build_type="DEBUG", silent=False, toolchain=None):
> # Run edk setup and update config
> if os.name == 'nt':
> edk2_setup_cmd = [os.path.join(config["EFI_SOURCE"], "edksetup"),
> - "Rebuild"]
> + "Rebuild"]
>
> if config.get("EDK_SETUP_OPTION") and \
> - config["EDK_SETUP_OPTION"] != " ":
> + config["EDK_SETUP_OPTION"] != " ":
> edk2_setup_cmd.append(config["EDK_SETUP_OPTION"])
>
> _, _, result, return_code = execute_script(edk2_setup_cmd,
> - config,
> - collect_env=True,
> - shell=True)
> + config,
> + collect_env=True,
> + shell=True)
> if return_code == 0 and result is not None and isinstance(result,
> - dict):
> + dict):
> config.update(result)
>
> # nmake BaseTools source
> @@ -355,7 +359,11 @@ def build(config):
> command.append("-D")
> command.append("MAX_SOCKET=" + config["MAX_SOCKET"])
>
> - _, _, _, exit_code = execute_script(command, config)
> + shell = True
> + if os.name == "posix":
> + shell = False
> +
> + _, _, _, exit_code = execute_script(command, config, shell=shell)
> if exit_code != 0:
> build_failed(config)
>
> --
> 2.7.4
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [edk2-devel] [edk2-platforms] [PATCH v2 2/5] KabylakeSiliconPkg: Casting functions to EFIAPI
2019-05-21 3:08 ` [edk2-platforms] [PATCH v2 2/5] KabylakeSiliconPkg: Casting functions to EFIAPI Agyeman, Prince
@ 2019-05-22 19:08 ` Kubacki, Michael A
2019-05-22 19:11 ` Nate DeSimone
2019-05-23 0:18 ` Chiu, Chasel
2 siblings, 0 replies; 18+ messages in thread
From: Kubacki, Michael A @ 2019-05-22 19:08 UTC (permalink / raw)
To: devel@edk2.groups.io, Agyeman, Prince
Cc: Chiu, Chasel, Kinney, Michael D, Desimone, Nathaniel L,
Gao, Liming, Sinha, Ankit
Reviewed-by: Michael Kubacki <michael.a.kubacki@intel.com>
> -----Original Message-----
> From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> Agyeman, Prince
> Sent: Monday, May 20, 2019 8:08 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel <chasel.chiu@intel.com>; Agyeman, Prince
> <prince.agyeman@intel.com>; Kubacki, Michael A
> <michael.a.kubacki@intel.com>; Kinney, Michael D
> <michael.d.kinney@intel.com>; Desimone, Nathaniel L
> <nathaniel.l.desimone@intel.com>; Gao, Liming <liming.gao@intel.com>;
> Sinha, Ankit <ankit.sinha@intel.com>
> Subject: [edk2-devel] [edk2-platforms] [PATCH v2 2/5] KabylakeSiliconPkg:
> Casting functions to EFIAPI
>
> From: Prince Agyeman <prince.agyeman@intel.com>
>
> This fixes the calling convension issues in gcc
>
> Gcc build was tested on Ubuntu 16.04.5 LTS with gcc version 5.4.0, nasm
> version 2.11.08
>
> Cc: Michael Kubacki <michael.a.kubacki@intel.com>
> Cc: Michael D Kinney <michael.d.kinney@intel.com>
> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
> Cc: Liming Gao <liming.gao@intel.com>
> Cc: Ankit Sinha <ankit.sinha@intel.com>
>
> Signed-off-by: Prince Agyeman <prince.agyeman@intel.com>
> ---
> Silicon/Intel/KabylakeSiliconPkg/Pch/PchInit/Smm/PchInitSmm.h | 3 ++-
> Silicon/Intel/KabylakeSiliconPkg/Pch/PchInit/Smm/PchPcieSmm.c | 3 ++-
> Silicon/Intel/KabylakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmm.h |
> 4 +++-
> .../Intel/KabylakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmmCore.c |
> 4 +++-
> 4 files changed, 10 insertions(+), 4 deletions(-)
>
> diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/PchInit/Smm/PchInitSmm.h
> b/Silicon/Intel/KabylakeSiliconPkg/Pch/PchInit/Smm/PchInitSmm.h
> index 44f151c..666340e 100644
> --- a/Silicon/Intel/KabylakeSiliconPkg/Pch/PchInit/Smm/PchInitSmm.h
> +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/PchInit/Smm/PchInitSmm.h
> @@ -1,7 +1,7 @@
> /** @file
> Header file for PCH Init SMM Handler
>
> -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> **/
> @@ -205,6 +205,7 @@ PchPcieLinkEqHandlerFunction (
>
> **/
> VOID
> +EFIAPI
> PchPcieIoTrapSmiCallback (
> IN EFI_HANDLE DispatchHandle,
> IN EFI_SMM_IO_TRAP_CONTEXT *CallbackContext,
> diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/PchInit/Smm/PchPcieSmm.c
> b/Silicon/Intel/KabylakeSiliconPkg/Pch/PchInit/Smm/PchPcieSmm.c
> index aed33bb..847fbfb 100644
> --- a/Silicon/Intel/KabylakeSiliconPkg/Pch/PchInit/Smm/PchPcieSmm.c
> +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/PchInit/Smm/PchPcieSmm.c
> @@ -1,7 +1,7 @@
> /** @file
> PCH Pcie SMM Driver Entry
>
> -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> **/
> @@ -238,6 +238,7 @@ PchPciePmIoTrapSmiCallback (
>
> **/
> VOID
> +EFIAPI
> PchPcieIoTrapSmiCallback (
> IN EFI_HANDLE DispatchHandle,
> IN EFI_SMM_IO_TRAP_CONTEXT *CallbackContext,
> diff --git
> a/Silicon/Intel/KabylakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmm.h
> b/Silicon/Intel/KabylakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmm.h
> index 508832e..a9f0664 100644
> ---
> a/Silicon/Intel/KabylakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmm.h
> +++
> b/Silicon/Intel/KabylakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmm.h
> @@ -1,7 +1,7 @@
> /** @file
> Prototypes and defines for the PCH SMM Dispatcher.
>
> -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> **/
> @@ -510,6 +510,7 @@ typedef struct {
> registered and the SMI source has been enabled.
> **/
> EFI_STATUS
> +EFIAPI
> PchSmmCoreRegister (
> IN PCH_SMM_GENERIC_PROTOCOL *This,
> IN EFI_SMM_HANDLER_ENTRY_POINT2 DispatchFunction,
> @@ -530,6 +531,7 @@ PchSmmCoreRegister (
> @retval EFI_INVALID_PARAMETER Handle is invalid.
> **/
> EFI_STATUS
> +EFIAPI
> PchSmmCoreUnRegister (
> IN PCH_SMM_GENERIC_PROTOCOL *This,
> IN EFI_HANDLE *DispatchHandle
> diff --git
> a/Silicon/Intel/KabylakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmmCore
> .c
> b/Silicon/Intel/KabylakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmmCor
> e.c
> index 0c494bf..cb3bfba 100644
> ---
> a/Silicon/Intel/KabylakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmmCore
> .c
> +++
> b/Silicon/Intel/KabylakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmmCo
> +++ re.c
> @@ -2,7 +2,7 @@
> This driver is responsible for the registration of child drivers
> and the abstraction of the PCH SMI sources.
>
> -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> **/
> @@ -325,6 +325,7 @@ SmiInputValueDuplicateCheck (
> registered and the SMI source has been enabled.
> **/
> EFI_STATUS
> +EFIAPI
> PchSmmCoreRegister (
> IN PCH_SMM_GENERIC_PROTOCOL *This,
> IN EFI_SMM_HANDLER_ENTRY_POINT2 DispatchFunction,
> @@ -596,6 +597,7 @@ Error:
> @retval EFI_INVALID_PARAMETER Handle is invalid.
> **/
> EFI_STATUS
> +EFIAPI
> PchSmmCoreUnRegister (
> IN PCH_SMM_GENERIC_PROTOCOL *This,
> IN EFI_HANDLE *DispatchHandle
> --
> 2.7.4
>
>
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [edk2-platforms] [PATCH v2 1/5] MinPlatformPkg: Added GCC5 build support
2019-05-21 3:08 ` [edk2-platforms] [PATCH v2 1/5] MinPlatformPkg: " Agyeman, Prince
2019-05-22 19:08 ` Kubacki, Michael A
@ 2019-05-22 19:11 ` Nate DeSimone
2019-05-23 0:15 ` Chiu, Chasel
1 sibling, 1 reply; 18+ messages in thread
From: Nate DeSimone @ 2019-05-22 19:11 UTC (permalink / raw)
To: Agyeman, Prince, devel@edk2.groups.io
Cc: Chiu, Chasel, Kubacki, Michael A, Kinney, Michael D, Gao, Liming,
Sinha, Ankit
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
-----Original Message-----
From: Agyeman, Prince
Sent: Monday, May 20, 2019 8:08 PM
To: devel@edk2.groups.io
Cc: Chiu, Chasel <chasel.chiu@intel.com>; Agyeman, Prince <prince.agyeman@intel.com>; Kubacki, Michael A <michael.a.kubacki@intel.com>; Kinney, Michael D <michael.d.kinney@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Gao, Liming <liming.gao@intel.com>; Sinha, Ankit <ankit.sinha@intel.com>
Subject: [edk2-platforms] [PATCH v2 1/5] MinPlatformPkg: Added GCC5 build support
From: Prince Agyeman <prince.agyeman@intel.com>
Fixes:
* Replacing .asm and .S with nasm in SecFspWrapperPlatformSecLib for cross-platform build support
* Modified RuleInclude.fdf
* Modified python files to be OS independent
Gcc build was tested on Ubuntu 16.04.5 LTS with gcc version 5.4.0, nasm version 2.11.08
Cc: Michael Kubacki <michael.a.kubacki@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Ankit Sinha <ankit.sinha@intel.com>
Signed-off-by: Prince Agyeman <prince.agyeman@intel.com>
---
.../Ia32/PeiCoreEntry.S | 117 -------
.../Ia32/{PeiCoreEntry.asm => PeiCoreEntry.nasm} | 46 +--
.../SecFspWrapperPlatformSecLib/Ia32/SecEntry.S | 342 ---------------------
.../Ia32/{SecEntry.asm => SecEntry.nasm} | 132 ++++----
.../SecFspWrapperPlatformSecLib/Ia32/Stack.S | 67 ----
.../Ia32/{Stack.asm => Stack.nasm} | 39 ++-
.../SecFspWrapperPlatformSecLib.inf | 12 +-
.../MinPlatformPkg/Include/Fdf/RuleInclude.fdf | 6 +-
.../Tools/Fsp/RebaseAndPatchFspBinBaseAddress.py | 2 +-
.../MinPlatformPkg/Tools/PatchFv/PatchBinFv.py | 8 +-
.../MinPlatformPkg/Tools/PatchFv/RebaseBinFv.py | 15 +-
Platform/Intel/build_bios.py | 28 +-
12 files changed, 143 insertions(+), 671 deletions(-) delete mode 100644 Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/PeiCoreEntry.S
rename Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/{PeiCoreEntry.asm => PeiCoreEntry.nasm} (66%) delete mode 100644 Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.S
rename Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/{SecEntry.asm => SecEntry.nasm} (72%) delete mode 100644 Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Stack.S
rename Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/{Stack.asm => Stack.nasm} (59%)
diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/PeiCoreEntry.S b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/PeiCoreEntry.S
deleted file mode 100644
index 8c8356f..0000000
--- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/PeiCoreEntry.S
+++ /dev/null
@@ -1,117 +0,0 @@
-## @file
-# Find and call SecStartup
-#
-# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -##
-
-ASM_GLOBAL ASM_PFX(CallPeiCoreEntryPoint)
-ASM_PFX(CallPeiCoreEntryPoint):
- #
- # Obtain the hob list pointer
- #
- movl 0x4(%esp), %eax
- #
- # Obtain the stack information
- # ECX: start of range
- # EDX: end of range
- #
- movl 0x8(%esp), %ecx
- movl 0xC(%esp), %edx
-
- #
- # Platform init
- #
- pushal
- pushl %edx
- pushl %ecx
- pushl %eax
- call ASM_PFX(PlatformInit)
- popl %eax
- popl %eax
- popl %eax
- popal
-
- #
- # Set stack top pointer
- #
- movl %edx, %esp
-
- #
- # Push the hob list pointer
- #
- pushl %eax
-
- #
- # Save the value
- # ECX: start of range
- # EDX: end of range
- #
- movl %esp, %ebp
- pushl %ecx
- pushl %edx
-
- #
- # Push processor count to stack first, then BIST status (AP then BSP)
- #
- movl $1, %eax
- cpuid
- shr $16, %ebx
- andl $0x000000FF, %ebx
- cmp $1, %bl
- jae PushProcessorCount
-
- #
- # Some processors report 0 logical processors. Effectively 0 = 1.
- # So we fix up the processor count
- #
- inc %ebx
-
-PushProcessorCount:
- pushl %ebx
-
- #
- # We need to implement a long-term solution for BIST capture. For now, we just copy BSP BIST
- # for all processor threads
- #
- xorl %ecx, %ecx
- movb %bl, %cl
-PushBist:
- movd %mm0, %eax
- pushl %eax
- loop PushBist
-
- # Save Time-Stamp Counter
- movd %mm5, %eax
- pushl %eax
-
- movd %mm6, %eax
- pushl %eax
-
- #
- # Pass entry point of the PEI core
- #
- movl $0xFFFFFFE0, %edi
- pushl %ds:(%edi)
-
- #
- # Pass BFV into the PEI Core
- #
- movl $0xFFFFFFFC, %edi
- pushl %ds:(%edi)
-
- #
- # Pass stack size into the PEI Core
- #
- movl -4(%ebp), %ecx
- movl -8(%ebp), %edx
- pushl %ecx # RamBase
-
- subl %ecx, %edx
- pushl %edx # RamSize
-
- #
- # Pass Control into the PEI Core
- #
- call ASM_PFX(SecStartup)
diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/PeiCoreEntry.asm b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/PeiCoreEntry.nasm
similarity index 66%
rename from Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/PeiCoreEntry.asm
rename to Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/PeiCoreEntry.nasm
index c854067..5c5b788 100644
--- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/PeiCoreEntry.asm
+++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat
+++ formSecLib/Ia32/PeiCoreEntry.nasm
@@ -1,21 +1,25 @@
-;; @file
-; Find and call SecStartup
+;----------------------------------------------------------------------
+--------
;
-; Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent ; -;;
-
+; Module Name:
+;
+; PeiCoreEntry.nasm
+;
+; Abstract:
+;
+; Find and call SecStartup
+;
+;----------------------------------------------------------------------
+--------
-.686p
-.xmm
-.model flat, c
-.code
+SECTION .text
-EXTRN SecStartup:NEAR
-EXTRN PlatformInit:NEAR
+extern ASM_PFX(SecStartup)
+extern ASM_PFX(PlatformInit)
-CallPeiCoreEntryPoint PROC PUBLIC
+global ASM_PFX(CallPeiCoreEntryPoint)
+ASM_PFX(CallPeiCoreEntryPoint):
;
; Obtain the hob list pointer
;
@@ -26,7 +30,7 @@ CallPeiCoreEntryPoint PROC PUBLIC
; EDX: end of range
;
mov ecx, [esp+8]
- mov edx, [esp+0Ch]
+ mov edx, [esp+0xC]
;
; Platform init
@@ -35,7 +39,7 @@ CallPeiCoreEntryPoint PROC PUBLIC
push edx
push ecx
push eax
- call PlatformInit
+ call ASM_PFX(PlatformInit)
pop eax
pop eax
pop eax
@@ -66,7 +70,7 @@ CallPeiCoreEntryPoint PROC PUBLIC
mov eax, 1
cpuid
shr ebx, 16
- and ebx, 0000000FFh
+ and ebx, 0xFF
cmp bl, 1
jae PushProcessorCount
@@ -100,14 +104,14 @@ PushBist:
;
; Pass entry point of the PEI core
;
- mov edi, 0FFFFFFE0h
- push DWORD PTR ds:[edi]
+ mov edi, 0xFFFFFFE0
+ push DWORD [edi]
;
; Pass BFV into the PEI Core
;
- mov edi, 0FFFFFFFCh
- push DWORD PTR ds:[edi]
+ mov edi, 0xFFFFFFFC
+ push DWORD [edi]
;
; Pass stack size into the PEI Core
@@ -122,7 +126,5 @@ PushBist:
;
; Pass Control into the PEI Core
;
- call SecStartup
-CallPeiCoreEntryPoint ENDP
+ call ASM_PFX(SecStartup)
-END
diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.S b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.S
deleted file mode 100644
index 63c420a..0000000
--- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.S
+++ /dev/null
@@ -1,342 +0,0 @@
-## @file
-# This is the code that goes from real-mode to protected mode.
-# It consumes the reset vector, calls TempRamInit API from FSP binary.
-#
-# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -##
-
-#include "Fsp.h"
-
-ASM_GLOBAL ASM_PFX(_gPcd_FixedAtBuild_PcdFsptBaseAddress)
-ASM_GLOBAL ASM_PFX(_gPcd_FixedAtBuild_PcdFspTemporaryRamSize)
-
-ASM_GLOBAL ASM_PFX(_TEXT_REALMODE)
-ASM_PFX(_TEXT_REALMODE):
-#----------------------------------------------------------------------------
-#
-# Procedure: _ModuleEntryPoint
-#
-# Input: None
-#
-# Output: None
-#
-# Destroys: Assume all registers
-#
-# Description:
-#
-# Transition to non-paged flat-model protected mode from a
-# hard-coded GDT that provides exactly two descriptors.
-# This is a bare bones transition to protected mode only
-# used for a while in PEI and possibly DXE.
-#
-# After enabling protected mode, a far jump is executed to
-# transfer to PEI using the newly loaded GDT.
-#
-# Return: None
-#
-# MMX Usage:
-# MM0 = BIST State
-# MM5 = Save time-stamp counter value high32bit
-# MM6 = Save time-stamp counter value low32bit.
-#
-#----------------------------------------------------------------------------
-
-ASM_GLOBAL ASM_PFX(_ModuleEntryPoint)
-ASM_PFX(_ModuleEntryPoint):
- fninit # clear any pending Floating point exceptions
- #
- # Store the BIST value in mm0
- #
- movd %eax, %mm0
- cli
-
- #
- # Check INIT# is asserted by port 0xCF9
- #
- mov $0x0CF9, %dx
- in %dx, %al
- cmp $0x04, %al
- jnz NotWarmStart
-
- #
- # @note Issue warm reset, since if CPU only reset is issued not all MSRs are restored to their defaults
- #
- movw $0x0CF9, %dx
- movb $0x06, %al
- out %al, %dx
-
- #
- # Save time-stamp counter value
- # rdtsc load 64bit time-stamp counter to EDX:EAX
- #
- rdtsc
- movd %edx, %mm5
- movd %ecx, %mm6
-
- #
- # Load the GDT table in GdtDesc
- #
- movl $GdtDesc, %esi
- .byte 0x66
- lgdt %cs:(%si)
-
- #
- # Transition to 16 bit protected mode
- #
- movl %cr0, %eax # Get control register 0
- orl $0x00000003, %eax # Set PE bit (bit #0) & MP bit (bit #1)
- movl %eax, %cr0 # Activate protected mode
-
- movl %cr4, %eax # Get control register 4
- orl $0x00000600, %eax # Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10)
- movl %eax, %cr4
-
- #
- # Now we're in 16 bit protected mode
- # Set up the selectors for 32 bit protected mode entry
- #
- mov $SYS_DATA_SEL, %ax
- mov %ax, %ds
- mov %ax, %es
- mov %ax, %fs
- mov %ax, %gs
- mov %ax, %ss
-
- #
- # Transition to Flat 32 bit protected mode
- # The jump to a far pointer causes the transition to 32 bit mode
- #
- movl $ProtectedModeEntryLinearAddress, %esi
- jmp *%cs:(%si)
-
-ASM_GLOBAL ASM_PFX(_TEXT_PROTECTED_MODE)
-ASM_PFX(_TEXT_PROTECTED_MODE):
-
-#----------------------------------------------------------------------------
-#
-# Procedure: ProtectedModeEntryPoint
-#
-# Input: None
-#
-# Output: None
-#
-# Destroys: Assume all registers
-#
-# Description:
-#
-# This function handles:
-# Call two basic APIs from FSP binary
-# Initializes stack with some early data (BIST, PEI entry, etc)
-#
-# Return: None
-#
-#----------------------------------------------------------------------------
-
-ASM_GLOBAL ASM_PFX(ProtectedModeEntryPoint)
-ASM_PFX(ProtectedModeEntryPoint):
-
- # Find the fsp info header
- movl PcdGet32(PcdFsptBaseAddress), %edi
-
- movl FVH_SIGINATURE_OFFSET(%edi), %eax
- cmp $FVH_SIGINATURE_VALID_VALUE, %eax
- jnz FspHeaderNotFound
-
- xorl %eax, %eax
- movw FVH_EXTHEADER_OFFSET_OFFSET(%edi), %ax
- cmp $0x00, %ax
- jnz FspFvExtHeaderExist
-
- xorl %eax, %eax
- movw FVH_HEADER_LENGTH_OFFSET(%edi), %ax # Bypass Fv Header
- addl %eax, %edi
- jmp FspCheckFfsHeader
-
-FspFvExtHeaderExist:
- addl %eax, %edi
- movl FVH_EXTHEADER_SIZE_OFFSET(%edi), %eax # Bypass Ext Fv Header
- addl %eax, %edi
-
- # Round up to 8 byte alignment
- movl %edi, %eax
- andb $0x07, %al
- jz FspCheckFfsHeader
-
- and $0xFFFFFFF8, %edi
- add $0x08, %edi
-
-FspCheckFfsHeader:
- # Check the ffs guid
- movl (%edi), %eax
- cmp $FSP_HEADER_GUID_DWORD1, %eax
- jnz FspHeaderNotFound
-
- movl 0x4(%edi), %eax
- cmp $FSP_HEADER_GUID_DWORD2, %eax
- jnz FspHeaderNotFound
-
- movl 0x08(%edi), %eax
- cmp $FSP_HEADER_GUID_DWORD3, %eax
- jnz FspHeaderNotFound
-
- movl 0x0c(%edi), %eax
- cmp $FSP_HEADER_GUID_DWORD4, %eax
- jnz FspHeaderNotFound
-
- add $FFS_HEADER_SIZE_VALUE, %edi # Bypass the ffs header
-
- # Check the section type as raw section
- movb SECTION_HEADER_TYPE_OFFSET(%edi), %al
- cmp $0x19, %al
- jnz FspHeaderNotFound
-
- addl $RAW_SECTION_HEADER_SIZE_VALUE, %edi # Bypass the section header
- jmp FspHeaderFound
-
-FspHeaderNotFound:
- jmp .
-
-FspHeaderFound:
- # Get the fsp TempRamInit Api address
- movl FSP_HEADER_IMAGEBASE_OFFSET(%edi), %eax
- addl FSP_HEADER_TEMPRAMINIT_OFFSET(%edi), %eax
-
- # Setup the hardcode stack
- movl $TempRamInitStack, %esp
-
- # Call the fsp TempRamInit Api
- jmp *%eax
-
-TempRamInitDone:
- cmp $0x8000000E, %eax #Check if EFI_NOT_FOUND returned. Error code for Microcode Update not found.
- je CallSecFspInit #If microcode not found, don't hang, but continue.
-
- cmp $0x0, %eax
- jnz FspApiFailed
-
- # ECX: start of range
- # EDX: end of range
-CallSecFspInit:
- subl PcdGet32 (PcdFspTemporaryRamSize), %edx # TemporaryRam for FSP
- xorl %eax, %eax
- movl %edx, %esp
-
- # Align the stack at DWORD
- addl $3, %esp
- andl $0xFFFFFFFC, %esp
-
- pushl %edx
- pushl %ecx
- pushl %eax # zero - no hob list yet
- call ASM_PFX(CallPeiCoreEntryPoint)
-
-FspApiFailed:
- jmp .
-
-.align 0x10
-TempRamInitStack:
- .long TempRamInitDone
- .long FsptUpdDataPtr
-
-#
-# ROM-based Global-Descriptor Table for the Tiano PEI Phase -# -.align 0x10
-
-#
-# GDT[0]: 0x00: Null entry, never used.
-#
-.equ NULL_SEL, . - GdtBase # Selector [0]
-GdtBase:
-BootGdtTable:
- .long 0
- .long 0
-
-#
-# Linear data segment descriptor
-#
-.equ LINEAR_SEL, . - GdtBase # Selector [0x8]
- .word 0xFFFF # limit 0xFFFFF
- .word 0 # base 0
- .byte 0
- .byte 0x92 # present, ring 0, data, expand-up, writable
- .byte 0xCF # page-granular, 32-bit
- .byte 0
-
-#
-# Linear code segment descriptor
-#
-.equ LINEAR_CODE_SEL, . - GdtBase # Selector [0x10]
- .word 0xFFFF # limit 0xFFFFF
- .word 0 # base 0
- .byte 0
- .byte 0x9B # present, ring 0, data, expand-up, not-writable
- .byte 0xCF # page-granular, 32-bit
- .byte 0
-#
-# System data segment descriptor
-#
-.equ SYS_DATA_SEL, . - GdtBase # Selector [0x18]
- .word 0xFFFF # limit 0xFFFFF
- .word 0 # base 0
- .byte 0
- .byte 0x93 # present, ring 0, data, expand-up, not-writable
- .byte 0xCF # page-granular, 32-bit
- .byte 0
-
-#
-# System code segment descriptor
-#
-.equ SYS_CODE_SEL, . - GdtBase # Selector [0x20]
- .word 0xFFFF # limit 0xFFFFF
- .word 0 # base 0
- .byte 0
- .byte 0x9A # present, ring 0, data, expand-up, writable
- .byte 0xCF # page-granular, 32-bit
- .byte 0
-#
-# Spare segment descriptor
-#
-.equ SYS16_CODE_SEL, . - GdtBase # Selector [0x28]
- .word 0xFFFF # limit 0xFFFFF
- .word 0 # base 0
- .byte 0x0E # Changed from F000 to E000.
- .byte 0x9B # present, ring 0, code, expand-up, writable
- .byte 0x00 # byte-granular, 16-bit
- .byte 0
-#
-# Spare segment descriptor
-#
-.equ SYS16_DATA_SEL, . - GdtBase # Selector [0x30]
- .word 0xFFFF # limit 0xFFFF
- .word 0 # base 0
- .byte 0
- .byte 0x93 # present, ring 0, data, expand-up, not-writable
- .byte 0x00 # byte-granular, 16-bit
- .byte 0
-
-#
-# Spare segment descriptor
-#
-.equ SPARE5_SEL, . - GdtBase # Selector [0x38]
- .word 0 # limit 0
- .word 0 # base 0
- .byte 0
- .byte 0 # present, ring 0, data, expand-up, writable
- .byte 0 # page-granular, 32-bit
- .byte 0
-.equ GDT_SIZE, . - BootGdtTable # Size, in bytes
-
-#
-# GDT Descriptor
-#
-GdtDesc: # GDT descriptor
- .word GDT_SIZE - 1 # GDT limit
- .long BootGdtTable # GDT base address
-
-ASM_PFX(ProtectedModeEntryLinearAddress):
-ProtectedModeEntryLinearOffset:
- .long ProtectedModeEntryPoint # Offset of our 32 bit code
- .word LINEAR_CODE_SEL
diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.asm b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
similarity index 72%
rename from Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.asm
rename to Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
index 2886a37..7f6d771 100644
--- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.asm
+++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat
+++ formSecLib/Ia32/SecEntry.nasm
@@ -1,28 +1,28 @@
-;; @file
-; This is the code that goes from real-mode to protected mode.
-; It consumes the reset vector, calls TempRamInit API from FSP binary.
+;----------------------------------------------------------------------
+--------
;
-; Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
+; Module Name:
;
-;;
+; SecEntry.nasm
+;
+; Abstract:
+;
+; This is the code that goes from real-mode to protected mode.
+; It consumes the reset vector, calls TempRamInit API from FSP binary.
+;
+;----------------------------------------------------------------------
+--------
#include "Fsp.h"
-.686p
-.xmm
-.model small, c
-
-EXTRN CallPeiCoreEntryPoint:NEAR
-EXTRN BoardBeforeTempRamInit:NEAR
-EXTRN FsptUpdDataPtr:FAR
+SECTION .text
+extern ASM_PFX(CallPeiCoreEntryPoint)
+extern ASM_PFX(FsptUpdDataPtr)
+extern ASM_PFX(BoardBeforeTempRamInit)
; Pcds
-EXTRN PcdGet32 (PcdFsptBaseAddress):DWORD
-EXTRN PcdGet32(PcdFspTemporaryRamSize):DWORD
-
-_TEXT_REALMODE SEGMENT PARA PUBLIC USE16 'CODE'
- ASSUME CS:_TEXT_REALMODE, DS:_TEXT_REALMODE
+extern ASM_PFX(PcdGet32 (PcdFspTemporaryRamSize))
+extern ASM_PFX(PcdGet32 (PcdFsptBaseAddress))
;----------------------------------------------------------------------------
;
@@ -53,8 +53,10 @@ _TEXT_REALMODE SEGMENT PARA PUBLIC USE16 'CODE'
;
;----------------------------------------------------------------------------
+BITS 16
align 4
-_ModuleEntryPoint PROC NEAR C PUBLIC
+global ASM_PFX(_ModuleEntryPoint)
+ASM_PFX(_ModuleEntryPoint):
fninit ; clear any pending Floating point exceptions
;
; Store the BIST value in mm0
@@ -70,6 +72,7 @@ _ModuleEntryPoint PROC NEAR C PUBLIC
cmp al, 04h
jnz NotWarmStart
+
;
; @note Issue warm reset, since if CPU only reset is issued not all MSRs are restored to their defaults
;
@@ -78,7 +81,6 @@ _ModuleEntryPoint PROC NEAR C PUBLIC
out dx, al
NotWarmStart:
-
;
; Save time-stamp counter value
; rdtsc load 64bit time-stamp counter to EDX:EAX @@ -90,9 +92,9 @@ NotWarmStart:
;
; Load the GDT table in GdtDesc
;
- mov esi, OFFSET GdtDesc
+ mov esi, GdtDesc
DB 66h
- lgdt fword ptr cs:[si]
+ lgdt [cs:si]
;
; Transition to 16 bit protected mode @@ -120,14 +122,8 @@ NotWarmStart:
; Transition to Flat 32 bit protected mode
; The jump to a far pointer causes the transition to 32 bit mode
;
- mov esi, offset ProtectedModeEntryLinearAddress
- jmp fword ptr cs:[si]
-
-_ModuleEntryPoint ENDP
-_TEXT_REALMODE ENDS
-
-_TEXT_PROTECTED_MODE SEGMENT PARA PUBLIC USE32 'CODE'
- ASSUME CS:_TEXT_PROTECTED_MODE, DS:_TEXT_PROTECTED_MODE
+ mov esi, ProtectedModeEntryLinearAddress
+ jmp dword far [cs:si]
;----------------------------------------------------------------------------
;
@@ -149,69 +145,69 @@ _TEXT_PROTECTED_MODE SEGMENT PARA PUBLIC USE32 'CODE'
;
;----------------------------------------------------------------------------
+BITS 32
align 4
-ProtectedModeEntryPoint PROC NEAR PUBLIC
-
- ;
- ; Early board hooks
- ;
- mov esp, BoardBeforeTempRamInitRet
- jmp BoardBeforeTempRamInit
+ProtectedModeEntryPoint:
+ ;
+ ; Early board hooks
+ ;
+ mov esp, BoardBeforeTempRamInitRet
+ jmp ASM_PFX(BoardBeforeTempRamInit)
BoardBeforeTempRamInitRet:
; Find the fsp info header
- mov edi, PcdGet32 (PcdFsptBaseAddress)
+ mov edi, [ASM_PFX(PcdGet32 (PcdFsptBaseAddress))]
- mov eax, dword ptr [edi + FVH_SIGINATURE_OFFSET]
+ mov eax, dword [edi + FVH_SIGINATURE_OFFSET]
cmp eax, FVH_SIGINATURE_VALID_VALUE
jnz FspHeaderNotFound
xor eax, eax
- mov ax, word ptr [edi + FVH_EXTHEADER_OFFSET_OFFSET]
+ mov ax, word [edi + FVH_EXTHEADER_OFFSET_OFFSET]
cmp ax, 0
jnz FspFvExtHeaderExist
xor eax, eax
- mov ax, word ptr [edi + FVH_HEADER_LENGTH_OFFSET] ; Bypass Fv Header
+ mov ax, word [edi + FVH_HEADER_LENGTH_OFFSET] ; Bypass Fv Header
add edi, eax
jmp FspCheckFfsHeader
FspFvExtHeaderExist:
add edi, eax
- mov eax, dword ptr [edi + FVH_EXTHEADER_SIZE_OFFSET] ; Bypass Ext Fv Header
+ mov eax, dword [edi + FVH_EXTHEADER_SIZE_OFFSET] ; Bypass Ext Fv
+ Header
add edi, eax
; Round up to 8 byte alignment
mov eax, edi
and al, 07h
- jz FspCheckFfsHeader
+ jz FspCheckFfsHeader
and edi, 0FFFFFFF8h
add edi, 08h
FspCheckFfsHeader:
; Check the ffs guid
- mov eax, dword ptr [edi]
+ mov eax, dword [edi]
cmp eax, FSP_HEADER_GUID_DWORD1
- jnz FspHeaderNotFound
+ jnz FspHeaderNotFound
- mov eax, dword ptr [edi + 4]
+ mov eax, dword [edi + 4]
cmp eax, FSP_HEADER_GUID_DWORD2
- jnz FspHeaderNotFound
+ jnz FspHeaderNotFound
- mov eax, dword ptr [edi + 8]
+ mov eax, dword [edi + 8]
cmp eax, FSP_HEADER_GUID_DWORD3
- jnz FspHeaderNotFound
+ jnz FspHeaderNotFound
- mov eax, dword ptr [edi + 0Ch]
+ mov eax, dword [edi + 0Ch]
cmp eax, FSP_HEADER_GUID_DWORD4
- jnz FspHeaderNotFound
+ jnz FspHeaderNotFound
add edi, FFS_HEADER_SIZE_VALUE ; Bypass the ffs header
; Check the section type as raw section
- mov al, byte ptr [edi + SECTION_HEADER_TYPE_OFFSET]
+ mov al, byte [edi + SECTION_HEADER_TYPE_OFFSET]
cmp al, 019h
jnz FspHeaderNotFound
@@ -223,11 +219,11 @@ FspHeaderNotFound:
FspHeaderFound:
; Get the fsp TempRamInit Api address
- mov eax, dword ptr [edi + FSP_HEADER_IMAGEBASE_OFFSET]
- add eax, dword ptr [edi + FSP_HEADER_TEMPRAMINIT_OFFSET]
+ mov eax, dword [edi + FSP_HEADER_IMAGEBASE_OFFSET] add eax, dword
+ [edi + FSP_HEADER_TEMPRAMINIT_OFFSET]
; Setup the hardcode stack
- mov esp, OFFSET TempRamInitStack
+ mov esp, TempRamInitStack
; Call the fsp TempRamInit Api
jmp eax
@@ -242,7 +238,7 @@ TempRamInitDone:
; ECX: start of range
; EDX: end of range
CallSecFspInit:
- sub edx, PcdGet32 (PcdFspTemporaryRamSize) ; TemporaryRam for FSP
+ sub edx, [ASM_PFX(PcdGet32 (PcdFspTemporaryRamSize))] ; TemporaryRam for FSP
xor eax, eax
mov esp, edx
@@ -253,30 +249,29 @@ CallSecFspInit:
push edx
push ecx
push eax ; zero - no hob list yet
- call CallPeiCoreEntryPoint
+ call ASM_PFX(CallPeiCoreEntryPoint)
FspApiFailed:
jmp $
align 10h
TempRamInitStack:
- DD OFFSET TempRamInitDone
- DD OFFSET FsptUpdDataPtr ; TempRamInitParams
-
-ProtectedModeEntryPoint ENDP
+ DD TempRamInitDone
+ DD ASM_PFX(FsptUpdDataPtr); TempRamInitParams
;
; ROM-based Global-Descriptor Table for the Tiano PEI Phase ; align 16 -PUBLIC BootGdtTable
+global ASM_PFX(BootGdtTable)
;
; GDT[0]: 0x00: Null entry, never used.
;
NULL_SEL EQU $ - GDT_BASE ; Selector [0]
GDT_BASE:
-BootGdtTable DD 0
+ASM_PFX(BootGdtTable):
+ DD 0
DD 0
;
; Linear data segment descriptor
@@ -350,20 +345,17 @@ SPARE5_SEL EQU $ - GDT_BASE ; Selector [0x38]
DB 0 ; present, ring 0, data, expand-up, writable
DB 0 ; page-granular, 32-bit
DB 0
-GDT_SIZE EQU $ - BootGdtTable ; Size, in bytes
+GDT_SIZE EQU $ - GDT_BASE ; Size, in bytes
;
; GDT Descriptor
;
GdtDesc: ; GDT descriptor
DW GDT_SIZE - 1 ; GDT limit
- DD OFFSET BootGdtTable ; GDT base address
+ DD GDT_BASE ; GDT base address
-ProtectedModeEntryLinearAddress LABEL FWORD
-ProtectedModeEntryLinearOffset LABEL DWORD
- DD OFFSET ProtectedModeEntryPoint ; Offset of our 32 bit code
+ProtectedModeEntryLinearAddress:
+ProtectedModeEntryLinear:
+ DD ProtectedModeEntryPoint ; Offset of our 32 bit code
DW LINEAR_CODE_SEL
-
-_TEXT_PROTECTED_MODE ENDS
-END
diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Stack.S b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Stack.S
deleted file mode 100644
index 9953daa..0000000
--- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Stack.S
+++ /dev/null
@@ -1,67 +0,0 @@
-## @file
-# Switch the stack from temporary memory to permenent memory.
-#
-# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -##
-
-#------------------------------------------------------------------------------
-# VOID
-# EFIAPI
-# SecSwitchStack (
-# UINT32 TemporaryMemoryBase,
-# UINT32 PermanentMemoryBase
-# )
-#------------------------------------------------------------------------------
-ASM_GLOBAL ASM_PFX (SecSwitchStack)
-ASM_PFX(SecSwitchStack):
- #
- # Save standard registers so they can be used to change stack
- #
- pushl %eax
- pushl %ebx
- pushl %ecx
- pushl %edx
-
- #
- # !!CAUTION!! this function address's is pushed into stack after
- # migration of whole temporary memory, so need save it to permanent
- # memory at first!
- #
- movl 20(%esp), %ebx # Save the first parameter
- movl 24(%esp), %ecx # Save the second parameter
-
- #
- # Save this function's return address into permanent memory at first.
- # Then, Fixup the esp point to permanent memory
- #
- movl %esp, %eax
- subl %ebx, %eax
- addl %ecx, %eax
- movl 0(%esp), %edx # copy pushed register's value to permanent memory
- movl %edx, 0(%eax)
- movl 4(%esp), %edx
- movl %edx, 4(%eax)
- movl 8(%esp), %edx
- movl %edx, 8(%eax)
- movl 12(%esp), %edx
- movl %edx, 12(%eax)
- movl 16(%esp), %edx # Update this function's return address into permanent memory
- movl %edx, 16(%eax)
- movl %eax, %esp # From now, esp is pointed to permanent memory
-
- #
- # Fixup the ebp point to permanent memory
- #
- movl %ebp, %eax
- subl %ebx, %eax
- addl %ecx, %eax
- movl %eax, %ebp # From now, ebp is pointed to permanent memory
-
- popl %edx
- popl %ecx
- popl %ebx
- popl %eax
- ret
-
diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Stack.asm b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Stack.nasm
similarity index 59%
rename from Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Stack.asm
rename to Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Stack.nasm
index 1830240..47db32d 100644
--- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Stack.asm
+++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat
+++ formSecLib/Ia32/Stack.nasm
@@ -1,14 +1,14 @@
-;; @file
-; Switch the stack from temporary memory to permenent memory.
+;----------------------------------------------------------------------
+--------
;
-; Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
+; Abstract:
+;
+; Switch the stack from temporary memory to permanent memory.
;
-;;
+;----------------------------------------------------------------------
+--------
- .586p
- .model flat,C
- .code
+ SECTION .text
;------------------------------------------------------------------------------
; VOID
@@ -18,7 +18,8 @@
; UINT32 PermanentMemoryBase
; );
;------------------------------------------------------------------------------
-SecSwitchStack PROC
+global ASM_PFX(SecSwitchStack)
+ASM_PFX(SecSwitchStack):
;
; Save three register: eax, ebx, ecx
;
@@ -43,16 +44,16 @@ SecSwitchStack PROC
mov eax, esp
sub eax, ebx
add eax, ecx
- mov edx, dword ptr [esp] ; copy pushed register's value to permanent memory
- mov dword ptr [eax], edx
- mov edx, dword ptr [esp + 4]
- mov dword ptr [eax + 4], edx
- mov edx, dword ptr [esp + 8]
- mov dword ptr [eax + 8], edx
- mov edx, dword ptr [esp + 12]
- mov dword ptr [eax + 12], edx
- mov edx, dword ptr [esp + 16] ; Update this function's return address into permanent memory
- mov dword ptr [eax + 16], edx
+ mov edx, dword [esp] ; copy pushed register's value to permanent memory
+ mov dword [eax], edx
+ mov edx, dword [esp + 4]
+ mov dword [eax + 4], edx
+ mov edx, dword [esp + 8]
+ mov dword [eax + 8], edx
+ mov edx, dword [esp + 12]
+ mov dword [eax + 12], edx
+ mov edx, dword [esp + 16] ; Update this function's return address into permanent memory
+ mov dword [eax + 16], edx
mov esp, eax ; From now, esp is pointed to permanent memory
;
@@ -68,6 +69,4 @@ SecSwitchStack PROC
pop ebx
pop eax
ret
-SecSwitchStack ENDP
- END
diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
index 6f2c95a..5d77e9e 100644
--- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
+++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat
+++ formSecLib/SecFspWrapperPlatformSecLib.inf
@@ -1,10 +1,11 @@
## @file
# Provide FSP wrapper platform sec related function.
#
-# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights
+reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent #
+#
##
################################################################################
@@ -42,13 +43,10 @@
PlatformInit.c
[Sources.IA32]
- Ia32/SecEntry.asm
- Ia32/PeiCoreEntry.asm
- Ia32/Stack.asm
+ Ia32/SecEntry.nasm
+ Ia32/PeiCoreEntry.nasm
+ Ia32/Stack.nasm
Ia32/Fsp.h
- Ia32/SecEntry.S
- Ia32/PeiCoreEntry.S
- Ia32/Stack.S
################################################################################
#
diff --git a/Platform/Intel/MinPlatformPkg/Include/Fdf/RuleInclude.fdf b/Platform/Intel/MinPlatformPkg/Include/Fdf/RuleInclude.fdf
index c4c4315..a1a8964 100644
--- a/Platform/Intel/MinPlatformPkg/Include/Fdf/RuleInclude.fdf
+++ b/Platform/Intel/MinPlatformPkg/Include/Fdf/RuleInclude.fdf
@@ -1,7 +1,7 @@
## @file
# FDF file of Platform.
#
-# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights
+reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -25,7 +25,7 @@
[Rule.Common.PEI_CORE]
FILE PEI_CORE = $(NAMED_GUID) {
- PE32 PE32 Align = 32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ PE32 PE32 Align = 64 $(INF_OUTPUT)/$(MODULE_NAME).efi
UI STRING="$(MODULE_NAME)" Optional
VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
}
@@ -40,7 +40,7 @@
[Rule.Common.PEIM]
FILE PEIM = $(NAMED_GUID) {
PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
- PE32 PE32 Align = 32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ PE32 PE32 Align = 64 $(INF_OUTPUT)/$(MODULE_NAME).efi
UI STRING="$(MODULE_NAME)" Optional
VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
}
diff --git a/Platform/Intel/MinPlatformPkg/Tools/Fsp/RebaseAndPatchFspBinBaseAddress.py b/Platform/Intel/MinPlatformPkg/Tools/Fsp/RebaseAndPatchFspBinBaseAddress.py
index 496b977..167a0e0 100644
--- a/Platform/Intel/MinPlatformPkg/Tools/Fsp/RebaseAndPatchFspBinBaseAddress.py
+++ b/Platform/Intel/MinPlatformPkg/Tools/Fsp/RebaseAndPatchFspBinBaseAd
+++ dress.py
@@ -76,7 +76,7 @@ file.close()
pythontool = 'python'
if 'PYTHON_HOME' in os.environ:
pythontool = os.environ['PYTHON_HOME'] + os.sep + 'python'
-Process = subprocess.Popen(pythontool + " " + splitFspBinPath + " info -f" + fspBinFilePath, stdout=subprocess.PIPE)
+Process = subprocess.Popen([pythontool, splitFspBinPath,
+"info","-f",fspBinFilePath], stdout=subprocess.PIPE)
Output = Process.communicate()[0]
FsptInfo = Output.rsplit("FSP_M", 1);
for line in FsptInfo[1].split("\n"):
diff --git a/Platform/Intel/MinPlatformPkg/Tools/PatchFv/PatchBinFv.py b/Platform/Intel/MinPlatformPkg/Tools/PatchFv/PatchBinFv.py
index 5b49b6b..b98c951 100644
--- a/Platform/Intel/MinPlatformPkg/Tools/PatchFv/PatchBinFv.py
+++ b/Platform/Intel/MinPlatformPkg/Tools/PatchFv/PatchBinFv.py
@@ -1,6 +1,6 @@
## @ PatchBinFv.py
#
-# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights
+reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent # ## @@ -107,7 +107,7 @@ class FileChecker:
return
def ProcessFvInf(self, fvName):
- sourceFileName = os.path.join(self.sourceRoot,fvName+"\\"+self.target+"\\"+fvName+".inf")
+ sourceFileName =
+ os.path.join(self.sourceRoot,fvName,self.target,fvName+".inf")
print "\nprocessing - " + sourceFileName
fileGuid = self.GetInfFileGuid (sourceFileName)
print "FV NAME GUID - " + fileGuid @@ -137,7 +137,7 @@ class FileChecker:
self.PrintPcdList(self.InfPcdList)
def PatchFv(self, fvName):
- sourceFileName = os.path.join(self.sourceRoot,fvName+"\\"+self.target+"\\"+fvName+".fv")
+ sourceFileName =
+ os.path.join(self.sourceRoot,fvName,self.target,fvName+".Fv")
print "patching - " + sourceFileName
try :
@@ -161,7 +161,7 @@ class FileChecker:
print " [" + hex(offset) + "] " + binascii.hexlify(data[offset:offset+2]) + " <= " + binascii.hexlify(h)
data[offset:offset+2] = h
elif (cmp (pcd[4], "UINT32") == 0):
- l = struct.pack("L", int(pcd[3],16))
+ l = struct.pack("I", int(pcd[3],16))
print " [" + hex(offset) + "] " + binascii.hexlify(data[offset:offset+4]) + " <= " + binascii.hexlify(l)
data[offset:offset+4] = l
elif (cmp (pcd[4], "UINT64") == 0):
diff --git a/Platform/Intel/MinPlatformPkg/Tools/PatchFv/RebaseBinFv.py b/Platform/Intel/MinPlatformPkg/Tools/PatchFv/RebaseBinFv.py
index 321f7c5..149630e 100644
--- a/Platform/Intel/MinPlatformPkg/Tools/PatchFv/RebaseBinFv.py
+++ b/Platform/Intel/MinPlatformPkg/Tools/PatchFv/RebaseBinFv.py
@@ -1,9 +1,8 @@
## @ PatchBinFv.py
#
-# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights
+reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent # -##
import os
import re
@@ -541,7 +540,7 @@ class FileChecker:
print "PCD: " + pcd[0] + "|" + pcd[3] + " <== " + pcd[1] + "(" + pcd[2] + ")"
def RebaseFv(self, fvName, rebasePcd):
- sourceFileName = os.path.join(self.sourceRoot,fvName+"\\"+self.target+"\\"+fvName+".fv")
+ sourceFileName =
+ os.path.join(self.sourceRoot,fvName,self.target,fvName+".Fv")
print "rebasing(FV) - " + sourceFileName
try :
@@ -617,7 +616,7 @@ class FileChecker:
if not line:
break
- newline = line[:-1]
+ newline = line[:-1].replace('\r','')
if (cmp (newline, TargetPkg) == 0):
FoundPkg = True
@@ -645,7 +644,7 @@ class FileChecker:
def GetOldFvBase (self, fvName, PcdName):
ParseBase = False
Value = ""
- fileName = os.path.join(self.sourceRoot,fvName+"\\"+self.target+"\\"+fvName+".inf")
+ fileName =
+ os.path.join(self.sourceRoot,fvName,self.target,fvName+".inf")
try :
file = open(fileName)
except Exception:
@@ -657,7 +656,7 @@ class FileChecker:
if not line:
break
- newline = line[:-1]
+ newline = line[:-1].replace('\r','')
if cmp (newline, "") == 0:
continue
@@ -681,7 +680,7 @@ class FileChecker:
return Value
def SetNewFvBase (self, fvName, PcdName, OldFvBase, NewFvBase):
- fileName = os.path.join(self.sourceRoot,fvName+"\\"+self.target+"\\"+fvName+".inf")
+ fileName =
+ os.path.join(self.sourceRoot,fvName,self.target,fvName+".inf")
print "update - " + fileName
try :
file = open(fileName, "r")
@@ -698,7 +697,7 @@ class FileChecker:
if not line:
break
- newline = line[:-1]
+ newline = line[:-1].strip()
if cmp (newline, "") == 0:
continue
diff --git a/Platform/Intel/build_bios.py b/Platform/Intel/build_bios.py index a4ea093..9effefc 100644
--- a/Platform/Intel/build_bios.py
+++ b/Platform/Intel/build_bios.py
@@ -135,12 +135,16 @@ def pre_build(build_config, build_type="DEBUG", silent=False, toolchain=None):
# get the python path
if os.environ.get("PYTHON_HOME") is None:
- config["PYTHON_HOME"] = None
if os.environ.get("PYTHONPATH") is not None:
config["PYTHON_HOME"] = os.environ.get("PYTHONPATH")
else:
- print("PYTHONPATH environment variable is not found")
- sys.exit(1)
+ config["PYTHON_HOME"] = os.path.dirname(sys.executable)
+ config["PYTHONPATH"] = config["PYTHON_HOME"]
+
+ if config.get("PYTHON_HOME") is None or \
+ not os.path.exists(config.get("PYTHON_HOME")):
+ print("PYTHON_HOME environment variable is not found")
+ sys.exit(1)
# if python is installed, disable the binary base tools.
# python is installed if this code is running :) @@ -151,18 +155,18 @@ def pre_build(build_config, build_type="DEBUG", silent=False, toolchain=None):
# Run edk setup and update config
if os.name == 'nt':
edk2_setup_cmd = [os.path.join(config["EFI_SOURCE"], "edksetup"),
- "Rebuild"]
+ "Rebuild"]
if config.get("EDK_SETUP_OPTION") and \
- config["EDK_SETUP_OPTION"] != " ":
+ config["EDK_SETUP_OPTION"] != " ":
edk2_setup_cmd.append(config["EDK_SETUP_OPTION"])
_, _, result, return_code = execute_script(edk2_setup_cmd,
- config,
- collect_env=True,
- shell=True)
+ config,
+ collect_env=True,
+ shell=True)
if return_code == 0 and result is not None and isinstance(result,
- dict):
+ dict):
config.update(result)
# nmake BaseTools source
@@ -355,7 +359,11 @@ def build(config):
command.append("-D")
command.append("MAX_SOCKET=" + config["MAX_SOCKET"])
- _, _, _, exit_code = execute_script(command, config)
+ shell = True
+ if os.name == "posix":
+ shell = False
+
+ _, _, _, exit_code = execute_script(command, config, shell=shell)
if exit_code != 0:
build_failed(config)
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [edk2-devel] [edk2-platforms] [PATCH v2 2/5] KabylakeSiliconPkg: Casting functions to EFIAPI
2019-05-21 3:08 ` [edk2-platforms] [PATCH v2 2/5] KabylakeSiliconPkg: Casting functions to EFIAPI Agyeman, Prince
2019-05-22 19:08 ` [edk2-devel] " Kubacki, Michael A
@ 2019-05-22 19:11 ` Nate DeSimone
2019-05-23 0:18 ` Chiu, Chasel
2 siblings, 0 replies; 18+ messages in thread
From: Nate DeSimone @ 2019-05-22 19:11 UTC (permalink / raw)
To: devel@edk2.groups.io, Agyeman, Prince
Cc: Chiu, Chasel, Kubacki, Michael A, Kinney, Michael D, Gao, Liming,
Sinha, Ankit
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Agyeman, Prince
Sent: Monday, May 20, 2019 8:08 PM
To: devel@edk2.groups.io
Cc: Chiu, Chasel <chasel.chiu@intel.com>; Agyeman, Prince <prince.agyeman@intel.com>; Kubacki, Michael A <michael.a.kubacki@intel.com>; Kinney, Michael D <michael.d.kinney@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Gao, Liming <liming.gao@intel.com>; Sinha, Ankit <ankit.sinha@intel.com>
Subject: [edk2-devel] [edk2-platforms] [PATCH v2 2/5] KabylakeSiliconPkg: Casting functions to EFIAPI
From: Prince Agyeman <prince.agyeman@intel.com>
This fixes the calling convension issues in gcc
Gcc build was tested on Ubuntu 16.04.5 LTS with gcc version 5.4.0, nasm version 2.11.08
Cc: Michael Kubacki <michael.a.kubacki@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Ankit Sinha <ankit.sinha@intel.com>
Signed-off-by: Prince Agyeman <prince.agyeman@intel.com>
---
Silicon/Intel/KabylakeSiliconPkg/Pch/PchInit/Smm/PchInitSmm.h | 3 ++-
Silicon/Intel/KabylakeSiliconPkg/Pch/PchInit/Smm/PchPcieSmm.c | 3 ++-
Silicon/Intel/KabylakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmm.h | 4 +++-
.../Intel/KabylakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmmCore.c | 4 +++-
4 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/PchInit/Smm/PchInitSmm.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/PchInit/Smm/PchInitSmm.h
index 44f151c..666340e 100644
--- a/Silicon/Intel/KabylakeSiliconPkg/Pch/PchInit/Smm/PchInitSmm.h
+++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/PchInit/Smm/PchInitSmm.h
@@ -1,7 +1,7 @@
/** @file
Header file for PCH Init SMM Handler
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -205,6 +205,7 @@ PchPcieLinkEqHandlerFunction (
**/
VOID
+EFIAPI
PchPcieIoTrapSmiCallback (
IN EFI_HANDLE DispatchHandle,
IN EFI_SMM_IO_TRAP_CONTEXT *CallbackContext,
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/PchInit/Smm/PchPcieSmm.c b/Silicon/Intel/KabylakeSiliconPkg/Pch/PchInit/Smm/PchPcieSmm.c
index aed33bb..847fbfb 100644
--- a/Silicon/Intel/KabylakeSiliconPkg/Pch/PchInit/Smm/PchPcieSmm.c
+++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/PchInit/Smm/PchPcieSmm.c
@@ -1,7 +1,7 @@
/** @file
PCH Pcie SMM Driver Entry
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -238,6 +238,7 @@ PchPciePmIoTrapSmiCallback (
**/
VOID
+EFIAPI
PchPcieIoTrapSmiCallback (
IN EFI_HANDLE DispatchHandle,
IN EFI_SMM_IO_TRAP_CONTEXT *CallbackContext,
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmm.h b/Silicon/Intel/KabylakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmm.h
index 508832e..a9f0664 100644
--- a/Silicon/Intel/KabylakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmm.h
+++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmm.h
@@ -1,7 +1,7 @@
/** @file
Prototypes and defines for the PCH SMM Dispatcher.
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -510,6 +510,7 @@ typedef struct {
registered and the SMI source has been enabled.
**/
EFI_STATUS
+EFIAPI
PchSmmCoreRegister (
IN PCH_SMM_GENERIC_PROTOCOL *This,
IN EFI_SMM_HANDLER_ENTRY_POINT2 DispatchFunction,
@@ -530,6 +531,7 @@ PchSmmCoreRegister (
@retval EFI_INVALID_PARAMETER Handle is invalid.
**/
EFI_STATUS
+EFIAPI
PchSmmCoreUnRegister (
IN PCH_SMM_GENERIC_PROTOCOL *This,
IN EFI_HANDLE *DispatchHandle
diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmmCore.c b/Silicon/Intel/KabylakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmmCore.c
index 0c494bf..cb3bfba 100644
--- a/Silicon/Intel/KabylakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmmCore.c
+++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmmCo
+++ re.c
@@ -2,7 +2,7 @@
This driver is responsible for the registration of child drivers
and the abstraction of the PCH SMI sources.
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -325,6 +325,7 @@ SmiInputValueDuplicateCheck (
registered and the SMI source has been enabled.
**/
EFI_STATUS
+EFIAPI
PchSmmCoreRegister (
IN PCH_SMM_GENERIC_PROTOCOL *This,
IN EFI_SMM_HANDLER_ENTRY_POINT2 DispatchFunction,
@@ -596,6 +597,7 @@ Error:
@retval EFI_INVALID_PARAMETER Handle is invalid.
**/
EFI_STATUS
+EFIAPI
PchSmmCoreUnRegister (
IN PCH_SMM_GENERIC_PROTOCOL *This,
IN EFI_HANDLE *DispatchHandle
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [edk2-devel] [edk2-platforms] [PATCH v2 3/5] KabylakeOpenBoardPkg: Added GCC5 build support
2019-05-21 3:08 ` [edk2-platforms] [PATCH v2 3/5] KabylakeOpenBoardPkg: Added GCC5 build support Agyeman, Prince
@ 2019-05-22 19:11 ` Nate DeSimone
2019-05-23 0:19 ` Chiu, Chasel
1 sibling, 0 replies; 18+ messages in thread
From: Nate DeSimone @ 2019-05-22 19:11 UTC (permalink / raw)
To: devel@edk2.groups.io, Agyeman, Prince; +Cc: Chiu, Chasel
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Agyeman, Prince
Sent: Monday, May 20, 2019 8:08 PM
To: devel@edk2.groups.io
Cc: Chiu, Chasel <chasel.chiu@intel.com>; Agyeman, Prince <prince.agyeman@intel.com>
Subject: [edk2-devel] [edk2-platforms] [PATCH v2 3/5] KabylakeOpenBoardPkg: Added GCC5 build support
From: Prince Agyeman <prince.agyeman@intel.com>
Fixed:
* Include file paths in dec
* Gcc build options
Gcc build was tested on Ubuntu 16.04.5 LTS with gcc version 5.4.0, nasm version 2.11.08
Signed-off-by: Prince Agyeman <prince.agyeman@intel.com>
---
.../KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgBuildOption.dsc | 4 +++-
Platform/Intel/KabylakeOpenBoardPkg/OpenBoardPkg.dec | 6 +++---
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgBuildOption.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgBuildOption.dsc
index 04c5786..8e885cc 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgBuildOption.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgBuild
+++ Option.dsc
@@ -1,7 +1,7 @@
## @file
# platform build option configuration file.
#
-# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights
+reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -102,6 +102,7 @@ DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $( # For IA32 Specific Build Flag #
GCC: *_*_IA32_PP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+GCC: *_*_IA32_CC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015 -DASF_PEI -Wno-unused -Wl,--allow-multiple-definition
MSFT: *_*_IA32_ASM_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
MSFT: *_*_IA32_CC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015 -DASF_PEI
MSFT: *_*_IA32_VFRPP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
@@ -124,6 +125,7 @@ MSFT: *_*_IA32_ASLCC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_D
# For X64 Specific Build Flag
#
GCC: *_*_X64_PP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+GCC: *_*_X64_CC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015 -Wno-unused -Wl,--allow-multiple-definition
MSFT: *_*_X64_ASM_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
MSFT: *_*_X64_CC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015
MSFT: *_*_X64_VFRPP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/OpenBoardPkg.dec b/Platform/Intel/KabylakeOpenBoardPkg/OpenBoardPkg.dec
index e326598..68977d0 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/OpenBoardPkg.dec
+++ b/Platform/Intel/KabylakeOpenBoardPkg/OpenBoardPkg.dec
@@ -5,7 +5,7 @@
# INF files to generate AutoGen.c and AutoGen.h files # for the build infrastructure.
#
-# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights
+reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -20,8 +20,8 @@ PACKAGE_GUID = 0A8BA6E8-C8AC-4AC1-87AC-52772FA6AE5E
[Includes]
Include
-KabylakeRvp3\Include
-Features\Tbt\Include
+KabylakeRvp3/Include
+Features/Tbt/Include
[Guids]
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [edk2-devel] [edk2-platforms] [PATCH v2 4/5] ClevoOpenBoardPkg: Added GCC5 build support
2019-05-21 3:08 ` [edk2-platforms] [PATCH v2 4/5] ClevoOpenBoardPkg: " Agyeman, Prince
@ 2019-05-22 19:11 ` Nate DeSimone
0 siblings, 0 replies; 18+ messages in thread
From: Nate DeSimone @ 2019-05-22 19:11 UTC (permalink / raw)
To: devel@edk2.groups.io, Agyeman, Prince; +Cc: Chiu, Chasel
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Agyeman, Prince
Sent: Monday, May 20, 2019 8:08 PM
To: devel@edk2.groups.io
Cc: Chiu, Chasel <chasel.chiu@intel.com>; Agyeman, Prince <prince.agyeman@intel.com>
Subject: [edk2-devel] [edk2-platforms] [PATCH v2 4/5] ClevoOpenBoardPkg: Added GCC5 build support
From: Prince Agyeman <prince.agyeman@intel.com>
Fixes:
* include file paths
* gcc build options
Gcc build was tested on Ubuntu 16.04.5 LTS with gcc version 5.4.0, nasm version 2.11.08
Signed-off-by: Prince Agyeman <prince.agyeman@intel.com>
---
Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgBuildOption.dsc | 2 ++
Platform/Intel/ClevoOpenBoardPkg/OpenBoardPkg.dec | 4 ++--
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgBuildOption.dsc b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgBuildOption.dsc
index 2cfcfdf..31e7f41 100644
--- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgBuildOption.dsc
+++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgBuildOption.ds
+++ c
@@ -102,6 +102,7 @@ DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $( # For IA32 Specific Build Flag #
GCC: *_*_IA32_PP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+GCC: *_*_IA32_CC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015 -Wno-unused -Wl,--allow-multiple-definition
MSFT: *_*_IA32_ASM_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
MSFT: *_*_IA32_CC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015 -DASF_PEI
MSFT: *_*_IA32_VFRPP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
@@ -124,6 +125,7 @@ MSFT: *_*_IA32_ASLCC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_D
# For X64 Specific Build Flag
#
GCC: *_*_X64_PP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
+GCC: *_*_X64_CC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015 -Wno-unused -Wl,--allow-multiple-definition
MSFT: *_*_X64_ASM_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
MSFT: *_*_X64_CC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015
MSFT: *_*_X64_VFRPP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
diff --git a/Platform/Intel/ClevoOpenBoardPkg/OpenBoardPkg.dec b/Platform/Intel/ClevoOpenBoardPkg/OpenBoardPkg.dec
index 29816e3..28aedfe 100644
--- a/Platform/Intel/ClevoOpenBoardPkg/OpenBoardPkg.dec
+++ b/Platform/Intel/ClevoOpenBoardPkg/OpenBoardPkg.dec
@@ -18,8 +18,8 @@ PACKAGE_GUID = D04CCA80-5F71-478D-9A26-72BC751D0106
[Includes]
Include
-N1xxWU\Include
-Features\Tbt\Include
+N1xxWU/Include
+Features/Tbt/Include
[Guids]
gBoardModuleTokenSpaceGuid = {0x72d1fff7, 0xa42a, 0x4219, {0xb9, 0x95, 0x5a, 0x67, 0x53, 0x6e, 0xa4, 0x2a}}
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [edk2-devel] [edk2-platforms] [PATCH v2 5/5] Intel/Readme.md: Updated readme with linux build instructions
2019-05-21 3:08 ` [edk2-platforms] [PATCH v2 5/5] Intel/Readme.md: Updated readme with linux build instructions Agyeman, Prince
2019-05-21 3:20 ` Chiu, Chasel
2019-05-22 19:06 ` [edk2-devel] " Kubacki, Michael A
@ 2019-05-22 19:12 ` Nate DeSimone
2 siblings, 0 replies; 18+ messages in thread
From: Nate DeSimone @ 2019-05-22 19:12 UTC (permalink / raw)
To: devel@edk2.groups.io, Agyeman, Prince; +Cc: Chiu, Chasel
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Agyeman, Prince
Sent: Monday, May 20, 2019 8:08 PM
To: devel@edk2.groups.io
Cc: Chiu, Chasel <chasel.chiu@intel.com>; Agyeman, Prince <prince.agyeman@intel.com>
Subject: [edk2-devel] [edk2-platforms] [PATCH v2 5/5] Intel/Readme.md: Updated readme with linux build instructions
From: Prince Agyeman <prince.agyeman@intel.com>
Signed-off-by: Prince Agyeman <prince.agyeman@intel.com>
---
Platform/Intel/Readme.md | 42 ++++++++++++++++++++++++------------------
1 file changed, 24 insertions(+), 18 deletions(-)
diff --git a/Platform/Intel/Readme.md b/Platform/Intel/Readme.md index 1da5d0a..443fb40 100644
--- a/Platform/Intel/Readme.md
+++ b/Platform/Intel/Readme.md
@@ -107,9 +107,13 @@ return back to the minimum platform caller.
**Building with the python script**
-1. Open command window, go to the workspace directory, e.g. c:\Kabylake.
-2. Type "cd edk2-platforms\Platform\Intel -3. Type "python build_bios.py -p REPLACE_WITH_BOARD_NAME"
+1. Open command window, go to the workspace directory, e.g. c:\Kabylake
+or ~/Kabylake in the case of a linux OS 2. If using a linux OS
+ * Type "cd edk2"
+ * Type "source edksetup.sh"
+ * Type "cd ../" to go back to the workspace directory 3. Type "cd
+edk2-platforms/Platform/Intel 4. Type "python build_bios.py -p
+REPLACE_WITH_BOARD_NAME"
* build_bios.py arguments:
@@ -132,18 +136,19 @@ return back to the minimum platform caller.
| |
* For more information on build options
- * ``Type "python build_bios.py -h"``
+ * Type "python build_bios.py -h"
* Note
- * ``Python 2.7.16 and Python 3.7.3 compatible``
- * ``These python build scripts have been tested on Windows due to`` [cross-platform limitations](#Known-limitations)
+ * Python 2.7.16 and Python 3.7.3 compatible
+ * This python build script has been tested on Windows 10 and Ubuntu
+ 16.04.5 LTS
+ * See [cross-platform limitations](#Known-limitations)
* Configuration Files
- * ``The edk2-platforms\Platform\Intel\build.cfg file contains the default settings used by build_bios.py``
- * ``The default settings are under the DEFAULT_CONFIG section``
- * ``Each board can have a settings file that will override the edk2-platforms\Platform\Intel\build.cfg settings``
- * ``An example of a board specific settings:``
- * ``edk2-platforms\Platform\Intel\KabylakeOpenBoardPkg\KabylakeRvp3\build_config.cfg``
+ * The edk2-platforms\Platform\Intel\build.cfg file contains the
+ default settings used by build_bios.py
+ * The default settings are under the DEFAULT_CONFIG section
+ * Each board can have a settings file that will override the
+ edk2-platforms\Platform\Intel\build.cfg settings
+ * An example of a board specific settings:
+ *
+ edk2-platforms\Platform\Intel\KabylakeOpenBoardPkg\KabylakeRvp3\build_
+ config.cfg
* Workspace view of the build scripts
* <pre>
@@ -212,14 +217,13 @@ Users can also flash the UEFI firmware image to the highest area of the flash re
### **Known limitations**
-* All firmware projects can only build on Windows with the validated configuration below.
- * Cross-platform build support is work-in-progress.
-
**KabylakeOpenBoardPkg**
1. This firmware project has only been tested on the Intel KabylakeRvp3 board.
2. This firmware project has only been tested booting to Microsoft Windows 10 x64 with AHCI mode and Integrated Graphic
Device.
-3. This firmware project build has only been tested using the Microsoft Visual Studio 2015 compiler.
+3. The Windows build was tested on Windows 10 with Microsoft Visual Studio 2015.
+4. The Linux build was tested on Ubuntu 16.04.5 LTS with GCC version 5.4.0.
+5. The build was tested with NASM version 2.11.08.
**PurleyOpenBoardPkg**
1. This firmware project has only been tested on the Microsoft MtOlympus board.
@@ -228,9 +232,11 @@ Users can also flash the UEFI firmware image to the highest area of the flash re
**ClevoOpenBoardPkg**
1. Currently, support is only being added for the N1xxWU series of boards.
-2. The firmware project build has only been tested using the Microsoft Visual Studio 2015 compiler.
-3. The firmware project has not been tested on an actual board, it *should not* be expected to boot.
-4. The firmware project applies to all Clevo supported board configurations but is only being tested on System 76 Galago
+2. The Windows build was tested on Windows 10 with Microsoft Visual Studio 2015 compiler.
+3. The Linux build was tested on Ubuntu 16.04.5 LTS with GCC version 5.4.0.
+4. The build was tested with NASM version 2.11.08.
+5. The firmware project has not been tested on an actual board, it *should not* be expected to boot.
+6. The firmware project applies to all Clevo supported board
+configurations but is only being tested on System 76 Galago
Pro devices.
### **Planned Activities**
--
2.7.4
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [edk2-platforms] [PATCH v2 1/5] MinPlatformPkg: Added GCC5 build support
2019-05-22 19:11 ` Nate DeSimone
@ 2019-05-23 0:15 ` Chiu, Chasel
0 siblings, 0 replies; 18+ messages in thread
From: Chiu, Chasel @ 2019-05-23 0:15 UTC (permalink / raw)
To: Desimone, Nathaniel L, Agyeman, Prince, devel@edk2.groups.io
Cc: Kubacki, Michael A, Kinney, Michael D, Gao, Liming, Sinha, Ankit
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
> -----Original Message-----
> From: Desimone, Nathaniel L
> Sent: Thursday, May 23, 2019 3:12 AM
> To: Agyeman, Prince <prince.agyeman@intel.com>; devel@edk2.groups.io
> Cc: Chiu, Chasel <chasel.chiu@intel.com>; Kubacki, Michael A
> <michael.a.kubacki@intel.com>; Kinney, Michael D
> <michael.d.kinney@intel.com>; Gao, Liming <liming.gao@intel.com>; Sinha,
> Ankit <ankit.sinha@intel.com>
> Subject: RE: [edk2-platforms] [PATCH v2 1/5] MinPlatformPkg: Added GCC5
> build support
>
> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
>
> -----Original Message-----
> From: Agyeman, Prince
> Sent: Monday, May 20, 2019 8:08 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel <chasel.chiu@intel.com>; Agyeman, Prince
> <prince.agyeman@intel.com>; Kubacki, Michael A
> <michael.a.kubacki@intel.com>; Kinney, Michael D
> <michael.d.kinney@intel.com>; Desimone, Nathaniel L
> <nathaniel.l.desimone@intel.com>; Gao, Liming <liming.gao@intel.com>; Sinha,
> Ankit <ankit.sinha@intel.com>
> Subject: [edk2-platforms] [PATCH v2 1/5] MinPlatformPkg: Added GCC5 build
> support
>
> From: Prince Agyeman <prince.agyeman@intel.com>
>
> Fixes:
> * Replacing .asm and .S with nasm in SecFspWrapperPlatformSecLib for
> cross-platform build support
> * Modified RuleInclude.fdf
> * Modified python files to be OS independent
>
> Gcc build was tested on Ubuntu 16.04.5 LTS with gcc version 5.4.0, nasm version
> 2.11.08
>
> Cc: Michael Kubacki <michael.a.kubacki@intel.com>
> Cc: Michael D Kinney <michael.d.kinney@intel.com>
> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
> Cc: Liming Gao <liming.gao@intel.com>
> Cc: Ankit Sinha <ankit.sinha@intel.com>
>
> Signed-off-by: Prince Agyeman <prince.agyeman@intel.com>
> ---
> .../Ia32/PeiCoreEntry.S | 117 -------
> .../Ia32/{PeiCoreEntry.asm => PeiCoreEntry.nasm} | 46 +--
> .../SecFspWrapperPlatformSecLib/Ia32/SecEntry.S | 342 ---------------------
> .../Ia32/{SecEntry.asm => SecEntry.nasm} | 132 ++++----
> .../SecFspWrapperPlatformSecLib/Ia32/Stack.S | 67 ----
> .../Ia32/{Stack.asm => Stack.nasm} | 39 ++-
> .../SecFspWrapperPlatformSecLib.inf | 12 +-
> .../MinPlatformPkg/Include/Fdf/RuleInclude.fdf | 6 +-
> .../Tools/Fsp/RebaseAndPatchFspBinBaseAddress.py | 2 +-
> .../MinPlatformPkg/Tools/PatchFv/PatchBinFv.py | 8 +-
> .../MinPlatformPkg/Tools/PatchFv/RebaseBinFv.py | 15 +-
> Platform/Intel/build_bios.py | 28 +-
> 12 files changed, 143 insertions(+), 671 deletions(-) delete mode 100644
> Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformS
> ecLib/Ia32/PeiCoreEntry.S
> rename
> Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformS
> ecLib/Ia32/{PeiCoreEntry.asm => PeiCoreEntry.nasm} (66%) delete mode
> 100644
> Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformS
> ecLib/Ia32/SecEntry.S
> rename
> Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformS
> ecLib/Ia32/{SecEntry.asm => SecEntry.nasm} (72%) delete mode 100644
> Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformS
> ecLib/Ia32/Stack.S
> rename
> Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformS
> ecLib/Ia32/{Stack.asm => Stack.nasm} (59%)
>
> diff --git
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/Ia32/PeiCoreEntry.S
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/Ia32/PeiCoreEntry.S
> deleted file mode 100644
> index 8c8356f..0000000
> ---
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/Ia32/PeiCoreEntry.S
> +++ /dev/null
> @@ -1,117 +0,0 @@
> -## @file
> -# Find and call SecStartup
> -#
> -# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> -#
> SPDX-License-Identifier: BSD-2-Clause-Patent -# -##
> -
> -ASM_GLOBAL ASM_PFX(CallPeiCoreEntryPoint)
> -ASM_PFX(CallPeiCoreEntryPoint):
> - #
> - # Obtain the hob list pointer
> - #
> - movl 0x4(%esp), %eax
> - #
> - # Obtain the stack information
> - # ECX: start of range
> - # EDX: end of range
> - #
> - movl 0x8(%esp), %ecx
> - movl 0xC(%esp), %edx
> -
> - #
> - # Platform init
> - #
> - pushal
> - pushl %edx
> - pushl %ecx
> - pushl %eax
> - call ASM_PFX(PlatformInit)
> - popl %eax
> - popl %eax
> - popl %eax
> - popal
> -
> - #
> - # Set stack top pointer
> - #
> - movl %edx, %esp
> -
> - #
> - # Push the hob list pointer
> - #
> - pushl %eax
> -
> - #
> - # Save the value
> - # ECX: start of range
> - # EDX: end of range
> - #
> - movl %esp, %ebp
> - pushl %ecx
> - pushl %edx
> -
> - #
> - # Push processor count to stack first, then BIST status (AP then BSP)
> - #
> - movl $1, %eax
> - cpuid
> - shr $16, %ebx
> - andl $0x000000FF, %ebx
> - cmp $1, %bl
> - jae PushProcessorCount
> -
> - #
> - # Some processors report 0 logical processors. Effectively 0 = 1.
> - # So we fix up the processor count
> - #
> - inc %ebx
> -
> -PushProcessorCount:
> - pushl %ebx
> -
> - #
> - # We need to implement a long-term solution for BIST capture. For now, we
> just copy BSP BIST
> - # for all processor threads
> - #
> - xorl %ecx, %ecx
> - movb %bl, %cl
> -PushBist:
> - movd %mm0, %eax
> - pushl %eax
> - loop PushBist
> -
> - # Save Time-Stamp Counter
> - movd %mm5, %eax
> - pushl %eax
> -
> - movd %mm6, %eax
> - pushl %eax
> -
> - #
> - # Pass entry point of the PEI core
> - #
> - movl $0xFFFFFFE0, %edi
> - pushl %ds:(%edi)
> -
> - #
> - # Pass BFV into the PEI Core
> - #
> - movl $0xFFFFFFFC, %edi
> - pushl %ds:(%edi)
> -
> - #
> - # Pass stack size into the PEI Core
> - #
> - movl -4(%ebp), %ecx
> - movl -8(%ebp), %edx
> - pushl %ecx # RamBase
> -
> - subl %ecx, %edx
> - pushl %edx # RamSize
> -
> - #
> - # Pass Control into the PEI Core
> - #
> - call ASM_PFX(SecStartup)
> diff --git
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/Ia32/PeiCoreEntry.asm
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/Ia32/PeiCoreEntry.nasm
> similarity index 66%
> rename from
> Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformS
> ecLib/Ia32/PeiCoreEntry.asm
> rename to
> Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformS
> ecLib/Ia32/PeiCoreEntry.nasm
> index c854067..5c5b788 100644
> ---
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/Ia32/PeiCoreEntry.asm
> +++
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat
> +++ formSecLib/Ia32/PeiCoreEntry.nasm
> @@ -1,21 +1,25 @@
> -;; @file
> -; Find and call SecStartup
> +;----------------------------------------------------------------------
> +--------
> ;
> -; Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> +; Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; -;;
> -
> +; Module Name:
> +;
> +; PeiCoreEntry.nasm
> +;
> +; Abstract:
> +;
> +; Find and call SecStartup
> +;
> +;----------------------------------------------------------------------
> +--------
>
> -.686p
> -.xmm
> -.model flat, c
> -.code
> +SECTION .text
>
> -EXTRN SecStartup:NEAR
> -EXTRN PlatformInit:NEAR
> +extern ASM_PFX(SecStartup)
> +extern ASM_PFX(PlatformInit)
>
> -CallPeiCoreEntryPoint PROC PUBLIC
> +global ASM_PFX(CallPeiCoreEntryPoint)
> +ASM_PFX(CallPeiCoreEntryPoint):
> ;
> ; Obtain the hob list pointer
> ;
> @@ -26,7 +30,7 @@ CallPeiCoreEntryPoint PROC PUBLIC
> ; EDX: end of range
> ;
> mov ecx, [esp+8]
> - mov edx, [esp+0Ch]
> + mov edx, [esp+0xC]
>
> ;
> ; Platform init
> @@ -35,7 +39,7 @@ CallPeiCoreEntryPoint PROC PUBLIC
> push edx
> push ecx
> push eax
> - call PlatformInit
> + call ASM_PFX(PlatformInit)
> pop eax
> pop eax
> pop eax
> @@ -66,7 +70,7 @@ CallPeiCoreEntryPoint PROC PUBLIC
> mov eax, 1
> cpuid
> shr ebx, 16
> - and ebx, 0000000FFh
> + and ebx, 0xFF
> cmp bl, 1
> jae PushProcessorCount
>
> @@ -100,14 +104,14 @@ PushBist:
> ;
> ; Pass entry point of the PEI core
> ;
> - mov edi, 0FFFFFFE0h
> - push DWORD PTR ds:[edi]
> + mov edi, 0xFFFFFFE0
> + push DWORD [edi]
>
> ;
> ; Pass BFV into the PEI Core
> ;
> - mov edi, 0FFFFFFFCh
> - push DWORD PTR ds:[edi]
> + mov edi, 0xFFFFFFFC
> + push DWORD [edi]
>
> ;
> ; Pass stack size into the PEI Core
> @@ -122,7 +126,5 @@ PushBist:
> ;
> ; Pass Control into the PEI Core
> ;
> - call SecStartup
> -CallPeiCoreEntryPoint ENDP
> + call ASM_PFX(SecStartup)
>
> -END
> diff --git
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/Ia32/SecEntry.S
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/Ia32/SecEntry.S
> deleted file mode 100644
> index 63c420a..0000000
> ---
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/Ia32/SecEntry.S
> +++ /dev/null
> @@ -1,342 +0,0 @@
> -## @file
> -# This is the code that goes from real-mode to protected mode.
> -# It consumes the reset vector, calls TempRamInit API from FSP binary.
> -#
> -# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> -#
> SPDX-License-Identifier: BSD-2-Clause-Patent -# -##
> -
> -#include "Fsp.h"
> -
> -ASM_GLOBAL ASM_PFX(_gPcd_FixedAtBuild_PcdFsptBaseAddress)
> -ASM_GLOBAL ASM_PFX(_gPcd_FixedAtBuild_PcdFspTemporaryRamSize)
> -
> -ASM_GLOBAL ASM_PFX(_TEXT_REALMODE)
> -ASM_PFX(_TEXT_REALMODE):
> -#----------------------------------------------------------------------------
> -#
> -# Procedure: _ModuleEntryPoint
> -#
> -# Input: None
> -#
> -# Output: None
> -#
> -# Destroys: Assume all registers
> -#
> -# Description:
> -#
> -# Transition to non-paged flat-model protected mode from a
> -# hard-coded GDT that provides exactly two descriptors.
> -# This is a bare bones transition to protected mode only
> -# used for a while in PEI and possibly DXE.
> -#
> -# After enabling protected mode, a far jump is executed to
> -# transfer to PEI using the newly loaded GDT.
> -#
> -# Return: None
> -#
> -# MMX Usage:
> -# MM0 = BIST State
> -# MM5 = Save time-stamp counter value high32bit
> -# MM6 = Save time-stamp counter value low32bit.
> -#
> -#----------------------------------------------------------------------------
> -
> -ASM_GLOBAL ASM_PFX(_ModuleEntryPoint)
> -ASM_PFX(_ModuleEntryPoint):
> - fninit # clear any pending Floating point exceptions
> - #
> - # Store the BIST value in mm0
> - #
> - movd %eax, %mm0
> - cli
> -
> - #
> - # Check INIT# is asserted by port 0xCF9
> - #
> - mov $0x0CF9, %dx
> - in %dx, %al
> - cmp $0x04, %al
> - jnz NotWarmStart
> -
> - #
> - # @note Issue warm reset, since if CPU only reset is issued not all MSRs are
> restored to their defaults
> - #
> - movw $0x0CF9, %dx
> - movb $0x06, %al
> - out %al, %dx
> -
> - #
> - # Save time-stamp counter value
> - # rdtsc load 64bit time-stamp counter to EDX:EAX
> - #
> - rdtsc
> - movd %edx, %mm5
> - movd %ecx, %mm6
> -
> - #
> - # Load the GDT table in GdtDesc
> - #
> - movl $GdtDesc, %esi
> - .byte 0x66
> - lgdt %cs:(%si)
> -
> - #
> - # Transition to 16 bit protected mode
> - #
> - movl %cr0, %eax # Get control register 0
> - orl $0x00000003, %eax # Set PE bit (bit #0) & MP bit (bit #1)
> - movl %eax, %cr0 # Activate protected mode
> -
> - movl %cr4, %eax # Get control register 4
> - orl $0x00000600, %eax # Set OSFXSR bit (bit #9) & OSXMMEXCPT
> bit (bit #10)
> - movl %eax, %cr4
> -
> - #
> - # Now we're in 16 bit protected mode
> - # Set up the selectors for 32 bit protected mode entry
> - #
> - mov $SYS_DATA_SEL, %ax
> - mov %ax, %ds
> - mov %ax, %es
> - mov %ax, %fs
> - mov %ax, %gs
> - mov %ax, %ss
> -
> - #
> - # Transition to Flat 32 bit protected mode
> - # The jump to a far pointer causes the transition to 32 bit mode
> - #
> - movl $ProtectedModeEntryLinearAddress, %esi
> - jmp *%cs:(%si)
> -
> -ASM_GLOBAL ASM_PFX(_TEXT_PROTECTED_MODE)
> -ASM_PFX(_TEXT_PROTECTED_MODE):
> -
> -#----------------------------------------------------------------------------
> -#
> -# Procedure: ProtectedModeEntryPoint
> -#
> -# Input: None
> -#
> -# Output: None
> -#
> -# Destroys: Assume all registers
> -#
> -# Description:
> -#
> -# This function handles:
> -# Call two basic APIs from FSP binary
> -# Initializes stack with some early data (BIST, PEI entry, etc)
> -#
> -# Return: None
> -#
> -#----------------------------------------------------------------------------
> -
> -ASM_GLOBAL ASM_PFX(ProtectedModeEntryPoint)
> -ASM_PFX(ProtectedModeEntryPoint):
> -
> - # Find the fsp info header
> - movl PcdGet32(PcdFsptBaseAddress), %edi
> -
> - movl FVH_SIGINATURE_OFFSET(%edi), %eax
> - cmp $FVH_SIGINATURE_VALID_VALUE, %eax
> - jnz FspHeaderNotFound
> -
> - xorl %eax, %eax
> - movw FVH_EXTHEADER_OFFSET_OFFSET(%edi), %ax
> - cmp $0x00, %ax
> - jnz FspFvExtHeaderExist
> -
> - xorl %eax, %eax
> - movw FVH_HEADER_LENGTH_OFFSET(%edi), %ax # Bypass Fv Header
> - addl %eax, %edi
> - jmp FspCheckFfsHeader
> -
> -FspFvExtHeaderExist:
> - addl %eax, %edi
> - movl FVH_EXTHEADER_SIZE_OFFSET(%edi), %eax # Bypass Ext Fv Header
> - addl %eax, %edi
> -
> - # Round up to 8 byte alignment
> - movl %edi, %eax
> - andb $0x07, %al
> - jz FspCheckFfsHeader
> -
> - and $0xFFFFFFF8, %edi
> - add $0x08, %edi
> -
> -FspCheckFfsHeader:
> - # Check the ffs guid
> - movl (%edi), %eax
> - cmp $FSP_HEADER_GUID_DWORD1, %eax
> - jnz FspHeaderNotFound
> -
> - movl 0x4(%edi), %eax
> - cmp $FSP_HEADER_GUID_DWORD2, %eax
> - jnz FspHeaderNotFound
> -
> - movl 0x08(%edi), %eax
> - cmp $FSP_HEADER_GUID_DWORD3, %eax
> - jnz FspHeaderNotFound
> -
> - movl 0x0c(%edi), %eax
> - cmp $FSP_HEADER_GUID_DWORD4, %eax
> - jnz FspHeaderNotFound
> -
> - add $FFS_HEADER_SIZE_VALUE, %edi # Bypass the ffs header
> -
> - # Check the section type as raw section
> - movb SECTION_HEADER_TYPE_OFFSET(%edi), %al
> - cmp $0x19, %al
> - jnz FspHeaderNotFound
> -
> - addl $RAW_SECTION_HEADER_SIZE_VALUE, %edi # Bypass the section
> header
> - jmp FspHeaderFound
> -
> -FspHeaderNotFound:
> - jmp .
> -
> -FspHeaderFound:
> - # Get the fsp TempRamInit Api address
> - movl FSP_HEADER_IMAGEBASE_OFFSET(%edi), %eax
> - addl FSP_HEADER_TEMPRAMINIT_OFFSET(%edi), %eax
> -
> - # Setup the hardcode stack
> - movl $TempRamInitStack, %esp
> -
> - # Call the fsp TempRamInit Api
> - jmp *%eax
> -
> -TempRamInitDone:
> - cmp $0x8000000E, %eax #Check if EFI_NOT_FOUND returned. Error code
> for Microcode Update not found.
> - je CallSecFspInit #If microcode not found, don't hang, but continue.
> -
> - cmp $0x0, %eax
> - jnz FspApiFailed
> -
> - # ECX: start of range
> - # EDX: end of range
> -CallSecFspInit:
> - subl PcdGet32 (PcdFspTemporaryRamSize), %edx # TemporaryRam for FSP
> - xorl %eax, %eax
> - movl %edx, %esp
> -
> - # Align the stack at DWORD
> - addl $3, %esp
> - andl $0xFFFFFFFC, %esp
> -
> - pushl %edx
> - pushl %ecx
> - pushl %eax # zero - no hob list yet
> - call ASM_PFX(CallPeiCoreEntryPoint)
> -
> -FspApiFailed:
> - jmp .
> -
> -.align 0x10
> -TempRamInitStack:
> - .long TempRamInitDone
> - .long FsptUpdDataPtr
> -
> -#
> -# ROM-based Global-Descriptor Table for the Tiano PEI Phase -# -.align 0x10
> -
> -#
> -# GDT[0]: 0x00: Null entry, never used.
> -#
> -.equ NULL_SEL, . - GdtBase # Selector [0]
> -GdtBase:
> -BootGdtTable:
> - .long 0
> - .long 0
> -
> -#
> -# Linear data segment descriptor
> -#
> -.equ LINEAR_SEL, . - GdtBase # Selector [0x8]
> - .word 0xFFFF # limit 0xFFFFF
> - .word 0 # base 0
> - .byte 0
> - .byte 0x92 # present, ring 0, data, expand-up,
> writable
> - .byte 0xCF # page-granular, 32-bit
> - .byte 0
> -
> -#
> -# Linear code segment descriptor
> -#
> -.equ LINEAR_CODE_SEL, . - GdtBase # Selector [0x10]
> - .word 0xFFFF # limit 0xFFFFF
> - .word 0 # base 0
> - .byte 0
> - .byte 0x9B # present, ring 0, data, expand-up,
> not-writable
> - .byte 0xCF # page-granular, 32-bit
> - .byte 0
> -#
> -# System data segment descriptor
> -#
> -.equ SYS_DATA_SEL, . - GdtBase # Selector [0x18]
> - .word 0xFFFF # limit 0xFFFFF
> - .word 0 # base 0
> - .byte 0
> - .byte 0x93 # present, ring 0, data, expand-up,
> not-writable
> - .byte 0xCF # page-granular, 32-bit
> - .byte 0
> -
> -#
> -# System code segment descriptor
> -#
> -.equ SYS_CODE_SEL, . - GdtBase # Selector [0x20]
> - .word 0xFFFF # limit 0xFFFFF
> - .word 0 # base 0
> - .byte 0
> - .byte 0x9A # present, ring 0, data, expand-up,
> writable
> - .byte 0xCF # page-granular, 32-bit
> - .byte 0
> -#
> -# Spare segment descriptor
> -#
> -.equ SYS16_CODE_SEL, . - GdtBase # Selector [0x28]
> - .word 0xFFFF # limit 0xFFFFF
> - .word 0 # base 0
> - .byte 0x0E # Changed from F000 to E000.
> - .byte 0x9B # present, ring 0, code, expand-up,
> writable
> - .byte 0x00 # byte-granular, 16-bit
> - .byte 0
> -#
> -# Spare segment descriptor
> -#
> -.equ SYS16_DATA_SEL, . - GdtBase # Selector [0x30]
> - .word 0xFFFF # limit 0xFFFF
> - .word 0 # base 0
> - .byte 0
> - .byte 0x93 # present, ring 0, data, expand-up,
> not-writable
> - .byte 0x00 # byte-granular, 16-bit
> - .byte 0
> -
> -#
> -# Spare segment descriptor
> -#
> -.equ SPARE5_SEL, . - GdtBase # Selector [0x38]
> - .word 0 # limit 0
> - .word 0 # base 0
> - .byte 0
> - .byte 0 # present, ring 0, data, expand-up, writable
> - .byte 0 # page-granular, 32-bit
> - .byte 0
> -.equ GDT_SIZE, . - BootGdtTable # Size, in bytes
> -
> -#
> -# GDT Descriptor
> -#
> -GdtDesc: # GDT descriptor
> - .word GDT_SIZE - 1 # GDT limit
> - .long BootGdtTable # GDT base address
> -
> -ASM_PFX(ProtectedModeEntryLinearAddress):
> -ProtectedModeEntryLinearOffset:
> - .long ProtectedModeEntryPoint # Offset of our 32 bit code
> - .word LINEAR_CODE_SEL
> diff --git
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/Ia32/SecEntry.asm
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/Ia32/SecEntry.nasm
> similarity index 72%
> rename from
> Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformS
> ecLib/Ia32/SecEntry.asm
> rename to
> Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformS
> ecLib/Ia32/SecEntry.nasm
> index 2886a37..7f6d771 100644
> ---
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/Ia32/SecEntry.asm
> +++
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat
> +++ formSecLib/Ia32/SecEntry.nasm
> @@ -1,28 +1,28 @@
> -;; @file
> -; This is the code that goes from real-mode to protected mode.
> -; It consumes the reset vector, calls TempRamInit API from FSP binary.
> +;----------------------------------------------------------------------
> +--------
> ;
> -; Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> +; Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> ; SPDX-License-Identifier: BSD-2-Clause-Patent
> +; Module Name:
> ;
> -;;
> +; SecEntry.nasm
> +;
> +; Abstract:
> +;
> +; This is the code that goes from real-mode to protected mode.
> +; It consumes the reset vector, calls TempRamInit API from FSP binary.
> +;
> +;----------------------------------------------------------------------
> +--------
>
> #include "Fsp.h"
>
> -.686p
> -.xmm
> -.model small, c
> -
> -EXTRN CallPeiCoreEntryPoint:NEAR
> -EXTRN BoardBeforeTempRamInit:NEAR
> -EXTRN FsptUpdDataPtr:FAR
> +SECTION .text
>
> +extern ASM_PFX(CallPeiCoreEntryPoint)
> +extern ASM_PFX(FsptUpdDataPtr)
> +extern ASM_PFX(BoardBeforeTempRamInit)
> ; Pcds
> -EXTRN PcdGet32 (PcdFsptBaseAddress):DWORD
> -EXTRN PcdGet32(PcdFspTemporaryRamSize):DWORD
> -
> -_TEXT_REALMODE SEGMENT PARA PUBLIC USE16 'CODE'
> - ASSUME CS:_TEXT_REALMODE, DS:_TEXT_REALMODE
> +extern ASM_PFX(PcdGet32 (PcdFspTemporaryRamSize))
> +extern ASM_PFX(PcdGet32 (PcdFsptBaseAddress))
>
> ;----------------------------------------------------------------------------
> ;
> @@ -53,8 +53,10 @@ _TEXT_REALMODE SEGMENT PARA PUBLIC USE16
> 'CODE'
> ;
> ;----------------------------------------------------------------------------
>
> +BITS 16
> align 4
> -_ModuleEntryPoint PROC NEAR C PUBLIC
> +global ASM_PFX(_ModuleEntryPoint)
> +ASM_PFX(_ModuleEntryPoint):
> fninit ; clear any pending Floating point exceptions
> ;
> ; Store the BIST value in mm0
> @@ -70,6 +72,7 @@ _ModuleEntryPoint PROC NEAR C PUBLIC
> cmp al, 04h
> jnz NotWarmStart
>
> +
> ;
> ; @note Issue warm reset, since if CPU only reset is issued not all MSRs are
> restored to their defaults
> ;
> @@ -78,7 +81,6 @@ _ModuleEntryPoint PROC NEAR C PUBLIC
> out dx, al
>
> NotWarmStart:
> -
> ;
> ; Save time-stamp counter value
> ; rdtsc load 64bit time-stamp counter to EDX:EAX @@ -90,9 +92,9 @@
> NotWarmStart:
> ;
> ; Load the GDT table in GdtDesc
> ;
> - mov esi, OFFSET GdtDesc
> + mov esi, GdtDesc
> DB 66h
> - lgdt fword ptr cs:[si]
> + lgdt [cs:si]
>
> ;
> ; Transition to 16 bit protected mode @@ -120,14 +122,8 @@ NotWarmStart:
> ; Transition to Flat 32 bit protected mode
> ; The jump to a far pointer causes the transition to 32 bit mode
> ;
> - mov esi, offset ProtectedModeEntryLinearAddress
> - jmp fword ptr cs:[si]
> -
> -_ModuleEntryPoint ENDP
> -_TEXT_REALMODE ENDS
> -
> -_TEXT_PROTECTED_MODE SEGMENT PARA PUBLIC USE32 'CODE'
> - ASSUME CS:_TEXT_PROTECTED_MODE,
> DS:_TEXT_PROTECTED_MODE
> + mov esi, ProtectedModeEntryLinearAddress
> + jmp dword far [cs:si]
>
> ;----------------------------------------------------------------------------
> ;
> @@ -149,69 +145,69 @@ _TEXT_PROTECTED_MODE SEGMENT PARA
> PUBLIC USE32 'CODE'
> ;
> ;----------------------------------------------------------------------------
>
> +BITS 32
> align 4
> -ProtectedModeEntryPoint PROC NEAR PUBLIC
> -
> - ;
> - ; Early board hooks
> - ;
> - mov esp, BoardBeforeTempRamInitRet
> - jmp BoardBeforeTempRamInit
> +ProtectedModeEntryPoint:
> + ;
> + ; Early board hooks
> + ;
> + mov esp, BoardBeforeTempRamInitRet
> + jmp ASM_PFX(BoardBeforeTempRamInit)
>
> BoardBeforeTempRamInitRet:
>
> ; Find the fsp info header
> - mov edi, PcdGet32 (PcdFsptBaseAddress)
> + mov edi, [ASM_PFX(PcdGet32 (PcdFsptBaseAddress))]
>
> - mov eax, dword ptr [edi + FVH_SIGINATURE_OFFSET]
> + mov eax, dword [edi + FVH_SIGINATURE_OFFSET]
> cmp eax, FVH_SIGINATURE_VALID_VALUE
> jnz FspHeaderNotFound
>
> xor eax, eax
> - mov ax, word ptr [edi + FVH_EXTHEADER_OFFSET_OFFSET]
> + mov ax, word [edi + FVH_EXTHEADER_OFFSET_OFFSET]
> cmp ax, 0
> jnz FspFvExtHeaderExist
>
> xor eax, eax
> - mov ax, word ptr [edi + FVH_HEADER_LENGTH_OFFSET] ; Bypass Fv
> Header
> + mov ax, word [edi + FVH_HEADER_LENGTH_OFFSET] ; Bypass Fv Header
> add edi, eax
> jmp FspCheckFfsHeader
>
> FspFvExtHeaderExist:
> add edi, eax
> - mov eax, dword ptr [edi + FVH_EXTHEADER_SIZE_OFFSET] ; Bypass Ext Fv
> Header
> + mov eax, dword [edi + FVH_EXTHEADER_SIZE_OFFSET] ; Bypass Ext Fv
> + Header
> add edi, eax
>
> ; Round up to 8 byte alignment
> mov eax, edi
> and al, 07h
> - jz FspCheckFfsHeader
> + jz FspCheckFfsHeader
>
> and edi, 0FFFFFFF8h
> add edi, 08h
>
> FspCheckFfsHeader:
> ; Check the ffs guid
> - mov eax, dword ptr [edi]
> + mov eax, dword [edi]
> cmp eax, FSP_HEADER_GUID_DWORD1
> - jnz FspHeaderNotFound
> + jnz FspHeaderNotFound
>
> - mov eax, dword ptr [edi + 4]
> + mov eax, dword [edi + 4]
> cmp eax, FSP_HEADER_GUID_DWORD2
> - jnz FspHeaderNotFound
> + jnz FspHeaderNotFound
>
> - mov eax, dword ptr [edi + 8]
> + mov eax, dword [edi + 8]
> cmp eax, FSP_HEADER_GUID_DWORD3
> - jnz FspHeaderNotFound
> + jnz FspHeaderNotFound
>
> - mov eax, dword ptr [edi + 0Ch]
> + mov eax, dword [edi + 0Ch]
> cmp eax, FSP_HEADER_GUID_DWORD4
> - jnz FspHeaderNotFound
> + jnz FspHeaderNotFound
>
> add edi, FFS_HEADER_SIZE_VALUE ; Bypass the ffs header
>
> ; Check the section type as raw section
> - mov al, byte ptr [edi + SECTION_HEADER_TYPE_OFFSET]
> + mov al, byte [edi + SECTION_HEADER_TYPE_OFFSET]
> cmp al, 019h
> jnz FspHeaderNotFound
>
> @@ -223,11 +219,11 @@ FspHeaderNotFound:
>
> FspHeaderFound:
> ; Get the fsp TempRamInit Api address
> - mov eax, dword ptr [edi + FSP_HEADER_IMAGEBASE_OFFSET]
> - add eax, dword ptr [edi + FSP_HEADER_TEMPRAMINIT_OFFSET]
> + mov eax, dword [edi + FSP_HEADER_IMAGEBASE_OFFSET] add eax, dword
> + [edi + FSP_HEADER_TEMPRAMINIT_OFFSET]
>
> ; Setup the hardcode stack
> - mov esp, OFFSET TempRamInitStack
> + mov esp, TempRamInitStack
>
> ; Call the fsp TempRamInit Api
> jmp eax
> @@ -242,7 +238,7 @@ TempRamInitDone:
> ; ECX: start of range
> ; EDX: end of range
> CallSecFspInit:
> - sub edx, PcdGet32 (PcdFspTemporaryRamSize) ; TemporaryRam for FSP
> + sub edx, [ASM_PFX(PcdGet32 (PcdFspTemporaryRamSize))] ;
> TemporaryRam for FSP
> xor eax, eax
> mov esp, edx
>
> @@ -253,30 +249,29 @@ CallSecFspInit:
> push edx
> push ecx
> push eax ; zero - no hob list yet
> - call CallPeiCoreEntryPoint
> + call ASM_PFX(CallPeiCoreEntryPoint)
>
> FspApiFailed:
> jmp $
>
> align 10h
> TempRamInitStack:
> - DD OFFSET TempRamInitDone
> - DD OFFSET FsptUpdDataPtr ; TempRamInitParams
> -
> -ProtectedModeEntryPoint ENDP
> + DD TempRamInitDone
> + DD ASM_PFX(FsptUpdDataPtr); TempRamInitParams
>
> ;
> ; ROM-based Global-Descriptor Table for the Tiano PEI Phase ; align 16
> -PUBLIC BootGdtTable
> +global ASM_PFX(BootGdtTable)
>
> ;
> ; GDT[0]: 0x00: Null entry, never used.
> ;
> NULL_SEL EQU $ - GDT_BASE ; Selector [0]
> GDT_BASE:
> -BootGdtTable DD 0
> +ASM_PFX(BootGdtTable):
> + DD 0
> DD 0
> ;
> ; Linear data segment descriptor
> @@ -350,20 +345,17 @@ SPARE5_SEL EQU $ - GDT_BASE ; Selector
> [0x38]
> DB 0 ; present, ring 0, data, expand-up, writable
> DB 0 ; page-granular, 32-bit
> DB 0
> -GDT_SIZE EQU $ - BootGdtTable ; Size, in bytes
> +GDT_SIZE EQU $ - GDT_BASE ; Size, in bytes
>
> ;
> ; GDT Descriptor
> ;
> GdtDesc: ; GDT descriptor
> DW GDT_SIZE - 1 ; GDT limit
> - DD OFFSET BootGdtTable ; GDT base address
> + DD GDT_BASE ; GDT base address
>
>
> -ProtectedModeEntryLinearAddress LABEL FWORD
> -ProtectedModeEntryLinearOffset LABEL DWORD
> - DD OFFSET ProtectedModeEntryPoint ; Offset of our 32 bit code
> +ProtectedModeEntryLinearAddress:
> +ProtectedModeEntryLinear:
> + DD ProtectedModeEntryPoint ; Offset of our 32 bit code
> DW LINEAR_CODE_SEL
> -
> -_TEXT_PROTECTED_MODE ENDS
> -END
> diff --git
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/Ia32/Stack.S
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/Ia32/Stack.S
> deleted file mode 100644
> index 9953daa..0000000
> ---
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/Ia32/Stack.S
> +++ /dev/null
> @@ -1,67 +0,0 @@
> -## @file
> -# Switch the stack from temporary memory to permenent memory.
> -#
> -# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR> -#
> SPDX-License-Identifier: BSD-2-Clause-Patent -# -##
> -
> -#------------------------------------------------------------------------------
> -# VOID
> -# EFIAPI
> -# SecSwitchStack (
> -# UINT32 TemporaryMemoryBase,
> -# UINT32 PermanentMemoryBase
> -# )
> -#------------------------------------------------------------------------------
> -ASM_GLOBAL ASM_PFX (SecSwitchStack)
> -ASM_PFX(SecSwitchStack):
> - #
> - # Save standard registers so they can be used to change stack
> - #
> - pushl %eax
> - pushl %ebx
> - pushl %ecx
> - pushl %edx
> -
> - #
> - # !!CAUTION!! this function address's is pushed into stack after
> - # migration of whole temporary memory, so need save it to permanent
> - # memory at first!
> - #
> - movl 20(%esp), %ebx # Save the first parameter
> - movl 24(%esp), %ecx # Save the second parameter
> -
> - #
> - # Save this function's return address into permanent memory at first.
> - # Then, Fixup the esp point to permanent memory
> - #
> - movl %esp, %eax
> - subl %ebx, %eax
> - addl %ecx, %eax
> - movl 0(%esp), %edx # copy pushed register's value to permanent
> memory
> - movl %edx, 0(%eax)
> - movl 4(%esp), %edx
> - movl %edx, 4(%eax)
> - movl 8(%esp), %edx
> - movl %edx, 8(%eax)
> - movl 12(%esp), %edx
> - movl %edx, 12(%eax)
> - movl 16(%esp), %edx # Update this function's return address into
> permanent memory
> - movl %edx, 16(%eax)
> - movl %eax, %esp # From now, esp is pointed to permanent
> memory
> -
> - #
> - # Fixup the ebp point to permanent memory
> - #
> - movl %ebp, %eax
> - subl %ebx, %eax
> - addl %ecx, %eax
> - movl %eax, %ebp # From now, ebp is pointed to permanent
> memory
> -
> - popl %edx
> - popl %ecx
> - popl %ebx
> - popl %eax
> - ret
> -
> diff --git
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/Ia32/Stack.asm
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/Ia32/Stack.nasm
> similarity index 59%
> rename from
> Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformS
> ecLib/Ia32/Stack.asm
> rename to
> Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformS
> ecLib/Ia32/Stack.nasm
> index 1830240..47db32d 100644
> ---
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/Ia32/Stack.asm
> +++
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat
> +++ formSecLib/Ia32/Stack.nasm
> @@ -1,14 +1,14 @@
> -;; @file
> -; Switch the stack from temporary memory to permenent memory.
> +;----------------------------------------------------------------------
> +--------
> ;
> -; Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> +; Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> ; SPDX-License-Identifier: BSD-2-Clause-Patent
> +; Abstract:
> +;
> +; Switch the stack from temporary memory to permanent memory.
> ;
> -;;
> +;----------------------------------------------------------------------
> +--------
>
> - .586p
> - .model flat,C
> - .code
> + SECTION .text
>
> ;------------------------------------------------------------------------------
> ; VOID
> @@ -18,7 +18,8 @@
> ; UINT32 PermanentMemoryBase
> ; );
> ;------------------------------------------------------------------------------
> -SecSwitchStack PROC
> +global ASM_PFX(SecSwitchStack)
> +ASM_PFX(SecSwitchStack):
> ;
> ; Save three register: eax, ebx, ecx
> ;
> @@ -43,16 +44,16 @@ SecSwitchStack PROC
> mov eax, esp
> sub eax, ebx
> add eax, ecx
> - mov edx, dword ptr [esp] ; copy pushed register's value to
> permanent memory
> - mov dword ptr [eax], edx
> - mov edx, dword ptr [esp + 4]
> - mov dword ptr [eax + 4], edx
> - mov edx, dword ptr [esp + 8]
> - mov dword ptr [eax + 8], edx
> - mov edx, dword ptr [esp + 12]
> - mov dword ptr [eax + 12], edx
> - mov edx, dword ptr [esp + 16] ; Update this function's return address
> into permanent memory
> - mov dword ptr [eax + 16], edx
> + mov edx, dword [esp] ; copy pushed register's value to permanent
> memory
> + mov dword [eax], edx
> + mov edx, dword [esp + 4]
> + mov dword [eax + 4], edx
> + mov edx, dword [esp + 8]
> + mov dword [eax + 8], edx
> + mov edx, dword [esp + 12]
> + mov dword [eax + 12], edx
> + mov edx, dword [esp + 16] ; Update this function's return address into
> permanent memory
> + mov dword [eax + 16], edx
> mov esp, eax ; From now, esp is pointed to permanent
> memory
>
> ;
> @@ -68,6 +69,4 @@ SecSwitchStack PROC
> pop ebx
> pop eax
> ret
> -SecSwitchStack ENDP
>
> - END
> diff --git
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/SecFspWrapperPlatformSecLib.inf
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/SecFspWrapperPlatformSecLib.inf
> index 6f2c95a..5d77e9e 100644
> ---
> a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor
> mSecLib/SecFspWrapperPlatformSecLib.inf
> +++
> b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlat
> +++ formSecLib/SecFspWrapperPlatformSecLib.inf
> @@ -1,10 +1,11 @@
> ## @file
> # Provide FSP wrapper platform sec related function.
> #
> -# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> +# Copyright (c) 2017 - 2019, Intel Corporation. All rights
> +reserved.<BR>
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent #
> +#
> ##
>
>
> ################################################################
> ################
> @@ -42,13 +43,10 @@
> PlatformInit.c
>
> [Sources.IA32]
> - Ia32/SecEntry.asm
> - Ia32/PeiCoreEntry.asm
> - Ia32/Stack.asm
> + Ia32/SecEntry.nasm
> + Ia32/PeiCoreEntry.nasm
> + Ia32/Stack.nasm
> Ia32/Fsp.h
> - Ia32/SecEntry.S
> - Ia32/PeiCoreEntry.S
> - Ia32/Stack.S
>
>
> ################################################################
> ################
> #
> diff --git a/Platform/Intel/MinPlatformPkg/Include/Fdf/RuleInclude.fdf
> b/Platform/Intel/MinPlatformPkg/Include/Fdf/RuleInclude.fdf
> index c4c4315..a1a8964 100644
> --- a/Platform/Intel/MinPlatformPkg/Include/Fdf/RuleInclude.fdf
> +++ b/Platform/Intel/MinPlatformPkg/Include/Fdf/RuleInclude.fdf
> @@ -1,7 +1,7 @@
> ## @file
> # FDF file of Platform.
> #
> -# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> +# Copyright (c) 2017 - 2019, Intel Corporation. All rights
> +reserved.<BR>
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -25,7 +25,7 @@
>
> [Rule.Common.PEI_CORE]
> FILE PEI_CORE = $(NAMED_GUID) {
> - PE32 PE32 Align = 32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + PE32 PE32 Align = 64 $(INF_OUTPUT)/$(MODULE_NAME).efi
> UI STRING="$(MODULE_NAME)" Optional
> VERSION STRING="$(INF_VERSION)" Optional
> BUILD_NUM=$(BUILD_NUMBER)
> }
> @@ -40,7 +40,7 @@
> [Rule.Common.PEIM]
> FILE PEIM = $(NAMED_GUID) {
> PEI_DEPEX PEI_DEPEX Optional
> $(INF_OUTPUT)/$(MODULE_NAME).depex
> - PE32 PE32 Align = 32 $(INF_OUTPUT)/$(MODULE_NAME).efi
> + PE32 PE32 Align = 64 $(INF_OUTPUT)/$(MODULE_NAME).efi
> UI STRING="$(MODULE_NAME)" Optional
> VERSION STRING="$(INF_VERSION)" Optional
> BUILD_NUM=$(BUILD_NUMBER)
> }
> diff --git
> a/Platform/Intel/MinPlatformPkg/Tools/Fsp/RebaseAndPatchFspBinBaseAddr
> ess.py
> b/Platform/Intel/MinPlatformPkg/Tools/Fsp/RebaseAndPatchFspBinBaseAddr
> ess.py
> index 496b977..167a0e0 100644
> ---
> a/Platform/Intel/MinPlatformPkg/Tools/Fsp/RebaseAndPatchFspBinBaseAddr
> ess.py
> +++
> b/Platform/Intel/MinPlatformPkg/Tools/Fsp/RebaseAndPatchFspBinBaseAd
> +++ dress.py
> @@ -76,7 +76,7 @@ file.close()
> pythontool = 'python'
> if 'PYTHON_HOME' in os.environ:
> pythontool = os.environ['PYTHON_HOME'] + os.sep + 'python'
> -Process = subprocess.Popen(pythontool + " " + splitFspBinPath + " info -f" +
> fspBinFilePath, stdout=subprocess.PIPE)
> +Process = subprocess.Popen([pythontool, splitFspBinPath,
> +"info","-f",fspBinFilePath], stdout=subprocess.PIPE)
> Output = Process.communicate()[0]
> FsptInfo = Output.rsplit("FSP_M", 1);
> for line in FsptInfo[1].split("\n"):
> diff --git a/Platform/Intel/MinPlatformPkg/Tools/PatchFv/PatchBinFv.py
> b/Platform/Intel/MinPlatformPkg/Tools/PatchFv/PatchBinFv.py
> index 5b49b6b..b98c951 100644
> --- a/Platform/Intel/MinPlatformPkg/Tools/PatchFv/PatchBinFv.py
> +++ b/Platform/Intel/MinPlatformPkg/Tools/PatchFv/PatchBinFv.py
> @@ -1,6 +1,6 @@
> ## @ PatchBinFv.py
> #
> -# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> +# Copyright (c) 2017 - 2019, Intel Corporation. All rights
> +reserved.<BR>
> # SPDX-License-Identifier: BSD-2-Clause-Patent # ## @@ -107,7 +107,7 @@
> class FileChecker:
> return
>
> def ProcessFvInf(self, fvName):
> - sourceFileName =
> os.path.join(self.sourceRoot,fvName+"\\"+self.target+"\\"+fvName+".inf")
> + sourceFileName =
> + os.path.join(self.sourceRoot,fvName,self.target,fvName+".inf")
> print "\nprocessing - " + sourceFileName
> fileGuid = self.GetInfFileGuid (sourceFileName)
> print "FV NAME GUID - " + fileGuid @@ -137,7 +137,7 @@ class
> FileChecker:
> self.PrintPcdList(self.InfPcdList)
>
> def PatchFv(self, fvName):
> - sourceFileName =
> os.path.join(self.sourceRoot,fvName+"\\"+self.target+"\\"+fvName+".fv")
> + sourceFileName =
> + os.path.join(self.sourceRoot,fvName,self.target,fvName+".Fv")
> print "patching - " + sourceFileName
>
> try :
> @@ -161,7 +161,7 @@ class FileChecker:
> print " [" + hex(offset) + "] " +
> binascii.hexlify(data[offset:offset+2]) + " <= " + binascii.hexlify(h)
> data[offset:offset+2] = h
> elif (cmp (pcd[4], "UINT32") == 0):
> - l = struct.pack("L", int(pcd[3],16))
> + l = struct.pack("I", int(pcd[3],16))
> print " [" + hex(offset) + "] " +
> binascii.hexlify(data[offset:offset+4]) + " <= " + binascii.hexlify(l)
> data[offset:offset+4] = l
> elif (cmp (pcd[4], "UINT64") == 0):
> diff --git a/Platform/Intel/MinPlatformPkg/Tools/PatchFv/RebaseBinFv.py
> b/Platform/Intel/MinPlatformPkg/Tools/PatchFv/RebaseBinFv.py
> index 321f7c5..149630e 100644
> --- a/Platform/Intel/MinPlatformPkg/Tools/PatchFv/RebaseBinFv.py
> +++ b/Platform/Intel/MinPlatformPkg/Tools/PatchFv/RebaseBinFv.py
> @@ -1,9 +1,8 @@
> ## @ PatchBinFv.py
> #
> -# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> +# Copyright (c) 2017 - 2019, Intel Corporation. All rights
> +reserved.<BR>
> # SPDX-License-Identifier: BSD-2-Clause-Patent # -##
>
> import os
> import re
> @@ -541,7 +540,7 @@ class FileChecker:
> print "PCD: " + pcd[0] + "|" + pcd[3] + " <== " + pcd[1] + "(" + pcd[2] + ")"
>
> def RebaseFv(self, fvName, rebasePcd):
> - sourceFileName =
> os.path.join(self.sourceRoot,fvName+"\\"+self.target+"\\"+fvName+".fv")
> + sourceFileName =
> + os.path.join(self.sourceRoot,fvName,self.target,fvName+".Fv")
> print "rebasing(FV) - " + sourceFileName
>
> try :
> @@ -617,7 +616,7 @@ class FileChecker:
> if not line:
> break
>
> - newline = line[:-1]
> + newline = line[:-1].replace('\r','')
>
> if (cmp (newline, TargetPkg) == 0):
> FoundPkg = True
> @@ -645,7 +644,7 @@ class FileChecker:
> def GetOldFvBase (self, fvName, PcdName):
> ParseBase = False
> Value = ""
> - fileName =
> os.path.join(self.sourceRoot,fvName+"\\"+self.target+"\\"+fvName+".inf")
> + fileName =
> + os.path.join(self.sourceRoot,fvName,self.target,fvName+".inf")
> try :
> file = open(fileName)
> except Exception:
> @@ -657,7 +656,7 @@ class FileChecker:
> if not line:
> break
>
> - newline = line[:-1]
> + newline = line[:-1].replace('\r','')
>
> if cmp (newline, "") == 0:
> continue
> @@ -681,7 +680,7 @@ class FileChecker:
> return Value
>
> def SetNewFvBase (self, fvName, PcdName, OldFvBase, NewFvBase):
> - fileName =
> os.path.join(self.sourceRoot,fvName+"\\"+self.target+"\\"+fvName+".inf")
> + fileName =
> + os.path.join(self.sourceRoot,fvName,self.target,fvName+".inf")
> print "update - " + fileName
> try :
> file = open(fileName, "r")
> @@ -698,7 +697,7 @@ class FileChecker:
> if not line:
> break
>
> - newline = line[:-1]
> + newline = line[:-1].strip()
>
> if cmp (newline, "") == 0:
> continue
> diff --git a/Platform/Intel/build_bios.py b/Platform/Intel/build_bios.py index
> a4ea093..9effefc 100644
> --- a/Platform/Intel/build_bios.py
> +++ b/Platform/Intel/build_bios.py
> @@ -135,12 +135,16 @@ def pre_build(build_config, build_type="DEBUG",
> silent=False, toolchain=None):
>
> # get the python path
> if os.environ.get("PYTHON_HOME") is None:
> - config["PYTHON_HOME"] = None
> if os.environ.get("PYTHONPATH") is not None:
> config["PYTHON_HOME"] = os.environ.get("PYTHONPATH")
> else:
> - print("PYTHONPATH environment variable is not found")
> - sys.exit(1)
> + config["PYTHON_HOME"] = os.path.dirname(sys.executable)
> + config["PYTHONPATH"] = config["PYTHON_HOME"]
> +
> + if config.get("PYTHON_HOME") is None or \
> + not os.path.exists(config.get("PYTHON_HOME")):
> + print("PYTHON_HOME environment variable is not found")
> + sys.exit(1)
>
> # if python is installed, disable the binary base tools.
> # python is installed if this code is running :) @@ -151,18 +155,18 @@ def
> pre_build(build_config, build_type="DEBUG", silent=False, toolchain=None):
> # Run edk setup and update config
> if os.name == 'nt':
> edk2_setup_cmd = [os.path.join(config["EFI_SOURCE"], "edksetup"),
> - "Rebuild"]
> + "Rebuild"]
>
> if config.get("EDK_SETUP_OPTION") and \
> - config["EDK_SETUP_OPTION"] != " ":
> + config["EDK_SETUP_OPTION"] != " ":
> edk2_setup_cmd.append(config["EDK_SETUP_OPTION"])
>
> _, _, result, return_code = execute_script(edk2_setup_cmd,
> - config,
> - collect_env=True,
> - shell=True)
> + config,
> + collect_env=True,
> + shell=True)
> if return_code == 0 and result is not None and isinstance(result,
> - dict):
> + dict):
> config.update(result)
>
> # nmake BaseTools source
> @@ -355,7 +359,11 @@ def build(config):
> command.append("-D")
> command.append("MAX_SOCKET=" + config["MAX_SOCKET"])
>
> - _, _, _, exit_code = execute_script(command, config)
> + shell = True
> + if os.name == "posix":
> + shell = False
> +
> + _, _, _, exit_code = execute_script(command, config, shell=shell)
> if exit_code != 0:
> build_failed(config)
>
> --
> 2.7.4
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [edk2-platforms] [PATCH v2 2/5] KabylakeSiliconPkg: Casting functions to EFIAPI
2019-05-21 3:08 ` [edk2-platforms] [PATCH v2 2/5] KabylakeSiliconPkg: Casting functions to EFIAPI Agyeman, Prince
2019-05-22 19:08 ` [edk2-devel] " Kubacki, Michael A
2019-05-22 19:11 ` Nate DeSimone
@ 2019-05-23 0:18 ` Chiu, Chasel
2 siblings, 0 replies; 18+ messages in thread
From: Chiu, Chasel @ 2019-05-23 0:18 UTC (permalink / raw)
To: Agyeman, Prince, devel@edk2.groups.io
Cc: Kubacki, Michael A, Kinney, Michael D, Desimone, Nathaniel L,
Gao, Liming, Sinha, Ankit
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
> -----Original Message-----
> From: Agyeman, Prince
> Sent: Tuesday, May 21, 2019 11:08 AM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel <chasel.chiu@intel.com>; Agyeman, Prince
> <prince.agyeman@intel.com>; Kubacki, Michael A
> <michael.a.kubacki@intel.com>; Kinney, Michael D
> <michael.d.kinney@intel.com>; Desimone, Nathaniel L
> <nathaniel.l.desimone@intel.com>; Gao, Liming <liming.gao@intel.com>; Sinha,
> Ankit <ankit.sinha@intel.com>
> Subject: [edk2-platforms] [PATCH v2 2/5] KabylakeSiliconPkg: Casting functions
> to EFIAPI
>
> From: Prince Agyeman <prince.agyeman@intel.com>
>
> This fixes the calling convension issues in gcc
>
> Gcc build was tested on Ubuntu 16.04.5 LTS with gcc version 5.4.0, nasm version
> 2.11.08
>
> Cc: Michael Kubacki <michael.a.kubacki@intel.com>
> Cc: Michael D Kinney <michael.d.kinney@intel.com>
> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
> Cc: Liming Gao <liming.gao@intel.com>
> Cc: Ankit Sinha <ankit.sinha@intel.com>
>
> Signed-off-by: Prince Agyeman <prince.agyeman@intel.com>
> ---
> Silicon/Intel/KabylakeSiliconPkg/Pch/PchInit/Smm/PchInitSmm.h | 3
> ++-
> Silicon/Intel/KabylakeSiliconPkg/Pch/PchInit/Smm/PchPcieSmm.c | 3
> ++-
> Silicon/Intel/KabylakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmm.h |
> 4 +++-
> .../Intel/KabylakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmmCore.c |
> 4 +++-
> 4 files changed, 10 insertions(+), 4 deletions(-)
>
> diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/PchInit/Smm/PchInitSmm.h
> b/Silicon/Intel/KabylakeSiliconPkg/Pch/PchInit/Smm/PchInitSmm.h
> index 44f151c..666340e 100644
> --- a/Silicon/Intel/KabylakeSiliconPkg/Pch/PchInit/Smm/PchInitSmm.h
> +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/PchInit/Smm/PchInitSmm.h
> @@ -1,7 +1,7 @@
> /** @file
> Header file for PCH Init SMM Handler
>
> -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> **/
> @@ -205,6 +205,7 @@ PchPcieLinkEqHandlerFunction (
>
> **/
> VOID
> +EFIAPI
> PchPcieIoTrapSmiCallback (
> IN EFI_HANDLE DispatchHandle,
> IN EFI_SMM_IO_TRAP_CONTEXT *CallbackContext,
> diff --git a/Silicon/Intel/KabylakeSiliconPkg/Pch/PchInit/Smm/PchPcieSmm.c
> b/Silicon/Intel/KabylakeSiliconPkg/Pch/PchInit/Smm/PchPcieSmm.c
> index aed33bb..847fbfb 100644
> --- a/Silicon/Intel/KabylakeSiliconPkg/Pch/PchInit/Smm/PchPcieSmm.c
> +++ b/Silicon/Intel/KabylakeSiliconPkg/Pch/PchInit/Smm/PchPcieSmm.c
> @@ -1,7 +1,7 @@
> /** @file
> PCH Pcie SMM Driver Entry
>
> -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> **/
> @@ -238,6 +238,7 @@ PchPciePmIoTrapSmiCallback (
>
> **/
> VOID
> +EFIAPI
> PchPcieIoTrapSmiCallback (
> IN EFI_HANDLE DispatchHandle,
> IN EFI_SMM_IO_TRAP_CONTEXT *CallbackContext,
> diff --git
> a/Silicon/Intel/KabylakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmm.h
> b/Silicon/Intel/KabylakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmm.h
> index 508832e..a9f0664 100644
> --- a/Silicon/Intel/KabylakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmm.h
> +++
> b/Silicon/Intel/KabylakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmm.h
> @@ -1,7 +1,7 @@
> /** @file
> Prototypes and defines for the PCH SMM Dispatcher.
>
> -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> **/
> @@ -510,6 +510,7 @@ typedef struct {
> registered and the SMI source has been enabled.
> **/
> EFI_STATUS
> +EFIAPI
> PchSmmCoreRegister (
> IN PCH_SMM_GENERIC_PROTOCOL *This,
> IN EFI_SMM_HANDLER_ENTRY_POINT2 DispatchFunction,
> @@ -530,6 +531,7 @@ PchSmmCoreRegister (
> @retval EFI_INVALID_PARAMETER Handle is invalid.
> **/
> EFI_STATUS
> +EFIAPI
> PchSmmCoreUnRegister (
> IN PCH_SMM_GENERIC_PROTOCOL *This,
> IN EFI_HANDLE *DispatchHandle
> diff --git
> a/Silicon/Intel/KabylakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmmCore.
> c
> b/Silicon/Intel/KabylakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmmCore.
> c
> index 0c494bf..cb3bfba 100644
> ---
> a/Silicon/Intel/KabylakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmmCore.
> c
> +++
> b/Silicon/Intel/KabylakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmmCo
> +++ re.c
> @@ -2,7 +2,7 @@
> This driver is responsible for the registration of child drivers
> and the abstraction of the PCH SMI sources.
>
> -Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
> **/
> @@ -325,6 +325,7 @@ SmiInputValueDuplicateCheck (
> registered and the SMI source has been enabled.
> **/
> EFI_STATUS
> +EFIAPI
> PchSmmCoreRegister (
> IN PCH_SMM_GENERIC_PROTOCOL *This,
> IN EFI_SMM_HANDLER_ENTRY_POINT2 DispatchFunction,
> @@ -596,6 +597,7 @@ Error:
> @retval EFI_INVALID_PARAMETER Handle is invalid.
> **/
> EFI_STATUS
> +EFIAPI
> PchSmmCoreUnRegister (
> IN PCH_SMM_GENERIC_PROTOCOL *This,
> IN EFI_HANDLE *DispatchHandle
> --
> 2.7.4
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [edk2-devel] [edk2-platforms] [PATCH v2 3/5] KabylakeOpenBoardPkg: Added GCC5 build support
2019-05-21 3:08 ` [edk2-platforms] [PATCH v2 3/5] KabylakeOpenBoardPkg: Added GCC5 build support Agyeman, Prince
2019-05-22 19:11 ` [edk2-devel] " Nate DeSimone
@ 2019-05-23 0:19 ` Chiu, Chasel
1 sibling, 0 replies; 18+ messages in thread
From: Chiu, Chasel @ 2019-05-23 0:19 UTC (permalink / raw)
To: devel@edk2.groups.io, Agyeman, Prince
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
> -----Original Message-----
> From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> Agyeman, Prince
> Sent: Tuesday, May 21, 2019 11:08 AM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel <chasel.chiu@intel.com>; Agyeman, Prince
> <prince.agyeman@intel.com>
> Subject: [edk2-devel] [edk2-platforms] [PATCH v2 3/5] KabylakeOpenBoardPkg:
> Added GCC5 build support
>
> From: Prince Agyeman <prince.agyeman@intel.com>
>
> Fixed:
> * Include file paths in dec
> * Gcc build options
>
> Gcc build was tested on Ubuntu 16.04.5 LTS with gcc version 5.4.0, nasm version
> 2.11.08
>
> Signed-off-by: Prince Agyeman <prince.agyeman@intel.com>
> ---
> .../KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgBuildOption.dsc |
> 4 +++-
> Platform/Intel/KabylakeOpenBoardPkg/OpenBoardPkg.dec | 6
> +++---
> 2 files changed, 6 insertions(+), 4 deletions(-)
>
> diff --git
> a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgBuildO
> ption.dsc
> b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgBuild
> Option.dsc
> index 04c5786..8e885cc 100644
> ---
> a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgBuildO
> ption.dsc
> +++
> b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgBuild
> +++ Option.dsc
> @@ -1,7 +1,7 @@
> ## @file
> # platform build option configuration file.
> #
> -# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> +# Copyright (c) 2017 - 2019, Intel Corporation. All rights
> +reserved.<BR>
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -102,6 +102,7 @@
> DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $( # For IA32 Specific Build Flag #
> GCC: *_*_IA32_PP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
> +GCC: *_*_IA32_CC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
> -D PI_SPECIFICATION_VERSION=0x00010015 -DASF_PEI -Wno-unused
> -Wl,--allow-multiple-definition
> MSFT: *_*_IA32_ASM_FLAGS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
> MSFT: *_*_IA32_CC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
> $(OPTIMIZE_DISABLE_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015
> -DASF_PEI
> MSFT: *_*_IA32_VFRPP_FLAGS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
> @@ -124,6 +125,7 @@ MSFT: *_*_IA32_ASLCC_FLAGS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_D
> # For X64 Specific Build Flag
> #
> GCC: *_*_X64_PP_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
> +GCC: *_*_X64_CC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
> -D PI_SPECIFICATION_VERSION=0x00010015 -Wno-unused
> -Wl,--allow-multiple-definition
> MSFT: *_*_X64_ASM_FLAGS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
> MSFT: *_*_X64_CC_FLAGS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)
> $(OPTIMIZE_DISABLE_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015
> MSFT: *_*_X64_VFRPP_FLAGS =
> $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)
> diff --git a/Platform/Intel/KabylakeOpenBoardPkg/OpenBoardPkg.dec
> b/Platform/Intel/KabylakeOpenBoardPkg/OpenBoardPkg.dec
> index e326598..68977d0 100644
> --- a/Platform/Intel/KabylakeOpenBoardPkg/OpenBoardPkg.dec
> +++ b/Platform/Intel/KabylakeOpenBoardPkg/OpenBoardPkg.dec
> @@ -5,7 +5,7 @@
> # INF files to generate AutoGen.c and AutoGen.h files # for the build
> infrastructure.
> #
> -# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
> +# Copyright (c) 2017 - 2019, Intel Corporation. All rights
> +reserved.<BR>
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -20,8 +20,8 @@
> PACKAGE_GUID = 0A8BA6E8-C8AC-4AC1-87AC-52772FA6AE5E
>
> [Includes]
> Include
> -KabylakeRvp3\Include
> -Features\Tbt\Include
> +KabylakeRvp3/Include
> +Features/Tbt/Include
>
> [Guids]
>
> --
> 2.7.4
>
>
>
^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2019-05-23 0:19 UTC | newest]
Thread overview: 18+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2019-05-21 3:08 [edk2-platforms] [PATCH v2 0/5] Added GCC5 build support Agyeman, Prince
2019-05-21 3:08 ` [edk2-platforms] [PATCH v2 1/5] MinPlatformPkg: " Agyeman, Prince
2019-05-22 19:08 ` Kubacki, Michael A
2019-05-22 19:11 ` Nate DeSimone
2019-05-23 0:15 ` Chiu, Chasel
2019-05-21 3:08 ` [edk2-platforms] [PATCH v2 2/5] KabylakeSiliconPkg: Casting functions to EFIAPI Agyeman, Prince
2019-05-22 19:08 ` [edk2-devel] " Kubacki, Michael A
2019-05-22 19:11 ` Nate DeSimone
2019-05-23 0:18 ` Chiu, Chasel
2019-05-21 3:08 ` [edk2-platforms] [PATCH v2 3/5] KabylakeOpenBoardPkg: Added GCC5 build support Agyeman, Prince
2019-05-22 19:11 ` [edk2-devel] " Nate DeSimone
2019-05-23 0:19 ` Chiu, Chasel
2019-05-21 3:08 ` [edk2-platforms] [PATCH v2 4/5] ClevoOpenBoardPkg: " Agyeman, Prince
2019-05-22 19:11 ` [edk2-devel] " Nate DeSimone
2019-05-21 3:08 ` [edk2-platforms] [PATCH v2 5/5] Intel/Readme.md: Updated readme with linux build instructions Agyeman, Prince
2019-05-21 3:20 ` Chiu, Chasel
2019-05-22 19:06 ` [edk2-devel] " Kubacki, Michael A
2019-05-22 19:12 ` Nate DeSimone
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox