From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.24, mailfrom: michael.a.kubacki@intel.com) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by groups.io with SMTP; Mon, 19 Aug 2019 18:04:37 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 19 Aug 2019 18:04:36 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,407,1559545200"; d="scan'208";a="378382891" Received: from orsmsx106.amr.corp.intel.com ([10.22.225.133]) by fmsmga006.fm.intel.com with ESMTP; 19 Aug 2019 18:04:35 -0700 Received: from orsmsx163.amr.corp.intel.com (10.22.240.88) by ORSMSX106.amr.corp.intel.com (10.22.225.133) with Microsoft SMTP Server (TLS) id 14.3.439.0; Mon, 19 Aug 2019 18:04:35 -0700 Received: from orsmsx122.amr.corp.intel.com ([169.254.11.68]) by ORSMSX163.amr.corp.intel.com ([169.254.9.208]) with mapi id 14.03.0439.000; Mon, 19 Aug 2019 18:04:35 -0700 From: "Kubacki, Michael A" To: "Wei, David Y" , "devel@edk2.groups.io" CC: "Wu, Hao A" , "Gao, Liming" , "Sinha, Ankit" , "Agyeman, Prince" , "Desimone, Nathaniel L" , "Kinney, Michael D" Subject: Re: [edk2-platform patch 6/7] SimicsOpenBoardPkg: Add board module for QSP Build tip Thread-Topic: [edk2-platform patch 6/7] SimicsOpenBoardPkg: Add board module for QSP Build tip Thread-Index: AQHVTwRdfJq7n1yNKUGeLD+atKqoF6cDP5yQ Date: Tue, 20 Aug 2019 01:04:35 +0000 Message-ID: <49AB4ACB9627B8468F29D589A27B745588A5005B@ORSMSX122.amr.corp.intel.com> References: <082165cee163a6a3d0ce63f652b673e25c58d5c8.1565389186.git.david.y.wei@intel.com> In-Reply-To: <082165cee163a6a3d0ce63f652b673e25c58d5c8.1565389186.git.david.y.wei@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiMWFiNmJhNjAtOGYzMC00ZDY3LTk1YTAtZGE4NWYwZTBjNjlmIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiRzBSQnFqNktoVG9Sck1wYVRzSkdCc0ZQaHB1VEhldkZGc2M0RjRZMmtUSCt2M0lzTjN5YlVnXC9MdGJIc3VIYzYifQ== x-ctpclassification: CTP_NT dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-originating-ip: [10.22.254.139] MIME-Version: 1.0 Return-Path: michael.a.kubacki@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Feedback I could not find already noted elsewhere: 1. Remove the batch build files: - GitEdk2X58ICH10.bat - bld.bat - prebuild.bat The changes must be built with the Python scripts. 2. General comment that applies to multiple files: Files such as "PlatformPkgBuildOption.dsc" should follow the pre-exist= ing open board package naming convention. For example, "OpenBoardPkgBuildOption.dsc" in Kabyl= akeOpenBoardPkg. 3. The first commit line should be "SimicsOpenBoardPkg/BoardX58Ich10 to ind= icate the files relative to their location in that board directory. 4. Some build option macros in here seem unnecessary. For example, "PURLEY_= FLAG". Can you please check and clean this up? 5. PlatformPkgConfig.dsc: The following PCDs should not always be TRUE as t= hey originate in the AdvancedFeaturePkg and should only be enabled for an advanced feature = boot. - gAdvancedFeaturePkgTokenSpaceGuid.PcdNetworkEnable - gAdvancedFeaturePkgTokenSpaceGuid.PcdSmbiosEnable > -----Original Message----- > From: Wei, David Y > Sent: Friday, August 9, 2019 3:47 PM > To: devel@edk2.groups.io > Cc: Wu, Hao A ; Gao, Liming ; > Sinha, Ankit ; Agyeman, Prince > ; Kubacki, Michael A > ; Desimone, Nathaniel L > ; Kinney, Michael D > > Subject: [edk2-platform patch 6/7] SimicsOpenBoardPkg: Add board module > for QSP Build tip >=20 > Add BoardX58ICH10 module for QSP Build tip >=20 > Cc: Hao Wu > Cc: Liming Gao > Cc: Ankit Sinha > Cc: Agyeman Prince > Cc: Kubacki Michael A > Cc: Nate DeSimone > Cc: Michael D Kinney > Contributed-under: TianoCore Contribution Agreement 1.0 >=20 > Signed-off-by: David Wei > --- > .../Library/BoardInitLib/PeiBoardInitPostMemLib.c | 44 +++ > .../Library/BoardInitLib/PeiBoardInitPreMemLib.c | 110 ++++++++ > .../Library/BoardInitLib/PeiX58ICH10Detect.c | 26 ++ > .../BoardInitLib/PeiX58ICH10InitPostMemLib.c | 34 +++ > .../BoardInitLib/PeiX58ICH10InitPreMemLib.c | 111 ++++++++ > .../BoardX58ICH10/DecomprScratchEnd.fdf.inc | 66 +++++ > .../BoardX58ICH10/GitEdk2X58ICH10.bat | 75 +++++ > .../BoardInitLib/PeiBoardInitPostMemLib.inf | 36 +++ > .../Library/BoardInitLib/PeiBoardInitPreMemLib.inf | 38 +++ > .../Library/BoardInitLib/PeiX58ICH10InitLib.h | 16 ++ > .../BoardX58ICH10/PlatformPkgBuildOption.dsc | 89 ++++++ > .../BoardX58ICH10/PlatformPkgConfig.dsc | 56 ++++ > .../BoardX58ICH10/PlatformPkgPcd.dsc | 283 +++++++++++++++= ++++ > .../BoardX58ICH10/SimicsX58Pkg.fdf.inc | 48 ++++ > .../BoardX58ICH10/SimicsX58PkgIa32X64.dsc | 244 +++++++++++++++= ++ > .../BoardX58ICH10/SimicsX58PkgIa32X64.fdf | 303 > +++++++++++++++++++++ > .../BoardX58ICH10/VarStore.fdf.inc | 53 ++++ > .../Intel/SimicsOpenBoardPkg/BoardX58ICH10/bld.bat | 139 ++++++++++ > .../BoardX58ICH10/build_config.cfg | 31 +++ > .../SimicsOpenBoardPkg/BoardX58ICH10/prebuild.bat | 198 > ++++++++++++++ > 20 files changed, 2000 insertions(+) > create mode 100644 > Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/Library/BoardInitLib/PeiB > oardInitPostMemLib.c > create mode 100644 > Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/Library/BoardInitLib/PeiB > oardInitPreMemLib.c > create mode 100644 > Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/Library/BoardInitLib/PeiX > 58ICH10Detect.c > create mode 100644 > Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/Library/BoardInitLib/PeiX > 58ICH10InitPostMemLib.c > create mode 100644 > Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/Library/BoardInitLib/PeiX > 58ICH10InitPreMemLib.c > create mode 100644 > Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/DecomprScratchEnd.fdf.i > nc > create mode 100644 > Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/GitEdk2X58ICH10.bat > create mode 100644 > Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/Library/BoardInitLib/PeiB > oardInitPostMemLib.inf > create mode 100644 > Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/Library/BoardInitLib/PeiB > oardInitPreMemLib.inf > create mode 100644 > Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/Library/BoardInitLib/PeiX > 58ICH10InitLib.h > create mode 100644 > Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/PlatformPkgBuildOption. > dsc > create mode 100644 > Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/PlatformPkgConfig.dsc > create mode 100644 > Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/PlatformPkgPcd.dsc > create mode 100644 > Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/SimicsX58Pkg.fdf.inc > create mode 100644 > Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/SimicsX58PkgIa32X64.ds > c > create mode 100644 > Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/SimicsX58PkgIa32X64.fdf > create mode 100644 > Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/VarStore.fdf.inc > create mode 100644 > Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/bld.bat > create mode 100644 > Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/build_config.cfg > create mode 100644 > Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/prebuild.bat >=20 > diff --git > a/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/Library/BoardInitLib/Pe > iBoardInitPostMemLib.c > b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/Library/BoardInitLib/Pe > iBoardInitPostMemLib.c > new file mode 100644 > index 0000000000..29df3d41ee > --- /dev/null > +++ > b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/Library/BoardInitLib/Pe > iBoardInitPostMemLib.c > @@ -0,0 +1,44 @@ > +/** @file > + Copyright (c) 2018 Intel Corporation. All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include > +#include > +#include > +#include > +#include > +#include > + > +EFI_STATUS > +EFIAPI > +X58ICH10BoardInitBeforeSiliconInit ( > + VOID > + ); > + > +EFI_STATUS > +EFIAPI > +X58ICH10BoardInitAfterSiliconInit ( > + VOID > + ); > + > +EFI_STATUS > +EFIAPI > +BoardInitBeforeSiliconInit ( > + VOID > + ) > +{ > + X58ICH10BoardInitBeforeSiliconInit (); > + return EFI_SUCCESS; > +} > + > +EFI_STATUS > +EFIAPI > +BoardInitAfterSiliconInit ( > + VOID > + ) > +{ > + X58ICH10BoardInitAfterSiliconInit (); > + return EFI_SUCCESS; > +} > diff --git > a/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/Library/BoardInitLib/Pe > iBoardInitPreMemLib.c > b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/Library/BoardInitLib/Pe > iBoardInitPreMemLib.c > new file mode 100644 > index 0000000000..228fd696df > --- /dev/null > +++ > b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/Library/BoardInitLib/Pe > iBoardInitPreMemLib.c > @@ -0,0 +1,110 @@ > +/** @file > + Copyright (c) 2018 Intel Corporation. All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include > +#include > +#include > +#include > +#include > +#include > + > +EFI_STATUS > +EFIAPI > +X58ICH10BoardDetect( > + VOID > + ); > + > +EFI_BOOT_MODE > +EFIAPI > +X58ICH10BoardBootModeDetect ( > + VOID > + ); > + > +EFI_STATUS > +EFIAPI > +X58ICH10BoardDebugInit ( > + VOID > + ); > + > +EFI_STATUS > +EFIAPI > +X58ICH10BoardInitBeforeMemoryInit ( > + VOID > + ); > + > +EFI_STATUS > +EFIAPI > +X58ICH10BoardInitAfterMemoryInit ( > + VOID > + ); > + > +EFI_STATUS > +EFIAPI > +BoardDetect ( > + VOID > + ) > +{ > + X58ICH10BoardDetect (); > + return EFI_SUCCESS; > +} > + > +EFI_STATUS > +EFIAPI > +BoardDebugInit ( > + VOID > + ) > +{ > + X58ICH10BoardDebugInit (); > + return EFI_SUCCESS; > +} > + > +EFI_BOOT_MODE > +EFIAPI > +BoardBootModeDetect ( > + VOID > + ) > +{ > + return X58ICH10BoardBootModeDetect (); > +} > + > +EFI_STATUS > +EFIAPI > +BoardInitBeforeMemoryInit ( > + VOID > + ) > +{ > + X58ICH10BoardInitBeforeMemoryInit (); > + return EFI_SUCCESS; > +} > + > +EFI_STATUS > +EFIAPI > +BoardInitAfterMemoryInit ( > + VOID > + ) > +{ > + X58ICH10BoardInitAfterMemoryInit (); > + return EFI_SUCCESS; > +} > + > +EFI_STATUS > +EFIAPI > +BoardInitBeforeTempRamExit ( > + VOID > + ) > +{ > + return EFI_SUCCESS; > +} > + > +EFI_STATUS > +EFIAPI > +BoardInitAfterTempRamExit ( > + VOID > + ) > +{ > + return EFI_SUCCESS; > +} > + > diff --git > a/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/Library/BoardInitLib/Pe > iX58ICH10Detect.c > b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/Library/BoardInitLib/Pe > iX58ICH10Detect.c > new file mode 100644 > index 0000000000..7305ce3181 > --- /dev/null > +++ > b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/Library/BoardInitLib/Pe > iX58ICH10Detect.c > @@ -0,0 +1,26 @@ > +/** @file > + Copyright (c) 2018 Intel Corporation. All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +EFI_STATUS > +EFIAPI > +X58ICH10BoardDetect ( > + VOID > + ) > +{ > + DEBUG ((EFI_D_INFO, "X58ICH10BoardDetect\n")); > + return EFI_SUCCESS; > +} > diff --git > a/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/Library/BoardInitLib/Pe > iX58ICH10InitPostMemLib.c > b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/Library/BoardInitLib/Pe > iX58ICH10InitPostMemLib.c > new file mode 100644 > index 0000000000..002f63a434 > --- /dev/null > +++ > b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/Library/BoardInitLib/Pe > iX58ICH10InitPostMemLib.c > @@ -0,0 +1,34 @@ > +/** @file > + Copyright (c) 2018 Intel Corporation. All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include "PeiX58ICH10InitLib.h" > +EFI_STATUS > +EFIAPI > +X58ICH10BoardInitBeforeSiliconInit ( > + VOID > + ) > +{ > + return EFI_SUCCESS; > +} > + > +EFI_STATUS > +EFIAPI > +X58ICH10BoardInitAfterSiliconInit ( > + VOID > + ) > +{ > + > + DEBUG((EFI_D_ERROR, "X58ICH10BoardInitAfterSiliconInit\n")); > + return EFI_SUCCESS; > +} > diff --git > a/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/Library/BoardInitLib/Pe > iX58ICH10InitPreMemLib.c > b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/Library/BoardInitLib/Pe > iX58ICH10InitPreMemLib.c > new file mode 100644 > index 0000000000..9f0dc91c8a > --- /dev/null > +++ > b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/Library/BoardInitLib/Pe > iX58ICH10InitPreMemLib.c > @@ -0,0 +1,111 @@ > +/** @file > + Copyright (c) 2018 Intel Corporation. All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include "PeiX58ICH10InitLib.h" > +#include > +/** > + Reads 8-bits of CMOS data. > + > + Reads the 8-bits of CMOS data at the location specified by Index. > + The 8-bit read value is returned. > + > + @param Index The CMOS location to read. > + > + @return The value read. > + > +**/ > +UINT8 > +EFIAPI > +CmosRead8( > + IN UINTN Index > + ) > +{ > + IoWrite8 (0x70, (UINT8)Index); > + return IoRead8(0x71); > +} > + > + > +/** > + Writes 8-bits of CMOS data. > + > + Writes 8-bits of CMOS data to the location specified by Index > + with the value specified by Value and returns Value. > + > + @param Index The CMOS location to write. > + @param Value The value to write to CMOS. > + > + @return The value written to CMOS. > + > +**/ > +UINT8 > +EFIAPI > +CmosWrite8( > + IN UINTN Index, > + IN UINT8 Value > + ) > +{ > + IoWrite8 (0x70, (UINT8)Index); > + IoWrite8 (0x71, Value); > + return Value; > +} > + > + > +EFI_STATUS > +EFIAPI > +X58ICH10BoardInitBeforeMemoryInit ( > + VOID > + ) > +{ > + return EFI_SUCCESS; > +} > + > +EFI_STATUS > +EFIAPI > +X58ICH10BoardInitAfterMemoryInit ( > + VOID > + ) > +{ > + return EFI_SUCCESS; > +} > + > +EFI_STATUS > +EFIAPI > +X58ICH10BoardDebugInit ( > + VOID > + ) > +{ > + return EFI_SUCCESS; > +} > + > +EFI_BOOT_MODE > +EFIAPI > +X58ICH10BoardBootModeDetect ( > + VOID > + ) > +{ > + EFI_BOOT_MODE BootMode =3D BOOT_WITH_FULL_CONFIGURATION; > + > + DEBUG((EFI_D_INFO, "modeValue =3D %x\n", > IoBitFieldRead16(ICH10_PMBASE_IO + 4, 10, 12))); > + if (IoBitFieldRead16(ICH10_PMBASE_IO + 4, 10, 12) =3D=3D 0x5) { > + BootMode =3D BOOT_ON_S3_RESUME; > + } > + > + return BootMode; > +} > diff --git > a/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/DecomprScratchEnd.fd > f.inc > b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/DecomprScratchEnd.fd > f.inc > new file mode 100644 > index 0000000000..394875f205 > --- /dev/null > +++ > b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/DecomprScratchEnd.fd > f.inc > @@ -0,0 +1,66 @@ > +## @file > +# This FDF include file computes the end of the scratch buffer used in > +# DecompressMemFvs() [SimicsX58Pkg/Sec/SecMain.c]. It is based on the > decompressed > +# (ie. original) size of the LZMA-compressed section of the one FFS fil= e in > +# the FVMAIN_COMPACT firmware volume. > +# > +# Copyright (C) 2015, Red Hat, Inc. > +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +## > + > +# The GUID EE4E5898-3914-4259-9D6E-DC7BD79403CF means > "LzmaCustomDecompress". > +# The decompressed output will have the following structure (see the fil= e > +# "9E21FD93-9C72-4c15-8C4B-E77F1DB2D792SEC1.guided.dummy" in the > +# Build/SimicsX58*/*/FV/Ffs/9E21FD93-9C72-4c15-8C4B-E77F1DB2D792/ > directory): > +# > +# Size Contents > +# ------------------- -------------------------------------------------= ------- > +# 4 EFI_COMMON_SECTION_HEADER, stating size 124 (0x7C= ) and > +# type 0x19 (EFI_SECTION_RAW). The purpose of this = section > +# is to pad the start of PEIFV to 128 bytes. > +# 120 Zero bytes (padding). > +# > +# 4 EFI_COMMON_SECTION_HEADER, stating size > +# (PcdSimicsPeiMemFvSize + 4), and type 0x17 > +# (EFI_SECTION_FIRMWARE_VOLUME_IMAGE). > +# PcdSimicsPeiMemFvSize PEIFV. Note that the above sizes pad the offset= of > this > +# object to 128 bytes. See also the "guided.dummy.t= xt" > +# file in the same directory. > +# > +# 4 EFI_COMMON_SECTION_HEADER, stating size 12 (0xC) = and > +# type 0x19 (EFI_SECTION_RAW). The purpose of this = section > +# is to pad the start of DXEFV to 16 bytes. > +# 8 Zero bytes (padding). > +# > +# 4 EFI_COMMON_SECTION_HEADER, stating size > +# (PcdSimicsDxeMemFvSize + 4), and type 0x17 > +# (EFI_SECTION_FIRMWARE_VOLUME_IMAGE). > +# PcdSimicsDxeMemFvSize DXEFV. Note that the above sizes pad the offset= of > this > +# object to 16 bytes. See also the "guided.dummy.tx= t" file > +# in the same directory. > +# > +# The total size after decompression is (128 + PcdSimicsPeiMemFvSize + 1= 6 + > +# PcdSimicsDxeMemFvSize). > + > +DEFINE OUTPUT_SIZE =3D (128 + > gSimicsX58PkgTokenSpaceGuid.PcdSimicsPeiMemFvSize + 16 + > gSimicsX58PkgTokenSpaceGuid.PcdSimicsDxeMemFvSize) > + > +# LzmaCustomDecompressLib uses a constant scratch buffer size of 64KB; s= ee > +# SCRATCH_BUFFER_REQUEST_SIZE in > +# "MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaDecompress.c". > + > +DEFINE DECOMP_SCRATCH_SIZE =3D 0x00010000 > + > +# Note: when we use PcdSimicsDxeMemFvBase in this context, BaseTools hav= e > not yet > +# offset it with MEMFD's base address. For that reason we have to do it > manually. > +# > +# The calculation below mirrors DecompressMemFvs() > [SimicsX58Pkg/Sec/SecMain.c]. > + > +DEFINE OUTPUT_BASE =3D ($(MEMFD_BASE_ADDRESS) + > gSimicsX58PkgTokenSpaceGuid.PcdSimicsDxeMemFvBase + 0x00100000) > +DEFINE DECOMP_SCRATCH_BASE_UNALIGNED =3D ($(OUTPUT_BASE) + > $(OUTPUT_SIZE)) > +DEFINE DECOMP_SCRATCH_BASE_ALIGNMENT =3D 0x000FFFFF > +DEFINE DECOMP_SCRATCH_BASE_MASK =3D 0xFFF00000 > +DEFINE DECOMP_SCRATCH_BASE =3D > (($(DECOMP_SCRATCH_BASE_UNALIGNED) + > $(DECOMP_SCRATCH_BASE_ALIGNMENT)) & > $(DECOMP_SCRATCH_BASE_MASK)) > + > +SET gSimicsX58PkgTokenSpaceGuid.PcdSimicsDecompressionScratchEnd =3D > $(DECOMP_SCRATCH_BASE) + $(DECOMP_SCRATCH_SIZE) > diff --git > a/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/GitEdk2X58ICH10.bat > b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/GitEdk2X58ICH10.bat > new file mode 100644 > index 0000000000..48e9c6b09d > --- /dev/null > +++ > b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/GitEdk2X58ICH10.bat > @@ -0,0 +1,75 @@ > +@echo off > +@REM @file > +@REM Copyright (c) 2018 Intel Corporation. All rights reserved.
> +@REM > +@REM SPDX-License-Identifier: BSD-2-Clause-Patent > +@REM > + > +@echo off > + > +pushd ..\..\..\..\..\ > + > +@REM Set WORKSPACE environment. > +set WORKSPACE=3D%cd% > +echo. > +echo Set WORKSPACE as: %WORKSPACE% > +echo. > + > +@REM Check whether Git has been installed and been added to system path. > +git --help >nul 2>nul > +if %ERRORLEVEL% NEQ 0 ( > + echo. > + echo The 'git' command is not recognized. > + echo Please make sure that Git is installed and has been added to syst= em path. > + echo. > + goto :EOF > +) > + > +@REM Create the Conf directory under WORKSPACE > +if not exist %WORKSPACE%\Conf ( > + mkdir Conf > +) > + > +@REM Set other environments. > +@REM Basic Rule: > +@REM Platform override Silicon override Core > +@REM Source override Binary > + > +set PACKAGES_PATH=3D%WORKSPACE%\edk2- > platforms\Platform\Intel;%WORKSPACE%\edk2- > platforms\Silicon\Intel;%WORKSPACE%\edk2- > platforms\Drivers;%WORKSPACE%\edk2-non- > osi\Silicon\Intel;%WORKSPACE%\edk2;%WORKSPACE% > + > +set EDK_TOOLS_BIN=3D%WORKSPACE%\edk2-BaseTools-win32 > + > +@if not defined PYTHON_HOME ( > + @if exist C:\Python27 ( > + set PYTHON_HOME=3DC:\Python27 > + ) > +) > + > +set EDK_SETUP_OPTION=3D > +@rem if python is installed, disable the binary base tools. > +if defined PYTHON_HOME ( > + set EDK_TOOLS_BIN=3D > + set EDK_SETUP_OPTION=3DRebuild > +) > +pushd %WORKSPACE%\edk2 > +call edksetup.bat %EDK_SETUP_OPTION% > +popd > + > +set openssl_path=3D%WORKSPACE% > + > +popd > + > +goto :EOF > + > +:Help > +echo. > +echo Usage: > +echo GitEdk2.bat [-w Workspace_Directory] (optional) [-b Branch_Name] > (optional) > +echo. > +echo -w A absolute/relative path to be the workspace. > +echo Default value is the current directory. > +echo. > +echo -b The branch name of the repository. Currently, only master, ud= k2015, > +echo trunk (same as master) and bp13 (same as udk2015) are support= ed. > +echo Default value is master. > +echo. > diff --git > a/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/Library/BoardInitLib/Pe > iBoardInitPostMemLib.inf > b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/Library/BoardInitLib/Pe > iBoardInitPostMemLib.inf > new file mode 100644 > index 0000000000..542b53547f > --- /dev/null > +++ > b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/Library/BoardInitLib/Pe > iBoardInitPostMemLib.inf > @@ -0,0 +1,36 @@ > +## @file > +# > +# Copyright (c) 2018 Intel Corporation. All rights reserved.
> +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +## > + > +[Defines] > + INF_VERSION =3D 0x00010005 > + BASE_NAME =3D PeiBoardPostMemInitLib > + FILE_GUID =3D 30F407D6-6B92-412A-B2DA-8E73E2B386E= 6 > + MODULE_TYPE =3D BASE > + VERSION_STRING =3D 1.0 > + LIBRARY_CLASS =3D BoardInitLib > + > +[LibraryClasses] > + BaseLib > + DebugLib > + BaseMemoryLib > + MemoryAllocationLib > + PcdLib > + > +[Packages] > + MinPlatformPkg/MinPlatformPkg.dec > + MdePkg/MdePkg.dec > + MdeModulePkg/MdeModulePkg.dec > + > +[Sources] > + PeiX58ICH10InitPostMemLib.c > + PeiBoardInitPostMemLib.c > + > +[FixedPcd] > + > +[Pcd] > + > diff --git > a/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/Library/BoardInitLib/Pe > iBoardInitPreMemLib.inf > b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/Library/BoardInitLib/Pe > iBoardInitPreMemLib.inf > new file mode 100644 > index 0000000000..ab1286602b > --- /dev/null > +++ > b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/Library/BoardInitLib/Pe > iBoardInitPreMemLib.inf > @@ -0,0 +1,38 @@ > +## @file > +# > +# Copyright (c) 2018 Intel Corporation. All rights reserved.
> +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +## > + > +[Defines] > + INF_VERSION =3D 0x00010005 > + BASE_NAME =3D PeiBoardInitPreMemLib > + FILE_GUID =3D 73AA24AE-FB20-43F9-A3BA-448953A03A7= 8 > + MODULE_TYPE =3D BASE > + VERSION_STRING =3D 1.0 > + LIBRARY_CLASS =3D BoardInitLib > + > +[LibraryClasses] > + BaseLib > + DebugLib > + BaseMemoryLib > + MemoryAllocationLib > + PcdLib > + > +[Packages] > + MinPlatformPkg/MinPlatformPkg.dec > + MdePkg/MdePkg.dec > + MdeModulePkg/MdeModulePkg.dec > + SimicsOpenBoardPkg/SimicsOpenBoardPkg.dec > + > +[Sources] > + PeiX58ICH10Detect.c > + PeiX58ICH10InitPreMemLib.c > + PeiBoardInitPreMemLib.c > + > +[Pcd] > + > +[FixedPcd] > + > diff --git > a/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/Library/BoardInitLib/Pe > iX58ICH10InitLib.h > b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/Library/BoardInitLib/Pe > iX58ICH10InitLib.h > new file mode 100644 > index 0000000000..996679e8f5 > --- /dev/null > +++ > b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/Library/BoardInitLib/Pe > iX58ICH10InitLib.h > @@ -0,0 +1,16 @@ > +/** @file > + Copyright (c) 2018 Intel Corporation. All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#ifndef _PEI_X58ICH10_BOARD_INIT_LIB_H_ > +#define _PEI_X58ICH10_BOARD_INIT_LIB_H_ > + > +#include > +#include > +#include > +#include > +#include > + > +#endif > diff --git > a/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/PlatformPkgBuildOptio > n.dsc > b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/PlatformPkgBuildOptio > n.dsc > new file mode 100644 > index 0000000000..8bce3c7a4f > --- /dev/null > +++ > b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/PlatformPkgBuildOptio > n.dsc > @@ -0,0 +1,89 @@ > +## @file > +# > +# Copyright (c) 2018 Intel Corporation. All rights reserved.
> +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +## > + > +[BuildOptions.Common.EDKII] > +# Append build options for EDK and EDKII drivers (=3D is Append, =3D=3D = is Replace) > + > + DEFINE CRB_EDKII_BUILD_OPTIONS =3D -D CRB_FLAG > + DEFINE EDKII_CPU_BUILD_OPTIONS =3D -D PURLEY_FLAG > + DEFINE TRAD_BUILD_OPTION =3D -D TRAD_FLAG=3D1 > + DEFINE SUS_WELL_RESTORE_BUILD_OPTION =3D -D SUS_WELL_RESTORE=3D1 > + DEFINE PCH_BUILD_OPTION =3D -D PCH_SERVER_BIOS_FLAG=3D1 > + DEFINE SERVER_BUILD_OPTION =3D -D SERVER_BIOS_FLAG=3D1 > + DEFINE PCH_PKG_OPTIONS =3D -D PCH_SPT > + DEFINE MAX_SOCKET_OPTIONS =3D -D MAX_SOCKET=3D2 > + > + DEFINE EDKII_ALL_PPO_OPTIONS =3D $(EDKII_CPU_BUILD_OPTIONS) > + DEFINE PCH_BIOS_BUILD_OPTIONS =3D $(TRAD_BUILD_OPTION) > $(ULT_BUILD_OPTION) $(PCH_BUILD_OPTION) > $(SUS_WELL_RESTORE_BUILD_OPTION) $(SERVER_BUILD_OPTION) > + DEFINE EDKII_DSC_FEATURE_BUILD_OPTIONS =3D > $(CRB_EDKII_BUILD_OPTIONS) $(PCH_BIOS_BUILD_OPTIONS) > $(PCH_PKG_OPTIONS) $(EDKII_ALL_PPO_OPTIONS) > $(SPARING_SCRATCHPAD_OPTION) $(TRACE_HUB_DEBUG_BUILD_OPTIONS) > $(TRACE_HUB_INIT_BUILD_OPTIONS) $(MAX_SOCKET_OPTIONS) -D > EFI_PCI_IOV_SUPPORT -D WHEA_SUPPORT -D SKX_HOST -D CLX_HOST > + > +!if $(TARGET) =3D=3D "DEBUG" > + DEFINE DEBUG_BUILD_FLAG =3D -D SERIAL_DBG_MSG=3D1 > +!else > + DEFINE DEBUG_BUILD_FLAG =3D -D MDEPKG_NDEBUG -D SILENT_MODE > +!endif > + > + DEFINE EDKII_DSC_FEATURE_BUILD_OPTIONS =3D > $(EDKII_DSC_FEATURE_BUILD_OPTIONS) $(DEBUG_BUILD_FLAG) > +# > +# PC_BUILD_END > +# > + > + > + DEFINE EDKII_DSC_FEATURE_BUILD_OPTIONS =3D > $(EDKII_DSC_FEATURE_BUILD_OPTIONS) > + > + > + *_*_IA32_CC_FLAGS =3D $(EDKII_DSC_FEATURE_BUILD_OPTIONS) > + *_*_IA32_VFRPP_FLAGS =3D $(EDKII_DSC_FEATURE_BUILD_OPTIONS) > + *_*_IA32_APP_FLAGS =3D $(EDKII_DSC_FEATURE_BUILD_OPTIONS) > + *_*_IA32_PP_FLAGS =3D $(EDKII_DSC_FEATURE_BUILD_OPTIONS) > + *_*_IA32_ASLPP_FLAGS =3D $(EDKII_DSC_FEATURE_BUILD_OPTIONS) > + *_*_IA32_ASLCC_FLAGS =3D $(EDKII_DSC_FEATURE_BUILD_OPTIONS) > + > + *_*_X64_CC_FLAGS =3D $(EDKII_DSC_FEATURE_BUILD_OPTIONS) > + *_*_X64_VFRPP_FLAGS =3D $(EDKII_DSC_FEATURE_BUILD_OPTIONS) > + *_*_X64_APP_FLAGS =3D $(EDKII_DSC_FEATURE_BUILD_OPTIONS) > + *_*_X64_PP_FLAGS =3D $(EDKII_DSC_FEATURE_BUILD_OPTIONS) > + *_*_X64_ASLPP_FLAGS =3D $(EDKII_DSC_FEATURE_BUILD_OPTIONS) > + *_*_X64_ASLCC_FLAGS =3D $(EDKII_DSC_FEATURE_BUILD_OPTIONS) > + > + > + > +# > +# Enable source level debugging for RELEASE build > +# > +!if $(TARGET) =3D=3D "RELEASE" > + DEFINE EDKII_RELEASE_SRCDBG_ASM_BUILD_OPTIONS =3D /Zi > + DEFINE EDKII_RELEASE_SRCDBG_CC_BUILD_OPTIONS =3D /Zi /Gm > + DEFINE EDKII_RELEASE_SRCDBG_DLINK_BUILD_OPTIONS =3D /DEBUG > + > + MSFT:*_*_*_ASM_FLAGS =3D > $(EDKII_RELEASE_SRCDBG_ASM_BUILD_OPTIONS) > + MSFT:*_*_*_CC_FLAGS =3D > $(EDKII_RELEASE_SRCDBG_CC_BUILD_OPTIONS) > + MSFT:*_*_*_DLINK_FLAGS =3D > $(EDKII_RELEASE_SRCDBG_DLINK_BUILD_OPTIONS) > +!endif > + > + > +# > +# Override the existing iasl path in tools_def.template > +# > +# MSFT:*_*_*_ASL_PATH =3D=3D c:/Iasl/iasl.exe > + > +# > +# Override the VFR compile flags to speed the build time > +# > + > +*_*_*_VFR_FLAGS =3D=3D -n > + > +# Force PE/COFF sections to be aligned at 4KB boundaries to support page= level > protection > +#[BuildOptions.common.EDKII.DXE_SMM_DRIVER, > BuildOptions.common.EDKII.SMM_CORE] > +# MSFT:*_*_*_DLINK_FLAGS =3D /ALIGN:4096 > +# GCC:*_*_*_DLINK_FLAGS =3D -z common-page-size=3D0x1000 > + > +# Force PE/COFF sections to be aligned at 4KB boundaries to support > MemoryAttribute table > +#[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] > +# MSFT:*_*_*_DLINK_FLAGS =3D /ALIGN:4096 > +# GCC:*_*_*_DLINK_FLAGS =3D -z common-page-size=3D0x1000 > diff --git > a/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/PlatformPkgConfig.dsc > b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/PlatformPkgConfig.dsc > new file mode 100644 > index 0000000000..f0ab846290 > --- /dev/null > +++ > b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/PlatformPkgConfig.dsc > @@ -0,0 +1,56 @@ > +## @file > +# > +# Copyright (c) 2018 Intel Corporation. All rights reserved.
> +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +## > + > +# > +# TRUE is ENABLE. FALSE is DISABLE. > +# > + > +[PcdsFixedAtBuild] > + gMinPlatformPkgTokenSpaceGuid.PcdBootStage|4 > + > +[PcdsFeatureFlag] > + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE > + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE > + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE > + gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|FALSE > + gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|FALSE > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 1 > + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|TRUE > +!endif > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 2 > + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE > + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|TRUE > +!endif > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 3 > + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE > + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|TRUE > +!endif > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 4 > + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE > +!endif > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 5 > + gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|TRUE > + gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|TRUE > +!endif > + > + !if $(TARGET) =3D=3D DEBUG > + gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE > + !else > + gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|FALSE > + !endif > + > + gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable|FALSE > + > + gAdvancedFeaturePkgTokenSpaceGuid.PcdNetworkEnable|TRUE > + gAdvancedFeaturePkgTokenSpaceGuid.PcdSmbiosEnable|TRUE > + > diff --git > a/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/PlatformPkgPcd.dsc > b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/PlatformPkgPcd.dsc > new file mode 100644 > index 0000000000..dc70adee34 > --- /dev/null > +++ > b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/PlatformPkgPcd.dsc > @@ -0,0 +1,283 @@ > +## @file > +# > +# Copyright (c) 2018 Intel Corporation. All rights reserved.
> +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +## > + > +############################################################ > #################### > +# > +# Pcd Section - list of all EDK II PCD Entries defined by this Platform > +# > +############################################################ > #################### > +[PcdsFeatureFlag.common] > +!if $(TARGET) =3D=3D RELEASE > + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE > +!else > + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE > +!endif > + # Server doesn't support capsle update on Reset. > + gEfiMdeModulePkgTokenSpaceGuid.PcdSupportUpdateCapsuleReset|FALSE > + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE > + gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugSupport|FALSE > + gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport|FALSE > + > + > +#S3 add > + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|TRUE > +#S3 add > + > + ## This PCD specified whether ACPI SDT protocol is installed. > + gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE > + > +[PcdsFeatureFlag.X64] > + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard|FALSE > + > +[PcdsFeatureFlag] > + > gEfiMdeModulePkgTokenSpaceGuid.PcdBrowerGrayOutReadOnlyMenu|TRUE > + > +[PcdsDynamicExDefault] > + > +[PcdsFixedAtBuild.common] > + > gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChan > ge|TRUE > +!if $(TARGET) =3D=3D "RELEASE" > + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x03 > +!else > + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 > +!endif > + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 > + gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|0 > + gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x0 > +#S3 modified > + gEfiMdeModulePkgTokenSpaceGuid.PcdShadowPeimOnS3Boot|TRUE > +#S3 modified > + > + gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x0 > + gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x0 > + gEfiMdePkgTokenSpaceGuid.PcdFSBClock|133333333 > + gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeiStackSize|0x100000 > + > gEfiMdeModulePkgTokenSpaceGuid.PcdMaxSizeNonPopulateCapsule|0x17000 > 00 > + > + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000 > + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|512 > + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x4000 > + > + ## Specifies delay value in microseconds after sending out an INIT IPI= . > + # @Prompt Configure delay value after send an INIT IPI > + gUefiCpuPkgTokenSpaceGuid.PcdCpuInitIpiDelayInMicroSeconds|10 > + > + ## Specifies max supported number of Logical Processors. > + # @Prompt Configure max supported number of Logical Processorss > + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|512 > + gUefiCpuPkgTokenSpaceGuid.PcdCpuApStackSize|0x1000 > +!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable =3D=3D TRUE > + gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1 > +!endif > + > + ## Defines the ACPI register set base address. > + # The invalid 0xFFFF is as its default value. It must be configured t= o the real > value. > + # @Prompt ACPI Timer IO Port Address > + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress | 0x04= 00 > + > + ## Defines the PCI Bus Number of the PCI device that contains the BAR = and > Enable for ACPI hardware registers. > + # @Prompt ACPI Hardware PCI Bus Number > + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber | 0x00 > + > + > gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision|0x00000002 > + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId|0x4C544E49 > + > gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision|0x200910 > 13 > + > + ## Defines the PCI Device Number of the PCI device that contains the B= AR and > Enable for ACPI hardware registers. > + # The invalid 0xFF is as its default value. It must be configured to = the real > value. > + # @Prompt ACPI Hardware PCI Device Number > + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber | 0x1F > + > + ## Defines the PCI Function Number of the PCI device that contains the= BAR > and Enable for ACPI hardware registers. > + # The invalid 0xFF is as its default value. It must be configured to = the real > value. > + # @Prompt ACPI Hardware PCI Function Number > + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber | 0x00 > + > + ## Defines the PCI Register Offset of the PCI device that contains the= Enable > for ACPI hardware registers. > + # The invalid 0xFFFF is as its default value. It must be configured t= o the real > value. > + # @Prompt ACPI Hardware PCI Register Offset > + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset |0x0044 > + > + ## Defines the bit mask that must be set to enable the APIC hardware r= egister > BAR. > + # @Prompt ACPI Hardware PCI Bar Enable BitMask > + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask | 0x80 > + > + ## Defines the PCI Register Offset of the PCI device that contains the= BAR for > ACPI hardware registers. > + # The invalid 0xFFFF is as its default value. It must be configured t= o the real > value. > + # @Prompt ACPI Hardware PCI Bar Register Offset > + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset |0x0040 > + > + ## Defines the offset to the 32-bit Timer Value register that resides = within the > ACPI BAR. > + # @Prompt Offset to 32-bit Timer register in ACPI BAR > + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset |0x0008 > + > + ## Defines the bit mask to retrieve ACPI IO Port Base Address > + # @Prompt ACPI IO Port Base Address Mask > + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddressMask |0xFFFC > + > + > gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChan > ge|FALSE > + > + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|4 > + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|128 > + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|4 > + gMinPlatformPkgTokenSpaceGuid.PcdLocalApicAddress|0xFEE00000 > + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicAddressBase|0xFEC01000 > + gMinPlatformPkgTokenSpaceGuid.PcdFadtPreferredPmProfile|0x0 > + gMinPlatformPkgTokenSpaceGuid.PcdFadtIaPcBootArch|0x0003 > + gMinPlatformPkgTokenSpaceGuid.PcdFadtFlags|0x000004A5 > + gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1AEventBlockAddress|0x400 > + gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1BEventBlockAddress|0 > + gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1AControlBlockAddress|0x404 > + gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1BControlBlockAddress|0 > + gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm2ControlBlockAddress|0x450 > + gMinPlatformPkgTokenSpaceGuid.PcdAcpiPmTimerBlockAddress|0x408 > + gMinPlatformPkgTokenSpaceGuid.PcdAcpiGpe0BlockAddress|0x420 > + gMinPlatformPkgTokenSpaceGuid.PcdAcpiGpe1BlockAddress|0 > + > +[PcdsFixedAtBuild.X64] > + gPcAtChipsetPkgTokenSpaceGuid.Pcd8259LegacyModeMask|0x0eB8 > + gPcAtChipsetPkgTokenSpaceGuid.PcdMinimalValidYear|2015 > + gPcAtChipsetPkgTokenSpaceGuid.PcdMaximalValidYear|2099 > + # Change PcdBootManagerMenuFile to UiApp > +## > + > + gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, > 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0= x23, > 0x31 } > + > + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable |TRUE > + > + [PcdsPatchableInModule.common] > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable =3D=3D TRUE > + > gEfiMdeModulePkgTokenSpaceGuid.PcdSmiHandlerProfilePropertyMask|0x1 > +!endif > + > + gPcAtChipsetPkgTokenSpaceGuid.PcdHpetBaseAddress|0xFED00000 > + > + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|1024 > + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|600 > + > + gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable|TRUE > + > + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase|0x0 > + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize|0x0 > + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress|0xFFE00000 > + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize|0x00200000 > + > +[PcdsDynamicExDefault.common.DEFAULT] > + gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|30000 > + gUefiCpuPkgTokenSpaceGuid.PcdCpuS3DataAddress|0 > + > +[PcdsDynamicExHii.common.DEFAULT] > + > gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobal > VariableGuid|0x0|50 # Variable: L"Timeout" > + > gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSuppo > rt"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport" > + > + > +[PcdsDynamicExDefault] > + > + gEfiMdeModulePkgTokenSpaceGuid.PcdMrIovSupport|FALSE > + gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSystemPageSize|0x1F > + > + > gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L""|VOID*|36 > + > + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId|{0x49, 0x4E, > 0x54, 0x45, 0x4C, 0x20} > + > gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x204657303 > 0363253 > + > +[PcdsDynamicExDefault.X64] > + > + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200 > + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8 > + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1 > + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1 > + gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|0 > + > + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|31 > + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|100 > + > + > gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|800 > + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|600 > + > + gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugDataAddress|0 > + > +[PcdsFeatureFlag] > + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|TRUE > + > gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSupportUefiDecompress|FALSE > + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|TRUE > + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE > + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE > + #gOptionRomPkgTokenSpaceGuid.PcdSupportGop|TRUE > + #gOptionRomPkgTokenSpaceGuid.PcdSupportUga|FALSE > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE > + gSimicsX58PkgTokenSpaceGuid.PcdSmmSmramRequire|TRUE > +!endif > + > +[PcdsFixedAtBuild] > + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeMemorySize|1 > + gEfiMdePkgTokenSpaceGuid.PcdMaximumGuidedExtractHandler|0x10 > + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x400 > + > gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x800 > 0 > + gEfiMdeModulePkgTokenSpaceGuid.PcdVariableStoreSize|0xc000 > + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0xc000 > + > gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x200 > 0 > + > gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x10000 > + > + gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0 > + > + # DEBUG_INIT 0x00000001 // Initialization > + # DEBUG_WARN 0x00000002 // Warnings > + # DEBUG_LOAD 0x00000004 // Load events > + # DEBUG_FS 0x00000008 // EFI File system > + # DEBUG_POOL 0x00000010 // Alloc & Free (pool) > + # DEBUG_PAGE 0x00000020 // Alloc & Free (page) > + # DEBUG_INFO 0x00000040 // Informational debug messages > + # DEBUG_DISPATCH 0x00000080 // PEI/DXE/SMM Dispatchers > + # DEBUG_VARIABLE 0x00000100 // Variable > + # DEBUG_BM 0x00000400 // Boot Manager > + # DEBUG_BLKIO 0x00001000 // BlkIo Driver > + # DEBUG_NET 0x00004000 // SNP Driver > + # DEBUG_UNDI 0x00010000 // UNDI Driver > + # DEBUG_LOADFILE 0x00020000 // LoadFile > + # DEBUG_EVENT 0x00080000 // Event messages > + # DEBUG_GCD 0x00100000 // Global Coherency Database changes > + # DEBUG_CACHE 0x00200000 // Memory range cachability changes > + # DEBUG_VERBOSE 0x00400000 // Detailed debug messages that may > + # // significantly impact boot performance > + # DEBUG_ERROR 0x80000000 // Error > + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000004F > + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F > + > + # > + # PCI feature overrides. > + # > + gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|FALSE > + gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE > + > +############################################################ > #################### > +# > +# Pcd Dynamic Section - list of all EDK II PCD Entries defined by this P= latform > +# > +############################################################ > #################### > + > +[PcdsDynamicDefault] > + gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved|0 > + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0 > + > + gSimicsX58PkgTokenSpaceGuid.PcdSimicsX58HostBridgePciDevId|0 > + gSimicsX58PkgTokenSpaceGuid.PcdPciIoBase|0x0 > + gSimicsX58PkgTokenSpaceGuid.PcdPciIoSize|0x0 > + gSimicsX58PkgTokenSpaceGuid.PcdPciMmio32Base|0x0 > + gSimicsX58PkgTokenSpaceGuid.PcdPciMmio32Size|0x0 > + gSimicsX58PkgTokenSpaceGuid.PcdPciMmio64Base|0x0 > + gSimicsX58PkgTokenSpaceGuid.PcdPciMmio64Size|0x800000000 > + > + > gAdvancedFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringBiosVersion|"Ve > r.1.0.0" > + > gAdvancedFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringProductName|" > QSP UEFI BIOS" > + > gAdvancedFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringProductName|" > QSP UEFI BIOS" > + > gAdvancedFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringBiosReleaseDate > |"2019-08-09" > + > + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiS3Enable|FALSE > diff --git > a/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/SimicsX58Pkg.fdf.inc > b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/SimicsX58Pkg.fdf.inc > new file mode 100644 > index 0000000000..f42e8b0e0e > --- /dev/null > +++ > b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/SimicsX58Pkg.fdf.inc > @@ -0,0 +1,48 @@ > +## @file > +# FDF include file that defines the main macros and sets the dependent = PCDs. > +# > +# Copyright (C) 2014, Red Hat, Inc. > +# Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved. > +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +## > + > +# > +# Default flash size is 2MB. > +# > +# Defining FD_SIZE_2MB on the build command line can override this. > +# > + > +DEFINE BLOCK_SIZE =3D 0x1000 > +DEFINE VARS_SIZE =3D 0x3e000 > +DEFINE VARS_BLOCKS =3D 0x3e > + > +DEFINE FW_BASE_ADDRESS =3D 0xFFE00000 > +DEFINE FW_SIZE =3D 0x00200000 > +DEFINE FW_BLOCKS =3D 0x200 > +DEFINE CODE_BASE_ADDRESS =3D 0xFFE80000 > +DEFINE CODE_SIZE =3D 0x00180000 > +DEFINE CODE_BLOCKS =3D 0x180 > +DEFINE FVMAIN_SIZE =3D 0x0016C000 > +DEFINE SECFV_OFFSET =3D 0x001EC000 > +DEFINE SECFV_SIZE =3D 0x14000 > + > + > +SET gSimicsX58PkgTokenSpaceGuid.PcdSimicsFdBaseAddress =3D > $(FW_BASE_ADDRESS) > +SET gSimicsX58PkgTokenSpaceGuid.PcdSimicsFirmwareFdSize =3D $(FW_SIZE= ) > +SET gSimicsX58PkgTokenSpaceGuid.PcdSimicsFirmwareBlockSize =3D > $(BLOCK_SIZE) > + > +SET gSimicsX58PkgTokenSpaceGuid.PcdSimicsFlashNvStorageVariableBase =3D > $(FW_BASE_ADDRESS) > +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize =3D > 0xE000 > + > +SET gSimicsX58PkgTokenSpaceGuid.PcdSimicsFlashNvStorageEventLogBase =3D > gSimicsX58PkgTokenSpaceGuid.PcdSimicsFlashNvStorageVariableBase + > gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize > +SET gSimicsX58PkgTokenSpaceGuid.PcdSimicsFlashNvStorageEventLogSize =3D > $(BLOCK_SIZE) > + > +SET gSimicsX58PkgTokenSpaceGuid.PcdSimicsFlashNvStorageFtwWorkingBase > =3D gSimicsX58PkgTokenSpaceGuid.PcdSimicsFlashNvStorageEventLogBase + > gSimicsX58PkgTokenSpaceGuid.PcdSimicsFlashNvStorageEventLogSize > +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize =3D > $(BLOCK_SIZE) > + > +SET gSimicsX58PkgTokenSpaceGuid.PcdSimicsFlashNvStorageFtwSpareBase =3D > gSimicsX58PkgTokenSpaceGuid.PcdSimicsFlashNvStorageFtwWorkingBase + > gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize > +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize =3D > 0x10000 > + > +DEFINE MEMFD_BASE_ADDRESS =3D 0x800000 > diff --git > a/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/SimicsX58PkgIa32X64. > dsc > b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/SimicsX58PkgIa32X64. > dsc > new file mode 100644 > index 0000000000..66ac16a940 > --- /dev/null > +++ > b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/SimicsX58PkgIa32X64. > dsc > @@ -0,0 +1,244 @@ > +## @file > +# > +# Copyright (c) 2018 Intel Corporation. All rights reserved.
> +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +## > + > +############################################################ > #################### > +# > +# Defines Section - statements that will be processed to create a Makefi= le. > +# > +############################################################ > #################### > +[Defines] > + DEFINE PLATFORM_PACKAGE =3D MinPlatformPkg > + DEFINE BOARD_NAME =3D BoardX58ICH10 > + DEFINE BOARD_PKG =3D SimicsOpenBoardPkg > + DEFINE SKT_PKG =3D SimicsX58SktPkg > + DEFINE PCH_PKG =3D SimicsICH10Pkg > + DEFINE DXE_ARCH =3D X64 > + DEFINE PEI_ARCH =3D IA32 > + > + PLATFORM_NAME =3D SimicsX58 > + PLATFORM_GUID =3D EE8EBB5A-CC95-412f-9987-2AF70F88B69= A > + PLATFORM_VERSION =3D 0.1 > + DSC_SPECIFICATION =3D 0x00010005 > + OUTPUT_DIRECTORY =3D Build/SimicsX58Ia32X64 > + SUPPORTED_ARCHITECTURES =3D IA32|X64 > + BUILD_TARGETS =3D DEBUG|RELEASE|NOOPT > + SKUID_IDENTIFIER =3D DEFAULT > + FLASH_DEFINITION =3D > $(BOARD_PKG)/$(BOARD_NAME)/SimicsX58PkgIa32X64.fdf > + > + DEFINE SMM_REQUIRE =3D TRUE > + > + # > + #PLATFORMX64_ENABLE is set to TRUE when PEI is IA32 and DXE is X64 > platform > + # > + DEFINE PLATFORMX64_ENABLE =3D TRUE > + DEFINE NETWORK_TLS_ENABLE =3D FALSE > + DEFINE NETWORK_ISCSI_ENABLE =3D FALSE > + DEFINE NETWORK_ALLOW_HTTP_CONNECTIONS =3D TRUE > + !include NetworkPkg/NetworkDefines.dsc.inc > +############################################################ > #################### > +# > +# SKU Identification section - list of all SKU IDs supported by this Pla= tform. > +# > +############################################################ > #################### > +[SkuIds] > + 0|DEFAULT > + > +############################################################ > #################### > +# > +# Library Class section - list of all Library Classes needed by this Pla= tform. > +# > +############################################################ > #################### > + > +[PcdsFeatureFlag] > + # > + # Platform On/Off features are defined here > + # > + !include $(BOARD_PKG)/$(BOARD_NAME)/PlatformPkgConfig.dsc > + !include MinPlatformPkg/Include/Dsc/CoreCommonLib.dsc > + !include $(PCH_PKG)/PchCommonLib.dsc > + > +[LibraryClasses] > + > ReportFvLib|MinPlatformPkg/PlatformInit/Library/PeiReportFvLib/PeiReportF= v > Lib.inf > + BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf > + SerialPortLib|PcAtChipsetPkg/Library/SerialIoLib/SerialIoLib.inf > + NvVarsFileLib|$(BOARD_PKG)/Library/NvVarsFileLib/NvVarsFileLib.inf > + > SerializeVariablesLib|$(BOARD_PKG)/Library/SerializeVariablesLib/Serializ= eVari > ablesLib.inf > + LoadLinuxLib|$(BOARD_PKG)/Library/LoadLinuxLib/LoadLinuxLib.inf > + > CpuExceptionHandlerLib|MdeModulePkg/Library/CpuExceptionHandlerLibNull/ > CpuExceptionHandlerLibNull.inf > + > + > TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLibNull/TestP= oi > ntCheckLibNull.inf > + > BoardInitLib|MinPlatformPkg/PlatformInit/Library/BoardInitLibNull/BoardIn= itLi > bNull.inf > + > SiliconPolicyInitLib|$(BOARD_PKG)/Policy/Library/SiliconPolicyInitLib/Sil= iconPol > icyInitLib.inf > + > SiliconPolicyUpdateLib|$(BOARD_PKG)/Policy/Library/SiliconPolicyUpdateLib= /S > iliconPolicyUpdateLib.inf > + > PciSegmentInfoLib|MinPlatformPkg/Pci/Library/PciSegmentInfoLibSimple/PciS > egmentInfoLibSimple.inf > + > + !include MinPlatformPkg/Include/Dsc/CorePeiLib.dsc > + > + > S3BootScriptLib|MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScri > ptLib.inf > + > AslUpdateLib|MinPlatformPkg/Acpi/Library/DxeAslUpdateLib/DxeAslUpdateLib. > inf > +[LibraryClasses.common.SEC] > + > ExtractGuidedSectionLib|MdePkg/Library/BaseExtractGuidedSectionLib/BaseEx= t > ractGuidedSectionLib.inf > + > +[LibraryClasses.common.PEI_CORE] > + > +[LibraryClasses.common.PEIM] > + > PeiResourcePublicationLib|MdePkg/Library/PeiResourcePublicationLib/PeiRes= o > urcePublicationLib.inf > + MpInitLib|UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf > + > +[LibraryClasses.IA32] > +!if $(TARGET) =3D=3D DEBUG > + > TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLib/PeiTestPo= i > ntCheckLib.inf > +!endif > + TestPointLib|MinPlatformPkg/Test/Library/TestPointLib/PeiTestPointLib.= inf > + > + !include MinPlatformPkg/Include/Dsc/CoreDxeLib.dsc > + > +[LibraryClasses.common.DXE_CORE] > + > +[LibraryClasses.common.DXE_RUNTIME_DRIVER] > + > PciLib|$(BOARD_PKG)/Overrides/MdePkg/Library/BasePciLibCf8/DxePciLibX58 > Ich10.inf > + > +[LibraryClasses.common.UEFI_DRIVER] > + > PciLib|$(BOARD_PKG)/Overrides/MdePkg/Library/BasePciLibCf8/DxePciLibX58 > Ich10.inf > + > +[LibraryClasses.common.DXE_DRIVER] > + > PlatformBootManagerLib|$(BOARD_PKG)/Overrides/MdeModulePkg/Library/P > latformBootManagerLib/PlatformBootManagerLib.inf > + > PciLib|$(BOARD_PKG)/Overrides/MdePkg/Library/BasePciLibCf8/DxePciLibX58 > Ich10.inf > + > +[LibraryClasses.common.UEFI_APPLICATION] > + > PciLib|$(BOARD_PKG)/Overrides/MdePkg/Library/BasePciLibCf8/DxePciLibX58 > Ich10.inf > + > +[LibraryClasses.common.DXE_SMM_DRIVER] > + > PciLib|$(BOARD_PKG)/Overrides/MdePkg/Library/BasePciLibCf8/DxePciLibX58 > Ich10.inf > + > SpiFlashCommonLib|$(PCH_PKG)/Library/SmmSpiFlashCommonLib/SmmSpiFla > shCommonLib.inf > + > +[LibraryClasses.common.SMM_CORE] > + > PciLib|$(BOARD_PKG)/Overrides/MdePkg/Library/BasePciLibCf8/DxePciLibX58 > Ich10.inf > + > + !include $(BOARD_PKG)/$(BOARD_NAME)/PlatformPkgPcd.dsc > + > +[Components.IA32] > + !include $(SKT_PKG)/SktPei.dsc > + !include MinPlatformPkg/Include/Dsc/CorePeiInclude.dsc > + > + $(BOARD_PKG)/PlatformPei/PlatformPei.inf { > + > + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf > + } > +# S3 SMM driver > +# UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.inf > + UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf { > + > + > LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxPeiLib.inf > + } > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE > + $(SKT_PKG)/Smm/Access/SmmAccessPei.inf { > + > + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf > + } > +!endif > + $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf > + > + MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf { > + > + > BoardInitLib|$(BOARD_PKG)/$(BOARD_NAME)/Library/BoardInitLib/PeiBoardI > nitPreMemLib.inf > + } > + MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf { > + > + > BoardInitLib|$(BOARD_PKG)/$(BOARD_NAME)/Library/BoardInitLib/PeiBoardI > nitPostMemLib.inf > + } > + MinPlatformPkg/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.in= f > + MinPlatformPkg/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMem.i= nf > + > +[Components.X64] > + !include MinPlatformPkg/Include/Dsc/CoreDxeInclude.dsc > + > $(BOARD_PKG)/Overrides/PcAtChipsetPkg/8259InterruptControllerDxe/8259.i > nf > + !include AdvancedFeaturePkg/Include/Dsc/CoreAdvancedDxeInclude.dsc > + > + MdeModulePkg/Universal/EbcDxe/EbcDxe.inf > + $(BOARD_PKG)/Overrides/MdeModulePkg/Logo/LogoDxe.inf > + > + MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf > + # > + # ISA Support > + # > + $(BOARD_PKG)/LegacySioDxe/LegacySioDxe.inf > + MdeModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2KeyboardDxe.inf > + > + $(BOARD_PKG)/SmbiosPlatformDxe/SmbiosPlatformDxe.inf > + $(BOARD_PKG)/AcpiTables/AcpiTables.inf > + # > + # Video support > + # > + $(BOARD_PKG)/Overrides/OvmfPkg/QemuVideoDxe/QemuVideoDxe.inf > + > + MinPlatformPkg/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf > + MinPlatformPkg/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf > + $(BOARD_PKG)/PlatformDxe/Platform.inf > + MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf > + > MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe. > inf > + > + # > + # Shell > + # > + ShellPkg/Application/Shell/Shell.inf { > + > + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE > + > + > NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2Command > sLib.inf > + > NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1Command > sLib.inf > + > NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3Command > sLib.inf > + > NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1Comma > ndsLib.inf > + > NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1Comma= n > dsLib.inf > + > NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1Comma > ndsLib.inf > + > NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1Co > mmandsLib.inf > + > NULL|ShellPkg/Library/UefiShellNetwork2CommandsLib/UefiShellNetwork2Co > mmandsLib.inf > + > ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLi > b.inf > + > HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingL= ib. > inf > + > BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCo > mmandLib.inf > + ShellCEntryLib|ShellPkg/Library/UefiShellCEntryLib/UefiShellCEntryL= ib.inf > + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf > + } > + > +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE > + $(SKT_PKG)/Smm/Access/SmmAccess2Dxe.inf > + $(PCH_PKG)/SmmControl/RuntimeDxe/SmmControl2Dxe.inf > + UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf > + $(PCH_PKG)/Spi/Smm/PchSpiSmm.inf > + MinPlatformPkg/Flash/SpiFvbService/SpiFvbServiceSmm.inf > + UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf > + MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf { > + > + > LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxSmmLib.inf > + } > +!endif > + MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf > + MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf > + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf { > + > + > PciHostBridgeLib|$(BOARD_PKG)/Overrides/MdeModulePkg/Library/PciHostBr > idgeLib/PciHostBridgeLib.inf > + } > + MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf > + > + UefiCpuPkg/CpuDxe/CpuDxe.inf > + MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf > + MdeModulePkg/Universal/PrintDxe/PrintDxe.inf > + MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf > + MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf > + # > + # ACPI Support > + # > + MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf > + $(BOARD_PKG)/Overrides/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf > + > +!if gAdvancedFeaturePkgTokenSpaceGuid.PcdSmbiosEnable =3D=3D TRUE > + AdvancedFeaturePkg/Smbios/SmbiosBasicDxe/SmbiosBasicDxe.inf > +!endif > + > + !include $(BOARD_PKG)/$(BOARD_NAME)/PlatformPkgBuildOption.dsc > diff --git > a/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/SimicsX58PkgIa32X64.f > df > b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/SimicsX58PkgIa32X64.f > df > new file mode 100644 > index 0000000000..d6c381a515 > --- /dev/null > +++ > b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/SimicsX58PkgIa32X64.f > df > @@ -0,0 +1,303 @@ > +## @file > +# > +# Copyright (c) 2018 Intel Corporation. All rights reserved.
> +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +## > + > +[Defines] > +!include SimicsX58Pkg.fdf.inc > + > +# > +# Build the variable store and the firmware code as one unified flash de= vice > +# image. > +# > +[FD.SIMICSX58IA32X64] > +BaseAddress =3D $(FW_BASE_ADDRESS) > +Size =3D $(FW_SIZE) > +ErasePolarity =3D 1 > +BlockSize =3D $(BLOCK_SIZE) > +NumBlocks =3D $(FW_BLOCKS) > + > +!include VarStore.fdf.inc > + > +$(VARS_SIZE)|0x00002000 > +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfi > MdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize > +#NV_FTW_WORKING > +DATA =3D { > + # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature =3D > gEdkiiWorkingBlockSignatureGuid =3D > + # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f,= 0x1b, > 0x95 }} > + 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49, > + 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95, > + # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, R= eserved > + 0xE2, 0x33, 0xF2, 0x03, 0xFE, 0xFF, 0xFF, 0xFF, > + # WriteQueueSize: UINT64 > + 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 > +} > + > +0x00040000|0x00040000 > +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMd > eModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize > +#NV_FTW_SPARE > + > +0x00080000|0x0016C000 > +FV =3D FVMAIN_COMPACT > + > +$(SECFV_OFFSET)|$(SECFV_SIZE) > +FV =3D FvTempMemorySilicon > + > +# > +# Build the variable store and the firmware code as separate flash devic= e > +# images. > +# > +[FD.SIMICS_VARS] > +BaseAddress =3D $(FW_BASE_ADDRESS) > +Size =3D 0x80000 > +ErasePolarity =3D 1 > +BlockSize =3D $(BLOCK_SIZE) > +NumBlocks =3D 0x80 > + > +!include VarStore.fdf.inc > + > +[FD.SIMICS_CODE] > +BaseAddress =3D $(CODE_BASE_ADDRESS) > +Size =3D $(CODE_SIZE) > +ErasePolarity =3D 1 > +BlockSize =3D $(BLOCK_SIZE) > +NumBlocks =3D $(CODE_BLOCKS) > + > +0x00000000|0x0016C000 > +FV =3D FVMAIN_COMPACT > + > +0x0016C000|$(SECFV_SIZE) > +FV =3D FvTempMemorySilicon > + > +[FD.MEMFD] > +BaseAddress =3D $(MEMFD_BASE_ADDRESS) > +Size =3D 0xB00000 > +ErasePolarity =3D 1 > +BlockSize =3D 0x10000 > +NumBlocks =3D 0xB0 > + > +0x000000|0x006000 > +gSimicsX58PkgTokenSpaceGuid.PcdSimicsSecPageTablesBase|gSimicsX58PkgT > okenSpaceGuid.PcdSimicsSecPageTablesSize > + > +0x006000|0x001000 > +gSimicsX58PkgTokenSpaceGuid.PcdSimicsLockBoxStorageBase|gSimicsX58Pkg > TokenSpaceGuid.PcdSimicsLockBoxStorageSize > + > +0x007000|0x001000 > +gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress|gSimicsX > 58PkgTokenSpaceGuid.PcdGuidedExtractHandlerTableSize > + > +0x010000|0x008000 > +gSimicsX58PkgTokenSpaceGuid.PcdSimicsSecPeiTempRamBase|gSimicsX58Pk > gTokenSpaceGuid.PcdSimicsSecPeiTempRamSize > + > +0x020000|0x0E0000 > +gSimicsX58PkgTokenSpaceGuid.PcdSimicsPeiMemFvBase|gSimicsX58PkgToke > nSpaceGuid.PcdSimicsPeiMemFvSize > +FV =3D FvPreMemory > + > +0x100000|0xA00000 > +gSimicsX58PkgTokenSpaceGuid.PcdSimicsDxeMemFvBase|gSimicsX58PkgTok > enSpaceGuid.PcdSimicsDxeMemFvSize > +FV =3D DXEFV > + > +############################################################ > #################### > + > +[FV.FvTempMemorySilicon] > +FvAlignment =3D 16 > +FvForceRebase =3D TRUE > +ERASE_POLARITY =3D 1 > +MEMORY_MAPPED =3D TRUE > +STICKY_WRITE =3D TRUE > +LOCK_CAP =3D TRUE > +LOCK_STATUS =3D TRUE > +WRITE_DISABLED_CAP =3D TRUE > +WRITE_ENABLED_CAP =3D TRUE > +WRITE_STATUS =3D TRUE > +WRITE_LOCK_CAP =3D TRUE > +WRITE_LOCK_STATUS =3D TRUE > +READ_DISABLED_CAP =3D TRUE > +READ_ENABLED_CAP =3D TRUE > +READ_STATUS =3D TRUE > +READ_LOCK_CAP =3D TRUE > +READ_LOCK_STATUS =3D TRUE > +FvNameGuid =3D 229EEDCE-8E76-4809-B233-EC36BFBF6989 > + > +!include $(SKT_PKG)/SktSecInclude.fdf > + > +[FV.FvPreMemory] > +FvAlignment =3D 16 > +FvForceRebase =3D TRUE > +ERASE_POLARITY =3D 1 > +MEMORY_MAPPED =3D TRUE > +STICKY_WRITE =3D TRUE > +LOCK_CAP =3D TRUE > +LOCK_STATUS =3D TRUE > +WRITE_DISABLED_CAP =3D TRUE > +WRITE_ENABLED_CAP =3D TRUE > +WRITE_STATUS =3D TRUE > +WRITE_LOCK_CAP =3D TRUE > +WRITE_LOCK_STATUS =3D TRUE > +READ_DISABLED_CAP =3D TRUE > +READ_ENABLED_CAP =3D TRUE > +READ_STATUS =3D TRUE > +READ_LOCK_CAP =3D TRUE > +READ_LOCK_STATUS =3D TRUE > +FvNameGuid =3D 6522280D-28F9-4131-ADC4-F40EBFA45864 > + > +## > +# PEI Apriori file example, more PEIM module added later. > +## > +INF MdeModulePkg/Core/Pei/PeiMain.inf > +!include $(SKT_PKG)/SktPreMemoryInclude.fdf > +!include $(PCH_PKG)/PchPreMemoryInclude.fdf > +!include MinPlatformPkg/Include/Fdf/CorePreMemoryInclude.fdf > +INF MinPlatformPkg/PlatformInit/ReportFv/ReportFvPei.inf > +INF MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf > +INF MinPlatformPkg/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem= .inf > +!include MinPlatformPkg/Include/Fdf/CoreSecurityPreMemoryInclude.fdf > +!include > AdvancedFeaturePkg/Include/Fdf/CoreAdvancedPreMemoryInclude.fdf > +INF $(BOARD_PKG)/PlatformPei/PlatformPei.inf > +!include $(SKT_PKG)/SktPostMemoryInclude.fdf > +!include $(PCH_PKG)/PchPostMemoryInclude.fdf > +!include MinPlatformPkg/Include/Fdf/CorePostMemoryInclude.fdf > +INF MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf > +INF > MinPlatformPkg/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMem.inf > +!include MinPlatformPkg/Include/Fdf/CoreSecurityPostMemoryInclude.fdf > +!include > AdvancedFeaturePkg/Include/Fdf/CoreAdvancedPostMemoryInclude.fdf > + > +INF UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf > +INF $(SKT_PKG)/Smm/Access/SmmAccessPei.inf > +# S3 SMM PEI driver > +#INF UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.inf > + > +[FV.DXEFV] > +FvNameGuid =3D EACAB9EA-C3C6-4438-8FD7-2270826DC0BB > +BlockSize =3D 0x10000 > +FvAlignment =3D 16 > +ERASE_POLARITY =3D 1 > +MEMORY_MAPPED =3D TRUE > +STICKY_WRITE =3D TRUE > +LOCK_CAP =3D TRUE > +LOCK_STATUS =3D TRUE > +WRITE_DISABLED_CAP =3D TRUE > +WRITE_ENABLED_CAP =3D TRUE > +WRITE_STATUS =3D TRUE > +WRITE_LOCK_CAP =3D TRUE > +WRITE_LOCK_STATUS =3D TRUE > +READ_DISABLED_CAP =3D TRUE > +READ_ENABLED_CAP =3D TRUE > +READ_STATUS =3D TRUE > +READ_LOCK_CAP =3D TRUE > +READ_LOCK_STATUS =3D TRUE > + > +!include MinPlatformPkg/Include/Fdf/CoreUefiBootInclude.fdf > +INF > $(BOARD_PKG)/Overrides/PcAtChipsetPkg/8259InterruptControllerDxe/8259.i > nf > +!include $(SKT_PKG)/SktUefiBootInclude.fdf > +!include $(PCH_PKG)/PchUefiBootInclude.fdf > + > +INF MdeModulePkg/Universal/EbcDxe/EbcDxe.inf > +INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf > +INF UefiCpuPkg/CpuDxe/CpuDxe.inf > + > +!include MinPlatformPkg/Include/Fdf/CoreOsBootInclude.fdf > +INF MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf > +INF > MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe. > inf > +INF UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf > +INF MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf > +INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf > +INF MdeModulePkg/Universal/PrintDxe/PrintDxe.inf > +INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf > +INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf > + > +INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf > +INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf > +INF MinPlatformPkg/Flash/SpiFvbService/SpiFvbServiceSmm.inf > +INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf > + > +INF $(BOARD_PKG)/LegacySioDxe/LegacySioDxe.inf > +INF MdeModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2KeyboardDxe.inf > + > +INF $(BOARD_PKG)/SmbiosPlatformDxe/SmbiosPlatformDxe.inf > + > +INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf > +INF > $(BOARD_PKG)/Overrides/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf > +INF RuleOverride=3DACPITABLE $(BOARD_PKG)/AcpiTables/AcpiTables.inf > + > +INF $(BOARD_PKG)/Overrides/OvmfPkg/QemuVideoDxe/QemuVideoDxe.inf > +INF $(BOARD_PKG)/Overrides/MdeModulePkg/Logo/LogoDxe.inf > +INF MinPlatformPkg/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf > +INF MinPlatformPkg/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf > +INF $(BOARD_PKG)/PlatformDxe/Platform.inf > + > +INF ShellPkg/Application/Shell/Shell.inf > + > +# > +# Network modules > +# > +FILE DRIVER =3D 5D695E11-9B3F-4b83-B25F-4A8D5D69BE07 { > + SECTION PE32 =3D SimicsICH10SiliconBinPkg/UndiBinary/GigUndiDxe.efi > + SECTION UI =3D "IntelIch10UNDI" > +} > +!include AdvancedFeaturePkg/Include/Fdf/CoreAdvancedLateInclude.fdf > + > +!if gAdvancedFeaturePkgTokenSpaceGuid.PcdSmbiosEnable =3D=3D TRUE > + INF AdvancedFeaturePkg/Smbios/SmbiosBasicDxe/SmbiosBasicDxe.inf > +!endif > + > +!include MinPlatformPkg/Include/Fdf/CoreSecurityLateInclude.fdf > + > +[FV.FVMAIN_COMPACT] > +FvNameGuid =3D 6189987A-DDA6-4060-B313-49168DA9BD46 > +FvAlignment =3D 16 > +ERASE_POLARITY =3D 1 > +MEMORY_MAPPED =3D TRUE > +STICKY_WRITE =3D TRUE > +LOCK_CAP =3D TRUE > +LOCK_STATUS =3D TRUE > +WRITE_DISABLED_CAP =3D TRUE > +WRITE_ENABLED_CAP =3D TRUE > +WRITE_STATUS =3D TRUE > +WRITE_LOCK_CAP =3D TRUE > +WRITE_LOCK_STATUS =3D TRUE > +READ_DISABLED_CAP =3D TRUE > +READ_ENABLED_CAP =3D TRUE > +READ_STATUS =3D TRUE > +READ_LOCK_CAP =3D TRUE > +READ_LOCK_STATUS =3D TRUE > + > +FILE FV_IMAGE =3D 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { > + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF > PROCESSING_REQUIRED =3D TRUE { > + # > + # These firmware volumes will have files placed in them uncompressed= , > + # and then both firmware volumes will be compressed in a single > + # compression operation in order to achieve better overall compressi= on. > + # > + SECTION FV_IMAGE =3D FvPreMemory > + SECTION FV_IMAGE =3D DXEFV > + } > +} > + > +!include DecomprScratchEnd.fdf.inc > + > + > +############################################################ > #################### > +# > +# Rules are use with the [FV] section's module INF type to define > +# how an FFS file is created for a given INF file. The following Rule ar= e the > default > +# rules for the different module type. User can add the customized rules= to > define the > +# content of the FFS file. > +# > +############################################################ > #################### > + > +!include MinPlatformPkg/Include/Fdf/RuleInclude.fdf > + > +[Rule.Common.SEC.RESET_VECTOR] > + FILE RAW =3D $(NAMED_GUID) { > + RAW RAW |.raw > + } > + > +[Rule.Common.SEC.RESET_SECMAIN] > + FILE SEC =3D $(NAMED_GUID) RELOCS_STRIPPED { > + UI STRING=3D"$(MODULE_NAME)" Optional > + VERSION STRING=3D"$(INF_VERSION)" Optional > BUILD_NUM=3D$(BUILD_NUMBER) > + PE32 PE32 Align =3D 16 $(INF_OUTPUT)/$(MODULE_NAME).efi > + } > diff --git > a/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/VarStore.fdf.inc > b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/VarStore.fdf.inc > new file mode 100644 > index 0000000000..76c28e9efc > --- /dev/null > +++ b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/VarStore.fdf.inc > @@ -0,0 +1,53 @@ > +## @file > +# FDF include file with Layout Regions that define an empty variable st= ore. > +# > +# Copyright (C) 2014, Red Hat, Inc. > +# Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved. > +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +## > + > +0x00000000|0x0003e000 > +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMde > ModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize > +#NV_VARIABLE_STORE > +DATA =3D { > + ## This is the EFI_FIRMWARE_VOLUME_HEADER > + # ZeroVector [] > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + # FileSystemGuid: gEfiSystemNvDataFvGuid =3D > + # { 0xFFF12B8D, 0x7696, 0x4C8B, > + # { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }} > + 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C, > + 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50, > + # FvLength: 0x80000 > + 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, > + #Signature "_FVH" #Attributes > + 0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00, > + #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision > + 0x48, 0x00, 0x2A, 0x09, 0x00, 0x00, 0x00, 0x02, > + #Blockmap[0]: 7 Blocks * 0x10000 Bytes / Block > + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, > + #Blockmap[1]: End > + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > + ## This is the VARIABLE_STORE_HEADER > +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE > + # Signature: gEfiAuthenticatedVariableGuid =3D > + # { 0xaaf32c78, 0x947b, 0x439a, > + # { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }} > + 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43, > + 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92, > +!else > + #Signature: gEfiVariableGuid =3D > + # { 0xddcf3616, 0x3275, 0x4164, { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f,= 0xfe, > 0x7d }} > + 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41, > + 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d, > +!endif > + #Size: 0x3E000 > (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48 > (size of EFI_FIRMWARE_VOLUME_HEADER) =3D 0x03DFB8 > + # This can speed up the Variable Dispatch a bit. > + 0xB8, 0xDF, 0x03, 0x00, > + # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: > UINT32 > + 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 > +} > + > diff --git a/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/bld.bat > b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/bld.bat > new file mode 100644 > index 0000000000..efce310dfe > --- /dev/null > +++ b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/bld.bat > @@ -0,0 +1,139 @@ > +@echo off > +@REM @file > +@REM Copyright (c) 2018 Intel Corporation. All rights reserved.
> +@REM > +@REM SPDX-License-Identifier: BSD-2-Clause-Patent > +@REM > + > +@echo off > + > +REM Run setlocal to take a snapshot of the environment variables. endlo= cal is > called to restore the environment. > +setlocal > +set SCRIPT_ERROR=3D0 > + > +REM ---- Do NOT use :: for comments Inside of code blocks() ---- > + > +::*********************************************************** > *********** > +:: Initial Setup > +::*********************************************************** > *********** > + > +:parseCmdLine > +if "%1"=3D=3D"" goto :argumentCheck > + > +if /I "%1"=3D=3D"debug" set TARGET=3DDEBUG > +if /I "%1"=3D=3D"release" set TARGET=3DRELEASE > + > +if /I "%1"=3D=3D"cleantree" ( > + set BUILD_TYPE=3Dcleantree > + call :cleantree > + goto :EOF > +) > + > +shift > +GOTO :parseCmdLine > + > +:argumentCheck: > + > +if /I "%TARGET%" =3D=3D "" ( > + echo Info: debug/release argument is empty, use DEBUG as default > + set TARGET=3DDEBUG > +) > + > +REM Art to notify which board you're working on > +echo. > +type logo.txt > +echo. > + > +:: > +:: Build configuration > +:: > +set BUILD_REPORT_FLAGS=3D > +set BUILD_CMD_LINE=3D > +set BUILD_LOG=3D%WORKSPACE%\Build\BuildSrc\build.log > +set BUILD_REPORT=3D%WORKSPACE%\Build\BuildSrc\BuildReport.txt > + > +del %BUILD_LOG% *.efi *.log 2>NUL > + > +echo -------------------------------------------------------------------= ------------------------- > +echo. > +echo QSP Build Start > +echo. > +echo -------------------------------------------------------------------= ------------------------- > + > + > +:doPreBuild > +echo. > +echo -------------------------------------------------------------------= - > +echo. > +echo Prebuild Start > +echo. > +echo -------------------------------------------------------------------= - > +call prebuild.bat > +if %SCRIPT_ERROR% NEQ 0 EXIT /b %ERRORLEVEL% > + > +echo -------------------------------------------------------------------= - > +echo. > +echo Prebuild End > +echo. > +echo -------------------------------------------------------------------= - > +if %ERRORLEVEL% NEQ 0 EXIT /b %ERRORLEVEL% > +timeout 1 > + > +:buildBios > +set BUILD_CMD_LINE=3D%BUILD_CMD_LINE% -D > MAX_SOCKET=3D%MAX_SOCKET% -y %BUILD_REPORT% > +echo -------------------------------------------------------------------= - > +echo. > +echo Build Start > +echo. > +echo -------------------------------------------------------------------= - > +echo. > +echo build %BUILD_CMD_LINE% --log=3D%BUILD_LOG% > %BUILD_REPORT_FLAGS% > +call build %BUILD_CMD_LINE% --log=3D%BUILD_LOG% > %BUILD_REPORT_FLAGS% > +echo -------------------------------------------------------------------= - > +echo. > +echo Build End > +echo. > +echo -------------------------------------------------------------------= - > +if %ERRORLEVEL% NEQ 0 EXIT /b %ERRORLEVEL% > +timeout 1 > + > +:postBuild > + > +echo -------------------------------------------------------------------= - > +echo. > +echo PostBuild Start > +echo. > +echo -------------------------------------------------------------------= - > +echo. > +REM call postbuild.bat > +if %ERRORLEVEL% NEQ 0 EXIT /b %ERRORLEVEL% > +timeout 1 > +echo -------------------------------------------------------------------= - > +echo. > +echo PostBuild End > +echo. > +echo -------------------------------------------------------------------= - > + > +echo %date% %time% > +echo. > + > +echo -------------------------------------------------------------------= ------------------------- > +echo. > +echo QSP Build End > +echo. > +echo -------------------------------------------------------------------= ------------------------- > + > +:done > +endlocal & EXIT /b %SCRIPT_ERROR% > + > +::-------------------------------------------------------- > +::-- Function section starts below here > +::-------------------------------------------------------- > +:cleantree > +choice /t 3 /d y /m "Confirm: clean tree of intermediate files created i= n tree > during build" > +if %ERRORLEVEL% EQU 2 goto :EOF > +goto :EOF > + > + > +:ErrorHandler: > +echo Error handler > diff --git > a/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/build_config.cfg > b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/build_config.cfg > new file mode 100644 > index 0000000000..ad3ae229e8 > --- /dev/null > +++ b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/build_config.cfg > @@ -0,0 +1,31 @@ > +# @ build_config.cfg > +# This is the BoardX58ICH10 board specific build settings > +# > +# Copyright (c) 2019, Intel Corporation. All rights reserved.
> +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > + > + > +[CONFIG] > +WORKSPACE_PLATFORM_BIN =3D WORKSPACE_PLATFORM_BIN > +EDK_SETUP_OPTION =3D > +openssl_path =3D > +PLATFORM_BOARD_PACKAGE =3D SimicsOpenBoardPkg > +PROJECT =3D SimicsOpenBoardPkg/BoardX58ICH10 > +BOARD =3D BoardX58ICH10 > +FLASH_MAP_FDF =3D > SimicsOpenBoardPkg/BoardX58ICH10/Include/Fdf/FlashMapInclude.fdf > +PROJECT_DSC =3D > SimicsOpenBoardPkg/BoardX58ICH10/SimicsX58PkgIa32X64.dsc > +BOARD_PKG_PCD_DSC =3D > SimicsOpenBoardPkg/BoardX58ICH10/PlatformPkgPcd.dsc > +PrepRELEASE =3D DEBUG > +SILENT_MODE =3D FALSE > +EXT_CONFIG_CLEAR =3D > +CapsuleBuild =3D FALSE > +EXT_BUILD_FLAGS =3D > +CAPSULE_BUILD =3D 0 > +TARGET =3D DEBUG > +TARGET_SHORT =3D D > +PERFORMANCE_BUILD =3D FALSE > +FSP_WRAPPER_BUILD =3D FALSE > +FSP_BINARY_BUILD =3D FALSE > +FSP_TEST_RELEASE =3D FALSE > +SECURE_BOOT_ENABLE =3D FALSE > diff --git a/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/prebuild.bat > b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/prebuild.bat > new file mode 100644 > index 0000000000..666332e2d4 > --- /dev/null > +++ b/Platform/Intel/SimicsOpenBoardPkg/BoardX58ICH10/prebuild.bat > @@ -0,0 +1,198 @@ > +@echo off > +@REM @file > +@REM Copyright (c) 2018 Intel Corporation. All rights reserved.
> +@REM > +@REM SPDX-License-Identifier: BSD-2-Clause-Patent > +@REM > + > +@set SCRIPT_ERROR=3D0 > + > +set /a prebuildstep=3D0 > + > +call :check_BuildTools > +if %SCRIPT_ERROR% NEQ 0 GOTO :done > + > +call :setBuildEnv > +if %SCRIPT_ERROR% NEQ 0 GOTO :done > + > +call :createTargetTxt > +if %SCRIPT_ERROR% NEQ 0 GOTO :done > + > +REM call :genPlatformOffsetHeaderFile > +REM if %SCRIPT_ERROR% NEQ 0 GOTO :done > + > +:prebuildFinish > +echo. > +echo ACTIVE_PLATFORM =3D %WORKSPACE%\edk2- > platforms\Platform\Intel\%BOARD_PKG%\%BOARD_NAME%\SimicsX58PkgIa3 > 2X64.dsc > +echo EDK_TOOLS_PATH =3D %EDK_TOOLS_PATH% > +echo TARGET =3D %TARGET% > +echo TARGET_ARCH =3D IA32 X64 > +echo TOOL_CHAIN_TAG =3D %TOOL_CHAIN_TAG% > +echo WORKSPACE =3D %WORKSPACE% > +echo PACKAGES_PATH =3D %PACKAGES_PATH% > +echo MAX_CONCURRENT_THREAD_NUMBER =3D > %BUILD_MAX_CON_THREAD_NUM% > +echo. > +echo Build Path =3D %OUTPUT_DIR% > +echo. > + > +REM Remove environment variable because it's no longer needed. > +set BUILD_MAX_CON_THREAD_NUM=3D > + > +:done > +REM Use done label to exit batch file and run any final steps; GOTO :EOF > immediately exits. > +EXIT /B %SCRIPT_ERROR% > + > +::-------------------------------------------------------- > +::-- Function section starts below here > +::-------------------------------------------------------- > + > +:cleanup_check_VSTools > +set COMPILER_VERSION_STRING=3D > +del cloutput.txt > nul > +REM cleanup_check_VSTools is called below. When a label is called, 'GOTO > :EOF' is used to return to caller. > +GOTO :EOF > + > +:check_BuildTools > +echo PreBuild.%prebuildstep% check_BuildTools > +echo ..VSTools > +set /a prebuildstep=3D%prebuildstep%+1 > +set TOOL_CHAIN_TAG=3D > +@if not defined TOOL_CHAIN_TAG ( > + echo. > + echo Prebuild: TOOL_CHAIN_TAG is not set before > + echo. > + > + @if defined VS140COMNTOOLS ( > + echo. > + echo Set the VS2015 environment. > + echo. > + set CL_SEL=3DVS2015 > + if /I "%VS140COMNTOOLS%" =3D=3D "C:\Program Files\Microsoft Visual S= tudio > 14.0\Common7\Tools\" ( > + set TOOL_CHAIN_TAG=3DVS2015 > + ) else ( > + set TOOL_CHAIN_TAG=3DVS2015x86 > + ) > + if /I "%PROCESSOR_ARCHITECTURE%" =3D=3D "AMD64" ( > + set CL_CMDLINE=3D"%VS140COMNTOOLS:~0,-14%VC\bin\amd64\cl.exe" > + ) else ( > + set CL_CMDLINE=3D"%VS140COMNTOOLS:~0,-14%VC\bin\cl.exe" > + ) > + ) else if defined VS120COMNTOOLS ( > + echo. > + echo Set the VS2013 environment. > + echo. > + set CL_SEL=3DVS2013 > + if /I "%VS120COMNTOOLS%" =3D=3D "C:\Program Files\Microsoft Visual S= tudio > 12.0\Common7\Tools\" ( > + set TOOL_CHAIN_TAG=3DVS2013 > + ) else ( > + set TOOL_CHAIN_TAG=3DVS2013x86 > + ) > + if /I "%PROCESSOR_ARCHITECTURE%" =3D=3D "AMD64" ( > + set CL_CMDLINE=3D"%VS120COMNTOOLS:~0,-14%VC\bin\amd64\cl.exe" > + ) else ( > + set CL_CMDLINE=3D"%VS120COMNTOOLS:~0,-14%VC\bin\cl.exe" > + ) > + ) else ( > + echo. > + echo !!! ERROR !!! VS2015 or VS2013 not installed correctly. !!! > + echo. > + goto :ErrorExit > + ) > +) > + > +echo ..iASL > +set CHECK_PATH_IASL=3D%IASL_PREFIX% > +if not exist %CHECK_PATH_IASL%\iasl.exe ( > + echo. > + echo !!! ERROR !!! Could not find iASL compiler at > %CHECK_PATH_IASL%\iasl.exe. !!! > + echo. > + set SCRIPT_ERROR=3D1 > +) > +set CHECK_PATH_IASL=3D > + > +echo ..NASM > +set CHECK_PATH_NASM=3Dc:\NASM > +if not exist %CHECK_PATH_NASM%\nasm.exe ( > + echo. > + echo !!! ERROR !!! Could not find NASM compiler at > %CHECK_PATH_NASM%\nasm.exe. !!! > + echo. > + set SCRIPT_ERROR=3D1 > +) > +set CHECK_PATH_NASM=3D > + > +echo ..Python > +set CHECK_PATH_PYTHON=3Dc:\Python27 > +if not exist %CHECK_PATH_PYTHON%\python.exe ( > + echo. > + echo !!! ERROR !!! Could not find Python at > %CHECK_PATH_PYTHON%\python.exe. !!! > + echo. > + set SCRIPT_ERROR=3D1 > +) > +set CHECK_PATH_PYTHON=3D > +set PYTHON_HOME=3DC:\Python27 > + > +GOTO :EOF > + > +:setBuildEnv > +echo PreBuild.%prebuildstep% SetBuildEnv > +set /a prebuildstep=3D%prebuildstep%+1 > + > +@set BOARD_PKG=3DSimicsOpenBoardPkg > +@set BOARD_NAME=3DBoardX58ICH10 > +@set MAX_SOCKET=3D2 > + > +echo. > +echo BOARD_NAME=3D%BOARD_NAME% > +echo BOARD_PKG=3D%BOARD_PKG% > +echo MAX_SOCKET=3D%MAX_SOCKET% > +echo TARGET=3D%TARGET% > + > +@set > OUTPUT_DIR=3D%WORKSPACE%\Build\BuildSrc\%BOARD_PKG%\%BOARD_NAM > E%\%TARGET%_%TOOL_CHAIN_TAG% > + > +if not exist %OUTPUT_DIR% mkdir %OUTPUT_DIR% > +GOTO :EOF > + > +:createTargetTxt > +echo PreBuild.%prebuildstep% CreateTargetTxt > +set /a prebuildstep=3D%prebuildstep%+1 > +set /a BUILD_MAX_CON_THREAD_NUM =3D %NUMBER_OF_PROCESSORS%-1 > +@REM set /a BUILD_MAX_CON_THREAD_NUM =3D 1 > +findstr /V "ACTIVE_PLATFORM TARGET TARGET_ARCH TOOL_CHAIN_TAG > BUILD_RULE_CONF MAX_CONCURRENT_THREAD_NUMBER" > %WORKSPACE%\Conf\target.txt > %OUTPUT_DIR%\target.txt 2>NUL > +echo ACTIVE_PLATFORM =3D %WORKSPACE%/edk2- > platforms/Platform/Intel/%BOARD_PKG%/%BOARD_NAME%/SimicsX58PkgIa3 > 2X64.dsc >> %OUTPUT_DIR%\target.txt > +echo TARGET =3D %TARGET% >> > %OUTPUT_DIR%\target.txt > +echo TARGET_ARCH =3D IA32 X64 >> > %OUTPUT_DIR%\target.txt > +echo TOOL_CHAIN_TAG =3D %TOOL_CHAIN_TAG% >> > %OUTPUT_DIR%\target.txt > +echo BUILD_RULE_CONF =3D Conf/build_rule.txt >> > %OUTPUT_DIR%\target.txt > +echo MAX_CONCURRENT_THREAD_NUMBER =3D > %BUILD_MAX_CON_THREAD_NUM% >> %OUTPUT_DIR%\target.txt > +if exist %WORKSPACE%\Conf\target.txt ( > + del /f %WORKSPACE%\Conf\target.txt > +) > +move /Y %OUTPUT_DIR%\target.txt %WORKSPACE%\Conf\ > nul > +if not exist %OUTPUT_DIR%\X64 mkdir %OUTPUT_DIR%\X64 > +GOTO :EOF > + > + > +:genPlatformOffsetHeaderFile > +echo. > +echo PreBuild.%prebuildstep% GenPlatformOffsetHeaderFile > +set /a prebuildstep=3D%prebuildstep%+1 > + > +echo Info: re-generating PlatformOffset header files > + > +set PRE_BUILD_CMD_LINE=3D%BUILD_CMD_LINE% -D > MAX_SOCKET=3D%MAX_SOCKET% > +set PRE_BUILD_LOG=3D%WORKSPACE%\Build\BuildSrc\prebuild.log > +set PRE_BUILD_REPORT=3D%WORKSPACE%\Build\BuildSrc\preBuildReport.txt > + > +echo build %PRE_BUILD_CMD_LINE% -m > %BOARD_PKG%\Acpi\BoardAcpiDxe\Dsdt.inf -y %PRE_BUILD_REPORT% -- > log=3D%PRE_BUILD_LOG% > +call build %PRE_BUILD_CMD_LINE% -m > %BOARD_PKG%\Acpi\BoardAcpiDxe\Dsdt.inf -y %PRE_BUILD_REPORT% -- > log=3D%PRE_BUILD_LOG% > +if %ERRORLEVEL% NEQ 0 EXIT /b %ERRORLEVEL% > + > +@REM PSYS =3D=3D FIX0 > +@REM MCTL =3D=3D FIX8 > +set AML_FILTER=3D"\"PSYS\" .MCTL\" .FIX[0-9,A-Z]\"" > +echo AML_FILTER=3D%AML_FILTER% > +%WORKSPACE%\edk2- > platforms\Platform\Intel\MinPlatformPkg\Tools\AmlGenOffset\AmlGenOffset. > py -d --aml_filter %AML_FILTER% -o %WORKSPACE%\edk2- > platforms\Platform\Intel\%BOARD_PKG%\Acpi\BoardAcpiDxe\AmlOffsetTable. > c > %OUTPUT_DIR%\X64\PurleyOpenBoardPkg\Acpi\BoardAcpiDxe\DSDT\OUTPU > T\Dsdt\WFPPlatform.offset.h > +echo. > +echo GenOffset done > + > +GOTO :EOF > -- > 2.16.2.windows.1