Re: [edk2-platforms PATCH v4 7/7] SimicsOpenBoardPkg/BoardX58Ich10: Add board modules for QSP Build tip

["Kubacki, Michael A" <michael.a.kubacki@intel.com>]

Reviewed-by: Michael Kubacki <michael.a.kubacki@intel.com>

> -----Original Message-----
> From: Wei, David Y
> Sent: Friday, August 30, 2019 2:19 PM
> To: devel@edk2.groups.io
> Cc: Wu, Hao A <hao.a.wu@intel.com>; Gao, Liming <liming.gao@intel.com>;
> Sinha, Ankit <ankit.sinha@intel.com>; Agyeman, Prince
> <prince.agyeman@intel.com>; Kubacki, Michael A
> <michael.a.kubacki@intel.com>; Desimone, Nathaniel L
> <nathaniel.l.desimone@intel.com>; Kinney, Michael D
> <michael.d.kinney@intel.com>
> Subject: [edk2-platforms PATCH v4 7/7] SimicsOpenBoardPkg/BoardX58Ich10:
> Add board modules for QSP Build tip
> 
> Add BoardX58ICH10 modules for QSP Build tip
> 
> Cc: Hao Wu <hao.a.wu@intel.com>
> Cc: Liming Gao <liming.gao@intel.com>
> Cc: Ankit Sinha <ankit.sinha@intel.com>
> Cc: Agyeman Prince <prince.agyeman@intel.com>
> Cc: Kubacki Michael A <michael.a.kubacki@intel.com>
> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
> Cc: Michael D Kinney <michael.d.kinney@intel.com>
> 
> Signed-off-by: David Wei <david.y.wei@intel.com>
> ---
>  .../Library/BoardInitLib/PeiBoardInitPostMemLib.c  |  44 +++
>  .../Library/BoardInitLib/PeiBoardInitPreMemLib.c   | 110 ++++++++
>  .../Library/BoardInitLib/PeiX58Ich10Detect.c       |  26 ++
>  .../BoardInitLib/PeiX58Ich10InitPostMemLib.c       |  34 +++
>  .../BoardInitLib/PeiX58Ich10InitPreMemLib.c        | 111 ++++++++
>  .../BoardX58Ich10/DecomprScratchEnd.fdf.inc        |  67 +++++
>  .../BoardInitLib/PeiBoardInitPostMemLib.inf        |  36 +++
>  .../Library/BoardInitLib/PeiBoardInitPreMemLib.inf |  39 +++
>  .../Library/BoardInitLib/PeiX58Ich10InitLib.h      |  16 ++
>  .../BoardX58Ich10/OpenBoardPkg.dsc                 | 233 ++++++++++++++++
>  .../BoardX58Ich10/OpenBoardPkg.fdf                 | 304 +++++++++++++++++++++
>  .../BoardX58Ich10/OpenBoardPkg.fdf.inc             |  54 ++++
>  .../BoardX58Ich10/OpenBoardPkgBuildOption.dsc      |  78 ++++++
>  .../BoardX58Ich10/OpenBoardPkgConfig.dsc           |  56 ++++
>  .../BoardX58Ich10/OpenBoardPkgPcd.dsc              | 281 +++++++++++++++++++
>  .../BoardX58Ich10/VarStore.fdf.inc                 |  53 ++++
>  .../BoardX58Ich10/build_config.cfg                 |  31 +++
>  17 files changed, 1573 insertions(+)
>  create mode 100644
> Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library/BoardInitLib/PeiBo
> ardInitPostMemLib.c
>  create mode 100644
> Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library/BoardInitLib/PeiBo
> ardInitPreMemLib.c
>  create mode 100644
> Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library/BoardInitLib/PeiX5
> 8Ich10Detect.c
>  create mode 100644
> Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library/BoardInitLib/PeiX5
> 8Ich10InitPostMemLib.c
>  create mode 100644
> Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library/BoardInitLib/PeiX5
> 8Ich10InitPreMemLib.c
>  create mode 100644
> Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/DecomprScratchEnd.fdf.in
> c
>  create mode 100644
> Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library/BoardInitLib/PeiBo
> ardInitPostMemLib.inf
>  create mode 100644
> Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library/BoardInitLib/PeiBo
> ardInitPreMemLib.inf
>  create mode 100644
> Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library/BoardInitLib/PeiX5
> 8Ich10InitLib.h
>  create mode 100644
> Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc
>  create mode 100644
> Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.fdf
>  create mode 100644
> Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.fdf.inc
>  create mode 100644
> Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgBuildOption
> .dsc
>  create mode 100644
> Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgConfig.dsc
>  create mode 100644
> Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.dsc
>  create mode 100644
> Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/VarStore.fdf.inc
>  create mode 100644
> Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/build_config.cfg
> 
> diff --git
> a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library/BoardInitLib/Pei
> BoardInitPostMemLib.c
> b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library/BoardInitLib/Pei
> BoardInitPostMemLib.c
> new file mode 100644
> index 0000000000..5ece8c6e34
> --- /dev/null
> +++
> b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library/BoardInitLib/Pei
> BoardInitPostMemLib.c
> @@ -0,0 +1,44 @@
> +/** @file
> +  Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include <PiPei.h>
> +#include <Library/BaseLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/BoardInitLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/DebugLib.h>
> +
> +EFI_STATUS
> +EFIAPI
> +X58Ich10BoardInitBeforeSiliconInit (
> +  VOID
> +  );
> +
> +EFI_STATUS
> +EFIAPI
> +X58Ich10BoardInitAfterSiliconInit (
> +  VOID
> +  );
> +
> +EFI_STATUS
> +EFIAPI
> +BoardInitBeforeSiliconInit (
> +  VOID
> +  )
> +{
> +  X58Ich10BoardInitBeforeSiliconInit ();
> +  return EFI_SUCCESS;
> +}
> +
> +EFI_STATUS
> +EFIAPI
> +BoardInitAfterSiliconInit (
> +  VOID
> +  )
> +{
> +  X58Ich10BoardInitAfterSiliconInit ();
> +  return EFI_SUCCESS;
> +}
> diff --git
> a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library/BoardInitLib/Pei
> BoardInitPreMemLib.c
> b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library/BoardInitLib/Pei
> BoardInitPreMemLib.c
> new file mode 100644
> index 0000000000..d16e649d34
> --- /dev/null
> +++
> b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library/BoardInitLib/Pei
> BoardInitPreMemLib.c
> @@ -0,0 +1,110 @@
> +/** @file
> +  Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include <PiPei.h>
> +#include <Library/BaseLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/BoardInitLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/DebugLib.h>
> +
> +EFI_STATUS
> +EFIAPI
> +X58Ich10BoardDetect(
> +  VOID
> +  );
> +
> +EFI_BOOT_MODE
> +EFIAPI
> +X58Ich10BoardBootModeDetect (
> +  VOID
> +  );
> +
> +EFI_STATUS
> +EFIAPI
> +X58Ich10BoardDebugInit (
> +  VOID
> +  );
> +
> +EFI_STATUS
> +EFIAPI
> +X58Ich10BoardInitBeforeMemoryInit (
> +  VOID
> +  );
> +
> +EFI_STATUS
> +EFIAPI
> +X58Ich10BoardInitAfterMemoryInit (
> +  VOID
> +  );
> +
> +EFI_STATUS
> +EFIAPI
> +BoardDetect (
> +  VOID
> +  )
> +{
> +  X58Ich10BoardDetect ();
> +  return EFI_SUCCESS;
> +}
> +
> +EFI_STATUS
> +EFIAPI
> +BoardDebugInit (
> +  VOID
> +  )
> +{
> +  X58Ich10BoardDebugInit ();
> +  return EFI_SUCCESS;
> +}
> +
> +EFI_BOOT_MODE
> +EFIAPI
> +BoardBootModeDetect (
> +  VOID
> +  )
> +{
> +  return X58Ich10BoardBootModeDetect ();
> +}
> +
> +EFI_STATUS
> +EFIAPI
> +BoardInitBeforeMemoryInit (
> +  VOID
> +  )
> +{
> +  X58Ich10BoardInitBeforeMemoryInit ();
> +  return EFI_SUCCESS;
> +}
> +
> +EFI_STATUS
> +EFIAPI
> +BoardInitAfterMemoryInit (
> +  VOID
> +  )
> +{
> +  X58Ich10BoardInitAfterMemoryInit ();
> +  return EFI_SUCCESS;
> +}
> +
> +EFI_STATUS
> +EFIAPI
> +BoardInitBeforeTempRamExit (
> +  VOID
> +  )
> +{
> +  return EFI_SUCCESS;
> +}
> +
> +EFI_STATUS
> +EFIAPI
> +BoardInitAfterTempRamExit (
> +  VOID
> +  )
> +{
> +  return EFI_SUCCESS;
> +}
> +
> diff --git
> a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library/BoardInitLib/Pei
> X58Ich10Detect.c
> b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library/BoardInitLib/Pei
> X58Ich10Detect.c
> new file mode 100644
> index 0000000000..03488ef1f4
> --- /dev/null
> +++
> b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library/BoardInitLib/Pei
> X58Ich10Detect.c
> @@ -0,0 +1,26 @@
> +/** @file
> +  Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include <PiPei.h>
> +#include <Library/DebugLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/HobLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/PciLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/BoardInitLib.h>
> +
> +EFI_STATUS
> +EFIAPI
> +X58Ich10BoardDetect (
> +  VOID
> +  )
> +{
> +  DEBUG ((EFI_D_INFO, "X58Ich10BoardDetect\n"));
> +  return EFI_SUCCESS;
> +}
> diff --git
> a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library/BoardInitLib/Pei
> X58Ich10InitPostMemLib.c
> b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library/BoardInitLib/Pei
> X58Ich10InitPostMemLib.c
> new file mode 100644
> index 0000000000..bd6924e269
> --- /dev/null
> +++
> b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library/BoardInitLib/Pei
> X58Ich10InitPostMemLib.c
> @@ -0,0 +1,34 @@
> +/** @file
> +  Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include <PiPei.h>
> +#include <Library/DebugLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/HobLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/PciLib.h>
> +
> +#include "PeiX58Ich10InitLib.h"
> +EFI_STATUS
> +EFIAPI
> +X58Ich10BoardInitBeforeSiliconInit (
> +  VOID
> +  )
> +{
> +  return EFI_SUCCESS;
> +}
> +
> +EFI_STATUS
> +EFIAPI
> +X58Ich10BoardInitAfterSiliconInit (
> +  VOID
> +  )
> +{
> +
> +  DEBUG((EFI_D_ERROR, "X58Ich10BoardInitAfterSiliconInit\n"));
> +  return EFI_SUCCESS;
> +}
> diff --git
> a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library/BoardInitLib/Pei
> X58Ich10InitPreMemLib.c
> b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library/BoardInitLib/Pei
> X58Ich10InitPreMemLib.c
> new file mode 100644
> index 0000000000..c3a31ed426
> --- /dev/null
> +++
> b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library/BoardInitLib/Pei
> X58Ich10InitPreMemLib.c
> @@ -0,0 +1,111 @@
> +/** @file
> +  Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include <Base.h>
> +#include <PiPei.h>
> +#include <Uefi.h>
> +#include <Library/DebugLib.h>
> +#include <Library/BaseLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/HobLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/PciLib.h>
> +#include <Library/BoardInitLib.h>
> +#include <Library/PeiServicesLib.h>
> +#include <Library/PeiServicesTablePointerLib.h>
> +
> +#include "PeiX58Ich10InitLib.h"
> +#include <Register/X58Ich10.h>
> +/**
> +  Reads 8-bits of CMOS data.
> +
> +  Reads the 8-bits of CMOS data at the location specified by Index.
> +  The 8-bit read value is returned.
> +
> +  @param  Index  The CMOS location to read.
> +
> +  @return The value read.
> +
> +**/
> +UINT8
> +EFIAPI
> +CmosRead8(
> +  IN  UINTN                     Index
> +  )
> +{
> +  IoWrite8 (0x70, (UINT8)Index);
> +  return IoRead8(0x71);
> +}
> +
> +
> +/**
> +  Writes 8-bits of CMOS data.
> +
> +  Writes 8-bits of CMOS data to the location specified by Index
> +  with the value specified by Value and returns Value.
> +
> +  @param  Index  The CMOS location to write.
> +  @param  Value  The value to write to CMOS.
> +
> +  @return The value written to CMOS.
> +
> +**/
> +UINT8
> +EFIAPI
> +CmosWrite8(
> +  IN  UINTN                     Index,
> +  IN  UINT8                     Value
> +  )
> +{
> +  IoWrite8 (0x70, (UINT8)Index);
> +  IoWrite8 (0x71, Value);
> +  return Value;
> +}
> +
> +
> +EFI_STATUS
> +EFIAPI
> +X58Ich10BoardInitBeforeMemoryInit (
> +  VOID
> +  )
> +{
> +  return EFI_SUCCESS;
> +}
> +
> +EFI_STATUS
> +EFIAPI
> +X58Ich10BoardInitAfterMemoryInit (
> +  VOID
> +  )
> +{
> +  return EFI_SUCCESS;
> +}
> +
> +EFI_STATUS
> +EFIAPI
> +X58Ich10BoardDebugInit (
> +  VOID
> +  )
> +{
> +  return EFI_SUCCESS;
> +}
> +
> +EFI_BOOT_MODE
> +EFIAPI
> +X58Ich10BoardBootModeDetect (
> +  VOID
> +  )
> +{
> +  EFI_BOOT_MODE BootMode = BOOT_WITH_FULL_CONFIGURATION;
> +
> +  DEBUG((EFI_D_INFO, "modeValue = %x\n",
> IoBitFieldRead16(ICH10_PMBASE_IO + 4, 10, 12)));
> +  if (IoBitFieldRead16(ICH10_PMBASE_IO + 4, 10, 12) == 0x5) {
> +    BootMode = BOOT_ON_S3_RESUME;
> +  }
> +
> +  return BootMode;
> +}
> diff --git
> a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/DecomprScratchEnd.fdf.
> inc
> b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/DecomprScratchEnd.fdf.
> inc
> new file mode 100644
> index 0000000000..ae9a625da9
> --- /dev/null
> +++
> b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/DecomprScratchEnd.fdf.
> inc
> @@ -0,0 +1,67 @@
> +## @file
> +#  This FDF include file computes the end of the scratch buffer used in
> +#  DecompressMemFvs() [SimicsX58Pkg/Sec/SecMain.c]. It is based on the
> decompressed
> +#  (ie. original) size of the LZMA-compressed section of the one FFS file in
> +#  the FVMAIN_COMPACT firmware volume.
> +#
> +#  Copyright (C) 2015, Red Hat, Inc.
> +#  Copyright (c) 2006 - 2019 Intel Corporation. All rights reserved. <BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +# The GUID EE4E5898-3914-4259-9D6E-DC7BD79403CF means
> "LzmaCustomDecompress".
> +# The decompressed output will have the following structure (see the file
> +# "9E21FD93-9C72-4c15-8C4B-E77F1DB2D792SEC1.guided.dummy" in the
> +# Build/SimicsX58*/*/FV/Ffs/9E21FD93-9C72-4c15-8C4B-E77F1DB2D792/
> directory):
> +#
> +# Size                 Contents
> +# -------------------  --------------------------------------------------------
> +#                   4  EFI_COMMON_SECTION_HEADER, stating size 124 (0x7C) and
> +#                      type 0x19 (EFI_SECTION_RAW). The purpose of this section
> +#                      is to pad the start of PEIFV to 128 bytes.
> +#                 120  Zero bytes (padding).
> +#
> +#                   4  EFI_COMMON_SECTION_HEADER, stating size
> +#                      (PcdSimicsPeiMemFvSize + 4), and type 0x17
> +#                      (EFI_SECTION_FIRMWARE_VOLUME_IMAGE).
> +# PcdSimicsPeiMemFvSize  PEIFV. Note that the above sizes pad the offset of
> this
> +#                      object to 128 bytes. See also the "guided.dummy.txt"
> +#                      file in the same directory.
> +#
> +#                   4  EFI_COMMON_SECTION_HEADER, stating size 12 (0xC) and
> +#                      type 0x19 (EFI_SECTION_RAW). The purpose of this section
> +#                      is to pad the start of DXEFV to 16 bytes.
> +#                   8  Zero bytes (padding).
> +#
> +#                   4  EFI_COMMON_SECTION_HEADER, stating size
> +#                      (PcdSimicsDxeMemFvSize + 4), and type 0x17
> +#                      (EFI_SECTION_FIRMWARE_VOLUME_IMAGE).
> +# PcdSimicsDxeMemFvSize  DXEFV. Note that the above sizes pad the offset of
> this
> +#                      object to 16 bytes. See also the "guided.dummy.txt" file
> +#                      in the same directory.
> +#
> +# The total size after decompression is (128 + PcdSimicsPeiMemFvSize + 16 +
> +# PcdSimicsDxeMemFvSize).
> +
> +DEFINE OUTPUT_SIZE = (128 +
> gBoardModuleTokenSpaceGuid.PcdSimicsPeiMemFvSize + 16 +
> gBoardModuleTokenSpaceGuid.PcdSimicsDxeMemFvSize)
> +
> +# LzmaCustomDecompressLib uses a constant scratch buffer size of 64KB; see
> +# SCRATCH_BUFFER_REQUEST_SIZE in
> +# "MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaDecompress.c".
> +
> +DEFINE DECOMP_SCRATCH_SIZE = 0x00010000
> +
> +# Note: when we use PcdSimicsDxeMemFvBase in this context, BaseTools have
> not yet
> +# offset it with MEMFD's base address. For that reason we have to do it
> manually.
> +#
> +# The calculation below mirrors DecompressMemFvs()
> [SimicsX58Pkg/Sec/SecMain.c].
> +
> +DEFINE OUTPUT_BASE                   = ($(MEMFD_BASE_ADDRESS) +
> gBoardModuleTokenSpaceGuid.PcdSimicsDxeMemFvBase + 0x00100000)
> +DEFINE DECOMP_SCRATCH_BASE_UNALIGNED = ($(OUTPUT_BASE) +
> $(OUTPUT_SIZE))
> +DEFINE DECOMP_SCRATCH_BASE_ALIGNMENT = 0x000FFFFF
> +DEFINE DECOMP_SCRATCH_BASE_MASK      = 0xFFF00000
> +DEFINE DECOMP_SCRATCH_BASE           =
> (($(DECOMP_SCRATCH_BASE_UNALIGNED) +
> $(DECOMP_SCRATCH_BASE_ALIGNMENT)) &
> $(DECOMP_SCRATCH_BASE_MASK))
> +
> +SET gBoardModuleTokenSpaceGuid.PcdSimicsDecompressionScratchEnd =
> $(DECOMP_SCRATCH_BASE) + $(DECOMP_SCRATCH_SIZE)
> diff --git
> a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library/BoardInitLib/Pei
> BoardInitPostMemLib.inf
> b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library/BoardInitLib/Pei
> BoardInitPostMemLib.inf
> new file mode 100644
> index 0000000000..a035eb0e50
> --- /dev/null
> +++
> b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library/BoardInitLib/Pei
> BoardInitPostMemLib.inf
> @@ -0,0 +1,36 @@
> +## @file
> +#
> +# Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +[Defines]
> +  INF_VERSION                    = 0x00010005
> +  BASE_NAME                      = PeiBoardPostMemInitLib
> +  FILE_GUID                      = 30F407D6-6B92-412A-B2DA-8E73E2B386E6
> +  MODULE_TYPE                    = BASE
> +  VERSION_STRING                 = 1.0
> +  LIBRARY_CLASS                  = BoardInitLib
> +
> +[LibraryClasses]
> +  BaseLib
> +  DebugLib
> +  BaseMemoryLib
> +  MemoryAllocationLib
> +  PcdLib
> +
> +[Packages]
> +  MinPlatformPkg/MinPlatformPkg.dec
> +  MdePkg/MdePkg.dec
> +  MdeModulePkg/MdeModulePkg.dec
> +
> +[Sources]
> +  PeiX58Ich10InitPostMemLib.c
> +  PeiBoardInitPostMemLib.c
> +
> +[FixedPcd]
> +
> +[Pcd]
> +
> diff --git
> a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library/BoardInitLib/Pei
> BoardInitPreMemLib.inf
> b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library/BoardInitLib/Pei
> BoardInitPreMemLib.inf
> new file mode 100644
> index 0000000000..08a6eb159a
> --- /dev/null
> +++
> b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library/BoardInitLib/Pei
> BoardInitPreMemLib.inf
> @@ -0,0 +1,39 @@
> +## @file
> +#
> +# Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +[Defines]
> +  INF_VERSION                    = 0x00010005
> +  BASE_NAME                      = PeiBoardInitPreMemLib
> +  FILE_GUID                      = 73AA24AE-FB20-43F9-A3BA-448953A03A78
> +  MODULE_TYPE                    = BASE
> +  VERSION_STRING                 = 1.0
> +  LIBRARY_CLASS                  = BoardInitLib
> +
> +[LibraryClasses]
> +  BaseLib
> +  DebugLib
> +  BaseMemoryLib
> +  MemoryAllocationLib
> +  PcdLib
> +
> +[Packages]
> +  MinPlatformPkg/MinPlatformPkg.dec
> +  MdePkg/MdePkg.dec
> +  MdeModulePkg/MdeModulePkg.dec
> +  SimicsOpenBoardPkg/OpenBoardPkg.dec
> +  SimicsIch10Pkg/Ich10Pkg.dec
> +
> +[Sources]
> +  PeiX58Ich10Detect.c
> +  PeiX58Ich10InitPreMemLib.c
> +  PeiBoardInitPreMemLib.c
> +
> +[Pcd]
> +
> +[FixedPcd]
> +
> diff --git
> a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library/BoardInitLib/Pei
> X58Ich10InitLib.h
> b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library/BoardInitLib/Pei
> X58Ich10InitLib.h
> new file mode 100644
> index 0000000000..93544a838b
> --- /dev/null
> +++
> b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library/BoardInitLib/Pei
> X58Ich10InitLib.h
> @@ -0,0 +1,16 @@
> +/** @file
> +  Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +
> +  SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PEI_X58Ich10_BOARD_INIT_LIB_H_
> +#define _PEI_X58Ich10_BOARD_INIT_LIB_H_
> +
> +#include <Uefi.h>
> +#include <Library/BaseLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +#include <Library/DebugLib.h>
> +
> +#endif
> diff --git
> a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc
> b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc
> new file mode 100644
> index 0000000000..59e13154a7
> --- /dev/null
> +++ b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc
> @@ -0,0 +1,233 @@
> +## @file
> +#
> +# Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +################################################################
> ################
> +#
> +# Defines Section - statements that will be processed to create a Makefile.
> +#
> +################################################################
> ################
> +[Defines]
> +  DEFINE PLATFORM_PACKAGE      = MinPlatformPkg
> +  DEFINE BOARD_NAME            = BoardX58Ich10
> +  DEFINE BOARD_PKG             = SimicsOpenBoardPkg
> +  DEFINE SKT_PKG               = SimicsX58SktPkg
> +  DEFINE PCH_PKG               = SimicsIch10Pkg
> +  DEFINE DXE_ARCH              = X64
> +  DEFINE PEI_ARCH              = IA32
> +
> +  PLATFORM_NAME                  = SimicsX58
> +  PLATFORM_GUID                  = EE8EBB5A-CC95-412f-9987-2AF70F88B69A
> +  PLATFORM_VERSION               = 0.1
> +  DSC_SPECIFICATION              = 0x00010005
> +  OUTPUT_DIRECTORY               = Build/SimicsX58Ia32X64
> +  SUPPORTED_ARCHITECTURES        = IA32|X64
> +  BUILD_TARGETS                  = DEBUG|RELEASE|NOOPT
> +  SKUID_IDENTIFIER               = DEFAULT
> +  FLASH_DEFINITION               =
> $(BOARD_PKG)/$(BOARD_NAME)/OpenBoardPkg.fdf
> +
> +  DEFINE SMM_REQUIRE             = TRUE
> +
> +  #
> +  #PLATFORMX64_ENABLE is set to TRUE when PEI is IA32 and DXE is X64
> platform
> +  #
> +  DEFINE PLATFORMX64_ENABLE             = TRUE
> +  DEFINE NETWORK_TLS_ENABLE             = FALSE
> +  DEFINE NETWORK_ISCSI_ENABLE           = FALSE
> +  DEFINE NETWORK_ALLOW_HTTP_CONNECTIONS = TRUE
> +  !include NetworkPkg/NetworkDefines.dsc.inc
> +################################################################
> ################
> +#
> +# SKU Identification section - list of all SKU IDs supported by this Platform.
> +#
> +################################################################
> ################
> +[SkuIds]
> +  0|DEFAULT
> +
> +################################################################
> ################
> +#
> +# Library Class section - list of all Library Classes needed by this Platform.
> +#
> +################################################################
> ################
> +
> +[PcdsFeatureFlag]
> +  #
> +  # Platform On/Off features are defined here
> +  #
> +  !include $(BOARD_PKG)/$(BOARD_NAME)/OpenBoardPkgConfig.dsc
> +  !include MinPlatformPkg/Include/Dsc/CoreCommonLib.dsc
> +  !include $(PCH_PKG)/IchCommonLib.dsc
> +
> +[LibraryClasses]
> +  ReportFvLib|$(BOARD_PKG)/Library/PeiReportFvLib/PeiReportFvLib.inf
> +  BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
> +  SerialPortLib|PcAtChipsetPkg/Library/SerialIoLib/SerialIoLib.inf
> +  NvVarsFileLib|$(BOARD_PKG)/Library/NvVarsFileLib/NvVarsFileLib.inf
> +
> SerializeVariablesLib|$(BOARD_PKG)/Library/SerializeVariablesLib/SerializeVaria
> blesLib.inf
> +  DxeLoadLinuxLib|$(BOARD_PKG)/Library/LoadLinuxLib/DxeLoadLinuxLib.inf
> +
> CpuExceptionHandlerLib|MdeModulePkg/Library/CpuExceptionHandlerLibNull/
> CpuExceptionHandlerLibNull.inf
> +
> +
> TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLibNull/TestPoi
> ntCheckLibNull.inf
> +
> BoardInitLib|MinPlatformPkg/PlatformInit/Library/BoardInitLibNull/BoardInitLib
> Null.inf
> +
> SiliconPolicyInitLib|$(BOARD_PKG)/Policy/Library/SiliconPolicyInitLib/SiliconPoli
> cyInitLib.inf
> +
> SiliconPolicyUpdateLib|$(BOARD_PKG)/Policy/Library/SiliconPolicyUpdateLib/Sil
> iconPolicyUpdateLib.inf
> +
> PciSegmentInfoLib|MinPlatformPkg/Pci/Library/PciSegmentInfoLibSimple/PciSe
> gmentInfoLibSimple.inf
> +
> +  !include MinPlatformPkg/Include/Dsc/CorePeiLib.dsc
> +
> +
> S3BootScriptLib|MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScript
> Lib.inf
> +
> AslUpdateLib|MinPlatformPkg/Acpi/Library/DxeAslUpdateLib/DxeAslUpdateLib.i
> nf
> +  LogoLib|$(BOARD_PKG)/Library/DxeLogoLib/DxeLogoLib.inf
> +[LibraryClasses.common.SEC]
> +
> ExtractGuidedSectionLib|MdePkg/Library/BaseExtractGuidedSectionLib/BaseExt
> ractGuidedSectionLib.inf
> +
> +[LibraryClasses.common.PEI_CORE]
> +
> +[LibraryClasses.common.PEIM]
> +
> PeiResourcePublicationLib|MdePkg/Library/PeiResourcePublicationLib/PeiReso
> urcePublicationLib.inf
> +  MpInitLib|UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf
> +
> +[LibraryClasses.IA32]
> +!if $(TARGET) == DEBUG
> +
> TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLib/PeiTestPoin
> tCheckLib.inf
> +!endif
> +  TestPointLib|MinPlatformPkg/Test/Library/TestPointLib/PeiTestPointLib.inf
> +
> +  !include MinPlatformPkg/Include/Dsc/CoreDxeLib.dsc
> +
> +[LibraryClasses.common.DXE_DRIVER]
> +
> PlatformBootManagerLib|$(BOARD_PKG)/Library/PlatformBootManagerLib/Pla
> tformBootManagerLib.inf
> +
> +[LibraryClasses.common.DXE_SMM_DRIVER]
> +
> SpiFlashCommonLib|$(PCH_PKG)/Library/SmmSpiFlashCommonLib/SmmSpiFlash
> CommonLib.inf
> +
> +  !include $(BOARD_PKG)/$(BOARD_NAME)/OpenBoardPkgPcd.dsc
> +
> +[Components.IA32]
> +  $(BOARD_PKG)/SecCore/SecMain.inf {
> +    <LibraryClasses>
> +
> NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecom
> pressLib.inf
> +  }
> +  !include $(SKT_PKG)/SktPkgPei.dsc
> +  !include MinPlatformPkg/Include/Dsc/CorePeiInclude.dsc
> +
> +  $(BOARD_PKG)/SimicsPei/SimicsPei.inf {
> +    <LibraryClasses>
> +      PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
> +  }
> +#  S3 SMM driver
> +#  UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.inf
> +  UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf {
> +    <LibraryClasses>
> +
> LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxPeiLib.inf
> +  }
> +
> +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
> +  $(SKT_PKG)/Smm/Access/SmmAccessPei.inf {
> +    <LibraryClasses>
> +      PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
> +  }
> +!endif
> +  $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf
> +
> +  MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf {
> +    <LibraryClasses>
> +
> BoardInitLib|$(BOARD_PKG)/$(BOARD_NAME)/Library/BoardInitLib/PeiBoardIni
> tPreMemLib.inf
> +  }
> +  MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf {
> +    <LibraryClasses>
> +
> BoardInitLib|$(BOARD_PKG)/$(BOARD_NAME)/Library/BoardInitLib/PeiBoardIni
> tPostMemLib.inf
> +  }
> +  MinPlatformPkg/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.inf
> +  MinPlatformPkg/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMem.inf
> +
> +[Components.X64]
> +  !include MinPlatformPkg/Include/Dsc/CoreDxeInclude.dsc
> +  !include AdvancedFeaturePkg/Include/Dsc/CoreAdvancedDxeInclude.dsc
> +
> +  MdeModulePkg/Universal/EbcDxe/EbcDxe.inf
> +
> +  MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
> +  #
> +  # ISA Support
> +  #
> +  $(BOARD_PKG)/LegacySioDxe/LegacySioDxe.inf
> +  MdeModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2KeyboardDxe.inf
> +
> +  $(BOARD_PKG)/SmbiosPlatformDxe/SmbiosPlatformDxe.inf
> +  $(BOARD_PKG)/AcpiTables/AcpiTables.inf
> +  #
> +  # Video support
> +  #
> +  $(BOARD_PKG)/SimicsVideoDxe/SimicsVideoDxe.inf
> +
> +  MinPlatformPkg/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf
> +  MinPlatformPkg/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf
> +  $(BOARD_PKG)/SimicsDxe/SimicsDxe.inf
> +  MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf
> +
> MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.
> inf
> +
> +  SimicsIch10BinPkg/UndiBinary/UndiDxe.inf
> +
> +  #
> +  # Shell
> +  #
> +  ShellPkg/Application/Shell/Shell.inf {
> +   <PcdsFixedAtBuild>
> +     gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
> +   <LibraryClasses>
> +
> NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2Commands
> Lib.inf
> +
> NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1Commands
> Lib.inf
> +
> NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3Commands
> Lib.inf
> +
> NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1Comman
> dsLib.inf
> +
> NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1Comman
> dsLib.inf
> +
> NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1Comma
> ndsLib.inf
> +
> NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1Co
> mmandsLib.inf
> +
> NULL|ShellPkg/Library/UefiShellNetwork2CommandsLib/UefiShellNetwork2Co
> mmandsLib.inf
> +
> ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLi
> b.inf
> +
> HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.i
> nf
> +
> BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCo
> mmandLib.inf
> +     ShellCEntryLib|ShellPkg/Library/UefiShellCEntryLib/UefiShellCEntryLib.inf
> +     ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
> +  }
> +
> +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
> +  $(SKT_PKG)/Smm/Access/SmmAccess2Dxe.inf
> +  $(PCH_PKG)/SmmControl/RuntimeDxe/SmmControl2Dxe.inf
> +  UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf
> +  $(PCH_PKG)/Spi/Smm/PchSpiSmm.inf
> +  MinPlatformPkg/Flash/SpiFvbService/SpiFvbServiceSmm.inf
> +  UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf
> +  MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf {
> +    <LibraryClasses>
> +
> LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxSmmLib.inf
> +  }
> +!endif
> +  MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
> +  MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
> +  MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf {
> +    <LibraryClasses>
> +
> PciHostBridgeLib|$(BOARD_PKG)/Library/PciHostBridgeLib/PciHostBridgeLib.inf
> +  }
> +  MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
> +
> +  UefiCpuPkg/CpuDxe/CpuDxe.inf
> +  MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
> +  MdeModulePkg/Universal/PrintDxe/PrintDxe.inf
> +  MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
> +  MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
> +  #
> +  # ACPI Support
> +  #
> +  MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
> +  $(BOARD_PKG)/AcpiTables/MinPlatformAcpiTables/AcpiPlatform.inf
> +
> +!if gAdvancedFeaturePkgTokenSpaceGuid.PcdSmbiosEnable == TRUE
> +  AdvancedFeaturePkg/Smbios/SmbiosBasicDxe/SmbiosBasicDxe.inf
> +!endif
> +
> +  !include $(BOARD_PKG)/$(BOARD_NAME)/OpenBoardPkgBuildOption.dsc
> diff --git
> a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.fdf
> b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.fdf
> new file mode 100644
> index 0000000000..6c1579bef7
> --- /dev/null
> +++ b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.fdf
> @@ -0,0 +1,304 @@
> +## @file
> +#
> +# Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +[Defines]
> +!include OpenBoardPkg.fdf.inc
> +
> +#
> +# Build the variable store and the firmware code as one unified flash device
> +# image.
> +#
> +[FD.SIMICSX58IA32X64]
> +BaseAddress   = $(FW_BASE_ADDRESS)
> +Size          = $(FW_SIZE)
> +ErasePolarity = 1
> +BlockSize     = $(BLOCK_SIZE)
> +NumBlocks     = $(FW_BLOCKS)
> +
> +!include VarStore.fdf.inc
> +
> +$(VARS_SIZE)|0x00002000
> +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfi
> MdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
> +#NV_FTW_WORKING
> +DATA = {
> +  # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature =
> gEdkiiWorkingBlockSignatureGuid         =
> +  #  { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65,  0x0, 0xfd, 0x9f, 0x1b,
> 0x95 }}
> +  0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49,
> +  0xa0, 0xce, 0x65,  0x0, 0xfd, 0x9f, 0x1b, 0x95,
> +  # Crc:UINT32            #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
> +  0xE2, 0x33, 0xF2, 0x03, 0xFE, 0xFF, 0xFF, 0xFF,
> +  # WriteQueueSize: UINT64
> +  0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
> +}
> +
> +0x00040000|0x00040000
> +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMd
> eModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
> +#NV_FTW_SPARE
> +
> +0x00080000|0x0016C000
> +FV = FVMAIN_COMPACT
> +
> +$(SECFV_OFFSET)|$(SECFV_SIZE)
> +FV = FvTempMemorySilicon
> +
> +#
> +# Build the variable store and the firmware code as separate flash device
> +# images.
> +#
> +[FD.SIMICS_VARS]
> +BaseAddress   = $(FW_BASE_ADDRESS)
> +Size          = 0x80000
> +ErasePolarity = 1
> +BlockSize     = $(BLOCK_SIZE)
> +NumBlocks     = 0x80
> +
> +!include VarStore.fdf.inc
> +
> +[FD.SIMICS_CODE]
> +BaseAddress   = $(CODE_BASE_ADDRESS)
> +Size          = $(CODE_SIZE)
> +ErasePolarity = 1
> +BlockSize     = $(BLOCK_SIZE)
> +NumBlocks     = $(CODE_BLOCKS)
> +
> +0x00000000|0x0016C000
> +FV = FVMAIN_COMPACT
> +
> +0x0016C000|$(SECFV_SIZE)
> +FV = FvTempMemorySilicon
> +
> +[FD.MEMFD]
> +BaseAddress   = $(MEMFD_BASE_ADDRESS)
> +Size          = 0xB00000
> +ErasePolarity = 1
> +BlockSize     = 0x10000
> +NumBlocks     = 0xB0
> +
> +0x000000|0x006000
> +gBoardModuleTokenSpaceGuid.PcdSimicsSecPageTablesBase|gBoardModuleT
> okenSpaceGuid.PcdSimicsSecPageTablesSize
> +
> +0x006000|0x001000
> +gBoardModuleTokenSpaceGuid.PcdSimicsLockBoxStorageBase|gBoardModule
> TokenSpaceGuid.PcdSimicsLockBoxStorageSize
> +
> +0x007000|0x001000
> +gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress|gBoardM
> oduleTokenSpaceGuid.PcdGuidedExtractHandlerTableSize
> +
> +0x010000|0x008000
> +gBoardModuleTokenSpaceGuid.PcdSimicsSecPeiTempRamBase|gBoardModule
> TokenSpaceGuid.PcdSimicsSecPeiTempRamSize
> +
> +0x020000|0x0E0000
> +gBoardModuleTokenSpaceGuid.PcdSimicsPeiMemFvBase|gBoardModuleToken
> SpaceGuid.PcdSimicsPeiMemFvSize
> +FV = FvPreMemory
> +
> +0x100000|0xA00000
> +gBoardModuleTokenSpaceGuid.PcdSimicsDxeMemFvBase|gBoardModuleToke
> nSpaceGuid.PcdSimicsDxeMemFvSize
> +FV = DXEFV
> +
> +################################################################
> ################
> +
> +[FV.FvTempMemorySilicon]
> +FvAlignment        = 16
> +FvForceRebase      = TRUE
> +ERASE_POLARITY     = 1
> +MEMORY_MAPPED      = TRUE
> +STICKY_WRITE       = TRUE
> +LOCK_CAP           = TRUE
> +LOCK_STATUS        = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP  = TRUE
> +WRITE_STATUS       = TRUE
> +WRITE_LOCK_CAP     = TRUE
> +WRITE_LOCK_STATUS  = TRUE
> +READ_DISABLED_CAP  = TRUE
> +READ_ENABLED_CAP   = TRUE
> +READ_STATUS        = TRUE
> +READ_LOCK_CAP      = TRUE
> +READ_LOCK_STATUS   = TRUE
> +FvNameGuid         = 229EEDCE-8E76-4809-B233-EC36BFBF6989
> +
> +INF  RuleOverride=RESET_SECMAIN USE = IA32
> $(BOARD_PKG)/SecCore/SecMain.inf
> +!include $(SKT_PKG)/SktSecInclude.fdf
> +
> +[FV.FvPreMemory]
> +FvAlignment        = 16
> +FvForceRebase      = TRUE
> +ERASE_POLARITY     = 1
> +MEMORY_MAPPED      = TRUE
> +STICKY_WRITE       = TRUE
> +LOCK_CAP           = TRUE
> +LOCK_STATUS        = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP  = TRUE
> +WRITE_STATUS       = TRUE
> +WRITE_LOCK_CAP     = TRUE
> +WRITE_LOCK_STATUS  = TRUE
> +READ_DISABLED_CAP  = TRUE
> +READ_ENABLED_CAP   = TRUE
> +READ_STATUS        = TRUE
> +READ_LOCK_CAP      = TRUE
> +READ_LOCK_STATUS   = TRUE
> +FvNameGuid         = 6522280D-28F9-4131-ADC4-F40EBFA45864
> +
> +##
> +#  PEI Apriori file example, more PEIM module added later.
> +##
> +INF  MdeModulePkg/Core/Pei/PeiMain.inf
> +!include $(SKT_PKG)/SktPreMemoryInclude.fdf
> +!include $(PCH_PKG)/IchPreMemoryInclude.fdf
> +!include MinPlatformPkg/Include/Fdf/CorePreMemoryInclude.fdf
> +INF  MinPlatformPkg/PlatformInit/ReportFv/ReportFvPei.inf
> +INF  MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf
> +INF  MinPlatformPkg/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.inf
> +!include MinPlatformPkg/Include/Fdf/CoreSecurityPreMemoryInclude.fdf
> +!include
> AdvancedFeaturePkg/Include/Fdf/CoreAdvancedPreMemoryInclude.fdf
> +INF  $(BOARD_PKG)/SimicsPei/SimicsPei.inf
> +!include $(SKT_PKG)/SktPostMemoryInclude.fdf
> +!include $(PCH_PKG)/IchPostMemoryInclude.fdf
> +!include MinPlatformPkg/Include/Fdf/CorePostMemoryInclude.fdf
> +INF  MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf
> +INF  MinPlatformPkg/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMem.inf
> +!include MinPlatformPkg/Include/Fdf/CoreSecurityPostMemoryInclude.fdf
> +!include
> AdvancedFeaturePkg/Include/Fdf/CoreAdvancedPostMemoryInclude.fdf
> +
> +INF  UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf
> +INF  $(SKT_PKG)/Smm/Access/SmmAccessPei.inf
> +# S3 SMM PEI driver
> +#INF  UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.inf
> +
> +[FV.DXEFV]
> +FvNameGuid         = EACAB9EA-C3C6-4438-8FD7-2270826DC0BB
> +BlockSize          = 0x10000
> +FvAlignment        = 16
> +ERASE_POLARITY     = 1
> +MEMORY_MAPPED      = TRUE
> +STICKY_WRITE       = TRUE
> +LOCK_CAP           = TRUE
> +LOCK_STATUS        = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP  = TRUE
> +WRITE_STATUS       = TRUE
> +WRITE_LOCK_CAP     = TRUE
> +WRITE_LOCK_STATUS  = TRUE
> +READ_DISABLED_CAP  = TRUE
> +READ_ENABLED_CAP   = TRUE
> +READ_STATUS        = TRUE
> +READ_LOCK_CAP      = TRUE
> +READ_LOCK_STATUS   = TRUE
> +
> +!include MinPlatformPkg/Include/Fdf/CoreUefiBootInclude.fdf
> +!include $(SKT_PKG)/SktUefiBootInclude.fdf
> +!include $(PCH_PKG)/IchUefiBootInclude.fdf
> +
> +INF  MdeModulePkg/Universal/EbcDxe/EbcDxe.inf
> +INF  MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
> +INF  UefiCpuPkg/CpuDxe/CpuDxe.inf
> +
> +!include MinPlatformPkg/Include/Fdf/CoreOsBootInclude.fdf
> +INF  MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf
> +INF
> MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.
> inf
> +INF  UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf
> +INF  MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf
> +INF  MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
> +INF  MdeModulePkg/Universal/PrintDxe/PrintDxe.inf
> +INF  MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf
> +INF  MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf
> +
> +INF  MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
> +INF  MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
> +INF  MinPlatformPkg/Flash/SpiFvbService/SpiFvbServiceSmm.inf
> +INF  MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
> +
> +INF  $(BOARD_PKG)/LegacySioDxe/LegacySioDxe.inf
> +INF  MdeModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2KeyboardDxe.inf
> +
> +INF  $(BOARD_PKG)/SmbiosPlatformDxe/SmbiosPlatformDxe.inf
> +
> +INF  MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
> +INF  $(BOARD_PKG)/AcpiTables/MinPlatformAcpiTables/AcpiPlatform.inf
> +INF  RuleOverride=ACPITABLE $(BOARD_PKG)/AcpiTables/AcpiTables.inf
> +
> +INF $(BOARD_PKG)/SimicsVideoDxe/SimicsVideoDxe.inf
> +INF  MinPlatformPkg/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf
> +INF  MinPlatformPkg/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf
> +INF  $(BOARD_PKG)/SimicsDxe/SimicsDxe.inf
> +
> +FILE FREEFORM = 7BB28B99-61BB-11D5-9A5D-0090273FC14D {
> +  SECTION RAW = $(BOARD_PKG)/Logo/Logo.bmp
> +}
> +
> +INF  ShellPkg/Application/Shell/Shell.inf
> +
> +#
> +# Network modules
> +#
> +INF  SimicsIch10BinPkg/UndiBinary/UndiDxe.inf
> +
> +!include AdvancedFeaturePkg/Include/Fdf/CoreAdvancedLateInclude.fdf
> +
> +!if gAdvancedFeaturePkgTokenSpaceGuid.PcdSmbiosEnable == TRUE
> +  INF  AdvancedFeaturePkg/Smbios/SmbiosBasicDxe/SmbiosBasicDxe.inf
> +!endif
> +
> +!include MinPlatformPkg/Include/Fdf/CoreSecurityLateInclude.fdf
> +
> +[FV.FVMAIN_COMPACT]
> +FvNameGuid         = 6189987A-DDA6-4060-B313-49168DA9BD46
> +FvAlignment        = 16
> +ERASE_POLARITY     = 1
> +MEMORY_MAPPED      = TRUE
> +STICKY_WRITE       = TRUE
> +LOCK_CAP           = TRUE
> +LOCK_STATUS        = TRUE
> +WRITE_DISABLED_CAP = TRUE
> +WRITE_ENABLED_CAP  = TRUE
> +WRITE_STATUS       = TRUE
> +WRITE_LOCK_CAP     = TRUE
> +WRITE_LOCK_STATUS  = TRUE
> +READ_DISABLED_CAP  = TRUE
> +READ_ENABLED_CAP   = TRUE
> +READ_STATUS        = TRUE
> +READ_LOCK_CAP      = TRUE
> +READ_LOCK_STATUS   = TRUE
> +
> +FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
> +  SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF
> PROCESSING_REQUIRED = TRUE {
> +    #
> +    # These firmware volumes will have files placed in them uncompressed,
> +    # and then both firmware volumes will be compressed in a single
> +    # compression operation in order to achieve better overall compression.
> +    #
> +    SECTION FV_IMAGE = FvPreMemory
> +    SECTION FV_IMAGE = DXEFV
> +  }
> +}
> +
> +!include DecomprScratchEnd.fdf.inc
> +
> +
> +################################################################
> ################
> +#
> +# Rules are use with the [FV] section's module INF type to define
> +# how an FFS file is created for a given INF file. The following Rule are the
> default
> +# rules for the different module type. User can add the customized rules to
> define the
> +# content of the FFS file.
> +#
> +################################################################
> ################
> +
> +!include MinPlatformPkg/Include/Fdf/RuleInclude.fdf
> +
> +[Rule.Common.SEC.RESET_VECTOR]
> +  FILE RAW = $(NAMED_GUID) {
> +    RAW RAW      |.raw
> +  }
> +
> +[Rule.Common.SEC.RESET_SECMAIN]
> +  FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {
> +    UI       STRING="$(MODULE_NAME)" Optional
> +    VERSION  STRING="$(INF_VERSION)" Optional
> BUILD_NUM=$(BUILD_NUMBER)
> +    PE32  PE32    Align = 16      $(INF_OUTPUT)/$(MODULE_NAME).efi
> +  }
> diff --git
> a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.fdf.inc
> b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.fdf.inc
> new file mode 100644
> index 0000000000..044129c941
> --- /dev/null
> +++
> b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.fdf.inc
> @@ -0,0 +1,54 @@
> +## @file
> +#  FDF include file that defines the main macros and sets the dependent PCDs.
> +#
> +#  Copyright (C) 2014, Red Hat, Inc.
> +#  Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
> +#
> +#  SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +#
> +# Default flash size is 2MB.
> +#
> +# Defining FD_SIZE_2MB on the build command line can override this.
> +#
> +
> +DEFINE BLOCK_SIZE        = 0x1000
> +DEFINE VARS_SIZE         = 0x3e000
> +DEFINE VARS_BLOCKS       = 0x3e
> +
> +DEFINE FW_BASE_ADDRESS   = 0xFFE00000
> +DEFINE FW_SIZE           = 0x00200000
> +DEFINE FW_BLOCKS         = 0x200
> +DEFINE CODE_BASE_ADDRESS = 0xFFE80000
> +DEFINE CODE_SIZE         = 0x00180000
> +DEFINE CODE_BLOCKS       = 0x180
> +DEFINE FVMAIN_SIZE       = 0x0016C000
> +DEFINE SECFV_OFFSET      = 0x001EC000
> +DEFINE SECFV_SIZE        = 0x14000
> +
> +
> +SET gBoardModuleTokenSpaceGuid.PcdSimicsFdBaseAddress     =
> $(FW_BASE_ADDRESS)
> +SET gBoardModuleTokenSpaceGuid.PcdSimicsFirmwareFdSize    = $(FW_SIZE)
> +SET gBoardModuleTokenSpaceGuid.PcdSimicsFirmwareBlockSize =
> $(BLOCK_SIZE)
> +
> +SET gBoardModuleTokenSpaceGuid.PcdSimicsFlashNvStorageVariableBase =
> $(FW_BASE_ADDRESS)
> +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize =
> 0xE000
> +
> +SET gBoardModuleTokenSpaceGuid.PcdSimicsFlashNvStorageEventLogBase =
> gBoardModuleTokenSpaceGuid.PcdSimicsFlashNvStorageVariableBase +
> gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
> +SET gBoardModuleTokenSpaceGuid.PcdSimicsFlashNvStorageEventLogSize =
> $(BLOCK_SIZE)
> +
> +SET gBoardModuleTokenSpaceGuid.PcdSimicsFlashNvStorageFtwWorkingBase
> = gBoardModuleTokenSpaceGuid.PcdSimicsFlashNvStorageEventLogBase +
> gBoardModuleTokenSpaceGuid.PcdSimicsFlashNvStorageEventLogSize
> +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize =
> $(BLOCK_SIZE)
> +
> +SET gBoardModuleTokenSpaceGuid.PcdSimicsFlashNvStorageFtwSpareBase =
> gBoardModuleTokenSpaceGuid.PcdSimicsFlashNvStorageFtwWorkingBase +
> gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
> +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize =
> 0x10000
> +
> +SET gEfiPchTokenSpaceGuid.PcdFlashAreaBaseAddress = 0xFFE00000
> +SET gEfiPchTokenSpaceGuid.PcdFlashAreaSize = 0x00200000
> +
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress =
> gEfiPchTokenSpaceGuid.PcdFlashAreaBaseAddress
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize =
> gEfiPchTokenSpaceGuid.PcdFlashAreaSize
> +
> +DEFINE MEMFD_BASE_ADDRESS = 0x800000
> diff --git
> a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgBuildOpti
> on.dsc
> b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgBuildOpti
> on.dsc
> new file mode 100644
> index 0000000000..25998b83e7
> --- /dev/null
> +++
> b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgBuildOpti
> on.dsc
> @@ -0,0 +1,78 @@
> +## @file
> +#
> +# Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +[BuildOptions.Common.EDKII]
> +# Append build options for EDK and EDKII drivers (= is Append, == is Replace)
> +
> +  DEFINE EDKII_DSC_FEATURE_BUILD_OPTIONS =
> +
> +!if $(TARGET) == "DEBUG"
> +  DEFINE DEBUG_BUILD_FLAG = -D SERIAL_DBG_MSG=1
> +!else
> +  DEFINE DEBUG_BUILD_FLAG = -D MDEPKG_NDEBUG -D SILENT_MODE
> +!endif
> +
> +  DEFINE EDKII_DSC_FEATURE_BUILD_OPTIONS     =
> $(EDKII_DSC_FEATURE_BUILD_OPTIONS) $(DEBUG_BUILD_FLAG)
> +#
> +# PC_BUILD_END
> +#
> +
> +
> +  DEFINE EDKII_DSC_FEATURE_BUILD_OPTIONS     =
> $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
> +
> +
> +  *_*_IA32_CC_FLAGS    = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
> +  *_*_IA32_VFRPP_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
> +  *_*_IA32_APP_FLAGS   = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
> +  *_*_IA32_PP_FLAGS    = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
> +  *_*_IA32_ASLPP_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
> +  *_*_IA32_ASLCC_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
> +
> +  *_*_X64_CC_FLAGS     = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
> +  *_*_X64_VFRPP_FLAGS  = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
> +  *_*_X64_APP_FLAGS    = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
> +  *_*_X64_PP_FLAGS     = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
> +  *_*_X64_ASLPP_FLAGS  = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
> +  *_*_X64_ASLCC_FLAGS  = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
> +
> +
> +
> +#
> +# Enable source level debugging for RELEASE build
> +#
> +!if $(TARGET) == "RELEASE"
> +  DEFINE EDKII_RELEASE_SRCDBG_ASM_BUILD_OPTIONS   = /Zi
> +  DEFINE EDKII_RELEASE_SRCDBG_CC_BUILD_OPTIONS    = /Zi /Gm
> +  DEFINE EDKII_RELEASE_SRCDBG_DLINK_BUILD_OPTIONS = /DEBUG
> +
> +  MSFT:*_*_*_ASM_FLAGS    =
> $(EDKII_RELEASE_SRCDBG_ASM_BUILD_OPTIONS)
> +  MSFT:*_*_*_CC_FLAGS     = $(EDKII_RELEASE_SRCDBG_CC_BUILD_OPTIONS)
> +  MSFT:*_*_*_DLINK_FLAGS  =
> $(EDKII_RELEASE_SRCDBG_DLINK_BUILD_OPTIONS)
> +!endif
> +
> +
> +#
> +# Override the existing iasl path in tools_def.template
> +#
> +#  MSFT:*_*_*_ASL_PATH == c:/Iasl/iasl.exe
> +
> +#
> +# Override the VFR compile flags to speed the build time
> +#
> +
> +*_*_*_VFR_FLAGS                     ==  -n
> +
> +# Force PE/COFF sections to be aligned at 4KB boundaries to support page level
> protection
> +#[BuildOptions.common.EDKII.DXE_SMM_DRIVER,
> BuildOptions.common.EDKII.SMM_CORE]
> +#  MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096
> +#  GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000
> +
> +# Force PE/COFF sections to be aligned at 4KB boundaries to support
> MemoryAttribute table
> +#[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
> +#  MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096
> +#  GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000
> diff --git
> a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgConfig.ds
> c
> b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgConfig.ds
> c
> new file mode 100644
> index 0000000000..75de60e5bc
> --- /dev/null
> +++
> b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgConfig.ds
> c
> @@ -0,0 +1,56 @@
> +## @file
> +#
> +# Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +#
> +# TRUE is ENABLE. FALSE is DISABLE.
> +#
> +
> +[PcdsFixedAtBuild]
> +  gMinPlatformPkgTokenSpaceGuid.PcdBootStage|4
> +
> +[PcdsFeatureFlag]
> +  gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE
> +  gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE
> +  gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE
> +  gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|FALSE
> +  gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|FALSE
> +
> +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 1
> +  gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|TRUE
> +!endif
> +
> +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 2
> +  gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE
> +  gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|TRUE
> +!endif
> +
> +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 3
> +  gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE
> +  gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|TRUE
> +!endif
> +
> +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 4
> +  gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE
> +!endif
> +
> +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 5
> +  gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|TRUE
> +  gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|TRUE
> +!endif
> +
> +  !if $(TARGET) == DEBUG
> +    gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE
> +  !else
> +    gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|FALSE
> +  !endif
> +
> +  gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable|FALSE
> +
> +  gAdvancedFeaturePkgTokenSpaceGuid.PcdNetworkEnable|TRUE
> +  gAdvancedFeaturePkgTokenSpaceGuid.PcdSmbiosEnable|TRUE
> +
> diff --git
> a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.dsc
> b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.dsc
> new file mode 100644
> index 0000000000..3bf10ee524
> --- /dev/null
> +++
> b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.dsc
> @@ -0,0 +1,281 @@
> +## @file
> +#
> +# Copyright (c) 2019 Intel Corporation. All rights reserved. <BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +################################################################
> ################
> +#
> +# Pcd Section - list of all EDK II PCD Entries defined by this Platform
> +#
> +################################################################
> ################
> +[PcdsFeatureFlag.common]
> +!if $(TARGET) == RELEASE
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE
> +!else
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE
> +!endif
> +  # Server doesn't support capsle update on Reset.
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdSupportUpdateCapsuleReset|FALSE
> +  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE
> +  gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugSupport|FALSE
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport|FALSE
> +
> +
> +#S3 add
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|TRUE
> +#S3 add
> +
> +  ## This PCD specified whether ACPI SDT protocol is installed.
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
> +
> +[PcdsFeatureFlag.X64]
> +  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard|FALSE
> +
> +[PcdsFeatureFlag]
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdBrowerGrayOutReadOnlyMenu|TRUE
> +
> +[PcdsDynamicExDefault]
> +
> +[PcdsFixedAtBuild.common]
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChang
> e|TRUE
> +!if $(TARGET) == "RELEASE"
> +  gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x03
> +!else
> +  gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
> +!endif
> +  gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|0
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x0
> +#S3 modified
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdShadowPeimOnS3Boot|TRUE
> +#S3 modified
> +
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x0
> +  gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x0
> +  gEfiMdePkgTokenSpaceGuid.PcdFSBClock|133333333
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeiStackSize|0x100000
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdMaxSizeNonPopulateCapsule|0x170000
> 0
> +
> +  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000
> +  gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|512
> +  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x4000
> +
> +  ## Specifies delay value in microseconds after sending out an INIT IPI.
> +  # @Prompt Configure delay value after send an INIT IPI
> +  gUefiCpuPkgTokenSpaceGuid.PcdCpuInitIpiDelayInMicroSeconds|10
> +
> +  ## Specifies max supported number of Logical Processors.
> +  # @Prompt Configure max supported number of Logical Processorss
> +  gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|512
> +  gUefiCpuPkgTokenSpaceGuid.PcdCpuApStackSize|0x1000
> +!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE
> +  gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1
> +!endif
> +
> +  ## Defines the ACPI register set base address.
> +  #  The invalid 0xFFFF is as its default value. It must be configured to the real
> value.
> +  # @Prompt ACPI Timer IO Port Address
> +  gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress         |  0x0400
> +
> +  ## Defines the PCI Bus Number of the PCI device that contains the BAR and
> Enable for ACPI hardware registers.
> +  # @Prompt ACPI Hardware PCI Bus Number
> +  gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber            |  0x00
> +
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision|0x00000002
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId|0x4C544E49
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision|0x2009101
> 3
> +
> +  ## Defines the PCI Device Number of the PCI device that contains the BAR and
> Enable for ACPI hardware registers.
> +  #  The invalid 0xFF is as its default value. It must be configured to the real
> value.
> +  # @Prompt ACPI Hardware PCI Device Number
> +  gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber         |  0x1F
> +
> +  ## Defines the PCI Function Number of the PCI device that contains the BAR
> and Enable for ACPI hardware registers.
> +  #  The invalid 0xFF is as its default value. It must be configured to the real
> value.
> +  # @Prompt ACPI Hardware PCI Function Number
> +  gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber       |  0x00
> +
> +  ## Defines the PCI Register Offset of the PCI device that contains the Enable
> for ACPI hardware registers.
> +  #  The invalid 0xFFFF is as its default value. It must be configured to the real
> value.
> +  # @Prompt ACPI Hardware PCI Register Offset
> +  gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset |0x0044
> +
> +  ## Defines the bit mask that must be set to enable the APIC hardware register
> BAR.
> +  # @Prompt ACPI Hardware PCI Bar Enable BitMask
> +  gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask           |  0x80
> +
> +  ## Defines the PCI Register Offset of the PCI device that contains the BAR for
> ACPI hardware registers.
> +  #  The invalid 0xFFFF is as its default value. It must be configured to the real
> value.
> +  # @Prompt ACPI Hardware PCI Bar Register Offset
> +  gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset    |0x0040
> +
> +  ## Defines the offset to the 32-bit Timer Value register that resides within the
> ACPI BAR.
> +  # @Prompt Offset to 32-bit Timer register in ACPI BAR
> +  gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset              |0x0008
> +
> +  ## Defines the bit mask to retrieve ACPI IO Port Base Address
> +  # @Prompt ACPI IO Port Base Address Mask
> +  gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddressMask     |0xFFFC
> +
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChang
> e|FALSE
> +
> +  gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|4
> +  gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|128
> +  gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|4
> +  gMinPlatformPkgTokenSpaceGuid.PcdLocalApicAddress|0xFEE00000
> +  gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicAddressBase|0xFEC01000
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtPreferredPmProfile|0x0
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtIaPcBootArch|0x0003
> +  gMinPlatformPkgTokenSpaceGuid.PcdFadtFlags|0x000004A5
> +  gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1AEventBlockAddress|0x400
> +  gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1BEventBlockAddress|0
> +  gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1AControlBlockAddress|0x404
> +  gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1BControlBlockAddress|0
> +  gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm2ControlBlockAddress|0x450
> +  gMinPlatformPkgTokenSpaceGuid.PcdAcpiPmTimerBlockAddress|0x408
> +  gMinPlatformPkgTokenSpaceGuid.PcdAcpiGpe0BlockAddress|0x420
> +  gMinPlatformPkgTokenSpaceGuid.PcdAcpiGpe1BlockAddress|0
> +
> +[PcdsFixedAtBuild.X64]
> +  gPcAtChipsetPkgTokenSpaceGuid.Pcd8259LegacyModeMask|0x0eB8
> +  gPcAtChipsetPkgTokenSpaceGuid.PcdMinimalValidYear|2015
> +  gPcAtChipsetPkgTokenSpaceGuid.PcdMaximalValidYear|2099
> +  # Change PcdBootManagerMenuFile to UiApp
> +##
> +
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa,
> 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23,
> 0x31 }
> +
> +  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable |TRUE
> +
> + [PcdsPatchableInModule.common]
> +
> +!if gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable == TRUE
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdSmiHandlerProfilePropertyMask|0x1
> +!endif
> +
> +  gPcAtChipsetPkgTokenSpaceGuid.PcdHpetBaseAddress|0xFED00000
> +
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|1024
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|600
> +
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable|TRUE
> +
> +  gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase|0x0
> +  gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize|0x0
> +
> +[PcdsDynamicExDefault.common.DEFAULT]
> +  gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|30000
> +  gUefiCpuPkgTokenSpaceGuid.PcdCpuS3DataAddress|0
> +
> +[PcdsDynamicExHii.common.DEFAULT]
> +
> gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalV
> ariableGuid|0x0|50 # Variable: L"Timeout"
> +
> gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSuppor
> t"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport"
> +
> +
> +[PcdsDynamicExDefault]
> +
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdMrIovSupport|FALSE
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSystemPageSize|0x1F
> +
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L""|VOID*|36
> +
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId|{0x49, 0x4E, 0x54,
> 0x45, 0x4C, 0x20}
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x2046573030
> 363253
> +
> +[PcdsDynamicExDefault.X64]
> +
> +  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
> +  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8
> +  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1
> +  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1
> +  gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|0
> +
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|31
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|100
> +
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|800
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|600
> +
> +  gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugDataAddress|0
> +
> +[PcdsFeatureFlag]
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|TRUE
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSupportUefiDecompress|FALSE
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|TRUE
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE
> +  #gOptionRomPkgTokenSpaceGuid.PcdSupportGop|TRUE
> +  #gOptionRomPkgTokenSpaceGuid.PcdSupportUga|FALSE
> +
> +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
> +  gSimicsX58PkgTokenSpaceGuid.PcdSmmSmramRequire|TRUE
> +!endif
> +
> +[PcdsFixedAtBuild]
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeMemorySize|1
> +  gEfiMdePkgTokenSpaceGuid.PcdMaximumGuidedExtractHandler|0x10
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x400
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x8000
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdVariableStoreSize|0xc000
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0xc000
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x2000
> +
> gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x10000
> +
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0
> +
> +  # DEBUG_INIT      0x00000001  // Initialization
> +  # DEBUG_WARN      0x00000002  // Warnings
> +  # DEBUG_LOAD      0x00000004  // Load events
> +  # DEBUG_FS        0x00000008  // EFI File system
> +  # DEBUG_POOL      0x00000010  // Alloc & Free (pool)
> +  # DEBUG_PAGE      0x00000020  // Alloc & Free (page)
> +  # DEBUG_INFO      0x00000040  // Informational debug messages
> +  # DEBUG_DISPATCH  0x00000080  // PEI/DXE/SMM Dispatchers
> +  # DEBUG_VARIABLE  0x00000100  // Variable
> +  # DEBUG_BM        0x00000400  // Boot Manager
> +  # DEBUG_BLKIO     0x00001000  // BlkIo Driver
> +  # DEBUG_NET       0x00004000  // SNP Driver
> +  # DEBUG_UNDI      0x00010000  // UNDI Driver
> +  # DEBUG_LOADFILE  0x00020000  // LoadFile
> +  # DEBUG_EVENT     0x00080000  // Event messages
> +  # DEBUG_GCD       0x00100000  // Global Coherency Database changes
> +  # DEBUG_CACHE     0x00200000  // Memory range cachability changes
> +  # DEBUG_VERBOSE   0x00400000  // Detailed debug messages that may
> +  #                             // significantly impact boot performance
> +  # DEBUG_ERROR     0x80000000  // Error
> +  gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000004F
> +  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F
> +
> +  #
> +  # PCI feature overrides.
> +  #
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|FALSE
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE
> +
> +################################################################
> ################
> +#
> +# Pcd Dynamic Section - list of all EDK II PCD Entries defined by this Platform
> +#
> +################################################################
> ################
> +
> +[PcdsDynamicDefault]
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved|0
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0
> +
> +  gBoardModuleTokenSpaceGuid.PcdSimicsX58HostBridgePciDevId|0
> +  gBoardModuleTokenSpaceGuid.PcdPciIoBase|0x0
> +  gBoardModuleTokenSpaceGuid.PcdPciIoSize|0x0
> +  gBoardModuleTokenSpaceGuid.PcdPciMmio32Base|0x0
> +  gBoardModuleTokenSpaceGuid.PcdPciMmio32Size|0x0
> +  gBoardModuleTokenSpaceGuid.PcdPciMmio64Base|0x0
> +  gBoardModuleTokenSpaceGuid.PcdPciMmio64Size|0x800000000
> +
> +
> gAdvancedFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringBiosVersion|"Ver.
> 1.0.0"
> +
> gAdvancedFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringProductName|"QS
> P UEFI BIOS"
> +
> gAdvancedFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringProductName|"QS
> P UEFI BIOS"
> +
> gAdvancedFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringBiosReleaseDate|
> "2019-08-09"
> +
> +  gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiS3Enable|FALSE
> diff --git a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/VarStore.fdf.inc
> b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/VarStore.fdf.inc
> new file mode 100644
> index 0000000000..ea5b86228f
> --- /dev/null
> +++ b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/VarStore.fdf.inc
> @@ -0,0 +1,53 @@
> +## @file
> +#  FDF include file with Layout Regions that define an empty variable store.
> +#
> +#  Copyright (C) 2014, Red Hat, Inc.
> +#  Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
> +#
> +#  SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +##
> +
> +0x00000000|0x0003e000
> +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMde
> ModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
> +#NV_VARIABLE_STORE
> +DATA = {
> +  ## This is the EFI_FIRMWARE_VOLUME_HEADER
> +  # ZeroVector []
> +  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +  # FileSystemGuid: gEfiSystemNvDataFvGuid         =
> +  #   { 0xFFF12B8D, 0x7696, 0x4C8B,
> +  #     { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }}
> +  0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
> +  0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
> +  # FvLength: 0x80000
> +  0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00,
> +  #Signature "_FVH"       #Attributes
> +  0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00,
> +  #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision
> +  0x48, 0x00, 0x2A, 0x09, 0x00, 0x00, 0x00, 0x02,
> +  #Blockmap[0]: 7 Blocks * 0x10000 Bytes / Block
> +  0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
> +  #Blockmap[1]: End
> +  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +  ## This is the VARIABLE_STORE_HEADER
> +!if $(SECURE_BOOT_ENABLE) == TRUE
> +  # Signature: gEfiAuthenticatedVariableGuid =
> +  #   { 0xaaf32c78, 0x947b, 0x439a,
> +  #     { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }}
> +  0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43,
> +  0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92,
> +!else
> +  #Signature: gEfiVariableGuid =
> +  #  { 0xddcf3616, 0x3275, 0x4164, { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe,
> 0x7d }}
> +  0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,
> +  0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,
> +!endif
> +  #Size: 0x3E000
> (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48
> (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x03DFB8
> +  # This can speed up the Variable Dispatch a bit.
> +  0xB8, 0xDF, 0x03, 0x00,
> +  # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1:
> UINT32
> +  0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
> +}
> +
> diff --git a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/build_config.cfg
> b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/build_config.cfg
> new file mode 100644
> index 0000000000..72512837f5
> --- /dev/null
> +++ b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/build_config.cfg
> @@ -0,0 +1,31 @@
> +# @ build_config.cfg
> +# This is the BoardX58Ich10 board specific build settings
> +#
> +# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +
> +
> +[CONFIG]
> +WORKSPACE_PLATFORM_BIN = edk2-non-osi/Platform/Intel
> +EDK_SETUP_OPTION =
> +openssl_path =
> +PLATFORM_BOARD_PACKAGE = SimicsOpenBoardPkg
> +PROJECT = SimicsOpenBoardPkg/BoardX58Ich10
> +BOARD = BoardX58Ich10
> +FLASH_MAP_FDF =
> SimicsOpenBoardPkg/BoardX58Ich10/Include/Fdf/FlashMapInclude.fdf
> +PROJECT_DSC = SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc
> +BOARD_PKG_PCD_DSC =
> SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.dsc
> +PrepRELEASE = DEBUG
> +SILENT_MODE = FALSE
> +EXT_CONFIG_CLEAR =
> +CapsuleBuild = FALSE
> +EXT_BUILD_FLAGS =
> +CAPSULE_BUILD = 0
> +TARGET = DEBUG
> +TARGET_SHORT = D
> +PERFORMANCE_BUILD = FALSE
> +FSP_WRAPPER_BUILD = FALSE
> +FSP_BINARY_BUILD = FALSE
> +FSP_TEST_RELEASE = FALSE
> +SECURE_BOOT_ENABLE = FALSE
> --
> 2.16.2.windows.1