From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 1474E8207C for ; Thu, 9 Feb 2017 20:59:13 -0800 (PST) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga105.fm.intel.com with ESMTP; 09 Feb 2017 20:59:12 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.35,139,1484035200"; d="scan'208";a="42364973" Received: from fmsmsx105.amr.corp.intel.com ([10.18.124.203]) by orsmga002.jf.intel.com with ESMTP; 09 Feb 2017 20:59:12 -0800 Received: from fmsmsx120.amr.corp.intel.com (10.18.124.208) by FMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP Server (TLS) id 14.3.248.2; Thu, 9 Feb 2017 20:59:11 -0800 Received: from shsmsx103.ccr.corp.intel.com (10.239.4.69) by fmsmsx120.amr.corp.intel.com (10.18.124.208) with Microsoft SMTP Server (TLS) id 14.3.248.2; Thu, 9 Feb 2017 20:59:11 -0800 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.88]) by SHSMSX103.ccr.corp.intel.com ([10.239.4.69]) with mapi id 14.03.0248.002; Fri, 10 Feb 2017 12:59:09 +0800 From: "Gao, Liming" To: Andrew Fish , edk2-devel Thread-Topic: [edk2] Should we add PCI VenderId defines to the PCI Includes in the MdePkg. Thread-Index: AQHSg05MRzyg0ezBlUeZdcG4cfpwpKFhrT6Q Date: Fri, 10 Feb 2017 04:59:09 +0000 Message-ID: <4A89E2EF3DFEDB4C8BFDE51014F606A14D6D9A29@shsmsx102.ccr.corp.intel.com> References: <734C28CD-1707-4053-89B8-3747FEB7017D@apple.com> In-Reply-To: <734C28CD-1707-4053-89B8-3747FEB7017D@apple.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: Should we add PCI VenderId defines to the PCI Includes in the MdePkg. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 10 Feb 2017 04:59:13 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Andrew: I agree with you. Could you help submit the tracker in bugzilla for this = request? >-----Original Message----- >From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of >Andrew Fish >Sent: Friday, February 10, 2017 11:31 AM >To: edk2-devel >Subject: [edk2] Should we add PCI VenderId defines to the PCI Includes in = the >MdePkg. > >Some one was asking me why the PCI VendorIds are not included in the >MdePkg and my answer was it seems like a good idea to me. > >We don't have to go crazy as we only really need the VendorIds for vendors >who make things that EFI deals with. It is probably easy enough to get an = initial >list, and then just add values on request. > >Looks like a bit of duplication is already in the tree... > >(master)>git grep -w 0x8086 -- *.h *.c >AppPkg/Applications/Python/Python-2.7.10/Objects/unicodetype_db.h:2636: >case 0x8086: >AppPkg/Applications/Python/Python-2.7.2/Objects/unicodetype_db.h:2636: >case 0x8086: >CorebootPayloadPkg/Library/PlatformBootManagerLib/PlatformConsole.c:50 >2: (Pci->Hdr.VendorId =3D=3D 0x8086) >DuetPkg/Library/DuetBdsLib/BdsPlatform.c:857: ((IS_PCI_ISA_PDECOD= E >(&Pci)) && (Pci.Hdr.VendorId =3D=3D 0x8086) && (Pci.Hdr.DeviceId =3D=3D 0x= 7110))) { >DuetPkg/PciBusNoEnumerationDxe/PciBus.h:222:#define >IS_INTEL_ISA_BRIDGE(_p) (IS_CLASS2 (_p, PCI_CLASS_BRIDGE, >PCI_CLASS_BRIDGE_ISA_PDECODE) && ((_p)->Hdr.VendorId =3D=3D 0x8086) && >((_p)->Hdr.DeviceId =3D=3D 0x7110)) >OptionRomPkg/UndiRuntimeDxe/E100b.h:23:#define PCI_VENDOR_ID_INTEL >0x8086 >OptionRomPkg/UndiRuntimeDxe/E100b.h:25:#define D100_VENDOR_ID >0x8086 >OptionRomPkg/UndiRuntimeDxe/Init.c:113: than contains a DevicePath, >PciIo protocol, Class code of 2, Vendor ID of 0x8086, >OvmfPkg/Csm/CsmSupportLib/LegacyPlatform.c:72: 0x8086, // UIN= T16 >CompatibleVid >OvmfPkg/Csm/CsmSupportLib/LegacyPlatform.h:50:#define >V_INTEL_VENDOR_ID 0x8086 >OvmfPkg/Library/PlatformBootManagerLib/BdsPlatform.c:848: (Pci- >>Hdr.VendorId =3D=3D 0x8086) && >PcAtChipsetPkg/IsaAcpiDxe/PcatIsaAcpi.c:118: Pci.Hdr.VendorId = =3D=3D >0x8086 ) { >QuarkPlatformPkg/Feature/Capsule/Library/PlatformFlashAccessLib/SpiFlash >Device.h:181:#define PFAB_CARD_VENDOR_ID 0x8086 >QuarkPlatformPkg/Platform/SpiFvbServices/SpiFlashDevice.h:182:#define >PFAB_CARD_VENDOR_ID 0x8086 >QuarkSocPkg/QuarkNorthCluster/Include/QuarkNcSocId.h:363:#define >V_INTEL_VENDOR_ID 0x8086 >QuarkSocPkg/QuarkSouthCluster/Include/Ioh.h:69:#define >INTEL_VENDOR_ID 0x8086 // Intel Vendor ID >Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Valleyview.h:3 >9:#define MC_VID 0x8086 >Vlv2DeviceRefCodePkg/ValleyView2Soc/NorthCluster/Include/Valleyview.h:5 >2:#define IGD_VID 0x8086 >Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs.h:119 >:#define V_PCH_INTEL_VENDOR_ID 0x8086 >Vlv2TbltDevicePkg/Include/CommonIncludes.h:24:#define V_INTEL_VID >0x8086 >Vlv2TbltDevicePkg/Include/Platform.h:136:#define >V_DEFAULT_SUBSYSTEM_VENDOR_ID 0x8086 >Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardSsidSvid/BoardSsidSvid.h:2 >4:#define SUBSYSTEM_VENDOR_ID1 0x8086 >Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardSsidSvid/BoardSsidSvid.h:2 >8:#define SUBSYSTEM_VENDOR_ID2 0x8086 >Vlv2TbltDevicePkg/Library/MultiPlatformLib/BoardSsidSvid/BoardSsidSvid.h:3 >2:#define SUBSYSTEM_VENDOR_ID 0x8086 >Vlv2TbltDevicePkg/PciPlatform/BoardPciPlatform.c:30:#define >V_INTEL_LAN_VENDOR_ID 0x8086 // INTEL 82574 Gbe Controller >Vendor ID >Vlv2TbltDevicePkg/PlatformDxe/PciDevice.c:42:#define INTEL_VENDOR_ID >0x8086 >Vlv2TbltDevicePkg/VlvPlatformInitDxe/IgdOpRegion.h:134: UINT16 VendorId; >// 0x8086 >Vlv2TbltDevicePkg/VlvPlatformInitDxe/VlvPlatformInit.h:61:#define IGD_VID >0x8086 >Vlv2TbltDevicePkg/Wpce791/LpcDriver.c:194: Pci.Hdr.VendorId =3D= =3D >0x8086 && > > >Thanks, > >Andrew Fish >_______________________________________________ >edk2-devel mailing list >edk2-devel@lists.01.org >https://lists.01.org/mailman/listinfo/edk2-devel