From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id A5AE720945023 for ; Thu, 6 Apr 2017 07:51:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=intel.com; i=@intel.com; q=dns/txt; s=intel; t=1491490300; x=1523026300; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; bh=zMteTTEKkCAh7oMwrVXLETinGtzZEnPoFpBT/B3FfAY=; b=a1dxOzVlvVWYdeWiMYaOzVgdU3CNxLDfu+rMd9yCvQJQ51pY4er43SeR FgVcWpdL5Flt6nfIP447+gHy4mbD7g==; Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 06 Apr 2017 07:51:33 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.37,160,1488873600"; d="scan'208";a="85751694" Received: from fmsmsx108.amr.corp.intel.com ([10.18.124.206]) by fmsmga006.fm.intel.com with ESMTP; 06 Apr 2017 07:51:33 -0700 Received: from FMSMSX109.amr.corp.intel.com (10.18.116.9) by FMSMSX108.amr.corp.intel.com (10.18.124.206) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 6 Apr 2017 07:51:33 -0700 Received: from shsmsx103.ccr.corp.intel.com (10.239.4.69) by fmsmsx109.amr.corp.intel.com (10.18.116.9) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 6 Apr 2017 07:51:32 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.246]) by SHSMSX103.ccr.corp.intel.com ([169.254.4.117]) with mapi id 14.03.0319.002; Thu, 6 Apr 2017 22:51:31 +0800 From: "Gao, Liming" To: Leo Duran , "edk2-devel@ml01.01.org" CC: "Kinney, Michael D" , Brijesh Singh Thread-Topic: [PATCH v7] MdePkg: BaseIoLibIntrinsic (IoLib class) library Thread-Index: AQHSruTa15DlSgD2KkqUASYctf7XFaG4bL7w Date: Thu, 6 Apr 2017 14:51:30 +0000 Message-ID: <4A89E2EF3DFEDB4C8BFDE51014F606A14D71B3F5@shsmsx102.ccr.corp.intel.com> References: <1491490081-4698-1-git-send-email-leo.duran@amd.com> <1491490081-4698-2-git-send-email-leo.duran@amd.com> In-Reply-To: <1491490081-4698-2-git-send-email-leo.duran@amd.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 10.0.102.7 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH v7] MdePkg: BaseIoLibIntrinsic (IoLib class) library X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 06 Apr 2017 14:51:41 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Liming Gao > -----Original Message----- > From: Leo Duran [mailto:leo.duran@amd.com] > Sent: Thursday, April 6, 2017 10:48 PM > To: edk2-devel@ml01.01.org > Cc: Leo Duran ; Kinney, Michael D ; Gao, Liming ; Brijesh > Singh > Subject: [PATCH v7] MdePkg: BaseIoLibIntrinsic (IoLib class) library >=20 > This patch adds an SEV-specific .INF and corresponding assembly > files, to unroll REP INSx/OUTSx on IoRead/WriteFifo#() routines > when the SEV feature is enabled under a hypervisor environment. >=20 > The new .INF only supports the IA32 and X64 architectures. >=20 > Cc: Michael D Kinney > Cc: Liming Gao > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Brijesh Singh > Signed-off-by: Leo Duran > --- > .../BaseIoLibIntrinsic/BaseIoLibIntrinsicSev.inf | 59 +++++ > .../Library/BaseIoLibIntrinsic/Ia32/IoFifoSev.nasm | 293 +++++++++++++++= ++++++ > .../Library/BaseIoLibIntrinsic/X64/IoFifoSev.nasm | 282 +++++++++++++++= +++++ > MdePkg/MdePkg.dsc | 1 + > 4 files changed, 635 insertions(+) > create mode 100644 MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicS= ev.inf > create mode 100644 MdePkg/Library/BaseIoLibIntrinsic/Ia32/IoFifoSev.nasm > create mode 100644 MdePkg/Library/BaseIoLibIntrinsic/X64/IoFifoSev.nasm >=20 > diff --git a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicSev.inf = b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicSev.inf > new file mode 100644 > index 0000000..0eec896 > --- /dev/null > +++ b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicSev.inf > @@ -0,0 +1,59 @@ > +## @file > +# Instance of I/O Library using compiler intrinsics. > +# > +# I/O Library that uses compiler intrinsics to perform IN and OUT instr= uctions > +# for IA-32 and x64. > +# > +# Copyright (c) 2007 - 2015, Intel Corporation. All rights reserved. > +# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved. > +# Copyright (c) 2017, AMD Incorporated. All rights reserved.
> +# > +# This program and the accompanying materials > +# are licensed and made available under the terms and conditions of the= BSD License > +# which accompanies this distribution. The full text of the license may= be found at > +# http://opensource.org/licenses/bsd-license.php. > +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR = IMPLIED. > +# > +## > + > +[Defines] > + INF_VERSION =3D 0x00010005 > + BASE_NAME =3D BaseIoLibIntrinsicSev > + MODULE_UNI_FILE =3D BaseIoLibIntrinsic.uni > + FILE_GUID =3D 93742f95-6e71-4581-b600-8e1da443f95= a > + MODULE_TYPE =3D BASE > + VERSION_STRING =3D 1.0 > + LIBRARY_CLASS =3D IoLib > + > + > +# > +# VALID_ARCHITECTURES =3D IA32 X64 > +# > + > +[Sources] > + IoLibMmioBuffer.c > + BaseIoLibIntrinsicInternal.h > + IoHighLevel.c > + > +[Sources.IA32] > + IoLibGcc.c | GCC > + IoLibMsc.c | MSFT > + IoLibIcc.c | INTEL > + IoLib.c > + Ia32/IoFifoSev.nasm > + > +[Sources.X64] > + IoLibGcc.c | GCC > + IoLibMsc.c | MSFT > + IoLibIcc.c | INTEL > + IoLib.c > + X64/IoFifoSev.nasm > + > +[Packages] > + MdePkg/MdePkg.dec > + > +[LibraryClasses] > + DebugLib > + BaseLib > + > diff --git a/MdePkg/Library/BaseIoLibIntrinsic/Ia32/IoFifoSev.nasm b/MdeP= kg/Library/BaseIoLibIntrinsic/Ia32/IoFifoSev.nasm > new file mode 100644 > index 0000000..9adb972 > --- /dev/null > +++ b/MdePkg/Library/BaseIoLibIntrinsic/Ia32/IoFifoSev.nasm > @@ -0,0 +1,293 @@ > +;-----------------------------------------------------------------------= ------- > +; > +; Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.
> +; Copyright (c) 2017, AMD Incorporated. All rights reserved.
> +; > +; This program and the accompanying materials are licensed and made avai= lable > +; under the terms and conditions of the BSD License which accompanies th= is > +; distribution. The full text of the license may be found at > +; http://opensource.org/licenses/bsd-license.php. > +; > +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR I= MPLIED. > +; > +;-----------------------------------------------------------------------= ------- > + > + SECTION .text > + > +;-----------------------------------------------------------------------= ------- > +; Check whether we need to unroll the String I/O under SEV guest > +; > +; Return // eax (1 - unroll, 0 - no unroll) > +;-----------------------------------------------------------------------= ------- > +global ASM_PFX(SevNoRepIo) > +ASM_PFX(SevNoRepIo): > + > + ; CPUID clobbers ebx, ecx and edx > + push ebx > + push ecx > + push edx > + > + ; Check if we are running under hypervisor > + ; CPUID(1).ECX Bit 31 > + mov eax, 1 > + cpuid > + bt ecx, 31 > + jnc @UseRepIo > + > + ; Check if we have Memory encryption CPUID leaf > + mov eax, 0x80000000 > + cpuid > + cmp eax, 0x8000001f > + jl @UseRepIo > + > + ; Check for memory encryption feature: > + ; CPUID Fn8000_001F[EAX] - Bit 1 > + ; > + mov eax, 0x8000001f > + cpuid > + bt eax, 1 > + jnc @UseRepIo > + > + ; Check if memory encryption is enabled > + ; MSR_0xC0010131 - Bit 0 (SEV enabled) > + ; MSR_0xC0010131 - Bit 1 (SEV-ES enabled) > + mov ecx, 0xc0010131 > + rdmsr > + > + ; Check for (SevEsEnabled =3D=3D 0 && SevEnabled =3D=3D 1) > + and eax, 3 > + cmp eax, 1 > + je @SevNoRepIo_Done > + > +@UseRepIo: > + xor eax, eax > + > +@SevNoRepIo_Done: > + pop edx > + pop ecx > + pop ebx > + ret > + > +;-----------------------------------------------------------------------= ------- > +; VOID > +; EFIAPI > +; IoReadFifo8 ( > +; IN UINTN Port, > +; IN UINTN Size, > +; OUT VOID *Buffer > +; ); > +;-----------------------------------------------------------------------= ------- > +global ASM_PFX(IoReadFifo8) > +ASM_PFX(IoReadFifo8): > + push edi > + mov dx, [esp + 8] > + mov ecx, [esp + 12] > + mov edi, [esp + 16] > + > + call SevNoRepIo ; Check if we need to unroll the rep > + test eax, eax > + jnz @IoReadFifo8_NoRep > + > + cld > + rep insb > + jmp @IoReadFifo8_Done > + > +@IoReadFifo8_NoRep: > + jecxz @IoReadFifo8_Done > + > +@IoReadFifo8_Loop: > + in al, dx > + mov byte [edi], al > + inc edi > + loop @IoReadFifo8_Loop > + > +@IoReadFifo8_Done: > + pop edi > + ret > + > +;-----------------------------------------------------------------------= ------- > +; VOID > +; EFIAPI > +; IoReadFifo16 ( > +; IN UINTN Port, > +; IN UINTN Size, > +; OUT VOID *Buffer > +; ); > +;-----------------------------------------------------------------------= ------- > +global ASM_PFX(IoReadFifo16) > +ASM_PFX(IoReadFifo16): > + push edi > + mov dx, [esp + 8] > + mov ecx, [esp + 12] > + mov edi, [esp + 16] > + > + call SevNoRepIo ; Check if we need to unroll the rep > + test eax, eax > + jnz @IoReadFifo16_NoRep > + > + cld > + rep insw > + jmp @IoReadFifo16_Done > + > +@IoReadFifo16_NoRep: > + jecxz @IoReadFifo16_Done > + > +@IoReadFifo16_Loop: > + in ax, dx > + mov word [edi], ax > + add edi, 2 > + loop @IoReadFifo16_Loop > + > +@IoReadFifo16_Done: > + pop edi > + ret > + > +;-----------------------------------------------------------------------= ------- > +; VOID > +; EFIAPI > +; IoReadFifo32 ( > +; IN UINTN Port, > +; IN UINTN Size, > +; OUT VOID *Buffer > +; ); > +;-----------------------------------------------------------------------= ------- > +global ASM_PFX(IoReadFifo32) > +ASM_PFX(IoReadFifo32): > + push edi > + mov dx, [esp + 8] > + mov ecx, [esp + 12] > + mov edi, [esp + 16] > + > + call SevNoRepIo ; Check if we need to unroll the rep > + test eax, eax > + jnz @IoReadFifo32_NoRep > + > + cld > + rep insd > + jmp @IoReadFifo32_Done > + > +@IoReadFifo32_NoRep: > + jecxz @IoReadFifo32_Done > + > +@IoReadFifo32_Loop: > + in eax, dx > + mov dword [edi], eax > + add edi, 4 > + loop @IoReadFifo32_Loop > + > +@IoReadFifo32_Done: > + pop edi > + ret > + > +;-----------------------------------------------------------------------= ------- > +; VOID > +; EFIAPI > +; IoWriteFifo8 ( > +; IN UINTN Port, > +; IN UINTN Size, > +; IN VOID *Buffer > +; ); > +;-----------------------------------------------------------------------= ------- > +global ASM_PFX(IoWriteFifo8) > +ASM_PFX(IoWriteFifo8): > + push esi > + mov dx, [esp + 8] > + mov ecx, [esp + 12] > + mov esi, [esp + 16] > + > + call SevNoRepIo ; Check if we need to unroll String I/O > + test eax, eax > + jnz @IoWriteFifo8_NoRep > + > + cld > + rep outsb > + jmp @IoWriteFifo8_Done > + > +@IoWriteFifo8_NoRep: > + jecxz @IoWriteFifo8_Done > + > +@IoWriteFifo8_Loop: > + mov byte [esi], al > + out dx, al > + inc esi > + loop @IoWriteFifo8_Loop > + > +@IoWriteFifo8_Done: > + pop esi > + ret > + > +;-----------------------------------------------------------------------= ------- > +; VOID > +; EFIAPI > +; IoWriteFifo16 ( > +; IN UINTN Port, > +; IN UINTN Size, > +; IN VOID *Buffer > +; ); > +;-----------------------------------------------------------------------= ------- > +global ASM_PFX(IoWriteFifo16) > +ASM_PFX(IoWriteFifo16): > + push esi > + mov dx, [esp + 8] > + mov ecx, [esp + 12] > + mov esi, [esp + 16] > + > + call SevNoRepIo ; Check if we need to unroll String I/O > + test eax, eax > + jnz @IoWriteFifo16_NoRep > + > + cld > + rep outsw > + jmp @IoWriteFifo16_Done > + > +@IoWriteFifo16_NoRep: > + jecxz @IoWriteFifo16_Done > + > +@IoWriteFifo16_Loop: > + mov word [esi], ax > + out dx, ax > + add esi, 2 > + loop @IoWriteFifo16_Loop > + > +@IoWriteFifo16_Done: > + pop esi > + ret > + > +;-----------------------------------------------------------------------= ------- > +; VOID > +; EFIAPI > +; IoWriteFifo32 ( > +; IN UINTN Port, > +; IN UINTN Size, > +; IN VOID *Buffer > +; ); > +;-----------------------------------------------------------------------= ------- > +global ASM_PFX(IoWriteFifo32) > +ASM_PFX(IoWriteFifo32): > + push esi > + mov dx, [esp + 8] > + mov ecx, [esp + 12] > + mov esi, [esp + 16] > + > + call SevNoRepIo ; Check if we need to unroll String I/O > + test eax, eax > + jnz @IoWriteFifo32_NoRep > + > + cld > + rep outsd > + jmp @IoWriteFifo32_Done > + > +@IoWriteFifo32_NoRep: > + jecxz @IoWriteFifo32_Done > + > +@IoWriteFifo32_Loop: > + mov dword [esi], eax > + out dx, eax > + add esi, 4 > + loop @IoWriteFifo32_Loop > + > +@IoWriteFifo32_Done: > + pop esi > + ret > + > diff --git a/MdePkg/Library/BaseIoLibIntrinsic/X64/IoFifoSev.nasm b/MdePk= g/Library/BaseIoLibIntrinsic/X64/IoFifoSev.nasm > new file mode 100644 > index 0000000..20e3e64 > --- /dev/null > +++ b/MdePkg/Library/BaseIoLibIntrinsic/X64/IoFifoSev.nasm > @@ -0,0 +1,282 @@ > +;-----------------------------------------------------------------------= ------- > +; > +; Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.
> +; Copyright (c) 2017, AMD Incorporated. All rights reserved.
> +; > +; This program and the accompanying materials are licensed and made avai= lable > +; under the terms and conditions of the BSD License which accompanies th= is > +; distribution. The full text of the license may be found at > +; http://opensource.org/licenses/bsd-license.php. > +; > +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR I= MPLIED. > +; > +;-----------------------------------------------------------------------= ------- > + > + DEFAULT REL > + SECTION .text > + > +;-----------------------------------------------------------------------= ------- > +; Check whether we need to unroll the String I/O in SEV guest > +; > +; Return // eax (1 - unroll, 0 - no unroll) > +;-----------------------------------------------------------------------= ------- > +global ASM_PFX(SevNoRepIo) > +ASM_PFX(SevNoRepIo): > + > + ; CPUID clobbers ebx, ecx and edx > + push rbx > + push rcx > + push rdx > + > + ; Check if we are runing under hypervisor > + ; CPUID(1).ECX Bit 31 > + mov eax, 1 > + cpuid > + bt ecx, 31 > + jnc @UseRepIo > + > + ; Check if we have Memory encryption CPUID leaf > + mov eax, 0x80000000 > + cpuid > + cmp eax, 0x8000001f > + jl @UseRepIo > + > + ; Check for memory encryption feature: > + ; CPUID Fn8000_001F[EAX] - Bit 1 > + ; > + mov eax, 0x8000001f > + cpuid > + bt eax, 1 > + jnc @UseRepIo > + > + ; Check if memory encryption is enabled > + ; MSR_0xC0010131 - Bit 0 (SEV enabled) > + ; MSR_0xC0010131 - Bit 1 (SEV-ES enabled) > + mov ecx, 0xc0010131 > + rdmsr > + > + ; Check for (SevEsEnabled =3D=3D 0 && SevEnabled =3D=3D 1) > + and eax, 3 > + cmp eax, 1 > + je @SevNoRepIo_Done > + > +@UseRepIo: > + xor eax, eax > + > +@SevNoRepIo_Done: > + pop rdx > + pop rcx > + pop rbx > + ret > + > +;-----------------------------------------------------------------------= ------- > +; VOID > +; EFIAPI > +; IoReadFifo8 ( > +; IN UINTN Port, // rcx > +; IN UINTN Size, // rdx > +; OUT VOID *Buffer // r8 > +; ); > +;-----------------------------------------------------------------------= ------- > +global ASM_PFX(IoReadFifo8) > +ASM_PFX(IoReadFifo8): > + xchg rcx, rdx > + xchg rdi, r8 ; rdi: buffer address; r8: save rdi > + > + call SevNoRepIo ; Check if we need to unroll String I/O > + test eax, eax > + jnz @IoReadFifo8_NoRep > + > + cld > + rep insb > + jmp @IoReadFifo8_Done > + > +@IoReadFifo8_NoRep: > + jrcxz @IoReadFifo8_Done > + > +@IoReadFifo8_Loop: > + in al, dx > + mov byte [rdi], al > + inc rdi > + loop @IoReadFifo8_Loop > + > +@IoReadFifo8_Done: > + mov rdi, r8 ; restore rdi > + ret > + > +;-----------------------------------------------------------------------= ------- > +; VOID > +; EFIAPI > +; IoReadFifo16 ( > +; IN UINTN Port, // rcx > +; IN UINTN Size, // rdx > +; OUT VOID *Buffer // r8 > +; ); > +;-----------------------------------------------------------------------= ------- > +global ASM_PFX(IoReadFifo16) > +ASM_PFX(IoReadFifo16): > + xchg rcx, rdx > + xchg rdi, r8 ; rdi: buffer address; r8: save rdi > + > + call SevNoRepIo ; Check if we need to unroll String I/O > + test eax, eax > + jnz @IoReadFifo16_NoRep > + > + cld > + rep insw > + jmp @IoReadFifo16_Done > + > +@IoReadFifo16_NoRep: > + jrcxz @IoReadFifo16_Done > + > +@IoReadFifo16_Loop: > + in ax, dx > + mov word [rdi], ax > + add rdi, 2 > + loop @IoReadFifo16_Loop > + > +@IoReadFifo16_Done: > + mov rdi, r8 ; restore rdi > + ret > + > +;-----------------------------------------------------------------------= ------- > +; VOID > +; EFIAPI > +; IoReadFifo32 ( > +; IN UINTN Port, // rcx > +; IN UINTN Size, // rdx > +; OUT VOID *Buffer // r8 > +; ); > +;-----------------------------------------------------------------------= ------- > +global ASM_PFX(IoReadFifo32) > +ASM_PFX(IoReadFifo32): > + xchg rcx, rdx > + xchg rdi, r8 ; rdi: buffer address; r8: save rdi > + > + call SevNoRepIo ; Check if we need to unroll String I/O > + test eax, eax > + jnz @IoReadFifo32_NoRep > + > + cld > + rep insd > + jmp @IoReadFifo32_Done > + > +@IoReadFifo32_NoRep: > + jrcxz @IoReadFifo32_Done > + > +@IoReadFifo32_Loop: > + in eax, dx > + mov dword [rdi], eax > + add rdi, 4 > + loop @IoReadFifo32_Loop > + > +@IoReadFifo32_Done: > + mov rdi, r8 ; restore rdi > + ret > + > +;-----------------------------------------------------------------------= ------- > +; VOID > +; EFIAPI > +; IoWriteFifo8 ( > +; IN UINTN Port, // rcx > +; IN UINTN Size, // rdx > +; IN VOID *Buffer // r8 > +; ); > +;-----------------------------------------------------------------------= ------- > +global ASM_PFX(IoWriteFifo8) > +ASM_PFX(IoWriteFifo8): > + xchg rcx, rdx > + xchg rsi, r8 ; rsi: buffer address; r8: save rsi > + > + call SevNoRepIo ; Check if we need to unroll String I/O > + test eax, eax > + jnz @IoWriteFifo8_NoRep > + > + cld > + rep outsb > + jmp @IoWriteFifo8_Done > + > +@IoWriteFifo8_NoRep: > + jrcxz @IoWriteFifo8_Done > + > +@IoWriteFifo8_Loop: > + mov byte [rsi], al > + out dx, al > + inc rsi > + loop @IoWriteFifo8_Loop > + > +@IoWriteFifo8_Done: > + mov rsi, r8 ; restore rsi > + ret > + > +;-----------------------------------------------------------------------= ------- > +; VOID > +; EFIAPI > +; IoWriteFifo16 ( > +; IN UINTN Port, // rcx > +; IN UINTN Size, // rdx > +; IN VOID *Buffer // r8 > +; ); > +;-----------------------------------------------------------------------= ------- > +global ASM_PFX(IoWriteFifo16) > +ASM_PFX(IoWriteFifo16): > + xchg rcx, rdx > + xchg rsi, r8 ; rsi: buffer address; r8: save rsi > + > + call SevNoRepIo ; Check if we need to unroll String I/O > + test eax, eax > + jnz @IoWriteFifo16_NoRep > + > + cld > + rep outsw > + jmp @IoWriteFifo16_Done > + > +@IoWriteFifo16_NoRep: > + jrcxz @IoWriteFifo16_Done > + > +@IoWriteFifo16_Loop: > + mov word [rsi], ax > + out dx, ax > + add rsi, 2 > + loop @IoWriteFifo16_Loop > + > +@IoWriteFifo16_Done: > + mov rsi, r8 ; restore rsi > + ret > + > +;-----------------------------------------------------------------------= ------- > +; VOID > +; EFIAPI > +; IoWriteFifo32 ( > +; IN UINTN Port, // rcx > +; IN UINTN Size, // rdx > +; IN VOID *Buffer // r8 > +; ); > +;-----------------------------------------------------------------------= ------- > +global ASM_PFX(IoWriteFifo32) > +ASM_PFX(IoWriteFifo32): > + xchg rcx, rdx > + xchg rsi, r8 ; rsi: buffer address; r8: save rsi > + > + call SevNoRepIo ; Check if we need to unroll String I/O > + test eax, eax > + jnz @IoWriteFifo32_NoRep > + > + cld > + rep outsd > + jmp @IoWriteFifo32_Done > + > +@IoWriteFifo32_NoRep: > + jrcxz @IoWriteFifo32_Done > + > +@IoWriteFifo32_Loop: > + mov dword [rsi], eax > + out dx, eax > + add rsi, 4 > + loop @IoWriteFifo32_Loop > + > +@IoWriteFifo32_Done: > + mov rsi, r8 ; restore rsi > + ret > + > diff --git a/MdePkg/MdePkg.dsc b/MdePkg/MdePkg.dsc > index 2144979..8b69de3 100644 > --- a/MdePkg/MdePkg.dsc > +++ b/MdePkg/MdePkg.dsc > @@ -134,6 +134,7 @@ >=20 > [Components.IA32, Components.X64] > MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf > + MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicSev.inf > MdePkg/Library/BaseMemoryLibMmx/BaseMemoryLibMmx.inf > MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf > MdePkg/Library/BaseMemoryLibOptPei/BaseMemoryLibOptPei.inf > -- > 2.7.4