From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 551FE21A00AD4 for ; Fri, 30 Jun 2017 06:28:17 -0700 (PDT) Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 30 Jun 2017 06:29:50 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.40,286,1496127600"; d="scan'208";a="103169104" Received: from fmsmsx104.amr.corp.intel.com ([10.18.124.202]) by orsmga004.jf.intel.com with ESMTP; 30 Jun 2017 06:29:50 -0700 Received: from FMSMSX110.amr.corp.intel.com (10.18.116.10) by fmsmsx104.amr.corp.intel.com (10.18.124.202) with Microsoft SMTP Server (TLS) id 14.3.319.2; Fri, 30 Jun 2017 06:29:50 -0700 Received: from shsmsx104.ccr.corp.intel.com (10.239.4.70) by fmsmsx110.amr.corp.intel.com (10.18.116.10) with Microsoft SMTP Server (TLS) id 14.3.319.2; Fri, 30 Jun 2017 06:29:49 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.146]) by SHSMSX104.ccr.corp.intel.com ([10.239.4.70]) with mapi id 14.03.0319.002; Fri, 30 Jun 2017 21:29:47 +0800 From: "Gao, Liming" To: Jun Nie , Leif Lindholm , Ard Biesheuvel , "edk2-devel@lists.01.org" , "linaro-uefi@lists.linaro.org" , "Alexei.Fedorov@arm.com" , "evan.lloyd@arm.com" Thread-Topic: [edk2] How to add support to different reg offset definition to share the same driver code? Thread-Index: AQHS8VHypvuFoYHxm061y88YkOYaLqI9ZSFA Date: Fri, 30 Jun 2017 13:29:47 +0000 Message-ID: <4A89E2EF3DFEDB4C8BFDE51014F606A14D750466@shsmsx102.ccr.corp.intel.com> References: In-Reply-To: Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 10.0.102.7 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: How to add support to different reg offset definition to share the same driver code? X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 30 Jun 2017 13:28:17 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Jun: You can add C MACRO in [BuildOptions] of Platform.dsc, then use DSC flag t= o control it.=20 For example: Platform.dsc [Defines] DEFINE ZX_PL011_FLAG =3D FALSE [BuildOptions] !if $(ZX_PL011_FLAG) =3D=3D TRUE *_*_*_CC_FLAGS =3D -D ZX_PL011_FLAG !endif Thanks Liming > -----Original Message----- > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Ju= n Nie > Sent: Friday, June 30, 2017 11:35 AM > To: Leif Lindholm ; Ard Biesheuvel ; edk2-devel@lists.01.org; > linaro-uefi@lists.linaro.org; Alexei.Fedorov@arm.com; evan.lloyd@arm.com > Subject: [edk2] How to add support to different reg offset definition to = share the same driver code? >=20 > Hi, >=20 > I am trying to add support to different reg offset and bit offset in > PL011 UART. It seems impossible to add macro in platform.dsc to enable > undef/redef in the header file with "#ifdef ZX_PL011_FLAG". Is there > any proper way to control the reg/bit offset definition? Or we have to > adopt the Linux driver method with a structure to hold different > offset value and wrap register access function as below? If so, > another Pcd is needed to specify the offset structure index for the > platforms. >=20 >=20 > static u16 pl011_st_offsets[REG_ARRAY_SIZE] =3D { > [REG_DR] =3D UART01x_DR, > [REG_ST_DMAWM] =3D ST_UART011_DMAWM, > [REG_ST_TIMEOUT] =3D ST_UART011_TIMEOUT, > ... > } >=20 > static unsigned int pl011_read(const struct uart_amba_port *uap, > unsigned int reg) > { > void __iomem *addr =3D uap->port.membase + uap->reg_offset[reg]; >=20 > return (uap->port.iotype =3D=3D UPIO_MEM32) ? > readl_relaxed(addr) : readw_relaxed(addr); > } >=20 > Jun > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel