From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 0065221ECCB15 for ; Wed, 20 Sep 2017 07:42:28 -0700 (PDT) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga105.fm.intel.com with ESMTP; 20 Sep 2017 07:45:34 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.42,421,1500966000"; d="scan'208";a="1197198630" Received: from fmsmsx104.amr.corp.intel.com ([10.18.124.202]) by fmsmga001.fm.intel.com with ESMTP; 20 Sep 2017 07:45:34 -0700 Received: from fmsmsx102.amr.corp.intel.com (10.18.124.200) by fmsmsx104.amr.corp.intel.com (10.18.124.202) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 20 Sep 2017 07:45:34 -0700 Received: from shsmsx151.ccr.corp.intel.com (10.239.6.50) by FMSMSX102.amr.corp.intel.com (10.18.124.200) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 20 Sep 2017 07:45:33 -0700 Received: from shsmsx152.ccr.corp.intel.com ([169.254.6.93]) by SHSMSX151.ccr.corp.intel.com ([169.254.3.98]) with mapi id 14.03.0319.002; Wed, 20 Sep 2017 22:45:32 +0800 From: "Gao, Liming" To: Leif Lindholm , "edk2-devel@lists.01.org" CC: "Kinney, Michael D" , Ard Biesheuvel Thread-Topic: [PATCH] MdePkg: add ARM/AARCH64 support to BaseCacheMaintenanceLib Thread-Index: AQHTMhOWDeEaJ69PmUS/qOJo0S4xYqK92U4w Date: Wed, 20 Sep 2017 14:45:30 +0000 Message-ID: <4A89E2EF3DFEDB4C8BFDE51014F606A14E15B35B@SHSMSX152.ccr.corp.intel.com> References: <20170920132252.11761-1-leif.lindholm@linaro.org> In-Reply-To: <20170920132252.11761-1-leif.lindholm@linaro.org> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.0.0.116 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH] MdePkg: add ARM/AARCH64 support to BaseCacheMaintenanceLib X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 20 Sep 2017 14:42:29 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Leif: This change lets MdePkg BaseCacheMaintenanceLib depend on ArmPkg ArmLib. = But, MdePkg is the basic package. It should not depend on other package. I = suggest to add this ARM specific BaseCacheMaintenanceLib library instance i= nto ArmPkg.=20 Thanks=09 Liming > -----Original Message----- > From: Leif Lindholm [mailto:leif.lindholm@linaro.org] > Sent: Wednesday, September 20, 2017 9:23 PM > To: edk2-devel@lists.01.org > Cc: Kinney, Michael D ; Gao, Liming ; Ard Biesheuvel > > Subject: [PATCH] MdePkg: add ARM/AARCH64 support to BaseCacheMaintenanceL= ib >=20 > ARM platforms have been using a separately located library in ArmPkg for > high-level cache maintenance calls. Resolve this anomaly by overwriting > ArmCache.c with the contents of > ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c, and add > the ArmLib dependency for the affected architectures. >=20 > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Leif Lindholm > --- >=20 > The intent is to delete the ArmPkg version once no upstream platforms > are using it. >=20 > MdePkg/Library/BaseCacheMaintenanceLib/ArmCache.c | 222 +++++----------= ------ > .../BaseCacheMaintenanceLib.inf | 2 + > 2 files changed, 55 insertions(+), 169 deletions(-) >=20 > diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/ArmCache.c b/MdePkg/L= ibrary/BaseCacheMaintenanceLib/ArmCache.c > index 79c84a0982..0759e38cd4 100644 > --- a/MdePkg/Library/BaseCacheMaintenanceLib/ArmCache.c > +++ b/MdePkg/Library/BaseCacheMaintenanceLib/ArmCache.c > @@ -1,67 +1,63 @@ > /** @file > - Cache Maintenance Functions. These functions vary by ARM architecture = so the MdePkg > - versions are null functions used to make sure things will compile. >=20 > - Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.
> - Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved. > + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
> + Copyright (c) 2011 - 2014, ARM Limited. All rights reserved. > + > This program and the accompanying materials > are licensed and made available under the terms and conditions of the = BSD License > which accompanies this distribution. The full text of the license may= be found at > - http://opensource.org/licenses/bsd-license.php. > + http://opensource.org/licenses/bsd-license.php >=20 > THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR I= MPLIED. >=20 > **/ > - > -// > -// Include common header file for this module. > -// > #include > +#include > #include > +#include >=20 > -/** > - Invalidates the entire instruction cache in cache coherency domain of = the > - calling CPU. > - > - Invalidates the entire instruction cache in cache coherency domain of = the > - calling CPU. > +STATIC > +VOID > +CacheRangeOperation ( > + IN VOID *Start, > + IN UINTN Length, > + IN LINE_OPERATION LineOperation, > + IN UINTN LineLength > + ) > +{ > + UINTN ArmCacheLineAlignmentMask =3D LineLength - 1; > + > + // Align address (rounding down) > + UINTN AlignedAddress =3D (UINTN)Start - ((UINTN)Start & ArmCacheLineAl= ignmentMask); > + UINTN EndAddress =3D (UINTN)Start + Length; > + > + // Perform the line operation on an address in each cache line > + while (AlignedAddress < EndAddress) { > + LineOperation(AlignedAddress); > + AlignedAddress +=3D LineLength; > + } > + ArmDataSynchronizationBarrier (); > +} >=20 > -**/ > VOID > EFIAPI > InvalidateInstructionCache ( > VOID > ) > { > - ASSERT(FALSE); > + ASSERT (FALSE); > } >=20 > -/** > - Invalidates a range of instruction cache lines in the cache coherency = domain > - of the calling CPU. > - > - Invalidates the instruction cache lines specified by Address and Lengt= h. If > - Address is not aligned on a cache line boundary, then entire instructi= on > - cache line containing Address is invalidated. If Address + Length is n= ot > - aligned on a cache line boundary, then the entire instruction cache li= ne > - containing Address + Length -1 is invalidated. This function may choos= e to > - invalidate the entire instruction cache if that is more efficient than > - invalidating the specified range. If Length is 0, then no instruction = cache > - lines are invalidated. Address is returned. > - > - If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). > - > - @param Address The base address of the instruction cache lines to > - invalidate. If the CPU is in a physical addressing mod= e, then > - Address is a physical address. If the CPU is in a virt= ual > - addressing mode, then Address is a virtual address. > - > - @param Length The number of bytes to invalidate from the instruction= cache. > - > - @return Address > +VOID > +EFIAPI > +InvalidateDataCache ( > + VOID > + ) > +{ > + ASSERT (FALSE); > +} >=20 > -**/ > VOID * > EFIAPI > InvalidateInstructionCacheRange ( > @@ -69,56 +65,26 @@ InvalidateInstructionCacheRange ( > IN UINTN Length > ) > { > - ASSERT (Length <=3D MAX_ADDRESS - (UINTN)Address + 1); > - ASSERT(FALSE); > - return Address; > -} > + CacheRangeOperation (Address, Length, ArmCleanDataCacheEntryToPoUByMVA= , > + ArmDataCacheLineLength ()); > + CacheRangeOperation (Address, Length, > + ArmInvalidateInstructionCacheEntryToPoUByMVA, > + ArmInstructionCacheLineLength ()); >=20 > -/** > - Writes back and invalidates the entire data cache in cache coherency d= omain > - of the calling CPU. > + ArmInstructionSynchronizationBarrier (); >=20 > - Writes Back and Invalidates the entire data cache in cache coherency d= omain > - of the calling CPU. This function guarantees that all dirty cache line= s are > - written back to system memory, and also invalidates all the data cache= lines > - in the cache coherency domain of the calling CPU. > + return Address; > +} >=20 > -**/ > VOID > EFIAPI > WriteBackInvalidateDataCache ( > VOID > ) > { > - ASSERT(FALSE); > + ASSERT (FALSE); > } >=20 > -/** > - Writes back and invalidates a range of data cache lines in the cache > - coherency domain of the calling CPU. > - > - Writes back and invalidates the data cache lines specified by Address = and > - Length. If Address is not aligned on a cache line boundary, then entir= e data > - cache line containing Address is written back and invalidated. If Addr= ess + > - Length is not aligned on a cache line boundary, then the entire data c= ache > - line containing Address + Length -1 is written back and invalidated. T= his > - function may choose to write back and invalidate the entire data cache= if > - that is more efficient than writing back and invalidating the specifie= d > - range. If Length is 0, then no data cache lines are written back and > - invalidated. Address is returned. > - > - If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). > - > - @param Address The base address of the data cache lines to write back= and > - invalidate. If the CPU is in a physical addressing mod= e, then > - Address is a physical address. If the CPU is in a virt= ual > - addressing mode, then Address is a virtual address. > - @param Length The number of bytes to write back and invalidate from = the > - data cache. > - > - @return Address > - > -**/ > VOID * > EFIAPI > WriteBackInvalidateDataCacheRange ( > @@ -126,55 +92,20 @@ WriteBackInvalidateDataCacheRange ( > IN UINTN Length > ) > { > - ASSERT (Length <=3D MAX_ADDRESS - (UINTN)Address + 1); > - ASSERT(FALSE); > + CacheRangeOperation(Address, Length, ArmCleanInvalidateDataCacheEntryB= yMVA, > + ArmDataCacheLineLength ()); > return Address; > } >=20 > -/** > - Writes back the entire data cache in cache coherency domain of the cal= ling > - CPU. > - > - Writes back the entire data cache in cache coherency domain of the cal= ling > - CPU. This function guarantees that all dirty cache lines are written b= ack to > - system memory. This function may also invalidate all the data cache li= nes in > - the cache coherency domain of the calling CPU. > - > -**/ > VOID > EFIAPI > WriteBackDataCache ( > VOID > ) > { > - ASSERT(FALSE); > + ASSERT (FALSE); > } >=20 > -/** > - Writes back a range of data cache lines in the cache coherency domain = of the > - calling CPU. > - > - Writes back the data cache lines specified by Address and Length. If A= ddress > - is not aligned on a cache line boundary, then entire data cache line > - containing Address is written back. If Address + Length is not aligned= on a > - cache line boundary, then the entire data cache line containing Addres= s + > - Length -1 is written back. This function may choose to write back the = entire > - data cache if that is more efficient than writing back the specified r= ange. > - If Length is 0, then no data cache lines are written back. This functi= on may > - also invalidate all the data cache lines in the specified range of the= cache > - coherency domain of the calling CPU. Address is returned. > - > - If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). > - > - @param Address The base address of the data cache lines to write back= . If > - the CPU is in a physical addressing mode, then Address= is a > - physical address. If the CPU is in a virtual addressin= g > - mode, then Address is a virtual address. > - @param Length The number of bytes to write back from the data cache. > - > - @return Address > - > -**/ > VOID * > EFIAPI > WriteBackDataCacheRange ( > @@ -182,58 +113,11 @@ WriteBackDataCacheRange ( > IN UINTN Length > ) > { > - ASSERT (Length <=3D MAX_ADDRESS - (UINTN)Address + 1); > - ASSERT(FALSE); > + CacheRangeOperation(Address, Length, ArmCleanDataCacheEntryByMVA, > + ArmDataCacheLineLength ()); > return Address; > } >=20 > -/** > - Invalidates the entire data cache in cache coherency domain of the cal= ling > - CPU. > - > - Invalidates the entire data cache in cache coherency domain of the cal= ling > - CPU. This function must be used with care because dirty cache lines ar= e not > - written back to system memory. It is typically used for cache diagnost= ics. If > - the CPU does not support invalidation of the entire data cache, then a= write > - back and invalidate operation should be performed on the entire data c= ache. > - > -**/ > -VOID > -EFIAPI > -InvalidateDataCache ( > - VOID > - ) > -{ > - ASSERT(FALSE); > -} > - > -/** > - Invalidates a range of data cache lines in the cache coherency domain = of the > - calling CPU. > - > - Invalidates the data cache lines specified by Address and Length. If A= ddress > - is not aligned on a cache line boundary, then entire data cache line > - containing Address is invalidated. If Address + Length is not aligned = on a > - cache line boundary, then the entire data cache line containing Addres= s + > - Length -1 is invalidated. This function must never invalidate any cach= e lines > - outside the specified range. If Length is 0, then no data cache lines = are > - invalidated. Address is returned. This function must be used with care > - because dirty cache lines are not written back to system memory. It is > - typically used for cache diagnostics. If the CPU does not support > - invalidation of a data cache range, then a write back and invalidate > - operation should be performed on the data cache range. > - > - If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT(). > - > - @param Address The base address of the data cache lines to invalidate= . If > - the CPU is in a physical addressing mode, then Address= is a > - physical address. If the CPU is in a virtual addressin= g mode, > - then Address is a virtual address. > - @param Length The number of bytes to invalidate from the data cache. > - > - @return Address > - > -**/ > VOID * > EFIAPI > InvalidateDataCacheRange ( > @@ -241,7 +125,7 @@ InvalidateDataCacheRange ( > IN UINTN Length > ) > { > - ASSERT (Length <=3D MAX_ADDRESS - (UINTN)Address + 1); > - ASSERT(FALSE); > + CacheRangeOperation(Address, Length, ArmInvalidateDataCacheEntryByMVA, > + ArmDataCacheLineLength ()); > return Address; > } > diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceL= ib.inf > b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf > index d659161f33..7440a0062b 100644 > --- a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf > +++ b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf > @@ -59,3 +59,5 @@ > [LibraryClasses.Ipf] > PalLib >=20 > +[LibraryClasses.ARM,LibraryClasses.AARCH64] > + ArmLib > -- > 2.11.0