From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.120; helo=mga04.intel.com; envelope-from=liming.gao@intel.com; receiver=edk2-devel@lists.01.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9B6992034C085 for ; Wed, 25 Oct 2017 07:37:42 -0700 (PDT) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 25 Oct 2017 07:41:26 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.43,431,1503385200"; d="scan'208";a="1029244618" Received: from fmsmsx103.amr.corp.intel.com ([10.18.124.201]) by orsmga003.jf.intel.com with ESMTP; 25 Oct 2017 07:41:26 -0700 Received: from fmsmsx122.amr.corp.intel.com (10.18.125.37) by FMSMSX103.amr.corp.intel.com (10.18.124.201) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 25 Oct 2017 07:41:26 -0700 Received: from shsmsx151.ccr.corp.intel.com (10.239.6.50) by fmsmsx122.amr.corp.intel.com (10.18.125.37) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 25 Oct 2017 07:41:26 -0700 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.152]) by SHSMSX151.ccr.corp.intel.com ([169.254.3.218]) with mapi id 14.03.0319.002; Wed, 25 Oct 2017 22:41:23 +0800 From: "Gao, Liming" To: Ard Biesheuvel , "edk2-devel@lists.01.org" CC: "leif.lindholm@linaro.org" , "Zhu, Yonghong" Thread-Topic: [PATCH] BaseTools/tools_def AARCH64: disable PIE linking Thread-Index: AQHTTXdpJnzzZqaRhEGg+n++W/sOfKL0o0DQ Date: Wed, 25 Oct 2017 14:41:23 +0000 Message-ID: <4A89E2EF3DFEDB4C8BFDE51014F606A14E170AEF@SHSMSX104.ccr.corp.intel.com> References: <20171025095511.25751-1-ard.biesheuvel@linaro.org> In-Reply-To: <20171025095511.25751-1-ard.biesheuvel@linaro.org> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.0.0.116 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH] BaseTools/tools_def AARCH64: disable PIE linking X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 25 Oct 2017 14:37:42 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Ard: I see ARM and AARCH64 CC flag have -fno-pie. Does it work on the prebuilt= GCC binary? And, if this change is required, why not add it for ARM_DLINK? > -----Original Message----- > From: Ard Biesheuvel [mailto:ard.biesheuvel@linaro.org] > Sent: Wednesday, October 25, 2017 5:55 PM > To: edk2-devel@lists.01.org > Cc: leif.lindholm@linaro.org; Gao, Liming ; Zhu, Yo= nghong ; Ard Biesheuvel > > Subject: [PATCH] BaseTools/tools_def AARCH64: disable PIE linking >=20 > Some prebuilt GCC toolchains targeting aarch64 (e.g., the Debian Stretch > one) will default to building PIE executables. This has been observed to > corrupt ACPI tables built from .aslc sources, so disable PIE linking > altogether when using the GCC toolchain to build for AARCH64. >=20 > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ard Biesheuvel > --- > BaseTools/Conf/tools_def.template | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) >=20 > diff --git a/BaseTools/Conf/tools_def.template b/BaseTools/Conf/tools_def= .template > index e93c2a0bf1ef..16ef935f5ef9 100755 > --- a/BaseTools/Conf/tools_def.template > +++ b/BaseTools/Conf/tools_def.template > @@ -4355,7 +4355,7 @@ DEFINE GCC_DLINK2_FLAGS_COMMON =3D -Wl,--script= =3D$(EDK_TOOLS_PATH)/Scripts/GccB > DEFINE GCC_IA32_X64_DLINK_COMMON =3D DEF(GCC_DLINK_FLAGS_COMMON) --gc-= sections > DEFINE GCC_ARM_AARCH64_DLINK_COMMON=3D -Wl,--emit-relocs -nostdlib -Wl,-= -gc-sections -u $(IMAGE_ENTRY_POINT) > -Wl,-e,$(IMAGE_ENTRY_POINT),-Map,$(DEST_DIR_DEBUG)/$(BASE_NAME).map > DEFINE GCC_ARM_DLINK_FLAGS =3D DEF(GCC_ARM_AARCH64_DLINK_COMMON)= -z common-page-size=3D0x20 > -DEFINE GCC_AARCH64_DLINK_FLAGS =3D DEF(GCC_ARM_AARCH64_DLINK_COMMON)= -z common-page-size=3D0x20 > +DEFINE GCC_AARCH64_DLINK_FLAGS =3D DEF(GCC_ARM_AARCH64_DLINK_COMMON)= -z common-page-size=3D0x20 -no-pie > DEFINE GCC_IA32_X64_ASLDLINK_FLAGS =3D DEF(GCC_IA32_X64_DLINK_COMMON) --= entry _ReferenceAcpiTable -u > $(IMAGE_ENTRY_POINT) > DEFINE GCC_ARM_ASLDLINK_FLAGS =3D DEF(GCC_ARM_DLINK_FLAGS) -Wl,--en= try,ReferenceAcpiTable -u > $(IMAGE_ENTRY_POINT) > DEFINE GCC_AARCH64_ASLDLINK_FLAGS =3D DEF(GCC_AARCH64_DLINK_FLAGS) -Wl,= --entry,ReferenceAcpiTable -u > $(IMAGE_ENTRY_POINT) > -- > 2.11.0