From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.43; helo=mga05.intel.com; envelope-from=liming.gao@intel.com; receiver=edk2-devel@lists.01.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 012F920347160 for ; Wed, 25 Oct 2017 19:14:41 -0700 (PDT) Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP; 25 Oct 2017 19:18:27 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.43,433,1503385200"; d="scan'208";a="165078727" Received: from fmsmsx105.amr.corp.intel.com ([10.18.124.203]) by orsmga005.jf.intel.com with ESMTP; 25 Oct 2017 19:18:26 -0700 Received: from fmsmsx126.amr.corp.intel.com (10.18.125.43) by FMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 25 Oct 2017 19:18:26 -0700 Received: from shsmsx102.ccr.corp.intel.com (10.239.4.154) by FMSMSX126.amr.corp.intel.com (10.18.125.43) with Microsoft SMTP Server (TLS) id 14.3.319.2; Wed, 25 Oct 2017 19:18:26 -0700 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.152]) by shsmsx102.ccr.corp.intel.com ([169.254.2.175]) with mapi id 14.03.0319.002; Thu, 26 Oct 2017 10:18:24 +0800 From: "Gao, Liming" To: Ard Biesheuvel , "edk2-devel@lists.01.org" CC: "leif.lindholm@linaro.org" , "Zhu, Yonghong" Thread-Topic: [PATCH v2] BaseTools/tools_def AARCH64 ARM: disable PIE linking Thread-Index: AQHTTc0E7QCixXz9/kWGOGC/UHHOmqL1Zbgg Date: Thu, 26 Oct 2017 02:18:24 +0000 Message-ID: <4A89E2EF3DFEDB4C8BFDE51014F606A14E170EBC@SHSMSX104.ccr.corp.intel.com> References: <20171025200805.1443-1-ard.biesheuvel@linaro.org> In-Reply-To: <20171025200805.1443-1-ard.biesheuvel@linaro.org> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH v2] BaseTools/tools_def AARCH64 ARM: disable PIE linking X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 26 Oct 2017 02:14:42 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Liming Gao >-----Original Message----- >From: Ard Biesheuvel [mailto:ard.biesheuvel@linaro.org] >Sent: Thursday, October 26, 2017 4:08 AM >To: edk2-devel@lists.01.org >Cc: leif.lindholm@linaro.org; Gao, Liming ; Zhu, >Yonghong ; Ard Biesheuvel > >Subject: [PATCH v2] BaseTools/tools_def AARCH64 ARM: disable PIE linking > >Some prebuilt GCC toolchains targeting aarch64 (e.g., the Debian Stretch >one) will default to building PIE executables. This has been observed to >corrupt ACPI tables built from .aslc sources, so disable PIE linking >altogether when using the GCC toolchain to build for AARCH64 or ARM. > >Contributed-under: TianoCore Contribution Agreement 1.1 >Signed-off-by: Ard Biesheuvel >--- >v2: - apply to both AARCH64 and ARM > - apply to GCC5 (and up) only - older versions of GCC don't support th= is > option > > BaseTools/Conf/tools_def.template | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > >diff --git a/BaseTools/Conf/tools_def.template >b/BaseTools/Conf/tools_def.template >index e93c2a0bf1ef..df7c109438fd 100755 >--- a/BaseTools/Conf/tools_def.template >+++ b/BaseTools/Conf/tools_def.template >@@ -4494,9 +4494,9 @@ DEFINE GCC5_ARM_CC_FLAGS =3D >DEF(GCC49_ARM_CC_FLAGS) > DEFINE GCC5_ARM_CC_XIPFLAGS =3D DEF(GCC49_ARM_CC_XIPFLAGS) > DEFINE GCC5_AARCH64_CC_FLAGS =3D DEF(GCC49_AARCH64_CC_FLAGS) > DEFINE GCC5_AARCH64_CC_XIPFLAGS =3D >DEF(GCC49_AARCH64_CC_XIPFLAGS) >-DEFINE GCC5_ARM_DLINK_FLAGS =3D DEF(GCC49_ARM_DLINK_FLAGS) >+DEFINE GCC5_ARM_DLINK_FLAGS =3D DEF(GCC49_ARM_DLINK_FLAGS) - >no-pie > DEFINE GCC5_ARM_DLINK2_FLAGS =3D DEF(GCC49_ARM_DLINK2_FLAGS) - >Wno-error >-DEFINE GCC5_AARCH64_DLINK_FLAGS =3D >DEF(GCC49_AARCH64_DLINK_FLAGS) >+DEFINE GCC5_AARCH64_DLINK_FLAGS =3D >DEF(GCC49_AARCH64_DLINK_FLAGS) -no-pie > DEFINE GCC5_AARCH64_DLINK2_FLAGS =3D >DEF(GCC49_AARCH64_DLINK2_FLAGS) -Wno-error > DEFINE GCC5_ARM_ASLDLINK_FLAGS =3D >DEF(GCC49_ARM_ASLDLINK_FLAGS) > DEFINE GCC5_AARCH64_ASLDLINK_FLAGS =3D >DEF(GCC49_AARCH64_ASLDLINK_FLAGS) >-- >2.11.0