From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.120; helo=mga04.intel.com; envelope-from=liming.gao@intel.com; receiver=edk2-devel@lists.01.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id DAA08202E5CD3 for ; Thu, 26 Oct 2017 01:48:51 -0700 (PDT) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 26 Oct 2017 01:52:30 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.43,434,1503385200"; d="scan'208";a="1029608833" Received: from fmsmsx107.amr.corp.intel.com ([10.18.124.205]) by orsmga003.jf.intel.com with ESMTP; 26 Oct 2017 01:52:29 -0700 Received: from fmsmsx117.amr.corp.intel.com (10.18.116.17) by fmsmsx107.amr.corp.intel.com (10.18.124.205) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 26 Oct 2017 01:52:29 -0700 Received: from shsmsx102.ccr.corp.intel.com (10.239.4.154) by fmsmsx117.amr.corp.intel.com (10.18.116.17) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 26 Oct 2017 01:52:28 -0700 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.152]) by shsmsx102.ccr.corp.intel.com ([169.254.2.175]) with mapi id 14.03.0319.002; Thu, 26 Oct 2017 16:52:27 +0800 From: "Gao, Liming" To: "Ni, Ruiyu" , "edk2-devel@lists.01.org" Thread-Topic: [PATCH] MdePkg/PciExpress21.h: Fix typo in PCI_REG_PCIE_SLOT_CONTROL Thread-Index: AQHTTjGTgjWmuLp1dkGTFyYpFlGTAaL10xQQ Date: Thu, 26 Oct 2017 08:52:27 +0000 Message-ID: <4A89E2EF3DFEDB4C8BFDE51014F606A14E171191@SHSMSX104.ccr.corp.intel.com> References: <20171026080741.225120-1-ruiyu.ni@intel.com> In-Reply-To: <20171026080741.225120-1-ruiyu.ni@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH] MdePkg/PciExpress21.h: Fix typo in PCI_REG_PCIE_SLOT_CONTROL X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 26 Oct 2017 08:48:52 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Liming Gao >-----Original Message----- >From: Ni, Ruiyu >Sent: Thursday, October 26, 2017 4:08 PM >To: edk2-devel@lists.01.org >Cc: Gao, Liming >Subject: [PATCH] MdePkg/PciExpress21.h: Fix typo in >PCI_REG_PCIE_SLOT_CONTROL > >PCI_REG_PCIE_SLOT_CONTROL contains a typo. It is defined as: >typedef union { > struct { > UINT32 AttentionButtonPressed : 1; > UINT32 ... > ... > } Bits; > UINT16 Uint16; >} PCI_REG_PCIE_SLOT_CONTROL; > >The bit field data type should be UINT16 instead of UINT32, >results sizeof (PCI_REG_PCIE_SLOT_CONTROL) equals to 4 instead of 2. > >Because this structure is used in PCI_CAPABILITY_PCIEXP as below: >typedef struct { > ... > PCI_REG_PCIE_SLOT_CONTROL SlotControl; > PCI_REG_PCIE_SLOT_STATUS SlotStatus; >} PCI_CAPABILITY_PCIEXP; > >It cause the OFFSET_OF (PCI_CAPABILITY_PCIEXP, SlotStatus) equal >to a wrong value. > >Contributed-under: TianoCore Contribution Agreement 1.1 >Signed-off-by: Ruiyu Ni >Cc: Liming Gao >--- > MdePkg/Include/IndustryStandard/PciExpress21.h | 24 ++++++++++++------- >----- > 1 file changed, 12 insertions(+), 12 deletions(-) > >diff --git a/MdePkg/Include/IndustryStandard/PciExpress21.h >b/MdePkg/Include/IndustryStandard/PciExpress21.h >index ce9c06a7c6..d90b5975ba 100644 >--- a/MdePkg/Include/IndustryStandard/PciExpress21.h >+++ b/MdePkg/Include/IndustryStandard/PciExpress21.h >@@ -182,18 +182,18 @@ typedef union { > > typedef union { > struct { >- UINT32 AttentionButtonPressed : 1; >- UINT32 PowerFaultDetected : 1; >- UINT32 MrlSensorChanged : 1; >- UINT32 PresenceDetectChanged : 1; >- UINT32 CommandCompletedInterrupt : 1; >- UINT32 HotPlugInterrupt : 1; >- UINT32 AttentionIndicator : 2; >- UINT32 PowerIndicator : 2; >- UINT32 PowerController : 1; >- UINT32 ElectromechanicalInterlock : 1; >- UINT32 DataLinkLayerStateChanged : 1; >- UINT32 Reserved : 3; >+ UINT16 AttentionButtonPressed : 1; >+ UINT16 PowerFaultDetected : 1; >+ UINT16 MrlSensorChanged : 1; >+ UINT16 PresenceDetectChanged : 1; >+ UINT16 CommandCompletedInterrupt : 1; >+ UINT16 HotPlugInterrupt : 1; >+ UINT16 AttentionIndicator : 2; >+ UINT16 PowerIndicator : 2; >+ UINT16 PowerController : 1; >+ UINT16 ElectromechanicalInterlock : 1; >+ UINT16 DataLinkLayerStateChanged : 1; >+ UINT16 Reserved : 3; > } Bits; > UINT16 Uint16; > } PCI_REG_PCIE_SLOT_CONTROL; >-- >2.12.2.windows.2