From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.65; helo=mga03.intel.com; envelope-from=liming.gao@intel.com; receiver=edk2-devel@lists.01.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id A36CB2034A875 for ; Thu, 26 Oct 2017 18:51:21 -0700 (PDT) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 26 Oct 2017 18:55:07 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.44,302,1505804400"; d="scan'208";a="1210657065" Received: from fmsmsx106.amr.corp.intel.com ([10.18.124.204]) by fmsmga001.fm.intel.com with ESMTP; 26 Oct 2017 18:55:07 -0700 Received: from fmsmsx102.amr.corp.intel.com (10.18.124.200) by FMSMSX106.amr.corp.intel.com (10.18.124.204) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 26 Oct 2017 18:55:07 -0700 Received: from shsmsx102.ccr.corp.intel.com (10.239.4.154) by FMSMSX102.amr.corp.intel.com (10.18.124.200) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 26 Oct 2017 18:55:07 -0700 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.152]) by shsmsx102.ccr.corp.intel.com ([169.254.2.175]) with mapi id 14.03.0319.002; Fri, 27 Oct 2017 09:55:05 +0800 From: "Gao, Liming" To: "Ruffin, Chris" , "edk2-devel@lists.01.org" Thread-Topic: [edk2] [PATCH] MdePkg/Include: fix incorrect structure definition Thread-Index: AQHTTr+lrQr+ktst50mEhmo9P71dG6L2752Q Date: Fri, 27 Oct 2017 01:55:04 +0000 Message-ID: <4A89E2EF3DFEDB4C8BFDE51014F606A14E1716E9@SHSMSX104.ccr.corp.intel.com> References: <20171027010429.41540-1-chris.ruffin@intel.com> In-Reply-To: <20171027010429.41540-1-chris.ruffin@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH] MdePkg/Include: fix incorrect structure definition X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 Oct 2017 01:51:21 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Chris: Ni, Ruiyu has sent this patch yesterday.=20 >-----Original Message----- >From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of >Chris Ruffin >Sent: Friday, October 27, 2017 9:04 AM >To: edk2-devel@lists.01.org >Subject: [edk2] [PATCH] MdePkg/Include: fix incorrect structure definition > >Fix incorrect structure definitions for PCI_REG_PCIE_SLOT_CONTROL in >PciExpress21.h. > >Contributed-under: TianoCore Contribution Agreement 1.0 >Signed-off-by: Chris Ruffin >--- > MdePkg/Include/IndustryStandard/PciExpress21.h | 24 ++++++++++++------- >----- > 1 file changed, 12 insertions(+), 12 deletions(-) > >diff --git a/MdePkg/Include/IndustryStandard/PciExpress21.h >b/MdePkg/Include/IndustryStandard/PciExpress21.h >index ce9c06a7c6..d90b5975ba 100644 >--- a/MdePkg/Include/IndustryStandard/PciExpress21.h >+++ b/MdePkg/Include/IndustryStandard/PciExpress21.h >@@ -182,18 +182,18 @@ typedef union { > > typedef union { > struct { >- UINT32 AttentionButtonPressed : 1; >- UINT32 PowerFaultDetected : 1; >- UINT32 MrlSensorChanged : 1; >- UINT32 PresenceDetectChanged : 1; >- UINT32 CommandCompletedInterrupt : 1; >- UINT32 HotPlugInterrupt : 1; >- UINT32 AttentionIndicator : 2; >- UINT32 PowerIndicator : 2; >- UINT32 PowerController : 1; >- UINT32 ElectromechanicalInterlock : 1; >- UINT32 DataLinkLayerStateChanged : 1; >- UINT32 Reserved : 3; >+ UINT16 AttentionButtonPressed : 1; >+ UINT16 PowerFaultDetected : 1; >+ UINT16 MrlSensorChanged : 1; >+ UINT16 PresenceDetectChanged : 1; >+ UINT16 CommandCompletedInterrupt : 1; >+ UINT16 HotPlugInterrupt : 1; >+ UINT16 AttentionIndicator : 2; >+ UINT16 PowerIndicator : 2; >+ UINT16 PowerController : 1; >+ UINT16 ElectromechanicalInterlock : 1; >+ UINT16 DataLinkLayerStateChanged : 1; >+ UINT16 Reserved : 3; > } Bits; > UINT16 Uint16; > } PCI_REG_PCIE_SLOT_CONTROL; >-- >2.13.3.windows.1 > >_______________________________________________ >edk2-devel mailing list >edk2-devel@lists.01.org >https://lists.01.org/mailman/listinfo/edk2-devel