From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.43; helo=mga05.intel.com; envelope-from=liming.gao@intel.com; receiver=edk2-devel@lists.01.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 8A451220C1C27 for ; Thu, 23 Nov 2017 02:12:55 -0800 (PST) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Nov 2017 02:17:12 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.44,441,1505804400"; d="scan'208";a="5516065" Received: from fmsmsx106.amr.corp.intel.com ([10.18.124.204]) by orsmga003.jf.intel.com with ESMTP; 23 Nov 2017 02:17:11 -0800 Received: from fmsmsx152.amr.corp.intel.com (10.18.125.5) by FMSMSX106.amr.corp.intel.com (10.18.124.204) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 23 Nov 2017 02:16:59 -0800 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by FMSMSX152.amr.corp.intel.com (10.18.125.5) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 23 Nov 2017 02:16:59 -0800 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.152]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.93]) with mapi id 14.03.0319.002; Thu, 23 Nov 2017 18:16:57 +0800 From: "Gao, Liming" To: Ard Biesheuvel , "edk2-devel@lists.01.org" , "leif.lindholm@linaro.org" Thread-Topic: [PATCH] BaseTools/tools_def AARCH64 ARM: suppres PIE sections via linker script Thread-Index: AQHTYuNTi1iCevoXyUCYv9SEctZlsKMhweyA Date: Thu, 23 Nov 2017 10:16:57 +0000 Message-ID: <4A89E2EF3DFEDB4C8BFDE51014F606A14E1826B0@SHSMSX104.ccr.corp.intel.com> References: <20171121161037.26573-1-ard.biesheuvel@linaro.org> In-Reply-To: <20171121161037.26573-1-ard.biesheuvel@linaro.org> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH] BaseTools/tools_def AARCH64 ARM: suppres PIE sections via linker script X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 23 Nov 2017 10:12:55 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Ard: Have you own GCC linker script? Is it not in BaseTools? Thanks Liming >-----Original Message----- >From: Ard Biesheuvel [mailto:ard.biesheuvel@linaro.org] >Sent: Wednesday, November 22, 2017 12:11 AM >To: edk2-devel@lists.01.org; leif.lindholm@linaro.org >Cc: mw@semihalf.com; Zhu, Yonghong ; Gao, >Liming ; daniel.thompson@linaro.org; Ard Biesheuvel > >Subject: [PATCH] BaseTools/tools_def AARCH64 ARM: suppres PIE sections >via linker script > >Recent distro builds of GCC 6 enable PIE linking by default, and allow >the previous behavior to be restored by passing the -no-pie command line >argument. This was implemented by commits 1894a7c64c0a and 3380a591232d >but unfortunately, it turns out that GCC 5 does not support this command >line argument, and exits with an error. > >To avoid the need for yet another toolchain tag, to distinguish between >GCC 5 and GCC 6, let's use our GCC linker scripts when building objects >from .aslc files. This will ensure that the extra sections that are added >by the PIE linker are discarded from the ELF binary, and so they will not >corrupt the resulting .acpi file. > >This reverts > >1894a7c64c0a BaseTools/tools_def AARCH64 ARM: disable PIE linking >3380a591232d BaseTools/tools_def AARCH64 ARM: disable PIE linking for .asl= c >sources > >Contributed-under: TianoCore Contribution Agreement 1.1 >Signed-off-by: Ard Biesheuvel >--- > BaseTools/Conf/tools_def.template | 13 +++++++------ > 1 file changed, 7 insertions(+), 6 deletions(-) > >diff --git a/BaseTools/Conf/tools_def.template >b/BaseTools/Conf/tools_def.template >index aebd7d558633..4d2a3b7dbe56 100755 >--- a/BaseTools/Conf/tools_def.template >+++ b/BaseTools/Conf/tools_def.template >@@ -4356,9 +4356,10 @@ DEFINE GCC_IA32_X64_DLINK_COMMON =3D >DEF(GCC_DLINK_FLAGS_COMMON) --gc-sections > DEFINE GCC_ARM_AARCH64_DLINK_COMMON=3D -Wl,--emit-relocs -nostdlib - >Wl,--gc-sections -u $(IMAGE_ENTRY_POINT) -Wl,- >e,$(IMAGE_ENTRY_POINT),-Map,$(DEST_DIR_DEBUG)/$(BASE_NAME).map > DEFINE GCC_ARM_DLINK_FLAGS =3D >DEF(GCC_ARM_AARCH64_DLINK_COMMON) -z common-page-size=3D0x20 > DEFINE GCC_AARCH64_DLINK_FLAGS =3D >DEF(GCC_ARM_AARCH64_DLINK_COMMON) -z common-page-size=3D0x20 >+DEFINE GCC_ARM_AARCH64_ASLDLINK_FLAGS =3D -Wl,-- >defsym=3DPECOFF_HEADER_SIZE=3D0 DEF(GCC_DLINK2_FLAGS_COMMON) -z >common-page-size=3D0x20 > DEFINE GCC_IA32_X64_ASLDLINK_FLAGS =3D >DEF(GCC_IA32_X64_DLINK_COMMON) --entry _ReferenceAcpiTable -u >$(IMAGE_ENTRY_POINT) >-DEFINE GCC_ARM_ASLDLINK_FLAGS =3D DEF(GCC_ARM_DLINK_FLAGS) - >Wl,--entry,ReferenceAcpiTable -u $(IMAGE_ENTRY_POINT) >-DEFINE GCC_AARCH64_ASLDLINK_FLAGS =3D >DEF(GCC_AARCH64_DLINK_FLAGS) -Wl,--entry,ReferenceAcpiTable -u >$(IMAGE_ENTRY_POINT) >+DEFINE GCC_ARM_ASLDLINK_FLAGS =3D DEF(GCC_ARM_DLINK_FLAGS) - >Wl,--entry,ReferenceAcpiTable -u $(IMAGE_ENTRY_POINT) >DEF(GCC_ARM_AARCH64_ASLDLINK_FLAGS) >+DEFINE GCC_AARCH64_ASLDLINK_FLAGS =3D >DEF(GCC_AARCH64_DLINK_FLAGS) -Wl,--entry,ReferenceAcpiTable -u >$(IMAGE_ENTRY_POINT) DEF(GCC_ARM_AARCH64_ASLDLINK_FLAGS) > DEFINE GCC_IA32_X64_DLINK_FLAGS =3D >DEF(GCC_IA32_X64_DLINK_COMMON) --entry _$(IMAGE_ENTRY_POINT) -- >file-alignment 0x20 --section-alignment 0x20 -Map >$(DEST_DIR_DEBUG)/$(BASE_NAME).map > DEFINE GCC_IPF_DLINK_FLAGS =3D -nostdlib -O2 --gc-sections --dll = -static -- >entry $(IMAGE_ENTRY_POINT) --undefined $(IMAGE_ENTRY_POINT) -Map >$(DEST_DIR_DEBUG)/$(BASE_NAME).map > DEFINE GCC_IPF_OBJCOPY_FLAGS =3D -I elf64-ia64-little -O efi-bsdrv-= ia64 >@@ -4494,12 +4495,12 @@ DEFINE GCC5_ARM_CC_FLAGS =3D >DEF(GCC49_ARM_CC_FLAGS) > DEFINE GCC5_ARM_CC_XIPFLAGS =3D DEF(GCC49_ARM_CC_XIPFLAGS) > DEFINE GCC5_AARCH64_CC_FLAGS =3D DEF(GCC49_AARCH64_CC_FLAGS) > DEFINE GCC5_AARCH64_CC_XIPFLAGS =3D >DEF(GCC49_AARCH64_CC_XIPFLAGS) >-DEFINE GCC5_ARM_DLINK_FLAGS =3D DEF(GCC49_ARM_DLINK_FLAGS) - >no-pie >+DEFINE GCC5_ARM_DLINK_FLAGS =3D DEF(GCC49_ARM_DLINK_FLAGS) > DEFINE GCC5_ARM_DLINK2_FLAGS =3D DEF(GCC49_ARM_DLINK2_FLAGS) - >Wno-error >-DEFINE GCC5_AARCH64_DLINK_FLAGS =3D >DEF(GCC49_AARCH64_DLINK_FLAGS) -no-pie >+DEFINE GCC5_AARCH64_DLINK_FLAGS =3D >DEF(GCC49_AARCH64_DLINK_FLAGS) > DEFINE GCC5_AARCH64_DLINK2_FLAGS =3D >DEF(GCC49_AARCH64_DLINK2_FLAGS) -Wno-error >-DEFINE GCC5_ARM_ASLDLINK_FLAGS =3D >DEF(GCC49_ARM_ASLDLINK_FLAGS) -no-pie >-DEFINE GCC5_AARCH64_ASLDLINK_FLAGS =3D >DEF(GCC49_AARCH64_ASLDLINK_FLAGS) -no-pie >+DEFINE GCC5_ARM_ASLDLINK_FLAGS =3D >DEF(GCC49_ARM_ASLDLINK_FLAGS) >+DEFINE GCC5_AARCH64_ASLDLINK_FLAGS =3D >DEF(GCC49_AARCH64_ASLDLINK_FLAGS) > > >########################################################### >######################### > # >-- >2.11.0