From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.100; helo=mga07.intel.com; envelope-from=liming.gao@intel.com; receiver=edk2-devel@lists.01.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 2D73022152383 for ; Mon, 4 Dec 2017 07:35:56 -0800 (PST) Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 04 Dec 2017 07:40:25 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.45,359,1508828400"; d="scan'208";a="181144860" Received: from fmsmsx103.amr.corp.intel.com ([10.18.124.201]) by orsmga005.jf.intel.com with ESMTP; 04 Dec 2017 07:40:25 -0800 Received: from fmsmsx119.amr.corp.intel.com (10.18.124.207) by FMSMSX103.amr.corp.intel.com (10.18.124.201) with Microsoft SMTP Server (TLS) id 14.3.319.2; Mon, 4 Dec 2017 07:40:25 -0800 Received: from shsmsx103.ccr.corp.intel.com (10.239.4.69) by FMSMSX119.amr.corp.intel.com (10.18.124.207) with Microsoft SMTP Server (TLS) id 14.3.319.2; Mon, 4 Dec 2017 07:40:25 -0800 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.152]) by SHSMSX103.ccr.corp.intel.com ([169.254.4.213]) with mapi id 14.03.0319.002; Mon, 4 Dec 2017 23:40:23 +0800 From: "Gao, Liming" To: Pete Batard , "edk2-devel@lists.01.org" Thread-Topic: [PATCH 3/6] MdePkg/Library/BaseLib: Enable VS2017/ARM builds Thread-Index: AQHTbQGMtN8BIwvS4EOiCNS/U0EbLqMzUiUA Date: Mon, 4 Dec 2017 15:40:22 +0000 Message-ID: <4A89E2EF3DFEDB4C8BFDE51014F606A14E189CF7@SHSMSX104.ccr.corp.intel.com> References: <20171204131205.11304-1-pete@akeo.ie> <20171204131205.11304-4-pete@akeo.ie> In-Reply-To: <20171204131205.11304-4-pete@akeo.ie> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.0.0.116 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH 3/6] MdePkg/Library/BaseLib: Enable VS2017/ARM builds X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 04 Dec 2017 15:35:56 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Pete: Why override compiler option /GL- here? > -----Original Message----- > From: Pete Batard [mailto:pete@akeo.ie] > Sent: Monday, December 4, 2017 9:12 PM > To: edk2-devel@lists.01.org > Cc: Gao, Liming > Subject: [PATCH 3/6] MdePkg/Library/BaseLib: Enable VS2017/ARM builds >=20 > Most of the RVCT assembly can be reused as is for MSFT except > for CpuBreakpoint.asm, which we need to force to Arm mode. >=20 > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Pete Batard > --- > MdePkg/Library/BaseLib/Arm/CpuBreakpoint.asm | 5 ++++- > MdePkg/Library/BaseLib/BaseLib.inf | 19 ++++++++++++++++--- > 2 files changed, 20 insertions(+), 4 deletions(-) >=20 > diff --git a/MdePkg/Library/BaseLib/Arm/CpuBreakpoint.asm b/MdePkg/Librar= y/BaseLib/Arm/CpuBreakpoint.asm > index 8a8065159bf2..2e508d6f1ad8 100644 > --- a/MdePkg/Library/BaseLib/Arm/CpuBreakpoint.asm > +++ b/MdePkg/Library/BaseLib/Arm/CpuBreakpoint.asm > @@ -16,7 +16,10 @@ >=20 > EXPORT CpuBreakpoint >=20 > - AREA Cpu_Breakpoint, CODE, READONLY > +; Force ARM mode for this section, as MSFT assembler defaults to THUMB > + AREA Cpu_Breakpoint, CODE, READONLY, ARM > + > + ARM >=20 > ;/** > ; Generates a breakpoint on the CPU. > diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/= BaseLib.inf > index 320ac457ea3d..4337a125d516 100644 > --- a/MdePkg/Library/BaseLib/BaseLib.inf > +++ b/MdePkg/Library/BaseLib/BaseLib.inf > @@ -821,8 +821,9 @@ [Sources.EBC] > [Sources.ARM] > Arm/InternalSwitchStack.c > Arm/Unaligned.c > - Math64.c | RVCT > - > + Math64.c | RVCT > + Math64.c | MSFT > + > Arm/SwitchStack.asm | RVCT > Arm/SetJumpLongJump.asm | RVCT > Arm/DisableInterrupts.asm | RVCT > @@ -831,7 +832,16 @@ [Sources.ARM] > Arm/CpuPause.asm | RVCT > Arm/CpuBreakpoint.asm | RVCT > Arm/MemoryFence.asm | RVCT > - > + > + Arm/SwitchStack.asm | MSFT > + Arm/SetJumpLongJump.asm | MSFT > + Arm/DisableInterrupts.asm | MSFT > + Arm/EnableInterrupts.asm | MSFT > + Arm/GetInterruptsState.asm | MSFT > + Arm/CpuPause.asm | MSFT > + Arm/CpuBreakpoint.asm | MSFT > + Arm/MemoryFence.asm | MSFT > + > Arm/Math64.S | GCC > Arm/SwitchStack.S | GCC > Arm/EnableInterrupts.S | GCC > @@ -870,3 +880,6 @@ [Pcd] >=20 > [FeaturePcd] > gEfiMdePkgTokenSpaceGuid.PcdVerifyNodeInList ## CONSUMES > + > +[BuildOptions] > + MSFT:*_*_ARM_CC_FLAGS =3D /GL- > -- > 2.9.3.windows.2