* [Patch 1/7] BaseTools: Disable -Wno-unused-const-variable in XCODE5 RELEASE target
2018-01-10 15:24 [Patch 0/7] EDK2: Enable XCODE5 tool chain with NASM source Liming Gao
@ 2018-01-10 15:24 ` Liming Gao
2018-01-16 8:22 ` Zhu, Yonghong
2018-01-10 15:24 ` [Patch 2/7] BaseTools: Use nasm as the preferred assembly source files for XCODE5 tool Liming Gao
` (6 subsequent siblings)
7 siblings, 1 reply; 18+ messages in thread
From: Liming Gao @ 2018-01-10 15:24 UTC (permalink / raw)
To: edk2-devel; +Cc: Yonghong Zhu, Andrew Fish
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Liming Gao <liming.gao@intel.com>
Cc: Yonghong Zhu <yonghong.zhu@intel.com>
Cc: Andrew Fish <afish@apple.com>
---
BaseTools/Conf/tools_def.template | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/BaseTools/Conf/tools_def.template b/BaseTools/Conf/tools_def.template
index 12278302b3..a961048288 100755
--- a/BaseTools/Conf/tools_def.template
+++ b/BaseTools/Conf/tools_def.template
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
# Portions copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
# Copyright (c) 2015, Hewlett-Packard Development Company, L.P.<BR>
@@ -7551,7 +7551,7 @@ RELEASE_XCODE5_IA32_ASM_FLAGS = -arch i386
DEBUG_XCODE5_IA32_CC_FLAGS = -arch i386 -c -g -Os -Wall -Werror -include AutoGen.h -funsigned-char -fno-stack-protector -fno-builtin -fshort-wchar -fasm-blocks -mdynamic-no-pic -mno-implicit-float -mms-bitfields -msoft-float -Wno-unused-parameter -Wno-missing-braces -Wno-missing-field-initializers -Wno-tautological-compare -Wno-sign-compare -Wno-varargs -ftrap-function=undefined_behavior_has_been_optimized_away_by_clang $(PLATFORM_FLAGS)
-RELEASE_XCODE5_IA32_CC_FLAGS = -arch i386 -c -Os -Wall -Werror -include AutoGen.h -funsigned-char -fno-stack-protector -fno-builtin -fshort-wchar -fasm-blocks -mdynamic-no-pic -mno-implicit-float -mms-bitfields -msoft-float -Wno-unused-parameter -Wno-missing-braces -Wno-missing-field-initializers -Wno-tautological-compare -Wno-sign-compare -Wno-varargs -ftrap-function=undefined_behavior_has_been_optimized_away_by_clang $(PLATFORM_FLAGS)
+RELEASE_XCODE5_IA32_CC_FLAGS = -arch i386 -c -Os -Wall -Werror -include AutoGen.h -funsigned-char -fno-stack-protector -fno-builtin -fshort-wchar -fasm-blocks -mdynamic-no-pic -mno-implicit-float -mms-bitfields -msoft-float -Wno-unused-parameter -Wno-missing-braces -Wno-missing-field-initializers -Wno-tautological-compare -Wno-sign-compare -Wno-varargs -Wno-unused-const-variable -ftrap-function=undefined_behavior_has_been_optimized_away_by_clang $(PLATFORM_FLAGS)
NOOPT_XCODE5_IA32_CC_FLAGS = -arch i386 -c -g -O0 -Wall -Werror -include AutoGen.h -funsigned-char -fno-stack-protector -fno-builtin -fshort-wchar -fasm-blocks -mdynamic-no-pic -mno-implicit-float -mms-bitfields -msoft-float -Wno-unused-parameter -Wno-missing-braces -Wno-missing-field-initializers -Wno-tautological-compare -Wno-sign-compare -Wno-varargs -ftrap-function=undefined_behavior_has_been_optimized_away_by_clang $(PLATFORM_FLAGS)
##################
@@ -7571,7 +7571,7 @@ RELEASE_XCODE5_X64_ASM_FLAGS = -arch x86_64
DEBUG_XCODE5_X64_CC_FLAGS = -target x86_64-pc-win32-macho -c -g -Os -Wall -Werror -Wextra -include AutoGen.h -funsigned-char -fno-ms-extensions -fno-stack-protector -fno-builtin -fshort-wchar -mno-implicit-float -mms-bitfields -Wno-unused-parameter -Wno-missing-braces -Wno-missing-field-initializers -Wno-tautological-compare -Wno-sign-compare -Wno-varargs -ftrap-function=undefined_behavior_has_been_optimized_away_by_clang -D NO_MSABI_VA_FUNCS $(PLATFORM_FLAGS)
NOOPT_XCODE5_X64_CC_FLAGS = -target x86_64-pc-win32-macho -c -g -O0 -Wall -Werror -Wextra -include AutoGen.h -funsigned-char -fno-ms-extensions -fno-stack-protector -fno-builtin -fshort-wchar -mno-implicit-float -mms-bitfields -Wno-unused-parameter -Wno-missing-braces -Wno-missing-field-initializers -Wno-tautological-compare -Wno-sign-compare -Wno-varargs -ftrap-function=undefined_behavior_has_been_optimized_away_by_clang -D NO_MSABI_VA_FUNCS $(PLATFORM_FLAGS)
-RELEASE_XCODE5_X64_CC_FLAGS = -target x86_64-pc-win32-macho -c -Os -Wall -Werror -Wextra -include AutoGen.h -funsigned-char -fno-ms-extensions -fno-stack-protector -fno-builtin -fshort-wchar -mno-implicit-float -mms-bitfields -Wno-unused-parameter -Wno-missing-braces -Wno-missing-field-initializers -Wno-tautological-compare -Wno-sign-compare -Wno-varargs -ftrap-function=undefined_behavior_has_been_optimized_away_by_clang -D NO_MSABI_VA_FUNCS $(PLATFORM_FLAGS)
+RELEASE_XCODE5_X64_CC_FLAGS = -target x86_64-pc-win32-macho -c -Os -Wall -Werror -Wextra -include AutoGen.h -funsigned-char -fno-ms-extensions -fno-stack-protector -fno-builtin -fshort-wchar -mno-implicit-float -mms-bitfields -Wno-unused-parameter -Wno-missing-braces -Wno-missing-field-initializers -Wno-tautological-compare -Wno-sign-compare -Wno-varargs -Wno-unused-const-variable -ftrap-function=undefined_behavior_has_been_optimized_away_by_clang -D NO_MSABI_VA_FUNCS $(PLATFORM_FLAGS)
####################################################################################
#
--
2.11.0.windows.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [Patch 1/7] BaseTools: Disable -Wno-unused-const-variable in XCODE5 RELEASE target
2018-01-10 15:24 ` [Patch 1/7] BaseTools: Disable -Wno-unused-const-variable in XCODE5 RELEASE target Liming Gao
@ 2018-01-16 8:22 ` Zhu, Yonghong
0 siblings, 0 replies; 18+ messages in thread
From: Zhu, Yonghong @ 2018-01-16 8:22 UTC (permalink / raw)
To: Gao, Liming, edk2-devel@lists.01.org; +Cc: Andrew Fish, Zhu, Yonghong
Reviewed-by: Yonghong Zhu <yonghong.zhu@intel.com>
Best Regards,
Zhu Yonghong
-----Original Message-----
From: Gao, Liming
Sent: Wednesday, January 10, 2018 11:24 PM
To: edk2-devel@lists.01.org
Cc: Zhu, Yonghong <yonghong.zhu@intel.com>; Andrew Fish <afish@apple.com>
Subject: [Patch 1/7] BaseTools: Disable -Wno-unused-const-variable in XCODE5 RELEASE target
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Liming Gao <liming.gao@intel.com>
Cc: Yonghong Zhu <yonghong.zhu@intel.com>
Cc: Andrew Fish <afish@apple.com>
---
BaseTools/Conf/tools_def.template | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/BaseTools/Conf/tools_def.template b/BaseTools/Conf/tools_def.template
index 12278302b3..a961048288 100755
--- a/BaseTools/Conf/tools_def.template
+++ b/BaseTools/Conf/tools_def.template
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2006 - 2018, Intel Corporation. All rights
+reserved.<BR>
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> # Portions copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR> # Copyright (c) 2015, Hewlett-Packard Development Company, L.P.<BR> @@ -7551,7 +7551,7 @@ RELEASE_XCODE5_IA32_ASM_FLAGS = -arch i386
DEBUG_XCODE5_IA32_CC_FLAGS = -arch i386 -c -g -Os -Wall -Werror -include AutoGen.h -funsigned-char -fno-stack-protector -fno-builtin -fshort-wchar -fasm-blocks -mdynamic-no-pic -mno-implicit-float -mms-bitfields -msoft-float -Wno-unused-parameter -Wno-missing-braces -Wno-missing-field-initializers -Wno-tautological-compare -Wno-sign-compare -Wno-varargs -ftrap-function=undefined_behavior_has_been_optimized_away_by_clang $(PLATFORM_FLAGS)
-RELEASE_XCODE5_IA32_CC_FLAGS = -arch i386 -c -Os -Wall -Werror -include AutoGen.h -funsigned-char -fno-stack-protector -fno-builtin -fshort-wchar -fasm-blocks -mdynamic-no-pic -mno-implicit-float -mms-bitfields -msoft-float -Wno-unused-parameter -Wno-missing-braces -Wno-missing-field-initializers -Wno-tautological-compare -Wno-sign-compare -Wno-varargs -ftrap-function=undefined_behavior_has_been_optimized_away_by_clang $(PLATFORM_FLAGS)
+RELEASE_XCODE5_IA32_CC_FLAGS = -arch i386 -c -Os -Wall -Werror -include AutoGen.h -funsigned-char -fno-stack-protector -fno-builtin -fshort-wchar -fasm-blocks -mdynamic-no-pic -mno-implicit-float -mms-bitfields -msoft-float -Wno-unused-parameter -Wno-missing-braces -Wno-missing-field-initializers -Wno-tautological-compare -Wno-sign-compare -Wno-varargs -Wno-unused-const-variable -ftrap-function=undefined_behavior_has_been_optimized_away_by_clang $(PLATFORM_FLAGS)
NOOPT_XCODE5_IA32_CC_FLAGS = -arch i386 -c -g -O0 -Wall -Werror -include AutoGen.h -funsigned-char -fno-stack-protector -fno-builtin -fshort-wchar -fasm-blocks -mdynamic-no-pic -mno-implicit-float -mms-bitfields -msoft-float -Wno-unused-parameter -Wno-missing-braces -Wno-missing-field-initializers -Wno-tautological-compare -Wno-sign-compare -Wno-varargs -ftrap-function=undefined_behavior_has_been_optimized_away_by_clang $(PLATFORM_FLAGS)
##################
@@ -7571,7 +7571,7 @@ RELEASE_XCODE5_X64_ASM_FLAGS = -arch x86_64
DEBUG_XCODE5_X64_CC_FLAGS = -target x86_64-pc-win32-macho -c -g -Os -Wall -Werror -Wextra -include AutoGen.h -funsigned-char -fno-ms-extensions -fno-stack-protector -fno-builtin -fshort-wchar -mno-implicit-float -mms-bitfields -Wno-unused-parameter -Wno-missing-braces -Wno-missing-field-initializers -Wno-tautological-compare -Wno-sign-compare -Wno-varargs -ftrap-function=undefined_behavior_has_been_optimized_away_by_clang -D NO_MSABI_VA_FUNCS $(PLATFORM_FLAGS)
NOOPT_XCODE5_X64_CC_FLAGS = -target x86_64-pc-win32-macho -c -g -O0 -Wall -Werror -Wextra -include AutoGen.h -funsigned-char -fno-ms-extensions -fno-stack-protector -fno-builtin -fshort-wchar -mno-implicit-float -mms-bitfields -Wno-unused-parameter -Wno-missing-braces -Wno-missing-field-initializers -Wno-tautological-compare -Wno-sign-compare -Wno-varargs -ftrap-function=undefined_behavior_has_been_optimized_away_by_clang -D NO_MSABI_VA_FUNCS $(PLATFORM_FLAGS)
-RELEASE_XCODE5_X64_CC_FLAGS = -target x86_64-pc-win32-macho -c -Os -Wall -Werror -Wextra -include AutoGen.h -funsigned-char -fno-ms-extensions -fno-stack-protector -fno-builtin -fshort-wchar -mno-implicit-float -mms-bitfields -Wno-unused-parameter -Wno-missing-braces -Wno-missing-field-initializers -Wno-tautological-compare -Wno-sign-compare -Wno-varargs -ftrap-function=undefined_behavior_has_been_optimized_away_by_clang -D NO_MSABI_VA_FUNCS $(PLATFORM_FLAGS)
+RELEASE_XCODE5_X64_CC_FLAGS = -target x86_64-pc-win32-macho -c -Os -Wall -Werror -Wextra -include AutoGen.h -funsigned-char -fno-ms-extensions -fno-stack-protector -fno-builtin -fshort-wchar -mno-implicit-float -mms-bitfields -Wno-unused-parameter -Wno-missing-braces -Wno-missing-field-initializers -Wno-tautological-compare -Wno-sign-compare -Wno-varargs -Wno-unused-const-variable -ftrap-function=undefined_behavior_has_been_optimized_away_by_clang -D NO_MSABI_VA_FUNCS $(PLATFORM_FLAGS)
####################################################################################
#
--
2.11.0.windows.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Patch 2/7] BaseTools: Use nasm as the preferred assembly source files for XCODE5 tool
2018-01-10 15:24 [Patch 0/7] EDK2: Enable XCODE5 tool chain with NASM source Liming Gao
2018-01-10 15:24 ` [Patch 1/7] BaseTools: Disable -Wno-unused-const-variable in XCODE5 RELEASE target Liming Gao
@ 2018-01-10 15:24 ` Liming Gao
2018-01-16 8:24 ` Zhu, Yonghong
2018-01-10 15:24 ` [Patch 3/7] MdeModulePkg: Update DebugSupportDxe to pass XCODE5 build Liming Gao
` (5 subsequent siblings)
7 siblings, 1 reply; 18+ messages in thread
From: Liming Gao @ 2018-01-10 15:24 UTC (permalink / raw)
To: edk2-devel; +Cc: Andrew Fish, Yonghong Zhu
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Liming Gao <liming.gao@intel.com>
Cc: Andrew Fish <afish@apple.com>
Cc: Yonghong Zhu <yonghong.zhu@intel.com>
---
BaseTools/Conf/tools_def.template | 1 -
1 file changed, 1 deletion(-)
diff --git a/BaseTools/Conf/tools_def.template b/BaseTools/Conf/tools_def.template
index a961048288..d8fde02ea3 100755
--- a/BaseTools/Conf/tools_def.template
+++ b/BaseTools/Conf/tools_def.template
@@ -7500,7 +7500,6 @@ NOOPT_MYTOOLS_IPF_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /LTCG /DLL /OPT
*_XCODE5_*_*_FAMILY = GCC
*_XCODE5_*_*_BUILDRULEFAMILY = XCODE
-*_XCODE5_*_*_BUILDRULEORDER = S s nasm
#
# use xcode-select to change Xcode version of command line tools
--
2.11.0.windows.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [Patch 2/7] BaseTools: Use nasm as the preferred assembly source files for XCODE5 tool
2018-01-10 15:24 ` [Patch 2/7] BaseTools: Use nasm as the preferred assembly source files for XCODE5 tool Liming Gao
@ 2018-01-16 8:24 ` Zhu, Yonghong
0 siblings, 0 replies; 18+ messages in thread
From: Zhu, Yonghong @ 2018-01-16 8:24 UTC (permalink / raw)
To: Gao, Liming, edk2-devel@lists.01.org; +Cc: Andrew Fish, Zhu, Yonghong
Reviewed-by: Yonghong Zhu <yonghong.zhu@intel.com>
Best Regards,
Zhu Yonghong
-----Original Message-----
From: Gao, Liming
Sent: Wednesday, January 10, 2018 11:24 PM
To: edk2-devel@lists.01.org
Cc: Andrew Fish <afish@apple.com>; Zhu, Yonghong <yonghong.zhu@intel.com>
Subject: [Patch 2/7] BaseTools: Use nasm as the preferred assembly source files for XCODE5 tool
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Liming Gao <liming.gao@intel.com>
Cc: Andrew Fish <afish@apple.com>
Cc: Yonghong Zhu <yonghong.zhu@intel.com>
---
BaseTools/Conf/tools_def.template | 1 -
1 file changed, 1 deletion(-)
diff --git a/BaseTools/Conf/tools_def.template b/BaseTools/Conf/tools_def.template
index a961048288..d8fde02ea3 100755
--- a/BaseTools/Conf/tools_def.template
+++ b/BaseTools/Conf/tools_def.template
@@ -7500,7 +7500,6 @@ NOOPT_MYTOOLS_IPF_DLINK_FLAGS = /NOLOGO /NODEFAULTLIB /LTCG /DLL /OPT
*_XCODE5_*_*_FAMILY = GCC
*_XCODE5_*_*_BUILDRULEFAMILY = XCODE
-*_XCODE5_*_*_BUILDRULEORDER = S s nasm
#
# use xcode-select to change Xcode version of command line tools
--
2.11.0.windows.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Patch 3/7] MdeModulePkg: Update DebugSupportDxe to pass XCODE5 build
2018-01-10 15:24 [Patch 0/7] EDK2: Enable XCODE5 tool chain with NASM source Liming Gao
2018-01-10 15:24 ` [Patch 1/7] BaseTools: Disable -Wno-unused-const-variable in XCODE5 RELEASE target Liming Gao
2018-01-10 15:24 ` [Patch 2/7] BaseTools: Use nasm as the preferred assembly source files for XCODE5 tool Liming Gao
@ 2018-01-10 15:24 ` Liming Gao
2018-01-11 2:31 ` Zeng, Star
2018-01-10 15:24 ` [Patch 4/7] UefiCpuPkg: Update CpuExceptionHandlerLib pass XCODE5 tool chain Liming Gao
` (4 subsequent siblings)
7 siblings, 1 reply; 18+ messages in thread
From: Liming Gao @ 2018-01-10 15:24 UTC (permalink / raw)
To: edk2-devel; +Cc: Andrew Fish, Star Zeng
XCODE5 doesn't support absolute addressing in the assembly code.
This change uses lea instruction to get the address.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Liming Gao <liming.gao@intel.com>
Cc: Andrew Fish <afish@apple.com>
Cc: Star Zeng <star.zeng@intel.com>
---
MdeModulePkg/Universal/DebugSupportDxe/X64/AsmFuncs.nasm | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/MdeModulePkg/Universal/DebugSupportDxe/X64/AsmFuncs.nasm b/MdeModulePkg/Universal/DebugSupportDxe/X64/AsmFuncs.nasm
index 134842a68a..31d8b0a717 100644
--- a/MdeModulePkg/Universal/DebugSupportDxe/X64/AsmFuncs.nasm
+++ b/MdeModulePkg/Universal/DebugSupportDxe/X64/AsmFuncs.nasm
@@ -1,7 +1,7 @@
;/** @file
; Low level x64 routines used by the debug support driver.
;
-; Copyright (c) 2007 - 2016, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
; This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
@@ -226,7 +226,7 @@ ASM_PFX(CommonIdtEntry):
pop rax
add rsp, 8 ; pop vector number
mov [AppRsp], rsp ; save stack top
- mov rsp, DebugStackBegin ; switch to debugger stack
+ lea rsp, [DebugStackBegin] ; switch to debugger stack
sub rsp, 8 ; leave space for vector number
;; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax;
@@ -529,7 +529,7 @@ Chain:
push rbx
mov rax, cs
push rax
- mov rax, PhonyIretq
+ lea rax, [PhonyIretq]
push rax
iretq
PhonyIretq:
--
2.11.0.windows.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [Patch 3/7] MdeModulePkg: Update DebugSupportDxe to pass XCODE5 build
2018-01-10 15:24 ` [Patch 3/7] MdeModulePkg: Update DebugSupportDxe to pass XCODE5 build Liming Gao
@ 2018-01-11 2:31 ` Zeng, Star
0 siblings, 0 replies; 18+ messages in thread
From: Zeng, Star @ 2018-01-11 2:31 UTC (permalink / raw)
To: Gao, Liming, edk2-devel@lists.01.org; +Cc: Andrew Fish, Zeng, Star
Reviewed-by: Star Zeng <star.zeng@intel.com>
Thanks,
Star
-----Original Message-----
From: Gao, Liming
Sent: Wednesday, January 10, 2018 11:24 PM
To: edk2-devel@lists.01.org
Cc: Andrew Fish <afish@apple.com>; Zeng, Star <star.zeng@intel.com>
Subject: [Patch 3/7] MdeModulePkg: Update DebugSupportDxe to pass XCODE5 build
XCODE5 doesn't support absolute addressing in the assembly code.
This change uses lea instruction to get the address.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Liming Gao <liming.gao@intel.com>
Cc: Andrew Fish <afish@apple.com>
Cc: Star Zeng <star.zeng@intel.com>
---
MdeModulePkg/Universal/DebugSupportDxe/X64/AsmFuncs.nasm | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/MdeModulePkg/Universal/DebugSupportDxe/X64/AsmFuncs.nasm b/MdeModulePkg/Universal/DebugSupportDxe/X64/AsmFuncs.nasm
index 134842a68a..31d8b0a717 100644
--- a/MdeModulePkg/Universal/DebugSupportDxe/X64/AsmFuncs.nasm
+++ b/MdeModulePkg/Universal/DebugSupportDxe/X64/AsmFuncs.nasm
@@ -1,7 +1,7 @@
;/** @file
; Low level x64 routines used by the debug support driver.
;
-; Copyright (c) 2007 - 2016, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2007 - 2018, Intel Corporation. All rights
+reserved.<BR>
; This program and the accompanying materials ; are licensed and made available under the terms and conditions of the BSD License ; which accompanies this distribution. The full text of the license may be found at @@ -226,7 +226,7 @@ ASM_PFX(CommonIdtEntry):
pop rax
add rsp, 8 ; pop vector number
mov [AppRsp], rsp ; save stack top
- mov rsp, DebugStackBegin ; switch to debugger stack
+ lea rsp, [DebugStackBegin] ; switch to debugger stack
sub rsp, 8 ; leave space for vector number
;; UINT64 Rdi, Rsi, Rbp, Rsp, Rbx, Rdx, Rcx, Rax; @@ -529,7 +529,7 @@ Chain:
push rbx
mov rax, cs
push rax
- mov rax, PhonyIretq
+ lea rax, [PhonyIretq]
push rax
iretq
PhonyIretq:
--
2.11.0.windows.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Patch 4/7] UefiCpuPkg: Update CpuExceptionHandlerLib pass XCODE5 tool chain
2018-01-10 15:24 [Patch 0/7] EDK2: Enable XCODE5 tool chain with NASM source Liming Gao
` (2 preceding siblings ...)
2018-01-10 15:24 ` [Patch 3/7] MdeModulePkg: Update DebugSupportDxe to pass XCODE5 build Liming Gao
@ 2018-01-10 15:24 ` Liming Gao
2018-01-10 19:21 ` Kinney, Michael D
2018-01-10 15:24 ` [Patch 5/7] UefiCpuPkg: Update SmmCpuFeatureLib " Liming Gao
` (3 subsequent siblings)
7 siblings, 1 reply; 18+ messages in thread
From: Liming Gao @ 2018-01-10 15:24 UTC (permalink / raw)
To: edk2-devel
Cc: Andrew Fish, Jiewen Yao, Eric Dong, Laszlo Ersek, Michael Kinney
Use the dummy address as jmp destination, and add the logic to fix up
the address to the absolute address at boot time.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Liming Gao <liming.gao@intel.com>
Cc: Andrew Fish <afish@apple.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
---
.../X64/ExceptionHandlerAsm.nasm | 29 ++++++++++++++++------
1 file changed, 22 insertions(+), 7 deletions(-)
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm
index ba8993d84b..a5fde0a875 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm
@@ -1,5 +1,5 @@
;------------------------------------------------------------------------------ ;
-; Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.<BR>
; This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
@@ -40,7 +40,8 @@ AsmIdtVectorBegin:
db 0x6a ; push #VectorNum
db ($ - AsmIdtVectorBegin) / ((AsmIdtVectorEnd - AsmIdtVectorBegin) / 32) ; VectorNum
push rax
- mov rax, ASM_PFX(CommonInterruptEntry)
+ db 0x48, 0xB8
+ dq 0 ; mov rax, ASM_PFX(CommonInterruptEntry)
jmp rax
%endrep
AsmIdtVectorEnd:
@@ -50,7 +51,9 @@ HookAfterStubHeaderBegin:
@VectorNum:
db 0 ; 0 will be fixed
push rax
- mov rax, HookAfterStubHeaderEnd
+ db 0x48, 0xB8
+JmpAbsoluteAddress:
+ dq 0 ; mov rax, HookAfterStubHeaderEnd
jmp rax
HookAfterStubHeaderEnd:
mov rax, rsp
@@ -260,8 +263,7 @@ HasErrorCode:
; and make sure RSP is 16-byte aligned
;
sub rsp, 4 * 8 + 8
- mov rax, ASM_PFX(CommonExceptionHandler)
- call rax
+ call ASM_PFX(CommonExceptionHandler)
add rsp, 4 * 8 + 8
cli
@@ -369,11 +371,24 @@ DoIret:
; comments here for definition of address map
global ASM_PFX(AsmGetTemplateAddressMap)
ASM_PFX(AsmGetTemplateAddressMap):
- mov rax, AsmIdtVectorBegin
+ lea rax, [AsmIdtVectorBegin]
mov qword [rcx], rax
mov qword [rcx + 0x8], (AsmIdtVectorEnd - AsmIdtVectorBegin) / 32
- mov rax, HookAfterStubHeaderBegin
+ lea rax, [HookAfterStubHeaderBegin]
mov qword [rcx + 0x10], rax
+
+; Fix up CommonInterruptEntry address
+ lea rax, [ASM_PFX(CommonInterruptEntry)]
+ lea rcx, [AsmIdtVectorBegin]
+%rep 32
+ mov qword [rcx + (JmpAbsoluteAddress - HookAfterStubHeaderBegin)], rax
+ add rcx, (AsmIdtVectorEnd - AsmIdtVectorBegin) / 32
+%endrep
+; Fix up HookAfterStubHeaderEnd
+ lea rax, [HookAfterStubHeaderEnd]
+ lea rcx, [JmpAbsoluteAddress]
+ mov qword [rcx], rax
+
ret
;-------------------------------------------------------------------------------------
--
2.11.0.windows.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [Patch 4/7] UefiCpuPkg: Update CpuExceptionHandlerLib pass XCODE5 tool chain
2018-01-10 15:24 ` [Patch 4/7] UefiCpuPkg: Update CpuExceptionHandlerLib pass XCODE5 tool chain Liming Gao
@ 2018-01-10 19:21 ` Kinney, Michael D
2018-01-10 21:57 ` Kinney, Michael D
0 siblings, 1 reply; 18+ messages in thread
From: Kinney, Michael D @ 2018-01-10 19:21 UTC (permalink / raw)
To: Gao, Liming, edk2-devel@lists.01.org, Kinney, Michael D
Cc: Andrew Fish, Yao, Jiewen, Dong, Eric, Laszlo Ersek
Liming,
Can we use NASM syntax for instructions instead of db bytes?
If you put the label for the fixup after the instruction, you
can patch by subtracting the size of the patch value from the
label.
For example, instead of:
> + db 0x48, 0xB8
> +JmpAbsoluteAddress:
> + dq 0 ; mov rax, HookAfterStubHeaderEnd
Use:
movq rax, 0
JmpAbsoluteAddress:
And in the patch loop:
mov qword [rcx + (JmpAbsoluteAddress - 8 - HookAfterStubHeaderBegin)], rax
If this works, then please use this technique to remove
use of db for instructions throughout this series.
Mike
> -----Original Message-----
> From: Gao, Liming
> Sent: Wednesday, January 10, 2018 7:24 AM
> To: edk2-devel@lists.01.org
> Cc: Andrew Fish <afish@apple.com>; Yao, Jiewen
> <jiewen.yao@intel.com>; Dong, Eric <eric.dong@intel.com>;
> Laszlo Ersek <lersek@redhat.com>; Kinney, Michael D
> <michael.d.kinney@intel.com>
> Subject: [Patch 4/7] UefiCpuPkg: Update
> CpuExceptionHandlerLib pass XCODE5 tool chain
>
> Use the dummy address as jmp destination, and add the
> logic to fix up
> the address to the absolute address at boot time.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Liming Gao <liming.gao@intel.com>
> Cc: Andrew Fish <afish@apple.com>
> Cc: Jiewen Yao <jiewen.yao@intel.com>
> Cc: Eric Dong <eric.dong@intel.com>
> Cc: Laszlo Ersek <lersek@redhat.com>
> Cc: Michael Kinney <michael.d.kinney@intel.com>
> ---
> .../X64/ExceptionHandlerAsm.nasm | 29
> ++++++++++++++++------
> 1 file changed, 22 insertions(+), 7 deletions(-)
>
> diff --git
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Exception
> HandlerAsm.nasm
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Exception
> HandlerAsm.nasm
> index ba8993d84b..a5fde0a875 100644
> ---
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Exception
> HandlerAsm.nasm
> +++
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Exception
> HandlerAsm.nasm
> @@ -1,5 +1,5 @@
> ;-------------------------------------------------------
> ----------------------- ;
> -; Copyright (c) 2012 - 2014, Intel Corporation. All
> rights reserved.<BR>
> +; Copyright (c) 2012 - 2018, Intel Corporation. All
> rights reserved.<BR>
> ; This program and the accompanying materials
> ; are licensed and made available under the terms and
> conditions of the BSD License
> ; which accompanies this distribution. The full text of
> the license may be found at
> @@ -40,7 +40,8 @@ AsmIdtVectorBegin:
> db 0x6a ; push #VectorNum
> db ($ - AsmIdtVectorBegin) / ((AsmIdtVectorEnd
> - AsmIdtVectorBegin) / 32) ; VectorNum
> push rax
> - mov rax, ASM_PFX(CommonInterruptEntry)
> + db 0x48, 0xB8
> + dq 0 ; mov rax,
> ASM_PFX(CommonInterruptEntry)
> jmp rax
> %endrep
> AsmIdtVectorEnd:
> @@ -50,7 +51,9 @@ HookAfterStubHeaderBegin:
> @VectorNum:
> db 0 ; 0 will be fixed
> push rax
> - mov rax, HookAfterStubHeaderEnd
> + db 0x48, 0xB8
> +JmpAbsoluteAddress:
> + dq 0 ; mov rax, HookAfterStubHeaderEnd
> jmp rax
> HookAfterStubHeaderEnd:
> mov rax, rsp
> @@ -260,8 +263,7 @@ HasErrorCode:
> ; and make sure RSP is 16-byte aligned
> ;
> sub rsp, 4 * 8 + 8
> - mov rax, ASM_PFX(CommonExceptionHandler)
> - call rax
> + call ASM_PFX(CommonExceptionHandler)
> add rsp, 4 * 8 + 8
>
> cli
> @@ -369,11 +371,24 @@ DoIret:
> ; comments here for definition of address map
> global ASM_PFX(AsmGetTemplateAddressMap)
> ASM_PFX(AsmGetTemplateAddressMap):
> - mov rax, AsmIdtVectorBegin
> + lea rax, [AsmIdtVectorBegin]
> mov qword [rcx], rax
> mov qword [rcx + 0x8], (AsmIdtVectorEnd -
> AsmIdtVectorBegin) / 32
> - mov rax, HookAfterStubHeaderBegin
> + lea rax, [HookAfterStubHeaderBegin]
> mov qword [rcx + 0x10], rax
> +
> +; Fix up CommonInterruptEntry address
> + lea rax, [ASM_PFX(CommonInterruptEntry)]
> + lea rcx, [AsmIdtVectorBegin]
> +%rep 32
> + mov qword [rcx + (JmpAbsoluteAddress -
> HookAfterStubHeaderBegin)], rax
> + add rcx, (AsmIdtVectorEnd - AsmIdtVectorBegin) /
> 32
> +%endrep
> +; Fix up HookAfterStubHeaderEnd
> + lea rax, [HookAfterStubHeaderEnd]
> + lea rcx, [JmpAbsoluteAddress]
> + mov qword [rcx], rax
> +
> ret
>
> ;-------------------------------------------------------
> ------------------------------
> --
> 2.11.0.windows.1
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [Patch 4/7] UefiCpuPkg: Update CpuExceptionHandlerLib pass XCODE5 tool chain
2018-01-10 19:21 ` Kinney, Michael D
@ 2018-01-10 21:57 ` Kinney, Michael D
2018-01-11 2:21 ` Gao, Liming
0 siblings, 1 reply; 18+ messages in thread
From: Kinney, Michael D @ 2018-01-10 21:57 UTC (permalink / raw)
To: Gao, Liming, edk2-devel@lists.01.org, Kinney, Michael D
Cc: Andrew Fish, Yao, Jiewen, Dong, Eric, Laszlo Ersek
Liming,
Here is a previous patch email series that demonstrates
this technique.
https://lists.01.org/pipermail/edk2-devel/2017-September/015109.html
https://github.com/tianocore/edk2/commit/4c34a8ea191155f438901e635bd87810072b19a4#diff-5d3b0f5982124c722c30f6d0e6b8711d
Thanks,
Mike
> -----Original Message-----
> From: Kinney, Michael D
> Sent: Wednesday, January 10, 2018 11:22 AM
> To: Gao, Liming <liming.gao@intel.com>; edk2-
> devel@lists.01.org; Kinney, Michael D
> <michael.d.kinney@intel.com>
> Cc: Andrew Fish <afish@apple.com>; Yao, Jiewen
> <jiewen.yao@intel.com>; Dong, Eric <eric.dong@intel.com>;
> Laszlo Ersek <lersek@redhat.com>
> Subject: RE: [Patch 4/7] UefiCpuPkg: Update
> CpuExceptionHandlerLib pass XCODE5 tool chain
>
> Liming,
>
> Can we use NASM syntax for instructions instead of db
> bytes?
>
> If you put the label for the fixup after the instruction,
> you
> can patch by subtracting the size of the patch value from
> the
> label.
>
> For example, instead of:
>
> > + db 0x48, 0xB8
> > +JmpAbsoluteAddress:
> > + dq 0 ; mov rax,
> HookAfterStubHeaderEnd
>
> Use:
>
> movq rax, 0
> JmpAbsoluteAddress:
>
> And in the patch loop:
>
> mov qword [rcx + (JmpAbsoluteAddress - 8 -
> HookAfterStubHeaderBegin)], rax
>
>
> If this works, then please use this technique to remove
> use of db for instructions throughout this series.
>
> Mike
>
> > -----Original Message-----
> > From: Gao, Liming
> > Sent: Wednesday, January 10, 2018 7:24 AM
> > To: edk2-devel@lists.01.org
> > Cc: Andrew Fish <afish@apple.com>; Yao, Jiewen
> > <jiewen.yao@intel.com>; Dong, Eric
> <eric.dong@intel.com>;
> > Laszlo Ersek <lersek@redhat.com>; Kinney, Michael D
> > <michael.d.kinney@intel.com>
> > Subject: [Patch 4/7] UefiCpuPkg: Update
> > CpuExceptionHandlerLib pass XCODE5 tool chain
> >
> > Use the dummy address as jmp destination, and add the
> > logic to fix up
> > the address to the absolute address at boot time.
> >
> > Contributed-under: TianoCore Contribution Agreement 1.1
> > Signed-off-by: Liming Gao <liming.gao@intel.com>
> > Cc: Andrew Fish <afish@apple.com>
> > Cc: Jiewen Yao <jiewen.yao@intel.com>
> > Cc: Eric Dong <eric.dong@intel.com>
> > Cc: Laszlo Ersek <lersek@redhat.com>
> > Cc: Michael Kinney <michael.d.kinney@intel.com>
> > ---
> > .../X64/ExceptionHandlerAsm.nasm |
> 29
> > ++++++++++++++++------
> > 1 file changed, 22 insertions(+), 7 deletions(-)
> >
> > diff --git
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Exception
> > HandlerAsm.nasm
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Exception
> > HandlerAsm.nasm
> > index ba8993d84b..a5fde0a875 100644
> > ---
> >
> a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Exception
> > HandlerAsm.nasm
> > +++
> >
> b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Exception
> > HandlerAsm.nasm
> > @@ -1,5 +1,5 @@
> > ;-----------------------------------------------------
> --
> > ----------------------- ;
> > -; Copyright (c) 2012 - 2014, Intel Corporation. All
> > rights reserved.<BR>
> > +; Copyright (c) 2012 - 2018, Intel Corporation. All
> > rights reserved.<BR>
> > ; This program and the accompanying materials
> > ; are licensed and made available under the terms and
> > conditions of the BSD License
> > ; which accompanies this distribution. The full text
> of
> > the license may be found at
> > @@ -40,7 +40,8 @@ AsmIdtVectorBegin:
> > db 0x6a ; push #VectorNum
> > db ($ - AsmIdtVectorBegin) /
> ((AsmIdtVectorEnd
> > - AsmIdtVectorBegin) / 32) ; VectorNum
> > push rax
> > - mov rax, ASM_PFX(CommonInterruptEntry)
> > + db 0x48, 0xB8
> > + dq 0 ; mov rax,
> > ASM_PFX(CommonInterruptEntry)
> > jmp rax
> > %endrep
> > AsmIdtVectorEnd:
> > @@ -50,7 +51,9 @@ HookAfterStubHeaderBegin:
> > @VectorNum:
> > db 0 ; 0 will be fixed
> > push rax
> > - mov rax, HookAfterStubHeaderEnd
> > + db 0x48, 0xB8
> > +JmpAbsoluteAddress:
> > + dq 0 ; mov rax,
> HookAfterStubHeaderEnd
> > jmp rax
> > HookAfterStubHeaderEnd:
> > mov rax, rsp
> > @@ -260,8 +263,7 @@ HasErrorCode:
> > ; and make sure RSP is 16-byte aligned
> > ;
> > sub rsp, 4 * 8 + 8
> > - mov rax, ASM_PFX(CommonExceptionHandler)
> > - call rax
> > + call ASM_PFX(CommonExceptionHandler)
> > add rsp, 4 * 8 + 8
> >
> > cli
> > @@ -369,11 +371,24 @@ DoIret:
> > ; comments here for definition of address map
> > global ASM_PFX(AsmGetTemplateAddressMap)
> > ASM_PFX(AsmGetTemplateAddressMap):
> > - mov rax, AsmIdtVectorBegin
> > + lea rax, [AsmIdtVectorBegin]
> > mov qword [rcx], rax
> > mov qword [rcx + 0x8], (AsmIdtVectorEnd -
> > AsmIdtVectorBegin) / 32
> > - mov rax, HookAfterStubHeaderBegin
> > + lea rax, [HookAfterStubHeaderBegin]
> > mov qword [rcx + 0x10], rax
> > +
> > +; Fix up CommonInterruptEntry address
> > + lea rax, [ASM_PFX(CommonInterruptEntry)]
> > + lea rcx, [AsmIdtVectorBegin]
> > +%rep 32
> > + mov qword [rcx + (JmpAbsoluteAddress -
> > HookAfterStubHeaderBegin)], rax
> > + add rcx, (AsmIdtVectorEnd - AsmIdtVectorBegin)
> /
> > 32
> > +%endrep
> > +; Fix up HookAfterStubHeaderEnd
> > + lea rax, [HookAfterStubHeaderEnd]
> > + lea rcx, [JmpAbsoluteAddress]
> > + mov qword [rcx], rax
> > +
> > ret
> >
> > ;-----------------------------------------------------
> --
> > ------------------------------
> > --
> > 2.11.0.windows.1
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Patch 4/7] UefiCpuPkg: Update CpuExceptionHandlerLib pass XCODE5 tool chain
2018-01-10 21:57 ` Kinney, Michael D
@ 2018-01-11 2:21 ` Gao, Liming
0 siblings, 0 replies; 18+ messages in thread
From: Gao, Liming @ 2018-01-11 2:21 UTC (permalink / raw)
To: Kinney, Michael D, edk2-devel@lists.01.org
Cc: Andrew Fish, Yao, Jiewen, Dong, Eric, Laszlo Ersek
Mike:
Thanks for your comments. The style "mov rax, strict qword 0" works. I will use it.
> -----Original Message-----
> From: Kinney, Michael D
> Sent: Thursday, January 11, 2018 5:58 AM
> To: Gao, Liming <liming.gao@intel.com>; edk2-devel@lists.01.org; Kinney, Michael D <michael.d.kinney@intel.com>
> Cc: Andrew Fish <afish@apple.com>; Yao, Jiewen <jiewen.yao@intel.com>; Dong, Eric <eric.dong@intel.com>; Laszlo Ersek
> <lersek@redhat.com>
> Subject: RE: [Patch 4/7] UefiCpuPkg: Update CpuExceptionHandlerLib pass XCODE5 tool chain
>
> Liming,
>
> Here is a previous patch email series that demonstrates
> this technique.
>
> https://lists.01.org/pipermail/edk2-devel/2017-September/015109.html
>
> https://github.com/tianocore/edk2/commit/4c34a8ea191155f438901e635bd87810072b19a4#diff-5d3b0f5982124c722c30f6d0e6b87
> 11d
>
> Thanks,
>
> Mike
>
> > -----Original Message-----
> > From: Kinney, Michael D
> > Sent: Wednesday, January 10, 2018 11:22 AM
> > To: Gao, Liming <liming.gao@intel.com>; edk2-
> > devel@lists.01.org; Kinney, Michael D
> > <michael.d.kinney@intel.com>
> > Cc: Andrew Fish <afish@apple.com>; Yao, Jiewen
> > <jiewen.yao@intel.com>; Dong, Eric <eric.dong@intel.com>;
> > Laszlo Ersek <lersek@redhat.com>
> > Subject: RE: [Patch 4/7] UefiCpuPkg: Update
> > CpuExceptionHandlerLib pass XCODE5 tool chain
> >
> > Liming,
> >
> > Can we use NASM syntax for instructions instead of db
> > bytes?
> >
> > If you put the label for the fixup after the instruction,
> > you
> > can patch by subtracting the size of the patch value from
> > the
> > label.
> >
> > For example, instead of:
> >
> > > + db 0x48, 0xB8
> > > +JmpAbsoluteAddress:
> > > + dq 0 ; mov rax,
> > HookAfterStubHeaderEnd
> >
> > Use:
> >
> > movq rax, 0
> > JmpAbsoluteAddress:
> >
> > And in the patch loop:
> >
> > mov qword [rcx + (JmpAbsoluteAddress - 8 -
> > HookAfterStubHeaderBegin)], rax
> >
> >
> > If this works, then please use this technique to remove
> > use of db for instructions throughout this series.
> >
> > Mike
> >
> > > -----Original Message-----
> > > From: Gao, Liming
> > > Sent: Wednesday, January 10, 2018 7:24 AM
> > > To: edk2-devel@lists.01.org
> > > Cc: Andrew Fish <afish@apple.com>; Yao, Jiewen
> > > <jiewen.yao@intel.com>; Dong, Eric
> > <eric.dong@intel.com>;
> > > Laszlo Ersek <lersek@redhat.com>; Kinney, Michael D
> > > <michael.d.kinney@intel.com>
> > > Subject: [Patch 4/7] UefiCpuPkg: Update
> > > CpuExceptionHandlerLib pass XCODE5 tool chain
> > >
> > > Use the dummy address as jmp destination, and add the
> > > logic to fix up
> > > the address to the absolute address at boot time.
> > >
> > > Contributed-under: TianoCore Contribution Agreement 1.1
> > > Signed-off-by: Liming Gao <liming.gao@intel.com>
> > > Cc: Andrew Fish <afish@apple.com>
> > > Cc: Jiewen Yao <jiewen.yao@intel.com>
> > > Cc: Eric Dong <eric.dong@intel.com>
> > > Cc: Laszlo Ersek <lersek@redhat.com>
> > > Cc: Michael Kinney <michael.d.kinney@intel.com>
> > > ---
> > > .../X64/ExceptionHandlerAsm.nasm |
> > 29
> > > ++++++++++++++++------
> > > 1 file changed, 22 insertions(+), 7 deletions(-)
> > >
> > > diff --git
> > >
> > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Exception
> > > HandlerAsm.nasm
> > >
> > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Exception
> > > HandlerAsm.nasm
> > > index ba8993d84b..a5fde0a875 100644
> > > ---
> > >
> > a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Exception
> > > HandlerAsm.nasm
> > > +++
> > >
> > b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Exception
> > > HandlerAsm.nasm
> > > @@ -1,5 +1,5 @@
> > > ;-----------------------------------------------------
> > --
> > > ----------------------- ;
> > > -; Copyright (c) 2012 - 2014, Intel Corporation. All
> > > rights reserved.<BR>
> > > +; Copyright (c) 2012 - 2018, Intel Corporation. All
> > > rights reserved.<BR>
> > > ; This program and the accompanying materials
> > > ; are licensed and made available under the terms and
> > > conditions of the BSD License
> > > ; which accompanies this distribution. The full text
> > of
> > > the license may be found at
> > > @@ -40,7 +40,8 @@ AsmIdtVectorBegin:
> > > db 0x6a ; push #VectorNum
> > > db ($ - AsmIdtVectorBegin) /
> > ((AsmIdtVectorEnd
> > > - AsmIdtVectorBegin) / 32) ; VectorNum
> > > push rax
> > > - mov rax, ASM_PFX(CommonInterruptEntry)
> > > + db 0x48, 0xB8
> > > + dq 0 ; mov rax,
> > > ASM_PFX(CommonInterruptEntry)
> > > jmp rax
> > > %endrep
> > > AsmIdtVectorEnd:
> > > @@ -50,7 +51,9 @@ HookAfterStubHeaderBegin:
> > > @VectorNum:
> > > db 0 ; 0 will be fixed
> > > push rax
> > > - mov rax, HookAfterStubHeaderEnd
> > > + db 0x48, 0xB8
> > > +JmpAbsoluteAddress:
> > > + dq 0 ; mov rax,
> > HookAfterStubHeaderEnd
> > > jmp rax
> > > HookAfterStubHeaderEnd:
> > > mov rax, rsp
> > > @@ -260,8 +263,7 @@ HasErrorCode:
> > > ; and make sure RSP is 16-byte aligned
> > > ;
> > > sub rsp, 4 * 8 + 8
> > > - mov rax, ASM_PFX(CommonExceptionHandler)
> > > - call rax
> > > + call ASM_PFX(CommonExceptionHandler)
> > > add rsp, 4 * 8 + 8
> > >
> > > cli
> > > @@ -369,11 +371,24 @@ DoIret:
> > > ; comments here for definition of address map
> > > global ASM_PFX(AsmGetTemplateAddressMap)
> > > ASM_PFX(AsmGetTemplateAddressMap):
> > > - mov rax, AsmIdtVectorBegin
> > > + lea rax, [AsmIdtVectorBegin]
> > > mov qword [rcx], rax
> > > mov qword [rcx + 0x8], (AsmIdtVectorEnd -
> > > AsmIdtVectorBegin) / 32
> > > - mov rax, HookAfterStubHeaderBegin
> > > + lea rax, [HookAfterStubHeaderBegin]
> > > mov qword [rcx + 0x10], rax
> > > +
> > > +; Fix up CommonInterruptEntry address
> > > + lea rax, [ASM_PFX(CommonInterruptEntry)]
> > > + lea rcx, [AsmIdtVectorBegin]
> > > +%rep 32
> > > + mov qword [rcx + (JmpAbsoluteAddress -
> > > HookAfterStubHeaderBegin)], rax
> > > + add rcx, (AsmIdtVectorEnd - AsmIdtVectorBegin)
> > /
> > > 32
> > > +%endrep
> > > +; Fix up HookAfterStubHeaderEnd
> > > + lea rax, [HookAfterStubHeaderEnd]
> > > + lea rcx, [JmpAbsoluteAddress]
> > > + mov qword [rcx], rax
> > > +
> > > ret
> > >
> > > ;-----------------------------------------------------
> > --
> > > ------------------------------
> > > --
> > > 2.11.0.windows.1
^ permalink raw reply [flat|nested] 18+ messages in thread
* [Patch 5/7] UefiCpuPkg: Update SmmCpuFeatureLib pass XCODE5 tool chain
2018-01-10 15:24 [Patch 0/7] EDK2: Enable XCODE5 tool chain with NASM source Liming Gao
` (3 preceding siblings ...)
2018-01-10 15:24 ` [Patch 4/7] UefiCpuPkg: Update CpuExceptionHandlerLib pass XCODE5 tool chain Liming Gao
@ 2018-01-10 15:24 ` Liming Gao
2018-01-10 15:24 ` [Patch 6/7] UefiCpuPkg: Update PiSmmCpuDxeSmm " Liming Gao
` (2 subsequent siblings)
7 siblings, 0 replies; 18+ messages in thread
From: Liming Gao @ 2018-01-10 15:24 UTC (permalink / raw)
To: edk2-devel
Cc: Andrew Fish, Jiewen Yao, Eric Dong, Laszlo Ersek, Michael Kinney
1. Use lea instruction to get the address instead of mov instruction.
2. Use the dummy address as jmp destination, and add the logic to fix up
the address to the absolute address at boot time.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Liming Gao <liming.gao@intel.com>
Cc: Andrew Fish <afish@apple.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
---
.../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm | 6 +++-
UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c | 8 +++--
UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.h | 11 +++++-
.../Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm | 42 +++++++++++++++-------
.../SmmCpuFeaturesLib/X64/SmiException.nasm | 10 +++---
5 files changed, 55 insertions(+), 22 deletions(-)
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm
index 00c0f0672c..057ec6d105 100644
--- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm
@@ -1,5 +1,5 @@
;------------------------------------------------------------------------------ ;
-; Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
; This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
@@ -273,3 +273,7 @@ _StmSmiHandler:
ASM_PFX(gcStmSmiHandlerSize) : DW $ - _StmSmiEntryPoint
ASM_PFX(gcStmSmiHandlerOffset) : DW _StmSmiHandler - _StmSmiEntryPoint
+
+global ASM_PFX(SmmCpuFeaturesLibStmSmiEntryFixupAddress)
+ASM_PFX(SmmCpuFeaturesLibStmSmiEntryFixupAddress):
+ ret
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
index 45015b8da4..8dc2d70527 100644
--- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c
@@ -1,7 +1,7 @@
/** @file
SMM STM support functions
- Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -116,7 +116,6 @@ UINTN mMsegSize = 0;
BOOLEAN mStmConfigurationTableInitialized = FALSE;
-
/**
The constructor function
@@ -139,6 +138,11 @@ SmmCpuFeaturesLibStmConstructor (
EFI_SMRAM_DESCRIPTOR *SmramDescriptor;
//
+ // Initialize address fixup
+ //
+ SmmCpuFeaturesLibStmSmiEntryFixupAddress ();
+
+ //
// Call the common constructor function
//
Status = SmmCpuFeaturesLibConstructor (ImageHandle, SystemTable);
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.h b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.h
index 92a4dc00eb..c98b660ecb 100644
--- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.h
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.h
@@ -1,7 +1,7 @@
/** @file
SMM STM support
- Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -173,4 +173,13 @@ GetStmResource (
VOID
);
+/**
+ This function fixes up the address of the global variable or function
+ referred in SmiEntry assembly files to be the absoute address.
+**/
+VOID
+EFIAPI
+SmmCpuFeaturesLibStmSmiEntryFixupAddress (
+ );
+
#endif
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm
index ea2d2970bd..e9c1306265 100644
--- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm
@@ -1,5 +1,5 @@
;------------------------------------------------------------------------------ ;
-; Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
; This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
@@ -164,7 +164,9 @@ Base:
mov cr0, rbx
retf
@LongMode: ; long mode (64-bit code) starts here
- mov rax, ASM_PFX(gStmSmiHandlerIdtr)
+ db 0x48, 0xB8
+StmSmiEntrySmiHandlerIdtrAbsAddr:
+ dq 0 ; mov rax, ASM_PFX(gStmSmiHandlerIdtr)
lidt [rax]
lea ebx, [rdi + DSC_OFFSET]
mov ax, [rbx + DSC_DS]
@@ -175,7 +177,10 @@ Base:
mov gs, eax
mov ax, [rbx + DSC_SS]
mov ss, eax
-
+ db 0x48, 0xB8
+StmSmiEntryCommonHandlerAbsAddr:
+ dq 0 ; mov rax, CommonHandler
+ jmp rax
CommonHandler:
mov rbx, [rsp + 0x08] ; rbx <- CpuIndex
@@ -188,16 +193,13 @@ CommonHandler:
add rsp, -0x20
mov rcx, rbx
- mov rax, ASM_PFX(CpuSmmDebugEntry)
- call rax
+ call ASM_PFX(CpuSmmDebugEntry)
mov rcx, rbx
- mov rax, ASM_PFX(SmiRendezvous) ; rax <- absolute addr of SmiRedezvous
- call rax
+ call ASM_PFX(SmiRendezvous)
mov rcx, rbx
- mov rax, ASM_PFX(CpuSmmDebugExit)
- call rax
+ call ASM_PFX(CpuSmmDebugExit)
add rsp, 0x20
@@ -208,7 +210,7 @@ CommonHandler:
add rsp, 0x200
- mov rax, ASM_PFX(gStmXdSupported)
+ lea rax, [ASM_PFX(gStmXdSupported)]
mov al, [rax]
cmp al, 0
jz .1
@@ -228,7 +230,7 @@ _StmSmiHandler:
; Check XD disable bit
;
xor r8, r8
- mov rax, ASM_PFX(gStmXdSupported)
+ lea rax, [ASM_PFX(gStmXdSupported)]
mov al, [rax]
cmp al, 0
jz @StmXdDone
@@ -249,8 +251,9 @@ _StmSmiHandler:
; below step is needed, because STM does not run above code.
; we have to run below code to set IDT/CR0/CR4
-
- mov rax, ASM_PFX(gStmSmiHandlerIdtr)
+ db 0x48, 0xB8
+StmSmiHandlerIdtrAbsAddr:
+ dq 0 ; mov rax, ASM_PFX(gStmSmiHandlerIdtr)
lidt [rax]
mov rax, cr0
@@ -264,3 +267,16 @@ _StmSmiHandler:
ASM_PFX(gcStmSmiHandlerSize) : DW $ - _StmSmiEntryPoint
ASM_PFX(gcStmSmiHandlerOffset) : DW _StmSmiHandler - _StmSmiEntryPoint
+
+global ASM_PFX(SmmCpuFeaturesLibStmSmiEntryFixupAddress)
+ASM_PFX(SmmCpuFeaturesLibStmSmiEntryFixupAddress):
+ lea rax, [ASM_PFX(gStmSmiHandlerIdtr)]
+ lea rcx, [StmSmiEntrySmiHandlerIdtrAbsAddr]
+ mov qword [rcx], rax
+ lea rcx, [StmSmiHandlerIdtrAbsAddr]
+ mov qword [rcx], rax
+
+ lea rax, [CommonHandler]
+ lea rcx, [StmSmiEntryCommonHandlerAbsAddr]
+ mov qword [rcx], rax
+ ret
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiException.nasm b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiException.nasm
index ce9d7c2bb6..b0ab87b0d4 100644
--- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiException.nasm
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiException.nasm
@@ -1,5 +1,5 @@
;------------------------------------------------------------------------------ ;
-; Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
; This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
@@ -95,7 +95,7 @@ ASM_PFX(OnStmSetup):
; Check XD disable bit
;
xor r8, r8
- mov rax, ASM_PFX(gStmXdSupported)
+ lea rax, [ASM_PFX(gStmXdSupported)]
mov al, [rax]
cmp al, 0
jz @StmXdDone1
@@ -118,7 +118,7 @@ ASM_PFX(OnStmSetup):
call ASM_PFX(SmmStmSetup)
add rsp, 0x20
- mov rax, ASM_PFX(gStmXdSupported)
+ lea rax, [ASM_PFX(gStmXdSupported)]
mov al, [rax]
cmp al, 0
jz .11
@@ -139,7 +139,7 @@ ASM_PFX(OnStmTeardown):
; Check XD disable bit
;
xor r8, r8
- mov rax, ASM_PFX(gStmXdSupported)
+ lea rax, [ASM_PFX(gStmXdSupported)]
mov al, [rax]
cmp al, 0
jz @StmXdDone2
@@ -162,7 +162,7 @@ ASM_PFX(OnStmTeardown):
call ASM_PFX(SmmStmTeardown)
add rsp, 0x20
- mov rax, ASM_PFX(gStmXdSupported)
+ lea rax, [ASM_PFX(gStmXdSupported)]
mov al, [rax]
cmp al, 0
jz .12
--
2.11.0.windows.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [Patch 6/7] UefiCpuPkg: Update PiSmmCpuDxeSmm pass XCODE5 tool chain
2018-01-10 15:24 [Patch 0/7] EDK2: Enable XCODE5 tool chain with NASM source Liming Gao
` (4 preceding siblings ...)
2018-01-10 15:24 ` [Patch 5/7] UefiCpuPkg: Update SmmCpuFeatureLib " Liming Gao
@ 2018-01-10 15:24 ` Liming Gao
2018-01-10 15:24 ` [Patch 7/7] OvmfPkg: Don't add -mno-mmx -mno-sse option for " Liming Gao
2018-01-11 9:54 ` [Patch 0/7] EDK2: Enable XCODE5 tool chain with NASM source Laszlo Ersek
7 siblings, 0 replies; 18+ messages in thread
From: Liming Gao @ 2018-01-10 15:24 UTC (permalink / raw)
To: edk2-devel
Cc: Andrew Fish, Jiewen Yao, Eric Dong, Laszlo Ersek, Michael Kinney
1. Use lea instruction to get the address instead of mov instruction.
2. Use the dummy address as jmp destination, and add the logic to fix up
the address to the absolute address at boot time.
3. On MpFuncs.nasm, use ExchangeInfo to record InitializeFloatingPointUnits.
This way is same to MpInitLib.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Liming Gao <liming.gao@intel.com>
Cc: Andrew Fish <afish@apple.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
---
UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 6 ++++-
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm | 5 +++-
UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm | 6 ++++-
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 8 ++++++-
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 20 +++++++++++++++-
UefiCpuPkg/PiSmmCpuDxeSmm/X64/MpFuncs.nasm | 9 ++++---
UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm | 32 +++++++++++++++++--------
UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiException.nasm | 4 ++--
UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm | 17 ++++++++++---
9 files changed, 82 insertions(+), 25 deletions(-)
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
index 94e5ab2c0e..554629536a 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
@@ -1,7 +1,7 @@
/** @file
Code for Processor S3 restoration
-Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -14,6 +14,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#include "PiSmmCpuDxeSmm.h"
+#pragma pack(1)
typedef struct {
UINTN Lock;
VOID *StackStart;
@@ -23,7 +24,9 @@ typedef struct {
IA32_DESCRIPTOR IdtrProfile;
UINT32 BufferStart;
UINT32 Cr3;
+ UINTN InitializeFloatingPointUnitsAddress;
} MP_CPU_EXCHANGE_INFO;
+#pragma pack()
typedef struct {
UINT8 *RendezvousFunnelAddress;
@@ -456,6 +459,7 @@ PrepareApStartupVector (
mExchangeInfo->StackSize = mAcpiCpuData.StackSize;
mExchangeInfo->BufferStart = (UINT32) StartupVector;
mExchangeInfo->Cr3 = (UINT32) (AsmReadCr3 ());
+ mExchangeInfo->InitializeFloatingPointUnitsAddress = (UINTN)InitializeFloatingPointUnits;
}
/**
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
index 4d2383ff97..a8324a7f4a 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
@@ -1,5 +1,5 @@
;------------------------------------------------------------------------------ ;
-; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
; This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
@@ -207,3 +207,6 @@ ASM_PFX(SmiHandler):
ASM_PFX(gcSmiHandlerSize): DW $ - _SmiEntryPoint
+global ASM_PFX(PiSmmCpuSmiEntryFixupAddress)
+ASM_PFX(PiSmmCpuSmiEntryFixupAddress):
+ ret
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm
index d9df3626c7..a5c62e77ce 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm
@@ -1,5 +1,5 @@
;------------------------------------------------------------------------------ ;
-; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
; This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
@@ -85,3 +85,7 @@ ASM_PFX(SmmRelocationSemaphoreComplete):
mov byte [eax], 1
pop eax
jmp [ASM_PFX(mSmmRelocationOriginalAddress)]
+
+global ASM_PFX(PiSmmCpuSmmInitFixupAddress)
+ASM_PFX(PiSmmCpuSmmInitFixupAddress):
+ ret
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
index 4b66a0dfd9..a27d1f4684 100755
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
@@ -1,7 +1,7 @@
/** @file
Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.
-Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
This program and the accompanying materials
@@ -543,6 +543,12 @@ PiCpuSmmEntry (
UINT32 Cr3;
//
+ // Initialize address fixup
+ //
+ PiSmmCpuSmmInitFixupAddress ();
+ PiSmmCpuSmiEntryFixupAddress ();
+
+ //
// Initialize Debug Agent to support source level debug in SMM code
//
InitializeDebugAgent (DEBUG_AGENT_INIT_SMM, NULL, NULL);
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
index ef32f17676..0323bfff92 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
@@ -1,7 +1,7 @@
/** @file
Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.
-Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
This program and the accompanying materials
@@ -1166,4 +1166,22 @@ EdkiiSmmGetMemoryAttributes (
IN UINT64 *Attributes
);
+/**
+ This function fixes up the address of the global variable or function
+ referred in SmmInit assembly files to be the absoute address.
+**/
+VOID
+EFIAPI
+PiSmmCpuSmmInitFixupAddress (
+ );
+
+/**
+ This function fixes up the address of the global variable or function
+ referred in SmiEntry assembly files to be the absoute address.
+**/
+VOID
+EFIAPI
+PiSmmCpuSmiEntryFixupAddress (
+ );
+
#endif
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/MpFuncs.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/MpFuncs.nasm
index 702233d6e4..704942ec27 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/MpFuncs.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/MpFuncs.nasm
@@ -1,5 +1,5 @@
;------------------------------------------------------------------------------ ;
-; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
; This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
@@ -18,8 +18,6 @@
;
;-------------------------------------------------------------------------------
-extern ASM_PFX(InitializeFloatingPointUnits)
-
%define VacantFlag 0x0
%define NotVacantFlag 0xff
@@ -31,6 +29,7 @@ extern ASM_PFX(InitializeFloatingPointUnits)
%define IdtrLocation LockLocation + 0x2A
%define BufferStartLocation LockLocation + 0x34
%define Cr3OffsetLocation LockLocation + 0x38
+%define InitializeFloatingPointUnitsAddress LockLocation + 0x3C
;-------------------------------------------------------------------------------------
;RendezvousFunnelProc procedure follows. All APs execute their procedure. This
@@ -153,7 +152,7 @@ Releaselock:
;
; Call assembly function to initialize FPU.
;
- mov rax, ASM_PFX(InitializeFloatingPointUnits)
+ mov rax, qword [esi + InitializeFloatingPointUnitsAddress]
sub rsp, 0x20
call rax
add rsp, 0x20
@@ -185,7 +184,7 @@ RendezvousFunnelProcEnd:
; comments here for definition of address map
global ASM_PFX(AsmGetAddressMap)
ASM_PFX(AsmGetAddressMap):
- mov rax, RendezvousFunnelProcStart
+ lea rax, [RendezvousFunnelProcStart]
mov qword [rcx], rax
mov qword [rcx+0x8], PMODE_ENTRY - RendezvousFunnelProcStart
mov qword [rcx+0x10], FLAT32_JUMP - RendezvousFunnelProcStart
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
index dc56dc7852..3944b3e68c 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
@@ -1,5 +1,5 @@
;------------------------------------------------------------------------------ ;
-; Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
; This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
@@ -158,7 +158,9 @@ Base:
mov cr0, rbx
retf
@LongMode: ; long mode (64-bit code) starts here
- mov rax, ASM_PFX(gSmiHandlerIdtr)
+ db 0x48, 0xB8
+SmiHandlerIdtrAbsAddr:
+ dq 0 ; mov rax, ASM_PFX(gSmiHandlerIdtr)
lidt [rax]
lea ebx, [rdi + DSC_OFFSET]
mov ax, [rbx + DSC_DS]
@@ -169,7 +171,10 @@ Base:
mov gs, eax
mov ax, [rbx + DSC_SS]
mov ss, eax
-; jmp _SmiHandler ; instruction is not needed
+ db 0x48, 0xB8
+_SmiHandlerAbsAddr:
+ dq 0 ; mov rax, _SmiHandler
+ jmp rax
_SmiHandler:
mov rbx, [rsp + 0x8] ; rcx <- CpuIndex
@@ -184,16 +189,13 @@ _SmiHandler:
add rsp, -0x20
mov rcx, rbx
- mov rax, ASM_PFX(CpuSmmDebugEntry)
- call rax
+ call ASM_PFX(CpuSmmDebugEntry)
mov rcx, rbx
- mov rax, ASM_PFX(SmiRendezvous) ; rax <- absolute addr of SmiRedezvous
- call rax
+ call ASM_PFX(SmiRendezvous)
mov rcx, rbx
- mov rax, ASM_PFX(CpuSmmDebugExit)
- call rax
+ call ASM_PFX(CpuSmmDebugExit)
add rsp, 0x20
@@ -205,7 +207,7 @@ _SmiHandler:
add rsp, 0x200
- mov rax, ASM_PFX(mXdSupported)
+ lea rax, [ASM_PFX(mXdSupported)]
mov al, [rax]
cmp al, 0
jz .1
@@ -222,3 +224,13 @@ _SmiHandler:
ASM_PFX(gcSmiHandlerSize) DW $ - _SmiEntryPoint
+global ASM_PFX(PiSmmCpuSmiEntryFixupAddress)
+ASM_PFX(PiSmmCpuSmiEntryFixupAddress):
+ lea rax, [ASM_PFX(gSmiHandlerIdtr)]
+ lea rcx, [SmiHandlerIdtrAbsAddr]
+ mov qword [rcx], rax
+
+ lea rax, [_SmiHandler]
+ lea rcx, [_SmiHandlerAbsAddr]
+ mov qword [rcx], rax
+ ret
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiException.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiException.nasm
index b2e2e6dee6..a8a9af3008 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiException.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiException.nasm
@@ -1,5 +1,5 @@
;------------------------------------------------------------------------------ ;
-; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
; This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
@@ -289,7 +289,7 @@ ASM_PFX(PageFaultIdtHandlerSmmProfile):
;; call into exception handler
mov rcx, [rbp + 8]
- mov rax, ASM_PFX(SmiPFHandler)
+ lea rax, [ASM_PFX(SmiPFHandler)]
;; Prepare parameter and call
mov rdx, rsp
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
index 9d05e2cb05..2701689c3d 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
@@ -1,5 +1,5 @@
;------------------------------------------------------------------------------ ;
-; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
; This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at
@@ -60,7 +60,7 @@ ASM_PFX(gSmmCr4): DD 0
ASM_PFX(gSmmCr0): DD 0
mov cr0, rax ; enable protected mode & paging
DB 0x66, 0xea ; far jmp to long mode
-ASM_PFX(gSmmJmpAddr): DQ @LongMode
+ASM_PFX(gSmmJmpAddr): DQ 0;@LongMode
@LongMode: ; long-mode starts here
DB 0x48, 0xbc ; mov rsp, imm64
ASM_PFX(gSmmInitStack): DQ 0
@@ -99,7 +99,7 @@ ASM_PFX(gcSmmInitTemplate):
sub ebp, 0x30000
jmp ebp
@L1:
- DQ ASM_PFX(SmmStartup)
+ DQ 0; ASM_PFX(SmmStartup)
ASM_PFX(gcSmmInitSize): DW $ - ASM_PFX(gcSmmInitTemplate)
@@ -128,3 +128,14 @@ ASM_PFX(mRebasedFlagAddr32): dd 0
;
db 0xff, 0x25
ASM_PFX(mSmmRelocationOriginalAddressPtr32): dd 0
+
+global ASM_PFX(PiSmmCpuSmmInitFixupAddress)
+ASM_PFX(PiSmmCpuSmmInitFixupAddress):
+ lea rax, [@LongMode]
+ lea rcx, [ASM_PFX(gSmmJmpAddr)]
+ mov qword [rcx], rax
+
+ lea rax, [ASM_PFX(SmmStartup)]
+ lea rcx, [@L1]
+ mov qword [rcx], rax
+ ret
--
2.11.0.windows.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* [Patch 7/7] OvmfPkg: Don't add -mno-mmx -mno-sse option for XCODE5 tool chain
2018-01-10 15:24 [Patch 0/7] EDK2: Enable XCODE5 tool chain with NASM source Liming Gao
` (5 preceding siblings ...)
2018-01-10 15:24 ` [Patch 6/7] UefiCpuPkg: Update PiSmmCpuDxeSmm " Liming Gao
@ 2018-01-10 15:24 ` Liming Gao
2018-01-10 18:22 ` Laszlo Ersek
2018-01-11 9:54 ` [Patch 0/7] EDK2: Enable XCODE5 tool chain with NASM source Laszlo Ersek
7 siblings, 1 reply; 18+ messages in thread
From: Liming Gao @ 2018-01-10 15:24 UTC (permalink / raw)
To: edk2-devel; +Cc: Andrew Fish, Laszlo Ersek
Ovmf appended option -mno-mmx -mno-sse, but these two options were enabled
in Openssl. The compiler option becomes -mmmx –msse -mno-mmx -mno-sse. It
trig mac clang compiler hang when compile one source file in openssl.
This issue is found when SECURE_BOOT_ENABLE is TRUE. This may be the compiler
issue. To work around it, don't add these two options for XCODE5 tool chain.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Liming Gao <liming.gao@intel.com>
Cc: Andrew Fish <afish@apple.com>
Cc: Laszlo Ersek <lersek@redhat.com>
---
OvmfPkg/OvmfPkgIa32.dsc | 4 +++-
OvmfPkg/OvmfPkgIa32X64.dsc | 4 +++-
OvmfPkg/OvmfPkgX64.dsc | 4 +++-
3 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc
index 9d23f8c162..d762955c5d 100644
--- a/OvmfPkg/OvmfPkgIa32.dsc
+++ b/OvmfPkg/OvmfPkgIa32.dsc
@@ -1,7 +1,7 @@
## @file
# EFI/Framework Open Virtual Machine Firmware (OVMF) platform
#
-# Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
# (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
#
# This program and the accompanying materials
@@ -64,7 +64,9 @@
GCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
INTEL:RELEASE_*_*_CC_FLAGS = /D MDEPKG_NDEBUG
MSFT:RELEASE_*_*_CC_FLAGS = /D MDEPKG_NDEBUG
+!if $(TOOL_CHAIN_TAG) != "XCODE5"
GCC:*_*_*_CC_FLAGS = -mno-mmx -mno-sse
+!endif
#
# Disable deprecated APIs.
diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc
index a9c667fed8..6bcbe70d64 100644
--- a/OvmfPkg/OvmfPkgIa32X64.dsc
+++ b/OvmfPkg/OvmfPkgIa32X64.dsc
@@ -1,7 +1,7 @@
## @file
# EFI/Framework Open Virtual Machine Firmware (OVMF) platform
#
-# Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
# (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
#
# This program and the accompanying materials
@@ -64,7 +64,9 @@
GCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
INTEL:RELEASE_*_*_CC_FLAGS = /D MDEPKG_NDEBUG
MSFT:RELEASE_*_*_CC_FLAGS = /D MDEPKG_NDEBUG
+!if $(TOOL_CHAIN_TAG) != "XCODE5"
GCC:*_*_*_CC_FLAGS = -mno-mmx -mno-sse
+!endif
!ifdef $(SOURCE_DEBUG_ENABLE)
MSFT:*_*_X64_GENFW_FLAGS = --keepexceptiontable
GCC:*_*_X64_GENFW_FLAGS = --keepexceptiontable
diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc
index abf570512a..70fcdcba11 100644
--- a/OvmfPkg/OvmfPkgX64.dsc
+++ b/OvmfPkg/OvmfPkgX64.dsc
@@ -1,7 +1,7 @@
## @file
# EFI/Framework Open Virtual Machine Firmware (OVMF) platform
#
-# Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
# (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
#
# This program and the accompanying materials
@@ -64,7 +64,9 @@
GCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
INTEL:RELEASE_*_*_CC_FLAGS = /D MDEPKG_NDEBUG
MSFT:RELEASE_*_*_CC_FLAGS = /D MDEPKG_NDEBUG
+!if $(TOOL_CHAIN_TAG) != "XCODE5"
GCC:*_*_*_CC_FLAGS = -mno-mmx -mno-sse
+!endif
!ifdef $(SOURCE_DEBUG_ENABLE)
MSFT:*_*_X64_GENFW_FLAGS = --keepexceptiontable
GCC:*_*_X64_GENFW_FLAGS = --keepexceptiontable
--
2.11.0.windows.1
^ permalink raw reply related [flat|nested] 18+ messages in thread* Re: [Patch 7/7] OvmfPkg: Don't add -mno-mmx -mno-sse option for XCODE5 tool chain
2018-01-10 15:24 ` [Patch 7/7] OvmfPkg: Don't add -mno-mmx -mno-sse option for " Liming Gao
@ 2018-01-10 18:22 ` Laszlo Ersek
0 siblings, 0 replies; 18+ messages in thread
From: Laszlo Ersek @ 2018-01-10 18:22 UTC (permalink / raw)
To: Liming Gao, edk2-devel; +Cc: Andrew Fish
On 01/10/18 16:24, Liming Gao wrote:
> Ovmf appended option -mno-mmx -mno-sse, but these two options were enabled
> in Openssl. The compiler option becomes -mmmx –msse -mno-mmx -mno-sse. It
> trig mac clang compiler hang when compile one source file in openssl.
> This issue is found when SECURE_BOOT_ENABLE is TRUE. This may be the compiler
> issue. To work around it, don't add these two options for XCODE5 tool chain.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Liming Gao <liming.gao@intel.com>
> Cc: Andrew Fish <afish@apple.com>
> Cc: Laszlo Ersek <lersek@redhat.com>
> ---
> OvmfPkg/OvmfPkgIa32.dsc | 4 +++-
> OvmfPkg/OvmfPkgIa32X64.dsc | 4 +++-
> OvmfPkg/OvmfPkgX64.dsc | 4 +++-
> 3 files changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc
> index 9d23f8c162..d762955c5d 100644
> --- a/OvmfPkg/OvmfPkgIa32.dsc
> +++ b/OvmfPkg/OvmfPkgIa32.dsc
> @@ -1,7 +1,7 @@
> ## @file
> # EFI/Framework Open Virtual Machine Firmware (OVMF) platform
> #
> -# Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
> +# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
> # (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
> #
> # This program and the accompanying materials
> @@ -64,7 +64,9 @@
> GCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
> INTEL:RELEASE_*_*_CC_FLAGS = /D MDEPKG_NDEBUG
> MSFT:RELEASE_*_*_CC_FLAGS = /D MDEPKG_NDEBUG
> +!if $(TOOL_CHAIN_TAG) != "XCODE5"
> GCC:*_*_*_CC_FLAGS = -mno-mmx -mno-sse
> +!endif
>
> #
> # Disable deprecated APIs.
> diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc
> index a9c667fed8..6bcbe70d64 100644
> --- a/OvmfPkg/OvmfPkgIa32X64.dsc
> +++ b/OvmfPkg/OvmfPkgIa32X64.dsc
> @@ -1,7 +1,7 @@
> ## @file
> # EFI/Framework Open Virtual Machine Firmware (OVMF) platform
> #
> -# Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
> +# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
> # (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
> #
> # This program and the accompanying materials
> @@ -64,7 +64,9 @@
> GCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
> INTEL:RELEASE_*_*_CC_FLAGS = /D MDEPKG_NDEBUG
> MSFT:RELEASE_*_*_CC_FLAGS = /D MDEPKG_NDEBUG
> +!if $(TOOL_CHAIN_TAG) != "XCODE5"
> GCC:*_*_*_CC_FLAGS = -mno-mmx -mno-sse
> +!endif
> !ifdef $(SOURCE_DEBUG_ENABLE)
> MSFT:*_*_X64_GENFW_FLAGS = --keepexceptiontable
> GCC:*_*_X64_GENFW_FLAGS = --keepexceptiontable
> diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc
> index abf570512a..70fcdcba11 100644
> --- a/OvmfPkg/OvmfPkgX64.dsc
> +++ b/OvmfPkg/OvmfPkgX64.dsc
> @@ -1,7 +1,7 @@
> ## @file
> # EFI/Framework Open Virtual Machine Firmware (OVMF) platform
> #
> -# Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
> +# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
> # (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
> #
> # This program and the accompanying materials
> @@ -64,7 +64,9 @@
> GCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
> INTEL:RELEASE_*_*_CC_FLAGS = /D MDEPKG_NDEBUG
> MSFT:RELEASE_*_*_CC_FLAGS = /D MDEPKG_NDEBUG
> +!if $(TOOL_CHAIN_TAG) != "XCODE5"
> GCC:*_*_*_CC_FLAGS = -mno-mmx -mno-sse
> +!endif
> !ifdef $(SOURCE_DEBUG_ENABLE)
> MSFT:*_*_X64_GENFW_FLAGS = --keepexceptiontable
> GCC:*_*_X64_GENFW_FLAGS = --keepexceptiontable
>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Patch 0/7] EDK2: Enable XCODE5 tool chain with NASM source
2018-01-10 15:24 [Patch 0/7] EDK2: Enable XCODE5 tool chain with NASM source Liming Gao
` (6 preceding siblings ...)
2018-01-10 15:24 ` [Patch 7/7] OvmfPkg: Don't add -mno-mmx -mno-sse option for " Liming Gao
@ 2018-01-11 9:54 ` Laszlo Ersek
2018-01-11 10:02 ` Laszlo Ersek
7 siblings, 1 reply; 18+ messages in thread
From: Laszlo Ersek @ 2018-01-11 9:54 UTC (permalink / raw)
To: Liming Gao; +Cc: edk2-devel, Andrew Fish
Liming,
On 01/10/18 16:24, Liming Gao wrote:
> 1. Use nasm source file for X86 tool chain, then ASM and S file can be removed.
> 2. Update Nasm source file to resolve the absolute addressing.
> 3. Verify OVMF IA32, IA32X64 and X64 boot to shell functionality with XCODE5
> Here is build command.
> build -p OvmfPkg\OvmfPkgIa32X64.dsc -a IA32 -a X64 -DSMM_REQUIRE=TRUE
> -DSECURE_BOOT_ENABLE=TRUE -DUSE_OLD_SHELL
> build -p OvmfPkg\OvmfPkgIa32.dsc -a IA32 -a X64 -DSMM_REQUIRE=TRUE
> -DSECURE_BOOT_ENABLE=TRUE -DUSE_OLD_SHELL
> build -p OvmfPkg\OvmfPkgX64.dsc -a IA32 -a X64 -DSMM_REQUIRE=TRUE
> -DSECURE_BOOT_ENABLE=TRUE -DUSE_OLD_SHELL
> 4. Known limitation is XCODE5 doesn't support HII resource section generation.
> So, new UEFI shell application tftp can't be used. Old shell is used.
After sleeping on this, I got a question: is there a public bug report
in the clang / llvm bug tracker about this shortcoming? It would be nice
to reference it in the commit messages.
The main reason I'm asking this is because these workarounds include
more and more DB / DW / DD / DQ mnemonics in the NASM source files. One
of the original promises of NASM was that we could cut down on the
binary representation of x86 instructions, just write real assembly
code. This was in part enabled by NASM supporting multi-mode assembly
files, such that mode transitions (e.g. from real mode to protected mode
to long mode) could still be implemented in a human-readable assembly file.
So this workaround is a step back in that regard (i.e., for readability
and future updates). I agree we are sometimes forced to do such things
to support all the toolchains we target, but it would be nice to have
proof that the clang / llvm developers *intend* to fix this (possibly in
the next major release of XCODE -- I'm not sure). So a public bug report
that we could reference in the commit messages would be great.
Thanks!
Laszlo
^ permalink raw reply [flat|nested] 18+ messages in thread* Re: [Patch 0/7] EDK2: Enable XCODE5 tool chain with NASM source
2018-01-11 9:54 ` [Patch 0/7] EDK2: Enable XCODE5 tool chain with NASM source Laszlo Ersek
@ 2018-01-11 10:02 ` Laszlo Ersek
2018-01-12 2:15 ` Gao, Liming
0 siblings, 1 reply; 18+ messages in thread
From: Laszlo Ersek @ 2018-01-11 10:02 UTC (permalink / raw)
To: Liming Gao; +Cc: edk2-devel, Andrew Fish
On 01/11/18 10:54, Laszlo Ersek wrote:
> Liming,
>
> On 01/10/18 16:24, Liming Gao wrote:
>> 1. Use nasm source file for X86 tool chain, then ASM and S file can be removed.
>> 2. Update Nasm source file to resolve the absolute addressing.
>> 3. Verify OVMF IA32, IA32X64 and X64 boot to shell functionality with XCODE5
>> Here is build command.
>> build -p OvmfPkg\OvmfPkgIa32X64.dsc -a IA32 -a X64 -DSMM_REQUIRE=TRUE
>> -DSECURE_BOOT_ENABLE=TRUE -DUSE_OLD_SHELL
>> build -p OvmfPkg\OvmfPkgIa32.dsc -a IA32 -a X64 -DSMM_REQUIRE=TRUE
>> -DSECURE_BOOT_ENABLE=TRUE -DUSE_OLD_SHELL
>> build -p OvmfPkg\OvmfPkgX64.dsc -a IA32 -a X64 -DSMM_REQUIRE=TRUE
>> -DSECURE_BOOT_ENABLE=TRUE -DUSE_OLD_SHELL
>> 4. Known limitation is XCODE5 doesn't support HII resource section generation.
>> So, new UEFI shell application tftp can't be used. Old shell is used.
>
> After sleeping on this, I got a question: is there a public bug report
> in the clang / llvm bug tracker about this shortcoming? It would be nice
> to reference it in the commit messages.
>
> The main reason I'm asking this is because these workarounds include
> more and more DB / DW / DD / DQ mnemonics in the NASM source files. One
> of the original promises of NASM was that we could cut down on the
> binary representation of x86 instructions, just write real assembly
> code. This was in part enabled by NASM supporting multi-mode assembly
> files, such that mode transitions (e.g. from real mode to protected mode
> to long mode) could still be implemented in a human-readable assembly file.
>
> So this workaround is a step back in that regard (i.e., for readability
> and future updates). I agree we are sometimes forced to do such things
> to support all the toolchains we target, but it would be nice to have
> proof that the clang / llvm developers *intend* to fix this (possibly in
> the next major release of XCODE -- I'm not sure). So a public bug report
> that we could reference in the commit messages would be great.
Nevermind, I just read Mike's comments and the new approach; it's much
better!
(Still, if we have an XCODE bug report, it would be nice to reference
that in the commit messages.)
Thanks!
Laszlo
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Patch 0/7] EDK2: Enable XCODE5 tool chain with NASM source
2018-01-11 10:02 ` Laszlo Ersek
@ 2018-01-12 2:15 ` Gao, Liming
0 siblings, 0 replies; 18+ messages in thread
From: Gao, Liming @ 2018-01-12 2:15 UTC (permalink / raw)
To: Laszlo Ersek; +Cc: edk2-devel@lists.01.org, Andrew Fish
Laszlo:
Thanks for comments. I submit two bugs. One is for UefiCpuPkg, another is for BaseTools.
https://bugzilla.tianocore.org/show_bug.cgi?id=849
https://bugzilla.tianocore.org/show_bug.cgi?id=850
> -----Original Message-----
> From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Laszlo Ersek
> Sent: Thursday, January 11, 2018 6:03 PM
> To: Gao, Liming <liming.gao@intel.com>
> Cc: edk2-devel@lists.01.org; Andrew Fish <afish@apple.com>
> Subject: Re: [edk2] [Patch 0/7] EDK2: Enable XCODE5 tool chain with NASM source
>
> On 01/11/18 10:54, Laszlo Ersek wrote:
> > Liming,
> >
> > On 01/10/18 16:24, Liming Gao wrote:
> >> 1. Use nasm source file for X86 tool chain, then ASM and S file can be removed.
> >> 2. Update Nasm source file to resolve the absolute addressing.
> >> 3. Verify OVMF IA32, IA32X64 and X64 boot to shell functionality with XCODE5
> >> Here is build command.
> >> build -p OvmfPkg\OvmfPkgIa32X64.dsc -a IA32 -a X64 -DSMM_REQUIRE=TRUE
> >> -DSECURE_BOOT_ENABLE=TRUE -DUSE_OLD_SHELL
> >> build -p OvmfPkg\OvmfPkgIa32.dsc -a IA32 -a X64 -DSMM_REQUIRE=TRUE
> >> -DSECURE_BOOT_ENABLE=TRUE -DUSE_OLD_SHELL
> >> build -p OvmfPkg\OvmfPkgX64.dsc -a IA32 -a X64 -DSMM_REQUIRE=TRUE
> >> -DSECURE_BOOT_ENABLE=TRUE -DUSE_OLD_SHELL
> >> 4. Known limitation is XCODE5 doesn't support HII resource section generation.
> >> So, new UEFI shell application tftp can't be used. Old shell is used.
> >
> > After sleeping on this, I got a question: is there a public bug report
> > in the clang / llvm bug tracker about this shortcoming? It would be nice
> > to reference it in the commit messages.
> >
> > The main reason I'm asking this is because these workarounds include
> > more and more DB / DW / DD / DQ mnemonics in the NASM source files. One
> > of the original promises of NASM was that we could cut down on the
> > binary representation of x86 instructions, just write real assembly
> > code. This was in part enabled by NASM supporting multi-mode assembly
> > files, such that mode transitions (e.g. from real mode to protected mode
> > to long mode) could still be implemented in a human-readable assembly file.
> >
> > So this workaround is a step back in that regard (i.e., for readability
> > and future updates). I agree we are sometimes forced to do such things
> > to support all the toolchains we target, but it would be nice to have
> > proof that the clang / llvm developers *intend* to fix this (possibly in
> > the next major release of XCODE -- I'm not sure). So a public bug report
> > that we could reference in the commit messages would be great.
>
> Nevermind, I just read Mike's comments and the new approach; it's much
> better!
>
> (Still, if we have an XCODE bug report, it would be nice to reference
> that in the commit messages.)
>
> Thanks!
> Laszlo
> _______________________________________________
> edk2-devel mailing list
> edk2-devel@lists.01.org
> https://lists.01.org/mailman/listinfo/edk2-devel
^ permalink raw reply [flat|nested] 18+ messages in thread