Re: [PATCH] MdePkg/Include/IndustryStandard: Add PCI Express 4.0 header file

["Gao, Liming" <liming.gao@intel.com>]

Felix:
  Structure PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_16_0 is not same to the one defined in spec. Could you define the complete structure?

Thanks
Liming
>-----Original Message-----
>From: Felix Polyudov [mailto:felixp@ami.com]
>Sent: Monday, February 26, 2018 10:20 PM
>To: edk2-devel@lists.01.org
>Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Gao, Liming
><liming.gao@intel.com>
>Subject: [PATCH] MdePkg/Include/IndustryStandard: Add PCI Express 4.0
>header file
>
>The header includes Physical Layer PCI Express Extended Capability definitions
>described in section 7.7.5 of PCI Express Base Specification rev. 4.0.
>
>Contributed-under: TianoCore Contribution Agreement 1.1
>Signed-off-by: Felix Polyudov <felixp@ami.com>
>---
> MdePkg/Include/IndustryStandard/PciExpress40.h | 69
>++++++++++++++++++++++++++
> 1 file changed, 69 insertions(+)
> create mode 100644 MdePkg/Include/IndustryStandard/PciExpress40.h
>
>diff --git a/MdePkg/Include/IndustryStandard/PciExpress40.h
>b/MdePkg/Include/IndustryStandard/PciExpress40.h
>new file mode 100644
>index 0000000..e0f4323
>--- /dev/null
>+++ b/MdePkg/Include/IndustryStandard/PciExpress40.h
>@@ -0,0 +1,69 @@
>+/** @file
>+Support for the PCI Express 4.0 standard.
>+
>+This header file may not define all structures.  Please extend as required.
>+
>+Copyright (c) 2018, American Megatrends, Inc. All rights reserved.<BR>
>+This program and the accompanying materials
>+are licensed and made available under the terms and conditions of the BSD
>License
>+which accompanies this distribution.  The full text of the license may be
>found at
>+http://opensource.org/licenses/bsd-license.php
>+
>+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>+
>+**/
>+
>+#ifndef _PCIEXPRESS40_H_
>+#define _PCIEXPRESS40_H_
>+
>+#include <IndustryStandard/PciExpress31.h>
>+
>+#pragma pack(1)
>+
>+/// The Physical Layer PCI Express Extended Capability definitions.
>+///
>+/// Based on section 7.7.5 of PCI Express Base Specification 4.0.
>+///@{
>+#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_16_0_ID
>0x0026
>+#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_16_0_VER1
>0x1
>+
>+// Register offsets from Physical Layer PCI-E Ext Cap Header
>+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES_OFFSET
>0x04
>+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL_OFFSET
>0x08
>+#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS_OFFSET
>0x0C
>+#define
>PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LOCAL_DATA_PARITY_STATUS_O
>FFSET             0x10
>+#define
>PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_FIRST_RETIMER_DATA_PARITY_S
>TATUS_OFFSET     0x14
>+#define
>PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_SECOND_RETIMER_DATA_PARITY
>_STATUS_OFFSET    0x18
>+#define
>PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL
>_OFFSET            0x20
>+
>+typedef union {
>+  struct {
>+    UINT32 EqualizationComplete      : 1; // bit 0
>+    UINT32 EqualizationPhase1Success : 1; // bit 1
>+    UINT32 EqualizationPhase2Success : 1; // bit 2
>+    UINT32 EqualizationPhase3Success : 1; // bit 3
>+    UINT32 LinkEqualizationRequest   : 1; // bit 4
>+    UINT32 Reserved                  : 27; // Reserved bit 5:31
>+  } Bits;
>+  UINT32   Uint32;
>+} PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS;
>+
>+typedef union {
>+  struct {
>+    UINT8 DownstreamPortTransmitterPreset : 4; //bit 0..3
>+    UINT8 UpstreamPortTransmitterPreset   : 4; //bit 4..7
>+  } Bits;
>+  UINT8   Uint8;
>+}
>PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL;
>+
>+typedef struct {
>+  PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER   Header;
>+  PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS Status;
>+
>PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL
>Control;
>+} PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_16_0;
>+///@}
>+
>+#pragma pack()
>+
>+#endif
>--
>2.10.0.windows.1
>
>
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