From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.24; helo=mga09.intel.com; envelope-from=liming.gao@intel.com; receiver=edk2-devel@lists.01.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 1CD9E2249275F for ; Fri, 2 Mar 2018 07:45:15 -0800 (PST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 02 Mar 2018 07:51:24 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.47,412,1515484800"; d="scan'208";a="24632547" Received: from fmsmsx103.amr.corp.intel.com ([10.18.124.201]) by fmsmga002.fm.intel.com with ESMTP; 02 Mar 2018 07:51:24 -0800 Received: from fmsmsx119.amr.corp.intel.com (10.18.124.207) by FMSMSX103.amr.corp.intel.com (10.18.124.201) with Microsoft SMTP Server (TLS) id 14.3.319.2; Fri, 2 Mar 2018 07:51:24 -0800 Received: from shsmsx101.ccr.corp.intel.com (10.239.4.153) by FMSMSX119.amr.corp.intel.com (10.18.124.207) with Microsoft SMTP Server (TLS) id 14.3.319.2; Fri, 2 Mar 2018 07:51:23 -0800 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.125]) by SHSMSX101.ccr.corp.intel.com ([169.254.1.253]) with mapi id 14.03.0319.002; Fri, 2 Mar 2018 23:51:21 +0800 From: "Gao, Liming" To: Felix Polyudov , "edk2-devel@lists.01.org" CC: "Kinney, Michael D" , "manickavasakamk@ami.com" Thread-Topic: [Patch v3] MdePkg/Include/IndustryStandard: Add PCI Express 4.0 header file Thread-Index: AQHTsj3wKxF9zzxaC0STQ6xDjWUbM6O9GB5w Date: Fri, 2 Mar 2018 15:51:21 +0000 Message-ID: <4A89E2EF3DFEDB4C8BFDE51014F606A14E1D680A@SHSMSX104.ccr.corp.intel.com> References: <20180302154830.5396-1-felixp@ami.com> In-Reply-To: <20180302154830.5396-1-felixp@ami.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-version: 11.0.0.116 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [Patch v3] MdePkg/Include/IndustryStandard: Add PCI Express 4.0 header file X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 02 Mar 2018 15:45:16 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Liming Gao > -----Original Message----- > From: Felix Polyudov [mailto:felixp@ami.com] > Sent: Friday, March 2, 2018 11:49 PM > To: edk2-devel@lists.01.org > Cc: Kinney, Michael D ; Gao, Liming ; manickavasakamk@ami.com > Subject: [Patch v3] MdePkg/Include/IndustryStandard: Add PCI Express 4.0 = header file >=20 > v3: LaneEqualizationControl is changed to be an array. >=20 > v2: The structure is updated to include all the fields defined > in the PCI-E specification. >=20 > The header includes Physical Layer PCI Express Extended Capability defini= tions > described in section 7.7.5 of PCI Express Base Specification rev. 4.0. >=20 > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Felix Polyudov > --- > MdePkg/Include/IndustryStandard/PciExpress40.h | 89 ++++++++++++++++++++= ++++++ > 1 file changed, 89 insertions(+) > create mode 100644 MdePkg/Include/IndustryStandard/PciExpress40.h >=20 > diff --git a/MdePkg/Include/IndustryStandard/PciExpress40.h b/MdePkg/Incl= ude/IndustryStandard/PciExpress40.h > new file mode 100644 > index 0000000..6a7139f > --- /dev/null > +++ b/MdePkg/Include/IndustryStandard/PciExpress40.h > @@ -0,0 +1,89 @@ > +/** @file > +Support for the PCI Express 4.0 standard. > + > +This header file may not define all structures. Please extend as requir= ed. > + > +Copyright (c) 2018, American Megatrends, Inc. All rights reserved.
> +This program and the accompanying materials > +are licensed and made available under the terms and conditions of the BS= D License > +which accompanies this distribution. The full text of the license may b= e found at > +http://opensource.org/licenses/bsd-license.php > + > +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. > + > +**/ > + > +#ifndef _PCIEXPRESS40_H_ > +#define _PCIEXPRESS40_H_ > + > +#include > + > +#pragma pack(1) > + > +/// The Physical Layer PCI Express Extended Capability definitions. > +/// > +/// Based on section 7.7.5 of PCI Express Base Specification 4.0. > +///@{ > +#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_16_0_ID 0x0026 > +#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_16_0_VER1 0x1 > + > +// Register offsets from Physical Layer PCI-E Ext Cap Header > +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES_OFFSET = 0x04 > +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL_OFFSET = 0x08 > +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS_OFFSET = 0x0C > +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LOCAL_DATA_PARITY_STATUS_OFF= SET 0x10 > +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_FIRST_RETIMER_DATA_PARITY_ST= ATUS_OFFSET 0x14 > +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_SECOND_RETIMER_DATA_PARITY_S= TATUS_OFFSET 0x18 > +#define PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL_OF= FSET 0x20 > + > +typedef union { > + struct { > + UINT32 Reserved : 32; // Reserved bit 0:31 > + } Bits; > + UINT32 Uint32; > +} PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES; > + > +typedef union { > + struct { > + UINT32 Reserved : 32; // Reserved bit 0:31 > + } Bits; > + UINT32 Uint32; > +} PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL; > + > +typedef union { > + struct { > + UINT32 EqualizationComplete : 1; // bit 0 > + UINT32 EqualizationPhase1Success : 1; // bit 1 > + UINT32 EqualizationPhase2Success : 1; // bit 2 > + UINT32 EqualizationPhase3Success : 1; // bit 3 > + UINT32 LinkEqualizationRequest : 1; // bit 4 > + UINT32 Reserved : 27; // Reserved bit 5:31 > + } Bits; > + UINT32 Uint32; > +} PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS; > + > +typedef union { > + struct { > + UINT8 DownstreamPortTransmitterPreset : 4; //bit 0..3 > + UINT8 UpstreamPortTransmitterPreset : 4; //bit 4..7 > + } Bits; > + UINT8 Uint8; > +} PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL; > + > +typedef struct { > + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; > + PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CAPABILITIES Capablit= ies; > + PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_CONTROL Control; > + PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_STATUS Status; > + UINT32 LocalDat= aParityMismatchStatus; > + UINT32 FirstRet= imerDataParityMismatchStatus; > + UINT32 SecondRe= timerDataParityMismatchStatus; > + UINT32 Reserved= ; > + PCI_EXPRESS_REG_PHYSICAL_LAYER_16_0_LANE_EQUALIZATION_CONTROL LaneEqua= lizationControl[1]; > +} PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_16_0; > +///@} > + > +#pragma pack() > + > +#endif > -- > 2.10.0.windows.1 >=20 >=20 >=20 > Please consider the environment before printing this email. >=20 > The information contained in this message may be confidential and proprie= tary to American Megatrends, Inc. This communication is > intended to be read only by the individual or entity to whom it is addres= sed or by their designee. If the reader of this message is not the > intended recipient, you are on notice that any distribution of this messa= ge, in any form, is strictly prohibited. Please promptly notify > the sender by reply e-mail or by telephone at 770-246-8600, and then dele= te or destroy all copies of the transmission.