* [PATCH 21/37] MdePkg: Removing ipf which is no longer supported from edk2.
@ 2018-06-13 3:44 chenc2
2018-06-13 5:48 ` Gao, Liming
0 siblings, 1 reply; 2+ messages in thread
From: chenc2 @ 2018-06-13 3:44 UTC (permalink / raw)
To: edk2-devel; +Cc: chenc2, Liming Gao, Michael D Kinney
Removing rules for Ipf sources file:
* Remove the source file which path with "ipf" and also listed in
[Sources.IPF] section of INF file.
* Remove the source file which listed in [Components.IPF] section
of DSC file and not listed in any other [Components] section.
* Remove the embedded Ipf code for MDE_CPU_IPF.
Removing rules for Inf file:
* Remove IPF from VALID_ARCHITECTURES comments.
* Remove DXE_SAL_DRIVER from LIBRARY_CLASS in [Defines] section.
* Remove the INF which only listed in [Components.IPF] section in DSC.
* Remove statements from [BuildOptions] that provide IPF specific flags.
* Remove any IPF sepcific sections.
Removing rules for Dec file:
* Remove [Includes.IPF] section from Dec.
Removing rules for Dsc file:
* Remove IPF from SUPPORTED_ARCHITECTURES in [Defines] section of DSC.
* Remove any IPF specific sections.
* Remove statements from [BuildOptions] that provide IPF specific flags.
Cc: Liming Gao <liming.gao@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: chenc2 <chen.a.chen@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
---
MdePkg/Include/Ipf/IpfMacro.i | 58 -
MdePkg/Include/Ipf/ProcessorBind.h | 324 ---
MdePkg/Include/Library/BaseLib.h | 1442 ------------
MdePkg/Include/Protocol/PxeBaseCode.h | 2 -
MdePkg/Include/Uefi/UefiBaseType.h | 7 -
MdePkg/Include/Uefi/UefiSpec.h | 2 -
.../BaseCacheMaintenanceLib.inf | 8 +-
MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c | 242 --
MdePkg/Library/BaseCpuLib/BaseCpuLib.inf | 10 +-
MdePkg/Library/BaseCpuLib/Ipf/CpuFlushTlb.s | 58 -
MdePkg/Library/BaseCpuLib/Ipf/CpuSleep.c | 66 -
.../Library/BaseDebugLibNull/BaseDebugLibNull.inf | 2 +-
.../BaseDebugLibSerialPort.inf | 2 +-
.../BaseDebugPrintErrorLevelLib.inf | 2 +-
| 2 +-
.../BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf | 11 +-
MdePkg/Library/BaseIoLibIntrinsic/IoLibIpf.c | 736 -------
MdePkg/Library/BaseLib/BaseLib.inf | 35 +-
MdePkg/Library/BaseLib/BaseLibInternals.h | 920 --------
MdePkg/Library/BaseLib/Ipf/AccessDbr.s | 118 -
MdePkg/Library/BaseLib/Ipf/AccessEicr.s | 512 -----
MdePkg/Library/BaseLib/Ipf/AccessGcr.s | 274 ---
MdePkg/Library/BaseLib/Ipf/AccessGp.s | 86 -
MdePkg/Library/BaseLib/Ipf/AccessKr.s | 360 ---
MdePkg/Library/BaseLib/Ipf/AccessKr7.s | 63 -
MdePkg/Library/BaseLib/Ipf/AccessMsr.s | 79 -
MdePkg/Library/BaseLib/Ipf/AccessMsrDb.s | 121 -
MdePkg/Library/BaseLib/Ipf/AccessPmr.s | 124 --
MdePkg/Library/BaseLib/Ipf/AccessPsr.s | 111 -
MdePkg/Library/BaseLib/Ipf/Asm.h | 27 -
MdePkg/Library/BaseLib/Ipf/AsmCpuMisc.s | 79 -
MdePkg/Library/BaseLib/Ipf/AsmPalCall.s | 158 --
MdePkg/Library/BaseLib/Ipf/CpuBreakpoint.c | 96 -
MdePkg/Library/BaseLib/Ipf/CpuBreakpointMsc.c | 102 -
MdePkg/Library/BaseLib/Ipf/CpuPause.s | 25 -
MdePkg/Library/BaseLib/Ipf/ExecFc.s | 66 -
MdePkg/Library/BaseLib/Ipf/FlushCacheRange.c | 51 -
MdePkg/Library/BaseLib/Ipf/GetInterruptState.s | 27 -
MdePkg/Library/BaseLib/Ipf/Ia64gen.h | 205 --
.../Library/BaseLib/Ipf/InternalFlushCacheRange.s | 94 -
MdePkg/Library/BaseLib/Ipf/InternalSwitchStack.c | 64 -
MdePkg/Library/BaseLib/Ipf/LongJmp.s | 121 -
MdePkg/Library/BaseLib/Ipf/ReadAr.s | 109 -
MdePkg/Library/BaseLib/Ipf/ReadCpuid.s | 40 -
MdePkg/Library/BaseLib/Ipf/ReadCr.s | 102 -
MdePkg/Library/BaseLib/Ipf/SetJmp.s | 108 -
MdePkg/Library/BaseLib/Ipf/SwitchStack.s | 52 -
MdePkg/Library/BaseLib/Ipf/Unaligned.c | 243 ---
MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf | 2 +-
.../BaseOrderedCollectionRedBlackTreeLib.inf | 2 +-
MdePkg/Library/BasePalLibNull/BasePalLibNull.inf | 40 -
MdePkg/Library/BasePalLibNull/PalCall.c | 59 -
MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf | 2 +-
MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf | 2 +-
.../BasePciExpressLib/BasePciExpressLib.inf | 2 +-
MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf | 2 +-
.../BasePciLibPciExpress/BasePciLibPciExpress.inf | 2 +-
.../BasePciSegmentInfoLibNull.inf | 2 +-
.../BasePciSegmentLibPci/BasePciSegmentLibPci.inf | 2 +-
| 2 +-
.../BasePeCoffGetEntryPointLib.inf | 2 +-
MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf | 5 +-
MdePkg/Library/BasePeCoffLib/Ipf/PeCoffLoaderEx.c | 422 ----
.../BasePerformanceLibNull.inf | 2 +-
.../BasePostCodeLibDebug/BasePostCodeLibDebug.inf | 2 +-
.../BasePostCodeLibPort80.inf | 2 +-
MdePkg/Library/BasePrintLib/BasePrintLib.inf | 2 +-
.../BaseReportStatusCodeLibNull.inf | 2 +-
.../BaseS3BootScriptLibNull.inf | 2 +-
MdePkg/Library/BaseS3IoLib/BaseS3IoLib.inf | 2 +-
MdePkg/Library/BaseS3PciLib/BaseS3PciLib.inf | 2 +-
.../BaseS3PciSegmentLib/BaseS3PciSegmentLib.inf | 2 +-
MdePkg/Library/BaseS3SmbusLib/BaseS3SmbusLib.inf | 2 +-
MdePkg/Library/BaseS3StallLib/BaseS3StallLib.inf | 2 +-
MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf | 2 +-
.../BaseSerialPortLibNull.inf | 2 +-
.../Library/BaseSmbusLibNull/BaseSmbusLibNull.inf | 2 +-
.../BaseSynchronizationLib.inf | 15 +-
.../Ipf/InterlockedCompareExchange16.s | 30 -
.../Ipf/InterlockedCompareExchange32.s | 29 -
.../Ipf/InterlockedCompareExchange64.s | 28 -
.../Ipf/InternalGetSpinLockProperties.c | 29 -
.../BaseSynchronizationLib/Ipf/Synchronization.c | 77 -
.../BaseTimerLibNullTemplate.inf | 2 +-
.../BaseUefiDecompressLib.inf | 2 +-
.../DxeCoreEntryPoint/DxeCoreEntryPoint.inf | 2 +-
MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf | 2 +-
.../DxeExtendedSalLib/DxeExtendedSalLib.inf | 46 -
MdePkg/Library/DxeExtendedSalLib/ExtendedSalLib.c | 1001 ---------
.../DxeExtendedSalLib/Ipf/AsmExtendedSalLib.s | 97 -
| 4 +-
MdePkg/Library/DxeHobLib/DxeHobLib.inf | 4 +-
MdePkg/Library/DxeHstiLib/DxeHstiLib.inf | 2 +-
MdePkg/Library/DxeIoLibCpuIo2/DxeIoLibCpuIo2.inf | 4 +-
MdePkg/Library/DxeIoLibEsal/DxeIoLibEsal.inf | 49 -
MdePkg/Library/DxeIoLibEsal/DxeIoLibEsalInternal.h | 28 -
MdePkg/Library/DxeIoLibEsal/IoHighLevel.c | 2303 --------------------
MdePkg/Library/DxeIoLibEsal/IoLib.c | 879 --------
MdePkg/Library/DxeIoLibEsal/IoLibMmioBuffer.c | 411 ----
MdePkg/Library/DxePalLibEsal/DxePalLibEsal.c | 73 -
MdePkg/Library/DxePalLibEsal/DxePalLibEsal.inf | 41 -
MdePkg/Library/DxePcdLib/DxePcdLib.inf | 4 +-
MdePkg/Library/DxePciLibEsal/DxePciLibEsal.inf | 40 -
MdePkg/Library/DxePciLibEsal/PciLib.c | 1464 -------------
.../DxePciSegmentLibEsal/DxePciSegmentLibEsal.inf | 40 -
MdePkg/Library/DxePciSegmentLibEsal/PciLib.c | 1416 ------------
.../DxeRuntimeDebugLibSerialPort.inf | 2 +-
.../DxeRuntimeExtendedSalLib.inf | 52 -
.../DxeRuntimeExtendedSalLib/ExtendedSalLib.c | 1124 ----------
.../Ipf/AsmExtendedSalLib.s | 131 --
.../DxeRuntimePciExpressLib.inf | 2 +-
MdePkg/Library/DxeSalLibEsal/DxeSalLibEsal.c | 286 ---
MdePkg/Library/DxeSalLibEsal/DxeSalLibEsal.inf | 38 -
MdePkg/Library/DxeServicesLib/DxeServicesLib.inf | 6 +-
.../DxeServicesTableLib/DxeServicesTableLib.inf | 4 +-
MdePkg/Library/DxeSmbusLib/DxeSmbusLib.inf | 4 +-
MdePkg/Library/DxeTimerLibEsal/DxeTimerLibEsal.c | 223 --
MdePkg/Library/DxeTimerLibEsal/DxeTimerLibEsal.inf | 41 -
.../BasePciSegmentLibSegmentInfo.inf | 2 +-
.../DxeRuntimePciSegmentLibSegmentInfo.inf | 2 +-
.../PeiCoreEntryPoint/PeiCoreEntryPoint.inf | 2 +-
.../PeiDxePostCodeLibReportStatusCode.inf | 4 +-
| 2 +-
MdePkg/Library/PeiHobLib/PeiHobLib.inf | 2 +-
MdePkg/Library/PeiIoLibCpuIo/PeiIoLibCpuIo.inf | 2 +-
.../PeiMemoryAllocationLib.inf | 2 +-
MdePkg/Library/PeiMemoryLib/PeiMemoryLib.inf | 2 +-
MdePkg/Library/PeiPalLib/PeiPalLib.c | 99 -
MdePkg/Library/PeiPalLib/PeiPalLib.inf | 51 -
MdePkg/Library/PeiPcdLib/PeiPcdLib.inf | 2 +-
.../Library/PeiPciLibPciCfg2/PeiPciLibPciCfg2.inf | 2 +-
.../PeiPciSegmentLibPciCfg2.inf | 2 +-
.../PeiResourcePublicationLib.inf | 2 +-
MdePkg/Library/PeiServicesLib/PeiServicesLib.inf | 2 +-
.../PeiServicesTablePointerLib.inf | 2 +-
.../PeiServicesTablePointer.c | 91 -
.../PeiServicesTablePointerLibKr7.inf | 42 -
.../PeiSmbusLibSmbus2Ppi/PeiSmbusLibSmbus2Ppi.inf | 2 +-
MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf | 2 +-
MdePkg/Library/SecPeiDxeTimerLibCpu/IpfTimerLib.c | 216 --
.../SecPeiDxeTimerLibCpu/SecPeiDxeTimerLibCpu.inf | 10 +-
.../SmiHandlerProfileLibNull.inf | 2 +-
MdePkg/Library/SmmLibNull/SmmLibNull.inf | 2 +-
.../UefiApplicationEntryPoint.inf | 2 +-
.../UefiBootServicesTableLib.inf | 4 +-
.../UefiDebugLibConOut/UefiDebugLibConOut.inf | 4 +-
.../UefiDebugLibDebugPortProtocol.inf | 4 +-
.../UefiDebugLibStdErr/UefiDebugLibStdErr.inf | 4 +-
.../UefiDevicePathLib/UefiDevicePathLib.inf | 4 +-
...UefiDevicePathLibOptionalDevicePathProtocol.inf | 6 +-
.../UefiDevicePathLibDevicePathProtocol.inf | 4 +-
.../UefiDriverEntryPoint/UefiDriverEntryPoint.inf | 4 +-
.../UefiFileHandleLib/UefiFileHandleLib.inf | 2 +-
MdePkg/Library/UefiLib/UefiLib.inf | 4 +-
.../UefiMemoryAllocationLib.inf | 4 +-
MdePkg/Library/UefiMemoryLib/UefiMemoryLib.inf | 4 +-
MdePkg/Library/UefiPalLib/UefiPalLib.c | 127 --
MdePkg/Library/UefiPalLib/UefiPalLib.inf | 49 -
.../UefiPciLibPciRootBridgeIo.inf | 4 +-
.../UefiPciSegmentLibPciRootBridgeIo.inf | 4 +-
MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf | 4 +-
.../UefiRuntimeServicesTableLib.inf | 4 +-
MdePkg/Library/UefiSalLib/UefiSalLib.c | 139 --
MdePkg/Library/UefiSalLib/UefiSalLib.inf | 47 -
MdePkg/Library/UefiScsiLib/UefiScsiLib.inf | 4 +-
MdePkg/Library/UefiUsbLib/UefiUsbLib.inf | 4 +-
MdePkg/MdePkg.dec | 18 -
MdePkg/MdePkg.dsc | 41 +-
168 files changed, 116 insertions(+), 19085 deletions(-)
delete mode 100644 MdePkg/Include/Ipf/IpfMacro.i
delete mode 100644 MdePkg/Include/Ipf/ProcessorBind.h
delete mode 100644 MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c
delete mode 100644 MdePkg/Library/BaseCpuLib/Ipf/CpuFlushTlb.s
delete mode 100644 MdePkg/Library/BaseCpuLib/Ipf/CpuSleep.c
delete mode 100644 MdePkg/Library/BaseIoLibIntrinsic/IoLibIpf.c
delete mode 100644 MdePkg/Library/BaseLib/Ipf/AccessDbr.s
delete mode 100644 MdePkg/Library/BaseLib/Ipf/AccessEicr.s
delete mode 100644 MdePkg/Library/BaseLib/Ipf/AccessGcr.s
delete mode 100644 MdePkg/Library/BaseLib/Ipf/AccessGp.s
delete mode 100644 MdePkg/Library/BaseLib/Ipf/AccessKr.s
delete mode 100644 MdePkg/Library/BaseLib/Ipf/AccessKr7.s
delete mode 100644 MdePkg/Library/BaseLib/Ipf/AccessMsr.s
delete mode 100644 MdePkg/Library/BaseLib/Ipf/AccessMsrDb.s
delete mode 100644 MdePkg/Library/BaseLib/Ipf/AccessPmr.s
delete mode 100644 MdePkg/Library/BaseLib/Ipf/AccessPsr.s
delete mode 100644 MdePkg/Library/BaseLib/Ipf/Asm.h
delete mode 100644 MdePkg/Library/BaseLib/Ipf/AsmCpuMisc.s
delete mode 100644 MdePkg/Library/BaseLib/Ipf/AsmPalCall.s
delete mode 100644 MdePkg/Library/BaseLib/Ipf/CpuBreakpoint.c
delete mode 100644 MdePkg/Library/BaseLib/Ipf/CpuBreakpointMsc.c
delete mode 100644 MdePkg/Library/BaseLib/Ipf/CpuPause.s
delete mode 100644 MdePkg/Library/BaseLib/Ipf/ExecFc.s
delete mode 100644 MdePkg/Library/BaseLib/Ipf/FlushCacheRange.c
delete mode 100644 MdePkg/Library/BaseLib/Ipf/GetInterruptState.s
delete mode 100644 MdePkg/Library/BaseLib/Ipf/Ia64gen.h
delete mode 100644 MdePkg/Library/BaseLib/Ipf/InternalFlushCacheRange.s
delete mode 100644 MdePkg/Library/BaseLib/Ipf/InternalSwitchStack.c
delete mode 100644 MdePkg/Library/BaseLib/Ipf/LongJmp.s
delete mode 100644 MdePkg/Library/BaseLib/Ipf/ReadAr.s
delete mode 100644 MdePkg/Library/BaseLib/Ipf/ReadCpuid.s
delete mode 100644 MdePkg/Library/BaseLib/Ipf/ReadCr.s
delete mode 100644 MdePkg/Library/BaseLib/Ipf/SetJmp.s
delete mode 100644 MdePkg/Library/BaseLib/Ipf/SwitchStack.s
delete mode 100644 MdePkg/Library/BaseLib/Ipf/Unaligned.c
delete mode 100644 MdePkg/Library/BasePalLibNull/BasePalLibNull.inf
delete mode 100644 MdePkg/Library/BasePalLibNull/PalCall.c
delete mode 100644 MdePkg/Library/BasePeCoffLib/Ipf/PeCoffLoaderEx.c
delete mode 100644 MdePkg/Library/BaseSynchronizationLib/Ipf/InterlockedCompareExchange16.s
delete mode 100644 MdePkg/Library/BaseSynchronizationLib/Ipf/InterlockedCompareExchange32.s
delete mode 100644 MdePkg/Library/BaseSynchronizationLib/Ipf/InterlockedCompareExchange64.s
delete mode 100644 MdePkg/Library/BaseSynchronizationLib/Ipf/InternalGetSpinLockProperties.c
delete mode 100644 MdePkg/Library/BaseSynchronizationLib/Ipf/Synchronization.c
delete mode 100644 MdePkg/Library/DxeExtendedSalLib/DxeExtendedSalLib.inf
delete mode 100644 MdePkg/Library/DxeExtendedSalLib/ExtendedSalLib.c
delete mode 100644 MdePkg/Library/DxeExtendedSalLib/Ipf/AsmExtendedSalLib.s
delete mode 100644 MdePkg/Library/DxeIoLibEsal/DxeIoLibEsal.inf
delete mode 100644 MdePkg/Library/DxeIoLibEsal/DxeIoLibEsalInternal.h
delete mode 100644 MdePkg/Library/DxeIoLibEsal/IoHighLevel.c
delete mode 100644 MdePkg/Library/DxeIoLibEsal/IoLib.c
delete mode 100644 MdePkg/Library/DxeIoLibEsal/IoLibMmioBuffer.c
delete mode 100644 MdePkg/Library/DxePalLibEsal/DxePalLibEsal.c
delete mode 100644 MdePkg/Library/DxePalLibEsal/DxePalLibEsal.inf
delete mode 100644 MdePkg/Library/DxePciLibEsal/DxePciLibEsal.inf
delete mode 100644 MdePkg/Library/DxePciLibEsal/PciLib.c
delete mode 100644 MdePkg/Library/DxePciSegmentLibEsal/DxePciSegmentLibEsal.inf
delete mode 100644 MdePkg/Library/DxePciSegmentLibEsal/PciLib.c
delete mode 100644 MdePkg/Library/DxeRuntimeExtendedSalLib/DxeRuntimeExtendedSalLib.inf
delete mode 100644 MdePkg/Library/DxeRuntimeExtendedSalLib/ExtendedSalLib.c
delete mode 100644 MdePkg/Library/DxeRuntimeExtendedSalLib/Ipf/AsmExtendedSalLib.s
delete mode 100644 MdePkg/Library/DxeSalLibEsal/DxeSalLibEsal.c
delete mode 100644 MdePkg/Library/DxeSalLibEsal/DxeSalLibEsal.inf
delete mode 100644 MdePkg/Library/DxeTimerLibEsal/DxeTimerLibEsal.c
delete mode 100644 MdePkg/Library/DxeTimerLibEsal/DxeTimerLibEsal.inf
delete mode 100644 MdePkg/Library/PeiPalLib/PeiPalLib.c
delete mode 100644 MdePkg/Library/PeiPalLib/PeiPalLib.inf
delete mode 100644 MdePkg/Library/PeiServicesTablePointerLibKr7/PeiServicesTablePointer.c
delete mode 100644 MdePkg/Library/PeiServicesTablePointerLibKr7/PeiServicesTablePointerLibKr7.inf
delete mode 100644 MdePkg/Library/SecPeiDxeTimerLibCpu/IpfTimerLib.c
delete mode 100644 MdePkg/Library/UefiPalLib/UefiPalLib.c
delete mode 100644 MdePkg/Library/UefiPalLib/UefiPalLib.inf
delete mode 100644 MdePkg/Library/UefiSalLib/UefiSalLib.c
delete mode 100644 MdePkg/Library/UefiSalLib/UefiSalLib.inf
diff --git a/MdePkg/Include/Ipf/IpfMacro.i b/MdePkg/Include/Ipf/IpfMacro.i
deleted file mode 100644
index e66a63b83c..0000000000
--- a/MdePkg/Include/Ipf/IpfMacro.i
+++ /dev/null
@@ -1,58 +0,0 @@
-// @file
-// Contains the macros required by calling procedures in Itanium-based assembly code.
-//
-// Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
-// This program and the accompanying materials
-// are licensed and made available under the terms and conditions of the BSD License
-// which accompanies this distribution. The full text of the license may be found at
-// http://opensource.org/licenses/bsd-license.php
-//
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-//
-
-#ifndef __IA64PROC_I__
-#define __IA64PROC_I__
-
-//
-// Delcare the begin of assembly function entry.
-//
-// @param name Name of function in assembly code.
-//
-#define PROCEDURE_ENTRY(name) .##text; \
- .##type name, @function; \
- .##proc name; \
-name::
-
-//
-// End of assembly function.
-//
-// @param name Name of function in assembly code.
-//
-#define PROCEDURE_EXIT(name) .##endp name
-
-//
-// NESTED_SETUP Requires number of locals (l) >= 3
-//
-#define NESTED_SETUP(i,l,o,r) \
- alloc loc1=ar##.##pfs,i,l,o,r ;\
- mov loc0=b0
-
-//
-// End of Nested
-//
-#define NESTED_RETURN \
- mov b0=loc0 ;\
- mov ar##.##pfs=loc1 ;;\
- br##.##ret##.##dpnt b0;;
-
-//
-// Export assembly function as the global function.
-//
-// @param Function Name of function in assembly code.
-//
-#define GLOBAL_FUNCTION(Function) \
- .##type Function, @function; \
- .##globl Function
-
-#endif
diff --git a/MdePkg/Include/Ipf/ProcessorBind.h b/MdePkg/Include/Ipf/ProcessorBind.h
deleted file mode 100644
index bfbae01abb..0000000000
--- a/MdePkg/Include/Ipf/ProcessorBind.h
+++ /dev/null
@@ -1,324 +0,0 @@
-/** @file
- Processor or Compiler specific defines and types for Intel Itanium(TM) processors.
-
-Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials are licensed and made available
-under the terms and conditions of the BSD License which accompanies this
-distribution. The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#ifndef __PROCESSOR_BIND_H__
-#define __PROCESSOR_BIND_H__
-
-
-///
-/// Define the processor type so other code can make processor-based choices.
-///
-#define MDE_CPU_IPF
-
-
-//
-// Make sure we are using the correct packing rules per EFI specification
-//
-#pragma pack()
-
-
-#if defined(__INTEL_COMPILER)
-//
-// Disable ICC's remark #869: "Parameter" was never referenced warning.
-// This is legal ANSI C code so we disable the remark that is turned on with -Wall
-//
-#pragma warning ( disable : 869 )
-
-//
-// Disable ICC's remark #1418: external function definition with no prior declaration.
-// This is legal ANSI C code so we disable the remark that is turned on with /W4
-//
-#pragma warning ( disable : 1418 )
-
-//
-// Disable ICC's remark #1419: external declaration in primary source file
-// This is legal ANSI C code so we disable the remark that is turned on with /W4
-//
-#pragma warning ( disable : 1419 )
-
-//
-// Disable ICC's remark #593: "Variable" was set but never used.
-// This is legal ANSI C code so we disable the remark that is turned on with /W4
-//
-#pragma warning ( disable : 593 )
-
-#endif
-
-
-#if defined(_MSC_EXTENSIONS)
-//
-// Disable warning that make it impossible to compile at /W4
-// This only works for Microsoft* tools
-//
-
-//
-// Disabling bitfield type checking warnings.
-//
-#pragma warning ( disable : 4214 )
-
-//
-// Disabling the unreferenced formal parameter warnings.
-//
-#pragma warning ( disable : 4100 )
-
-//
-// Disable slightly different base types warning as CHAR8 * can not be set
-// to a constant string.
-//
-#pragma warning ( disable : 4057 )
-
-//
-// Disable warning on conversion from function pointer to a data pointer
-//
-#pragma warning ( disable : 4054 )
-
-//
-// ASSERT(FALSE) or while (TRUE) are legal constructs so suppress this warning
-//
-#pragma warning ( disable : 4127 )
-
-//
-// Can not cast a function pointer to a data pointer. We need to do this on
-// Itanium processors to get access to the PLABEL.
-//
-#pragma warning ( disable : 4514 )
-
-//
-// This warning is caused by functions defined but not used. For precompiled header only.
-//
-#pragma warning ( disable : 4505 )
-
-//
-// This warning is caused by empty (after preprocessing) source file. For precompiled header only.
-//
-#pragma warning ( disable : 4206 )
-
-#endif
-
-#if defined(_MSC_EXTENSIONS)
- //
- // use Microsoft C compiler dependent integer width types
- //
-
- ///
- /// 8-byte unsigned value.
- ///
- typedef unsigned __int64 UINT64;
- ///
- /// 8-byte signed value.
- ///
- typedef __int64 INT64;
- ///
- /// 4-byte unsigned value.
- ///
- typedef unsigned __int32 UINT32;
- ///
- /// 4-byte signed value.
- ///
- typedef __int32 INT32;
- ///
- /// 2-byte unsigned value.
- ///
- typedef unsigned short UINT16;
- ///
- /// 2-byte Character. Unless otherwise specified all strings are stored in the
- /// UTF-16 encoding format as defined by Unicode 2.1 and ISO/IEC 10646 standards.
- ///
- typedef unsigned short CHAR16;
- ///
- /// 2-byte signed value.
- ///
- typedef short INT16;
- ///
- /// Logical Boolean. 1-byte value containing 0 for FALSE or a 1 for TRUE. Other
- /// values are undefined.
- ///
- typedef unsigned char BOOLEAN;
- ///
- /// 1-byte unsigned value.
- ///
- typedef unsigned char UINT8;
- ///
- /// 1-byte Character.
- ///
- typedef char CHAR8;
- ///
- /// 1-byte signed value.
- ///
- typedef signed char INT8;
-#else
- ///
- /// 8-byte unsigned value.
- ///
- typedef unsigned long long UINT64;
- ///
- /// 8-byte signed value.
- ///
- typedef long long INT64;
- ///
- /// 4-byte unsigned value.
- ///
- typedef unsigned int UINT32;
- ///
- /// 4-byte signed value.
- ///
- typedef int INT32;
- ///
- /// 2-byte unsigned value.
- ///
- typedef unsigned short UINT16;
- ///
- /// 2-byte Character. Unless otherwise specified all strings are stored in the
- /// UTF-16 encoding format as defined by Unicode 2.1 and ISO/IEC 10646 standards.
- ///
- typedef unsigned short CHAR16;
- ///
- /// 2-byte signed value.
- ///
- typedef short INT16;
- ///
- /// Logical Boolean. 1-byte value containing 0 for FALSE or a 1 for TRUE. Other
- /// values are undefined.
- ///
- typedef unsigned char BOOLEAN;
- ///
- /// 1-byte unsigned value.
- ///
- typedef unsigned char UINT8;
- ///
- /// 1-byte Character.
- ///
- typedef char CHAR8;
- ///
- /// 1-byte signed value.
- ///
- typedef signed char INT8;
-#endif
-
-///
-/// Unsigned value of native width. (4 bytes on supported 32-bit processor instructions;
-/// 8 bytes on supported 64-bit processor instructions.)
-///
-typedef UINT64 UINTN;
-///
-/// Signed value of native width. (4 bytes on supported 32-bit processor instructions;
-/// 8 bytes on supported 64-bit processor instructions.)
-///
-typedef INT64 INTN;
-
-
-//
-// Processor specific defines
-//
-
-///
-/// A value of native width with the highest bit set.
-///
-#define MAX_BIT 0x8000000000000000ULL
-///
-/// A value of native width with the two highest bits set.
-///
-#define MAX_2_BITS 0xC000000000000000ULL
-
-///
-/// The maximum legal Itanium-based address
-///
-#define MAX_ADDRESS 0xFFFFFFFFFFFFFFFFULL
-
-///
-/// Maximum legal Itanium-based INTN and UINTN values.
-///
-#define MAX_INTN ((INTN)0x7FFFFFFFFFFFFFFFULL)
-#define MAX_UINTN ((UINTN)0xFFFFFFFFFFFFFFFFULL)
-
-///
-/// Minimum legal Itanium-based INTN value.
-///
-#define MIN_INTN (((INTN)-9223372036854775807LL) - 1)
-
-///
-/// Per the Itanium Software Conventions and Runtime Architecture Guide,
-/// section 3.3.4, IPF stack must always be 16-byte aligned.
-///
-#define CPU_STACK_ALIGNMENT 16
-
-///
-/// Page allocation granularity for Itanium
-///
-#define DEFAULT_PAGE_ALLOCATION_GRANULARITY (0x1000)
-#define RUNTIME_PAGE_ALLOCATION_GRANULARITY (0x2000)
-
-//
-// Modifier to ensure that all protocol member functions and EFI intrinsics
-// use the correct C calling convention. All protocol member functions and
-// EFI intrinsics are required to modify their member functions with EFIAPI.
-//
-#ifdef EFIAPI
- ///
- /// If EFIAPI is already defined, then we use that definition.
- ///
-#elif defined(_MSC_EXTENSIONS)
- ///
- /// Microsoft* compiler-specific method for EFIAPI calling convention.
- ///
- #define EFIAPI __cdecl
-#else
- #define EFIAPI
-#endif
-
-///
-/// For GNU assembly code, .global or .globl can declare global symbols.
-/// Define this macro to unify the usage.
-///
-#define ASM_GLOBAL .globl
-
-///
-/// A pointer to a function in IPF points to a plabel.
-///
-typedef struct {
- UINT64 EntryPoint;
- UINT64 GP;
-} EFI_PLABEL;
-
-///
-/// PAL Call return structure.
-///
-typedef struct {
- UINT64 Status;
- UINT64 r9;
- UINT64 r10;
- UINT64 r11;
-} PAL_CALL_RETURN;
-
-/**
- Return the pointer to the first instruction of a function given a function pointer.
- For Itanium processors, all function calls are made through a PLABEL, so a pointer to a function
- is actually a pointer to a PLABEL. The pointer to the first instruction of the function
- is contained within the PLABEL. This macro may be used to retrieve a pointer to the first
- instruction of a function independent of the CPU architecture being used. This is very
- useful when printing function addresses through DEBUG() macros.
-
- @param FunctionPointer A pointer to a function.
-
- @return The pointer to the first instruction of a function given a function pointer.
-
-**/
-#define FUNCTION_ENTRY_POINT(FunctionPointer) (VOID *)(UINTN)(((EFI_PLABEL *)(FunctionPointer))->EntryPoint)
-
-#ifndef __USER_LABEL_PREFIX__
-#define __USER_LABEL_PREFIX__
-#endif
-
-#endif
-
diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index eb2899f852..99b74e8650 100644
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -37,56 +37,6 @@ typedef struct {
#endif // defined (MDE_CPU_IA32)
-#if defined (MDE_CPU_IPF)
-
-///
-/// The Itanium architecture context buffer used by SetJump() and LongJump().
-///
-typedef struct {
- UINT64 F2[2];
- UINT64 F3[2];
- UINT64 F4[2];
- UINT64 F5[2];
- UINT64 F16[2];
- UINT64 F17[2];
- UINT64 F18[2];
- UINT64 F19[2];
- UINT64 F20[2];
- UINT64 F21[2];
- UINT64 F22[2];
- UINT64 F23[2];
- UINT64 F24[2];
- UINT64 F25[2];
- UINT64 F26[2];
- UINT64 F27[2];
- UINT64 F28[2];
- UINT64 F29[2];
- UINT64 F30[2];
- UINT64 F31[2];
- UINT64 R4;
- UINT64 R5;
- UINT64 R6;
- UINT64 R7;
- UINT64 SP;
- UINT64 BR0;
- UINT64 BR1;
- UINT64 BR2;
- UINT64 BR3;
- UINT64 BR4;
- UINT64 BR5;
- UINT64 InitialUNAT;
- UINT64 AfterSpillUNAT;
- UINT64 PFS;
- UINT64 BSP;
- UINT64 Predicates;
- UINT64 LoopCount;
- UINT64 FPSR;
-} BASE_LIBRARY_JUMP_BUFFER;
-
-#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 0x10
-
-#endif // defined (MDE_CPU_IPF)
-
#if defined (MDE_CPU_X64)
///
/// The x64 architecture context buffer used by SetJump() and LongJump().
@@ -5104,1398 +5054,6 @@ EFIAPI
CpuDeadLoop (
VOID
);
-
-#if defined (MDE_CPU_IPF)
-
-/**
- Flush a range of cache lines in the cache coherency domain of the calling
- CPU.
-
- Flushes the cache lines specified by Address and Length. If Address is not aligned
- on a cache line boundary, then entire cache line containing Address is flushed.
- If Address + Length is not aligned on a cache line boundary, then the entire cache
- line containing Address + Length - 1 is flushed. This function may choose to flush
- the entire cache if that is more efficient than flushing the specified range. If
- Length is 0, the no cache lines are flushed. Address is returned.
- This function is only available on Itanium processors.
-
- If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
-
- @param Address The base address of the instruction lines to invalidate. If
- the CPU is in a physical addressing mode, then Address is a
- physical address. If the CPU is in a virtual addressing mode,
- then Address is a virtual address.
-
- @param Length The number of bytes to invalidate from the instruction cache.
-
- @return Address.
-
-**/
-VOID *
-EFIAPI
-AsmFlushCacheRange (
- IN VOID *Address,
- IN UINTN Length
- );
-
-
-/**
- Executes an FC instruction.
- Executes an FC instruction on the cache line specified by Address.
- The cache line size affected is at least 32-bytes (aligned on a 32-byte boundary).
- An implementation may flush a larger region. This function is only available on Itanium processors.
-
- @param Address The Address of cache line to be flushed.
-
- @return The address of FC instruction executed.
-
-**/
-UINT64
-EFIAPI
-AsmFc (
- IN UINT64 Address
- );
-
-
-/**
- Executes an FC.I instruction.
- Executes an FC.I instruction on the cache line specified by Address.
- The cache line size affected is at least 32-bytes (aligned on a 32-byte boundary).
- An implementation may flush a larger region. This function is only available on Itanium processors.
-
- @param Address The Address of cache line to be flushed.
-
- @return The address of the FC.I instruction executed.
-
-**/
-UINT64
-EFIAPI
-AsmFci (
- IN UINT64 Address
- );
-
-
-/**
- Reads the current value of a Processor Identifier Register (CPUID).
-
- Reads and returns the current value of Processor Identifier Register specified by Index.
- The Index of largest implemented CPUID (One less than the number of implemented CPUID
- registers) is determined by CPUID [3] bits {7:0}.
- No parameter checking is performed on Index. If the Index value is beyond the
- implemented CPUID register range, a Reserved Register/Field fault may occur. The caller
- must either guarantee that Index is valid, or the caller must set up fault handlers to
- catch the faults. This function is only available on Itanium processors.
-
- @param Index The 8-bit Processor Identifier Register index to read.
-
- @return The current value of Processor Identifier Register specified by Index.
-
-**/
-UINT64
-EFIAPI
-AsmReadCpuid (
- IN UINT8 Index
- );
-
-
-/**
- Reads the current value of 64-bit Processor Status Register (PSR).
- This function is only available on Itanium processors.
-
- @return The current value of PSR.
-
-**/
-UINT64
-EFIAPI
-AsmReadPsr (
- VOID
- );
-
-
-/**
- Writes the current value of 64-bit Processor Status Register (PSR).
-
- No parameter checking is performed on Value. All bits of Value corresponding to
- reserved fields of PSR must be 0 or a Reserved Register/Field fault may occur.
- The caller must either guarantee that Value is valid, or the caller must set up
- fault handlers to catch the faults. This function is only available on Itanium processors.
-
- @param Value The 64-bit value to write to PSR.
-
- @return The 64-bit value written to the PSR.
-
-**/
-UINT64
-EFIAPI
-AsmWritePsr (
- IN UINT64 Value
- );
-
-
-/**
- Reads the current value of 64-bit Kernel Register #0 (KR0).
-
- Reads and returns the current value of KR0.
- This function is only available on Itanium processors.
-
- @return The current value of KR0.
-
-**/
-UINT64
-EFIAPI
-AsmReadKr0 (
- VOID
- );
-
-
-/**
- Reads the current value of 64-bit Kernel Register #1 (KR1).
-
- Reads and returns the current value of KR1.
- This function is only available on Itanium processors.
-
- @return The current value of KR1.
-
-**/
-UINT64
-EFIAPI
-AsmReadKr1 (
- VOID
- );
-
-
-/**
- Reads the current value of 64-bit Kernel Register #2 (KR2).
-
- Reads and returns the current value of KR2.
- This function is only available on Itanium processors.
-
- @return The current value of KR2.
-
-**/
-UINT64
-EFIAPI
-AsmReadKr2 (
- VOID
- );
-
-
-/**
- Reads the current value of 64-bit Kernel Register #3 (KR3).
-
- Reads and returns the current value of KR3.
- This function is only available on Itanium processors.
-
- @return The current value of KR3.
-
-**/
-UINT64
-EFIAPI
-AsmReadKr3 (
- VOID
- );
-
-
-/**
- Reads the current value of 64-bit Kernel Register #4 (KR4).
-
- Reads and returns the current value of KR4.
- This function is only available on Itanium processors.
-
- @return The current value of KR4.
-
-**/
-UINT64
-EFIAPI
-AsmReadKr4 (
- VOID
- );
-
-
-/**
- Reads the current value of 64-bit Kernel Register #5 (KR5).
-
- Reads and returns the current value of KR5.
- This function is only available on Itanium processors.
-
- @return The current value of KR5.
-
-**/
-UINT64
-EFIAPI
-AsmReadKr5 (
- VOID
- );
-
-
-/**
- Reads the current value of 64-bit Kernel Register #6 (KR6).
-
- Reads and returns the current value of KR6.
- This function is only available on Itanium processors.
-
- @return The current value of KR6.
-
-**/
-UINT64
-EFIAPI
-AsmReadKr6 (
- VOID
- );
-
-
-/**
- Reads the current value of 64-bit Kernel Register #7 (KR7).
-
- Reads and returns the current value of KR7.
- This function is only available on Itanium processors.
-
- @return The current value of KR7.
-
-**/
-UINT64
-EFIAPI
-AsmReadKr7 (
- VOID
- );
-
-
-/**
- Write the current value of 64-bit Kernel Register #0 (KR0).
-
- Writes the current value of KR0. The 64-bit value written to
- the KR0 is returned. This function is only available on Itanium processors.
-
- @param Value The 64-bit value to write to KR0.
-
- @return The 64-bit value written to the KR0.
-
-**/
-UINT64
-EFIAPI
-AsmWriteKr0 (
- IN UINT64 Value
- );
-
-
-/**
- Write the current value of 64-bit Kernel Register #1 (KR1).
-
- Writes the current value of KR1. The 64-bit value written to
- the KR1 is returned. This function is only available on Itanium processors.
-
- @param Value The 64-bit value to write to KR1.
-
- @return The 64-bit value written to the KR1.
-
-**/
-UINT64
-EFIAPI
-AsmWriteKr1 (
- IN UINT64 Value
- );
-
-
-/**
- Write the current value of 64-bit Kernel Register #2 (KR2).
-
- Writes the current value of KR2. The 64-bit value written to
- the KR2 is returned. This function is only available on Itanium processors.
-
- @param Value The 64-bit value to write to KR2.
-
- @return The 64-bit value written to the KR2.
-
-**/
-UINT64
-EFIAPI
-AsmWriteKr2 (
- IN UINT64 Value
- );
-
-
-/**
- Write the current value of 64-bit Kernel Register #3 (KR3).
-
- Writes the current value of KR3. The 64-bit value written to
- the KR3 is returned. This function is only available on Itanium processors.
-
- @param Value The 64-bit value to write to KR3.
-
- @return The 64-bit value written to the KR3.
-
-**/
-UINT64
-EFIAPI
-AsmWriteKr3 (
- IN UINT64 Value
- );
-
-
-/**
- Write the current value of 64-bit Kernel Register #4 (KR4).
-
- Writes the current value of KR4. The 64-bit value written to
- the KR4 is returned. This function is only available on Itanium processors.
-
- @param Value The 64-bit value to write to KR4.
-
- @return The 64-bit value written to the KR4.
-
-**/
-UINT64
-EFIAPI
-AsmWriteKr4 (
- IN UINT64 Value
- );
-
-
-/**
- Write the current value of 64-bit Kernel Register #5 (KR5).
-
- Writes the current value of KR5. The 64-bit value written to
- the KR5 is returned. This function is only available on Itanium processors.
-
- @param Value The 64-bit value to write to KR5.
-
- @return The 64-bit value written to the KR5.
-
-**/
-UINT64
-EFIAPI
-AsmWriteKr5 (
- IN UINT64 Value
- );
-
-
-/**
- Write the current value of 64-bit Kernel Register #6 (KR6).
-
- Writes the current value of KR6. The 64-bit value written to
- the KR6 is returned. This function is only available on Itanium processors.
-
- @param Value The 64-bit value to write to KR6.
-
- @return The 64-bit value written to the KR6.
-
-**/
-UINT64
-EFIAPI
-AsmWriteKr6 (
- IN UINT64 Value
- );
-
-
-/**
- Write the current value of 64-bit Kernel Register #7 (KR7).
-
- Writes the current value of KR7. The 64-bit value written to
- the KR7 is returned. This function is only available on Itanium processors.
-
- @param Value The 64-bit value to write to KR7.
-
- @return The 64-bit value written to the KR7.
-
-**/
-UINT64
-EFIAPI
-AsmWriteKr7 (
- IN UINT64 Value
- );
-
-
-/**
- Reads the current value of Interval Timer Counter Register (ITC).
-
- Reads and returns the current value of ITC.
- This function is only available on Itanium processors.
-
- @return The current value of ITC.
-
-**/
-UINT64
-EFIAPI
-AsmReadItc (
- VOID
- );
-
-
-/**
- Reads the current value of Interval Timer Vector Register (ITV).
-
- Reads and returns the current value of ITV.
- This function is only available on Itanium processors.
-
- @return The current value of ITV.
-
-**/
-UINT64
-EFIAPI
-AsmReadItv (
- VOID
- );
-
-
-/**
- Reads the current value of Interval Timer Match Register (ITM).
-
- Reads and returns the current value of ITM.
- This function is only available on Itanium processors.
-
- @return The current value of ITM.
-**/
-UINT64
-EFIAPI
-AsmReadItm (
- VOID
- );
-
-
-/**
- Writes the current value of 64-bit Interval Timer Counter Register (ITC).
-
- Writes the current value of ITC. The 64-bit value written to the ITC is returned.
- This function is only available on Itanium processors.
-
- @param Value The 64-bit value to write to ITC.
-
- @return The 64-bit value written to the ITC.
-
-**/
-UINT64
-EFIAPI
-AsmWriteItc (
- IN UINT64 Value
- );
-
-
-/**
- Writes the current value of 64-bit Interval Timer Match Register (ITM).
-
- Writes the current value of ITM. The 64-bit value written to the ITM is returned.
- This function is only available on Itanium processors.
-
- @param Value The 64-bit value to write to ITM.
-
- @return The 64-bit value written to the ITM.
-
-**/
-UINT64
-EFIAPI
-AsmWriteItm (
- IN UINT64 Value
- );
-
-
-/**
- Writes the current value of 64-bit Interval Timer Vector Register (ITV).
-
- Writes the current value of ITV. The 64-bit value written to the ITV is returned.
- No parameter checking is performed on Value. All bits of Value corresponding to
- reserved fields of ITV must be 0 or a Reserved Register/Field fault may occur.
- The caller must either guarantee that Value is valid, or the caller must set up
- fault handlers to catch the faults.
- This function is only available on Itanium processors.
-
- @param Value The 64-bit value to write to ITV.
-
- @return The 64-bit value written to the ITV.
-
-**/
-UINT64
-EFIAPI
-AsmWriteItv (
- IN UINT64 Value
- );
-
-
-/**
- Reads the current value of Default Control Register (DCR).
-
- Reads and returns the current value of DCR. This function is only available on Itanium processors.
-
- @return The current value of DCR.
-
-**/
-UINT64
-EFIAPI
-AsmReadDcr (
- VOID
- );
-
-
-/**
- Reads the current value of Interruption Vector Address Register (IVA).
-
- Reads and returns the current value of IVA. This function is only available on Itanium processors.
-
- @return The current value of IVA.
-**/
-UINT64
-EFIAPI
-AsmReadIva (
- VOID
- );
-
-
-/**
- Reads the current value of Page Table Address Register (PTA).
-
- Reads and returns the current value of PTA. This function is only available on Itanium processors.
-
- @return The current value of PTA.
-
-**/
-UINT64
-EFIAPI
-AsmReadPta (
- VOID
- );
-
-
-/**
- Writes the current value of 64-bit Default Control Register (DCR).
-
- Writes the current value of DCR. The 64-bit value written to the DCR is returned.
- No parameter checking is performed on Value. All bits of Value corresponding to
- reserved fields of DCR must be 0 or a Reserved Register/Field fault may occur.
- The caller must either guarantee that Value is valid, or the caller must set up
- fault handlers to catch the faults.
- This function is only available on Itanium processors.
-
- @param Value The 64-bit value to write to DCR.
-
- @return The 64-bit value written to the DCR.
-
-**/
-UINT64
-EFIAPI
-AsmWriteDcr (
- IN UINT64 Value
- );
-
-
-/**
- Writes the current value of 64-bit Interruption Vector Address Register (IVA).
-
- Writes the current value of IVA. The 64-bit value written to the IVA is returned.
- The size of vector table is 32 K bytes and is 32 K bytes aligned
- the low 15 bits of Value is ignored when written.
- This function is only available on Itanium processors.
-
- @param Value The 64-bit value to write to IVA.
-
- @return The 64-bit value written to the IVA.
-
-**/
-UINT64
-EFIAPI
-AsmWriteIva (
- IN UINT64 Value
- );
-
-
-/**
- Writes the current value of 64-bit Page Table Address Register (PTA).
-
- Writes the current value of PTA. The 64-bit value written to the PTA is returned.
- No parameter checking is performed on Value. All bits of Value corresponding to
- reserved fields of DCR must be 0 or a Reserved Register/Field fault may occur.
- The caller must either guarantee that Value is valid, or the caller must set up
- fault handlers to catch the faults.
- This function is only available on Itanium processors.
-
- @param Value The 64-bit value to write to PTA.
-
- @return The 64-bit value written to the PTA.
-**/
-UINT64
-EFIAPI
-AsmWritePta (
- IN UINT64 Value
- );
-
-
-/**
- Reads the current value of Local Interrupt ID Register (LID).
-
- Reads and returns the current value of LID. This function is only available on Itanium processors.
-
- @return The current value of LID.
-
-**/
-UINT64
-EFIAPI
-AsmReadLid (
- VOID
- );
-
-
-/**
- Reads the current value of External Interrupt Vector Register (IVR).
-
- Reads and returns the current value of IVR. This function is only available on Itanium processors.
-
- @return The current value of IVR.
-
-**/
-UINT64
-EFIAPI
-AsmReadIvr (
- VOID
- );
-
-
-/**
- Reads the current value of Task Priority Register (TPR).
-
- Reads and returns the current value of TPR. This function is only available on Itanium processors.
-
- @return The current value of TPR.
-
-**/
-UINT64
-EFIAPI
-AsmReadTpr (
- VOID
- );
-
-
-/**
- Reads the current value of External Interrupt Request Register #0 (IRR0).
-
- Reads and returns the current value of IRR0. This function is only available on Itanium processors.
-
- @return The current value of IRR0.
-
-**/
-UINT64
-EFIAPI
-AsmReadIrr0 (
- VOID
- );
-
-
-/**
- Reads the current value of External Interrupt Request Register #1 (IRR1).
-
- Reads and returns the current value of IRR1. This function is only available on Itanium processors.
-
- @return The current value of IRR1.
-
-**/
-UINT64
-EFIAPI
-AsmReadIrr1 (
- VOID
- );
-
-
-/**
- Reads the current value of External Interrupt Request Register #2 (IRR2).
-
- Reads and returns the current value of IRR2. This function is only available on Itanium processors.
-
- @return The current value of IRR2.
-
-**/
-UINT64
-EFIAPI
-AsmReadIrr2 (
- VOID
- );
-
-
-/**
- Reads the current value of External Interrupt Request Register #3 (IRR3).
-
- Reads and returns the current value of IRR3. This function is only available on Itanium processors.
-
- @return The current value of IRR3.
-
-**/
-UINT64
-EFIAPI
-AsmReadIrr3 (
- VOID
- );
-
-
-/**
- Reads the current value of Performance Monitor Vector Register (PMV).
-
- Reads and returns the current value of PMV. This function is only available on Itanium processors.
-
- @return The current value of PMV.
-
-**/
-UINT64
-EFIAPI
-AsmReadPmv (
- VOID
- );
-
-
-/**
- Reads the current value of Corrected Machine Check Vector Register (CMCV).
-
- Reads and returns the current value of CMCV. This function is only available on Itanium processors.
-
- @return The current value of CMCV.
-
-**/
-UINT64
-EFIAPI
-AsmReadCmcv (
- VOID
- );
-
-
-/**
- Reads the current value of Local Redirection Register #0 (LRR0).
-
- Reads and returns the current value of LRR0. This function is only available on Itanium processors.
-
- @return The current value of LRR0.
-
-**/
-UINT64
-EFIAPI
-AsmReadLrr0 (
- VOID
- );
-
-
-/**
- Reads the current value of Local Redirection Register #1 (LRR1).
-
- Reads and returns the current value of LRR1. This function is only available on Itanium processors.
-
- @return The current value of LRR1.
-
-**/
-UINT64
-EFIAPI
-AsmReadLrr1 (
- VOID
- );
-
-
-/**
- Writes the current value of 64-bit Page Local Interrupt ID Register (LID).
-
- Writes the current value of LID. The 64-bit value written to the LID is returned.
- No parameter checking is performed on Value. All bits of Value corresponding to
- reserved fields of LID must be 0 or a Reserved Register/Field fault may occur.
- The caller must either guarantee that Value is valid, or the caller must set up
- fault handlers to catch the faults.
- This function is only available on Itanium processors.
-
- @param Value The 64-bit value to write to LID.
-
- @return The 64-bit value written to the LID.
-
-**/
-UINT64
-EFIAPI
-AsmWriteLid (
- IN UINT64 Value
- );
-
-
-/**
- Writes the current value of 64-bit Task Priority Register (TPR).
-
- Writes the current value of TPR. The 64-bit value written to the TPR is returned.
- No parameter checking is performed on Value. All bits of Value corresponding to
- reserved fields of TPR must be 0 or a Reserved Register/Field fault may occur.
- The caller must either guarantee that Value is valid, or the caller must set up
- fault handlers to catch the faults.
- This function is only available on Itanium processors.
-
- @param Value The 64-bit value to write to TPR.
-
- @return The 64-bit value written to the TPR.
-
-**/
-UINT64
-EFIAPI
-AsmWriteTpr (
- IN UINT64 Value
- );
-
-
-/**
- Performs a write operation on End OF External Interrupt Register (EOI).
-
- Writes a value of 0 to the EOI Register. This function is only available on Itanium processors.
-
-**/
-VOID
-EFIAPI
-AsmWriteEoi (
- VOID
- );
-
-
-/**
- Writes the current value of 64-bit Performance Monitor Vector Register (PMV).
-
- Writes the current value of PMV. The 64-bit value written to the PMV is returned.
- No parameter checking is performed on Value. All bits of Value corresponding
- to reserved fields of PMV must be 0 or a Reserved Register/Field fault may occur.
- The caller must either guarantee that Value is valid, or the caller must set up
- fault handlers to catch the faults.
- This function is only available on Itanium processors.
-
- @param Value The 64-bit value to write to PMV.
-
- @return The 64-bit value written to the PMV.
-
-**/
-UINT64
-EFIAPI
-AsmWritePmv (
- IN UINT64 Value
- );
-
-
-/**
- Writes the current value of 64-bit Corrected Machine Check Vector Register (CMCV).
-
- Writes the current value of CMCV. The 64-bit value written to the CMCV is returned.
- No parameter checking is performed on Value. All bits of Value corresponding
- to reserved fields of CMCV must be 0 or a Reserved Register/Field fault may occur.
- The caller must either guarantee that Value is valid, or the caller must set up
- fault handlers to catch the faults.
- This function is only available on Itanium processors.
-
- @param Value The 64-bit value to write to CMCV.
-
- @return The 64-bit value written to the CMCV.
-
-**/
-UINT64
-EFIAPI
-AsmWriteCmcv (
- IN UINT64 Value
- );
-
-
-/**
- Writes the current value of 64-bit Local Redirection Register #0 (LRR0).
-
- Writes the current value of LRR0. The 64-bit value written to the LRR0 is returned.
- No parameter checking is performed on Value. All bits of Value corresponding
- to reserved fields of LRR0 must be 0 or a Reserved Register/Field fault may occur.
- The caller must either guarantee that Value is valid, or the caller must set up
- fault handlers to catch the faults.
- This function is only available on Itanium processors.
-
- @param Value The 64-bit value to write to LRR0.
-
- @return The 64-bit value written to the LRR0.
-
-**/
-UINT64
-EFIAPI
-AsmWriteLrr0 (
- IN UINT64 Value
- );
-
-
-/**
- Writes the current value of 64-bit Local Redirection Register #1 (LRR1).
-
- Writes the current value of LRR1. The 64-bit value written to the LRR1 is returned.
- No parameter checking is performed on Value. All bits of Value corresponding
- to reserved fields of LRR1 must be 0 or a Reserved Register/Field fault may occur.
- The caller must either guarantee that Value is valid, or the caller must
- set up fault handlers to catch the faults.
- This function is only available on Itanium processors.
-
- @param Value The 64-bit value to write to LRR1.
-
- @return The 64-bit value written to the LRR1.
-
-**/
-UINT64
-EFIAPI
-AsmWriteLrr1 (
- IN UINT64 Value
- );
-
-
-/**
- Reads the current value of Instruction Breakpoint Register (IBR).
-
- The Instruction Breakpoint Registers are used in pairs. The even numbered
- registers contain breakpoint addresses, and the odd numbered registers contain
- breakpoint mask conditions. At least four instruction registers pairs are implemented
- on all processor models. Implemented registers are contiguous starting with
- register 0. No parameter checking is performed on Index, and if the Index value
- is beyond the implemented IBR register range, a Reserved Register/Field fault may
- occur. The caller must either guarantee that Index is valid, or the caller must
- set up fault handlers to catch the faults.
- This function is only available on Itanium processors.
-
- @param Index The 8-bit Instruction Breakpoint Register index to read.
-
- @return The current value of Instruction Breakpoint Register specified by Index.
-
-**/
-UINT64
-EFIAPI
-AsmReadIbr (
- IN UINT8 Index
- );
-
-
-/**
- Reads the current value of Data Breakpoint Register (DBR).
-
- The Data Breakpoint Registers are used in pairs. The even numbered registers
- contain breakpoint addresses, and odd numbered registers contain breakpoint
- mask conditions. At least four data registers pairs are implemented on all processor
- models. Implemented registers are contiguous starting with register 0.
- No parameter checking is performed on Index. If the Index value is beyond
- the implemented DBR register range, a Reserved Register/Field fault may occur.
- The caller must either guarantee that Index is valid, or the caller must set up
- fault handlers to catch the faults.
- This function is only available on Itanium processors.
-
- @param Index The 8-bit Data Breakpoint Register index to read.
-
- @return The current value of Data Breakpoint Register specified by Index.
-
-**/
-UINT64
-EFIAPI
-AsmReadDbr (
- IN UINT8 Index
- );
-
-
-/**
- Reads the current value of Performance Monitor Configuration Register (PMC).
-
- All processor implementations provide at least four performance counters
- (PMC/PMD [4]...PMC/PMD [7] pairs), and four performance monitor counter overflow
- status registers (PMC [0]... PMC [3]). Processor implementations may provide
- additional implementation-dependent PMC and PMD to increase the number of
- 'generic' performance counters (PMC/PMD pairs). The remainder of PMC and PMD
- register set is implementation dependent. No parameter checking is performed
- on Index. If the Index value is beyond the implemented PMC register range,
- zero value will be returned.
- This function is only available on Itanium processors.
-
- @param Index The 8-bit Performance Monitor Configuration Register index to read.
-
- @return The current value of Performance Monitor Configuration Register
- specified by Index.
-
-**/
-UINT64
-EFIAPI
-AsmReadPmc (
- IN UINT8 Index
- );
-
-
-/**
- Reads the current value of Performance Monitor Data Register (PMD).
-
- All processor implementations provide at least 4 performance counters
- (PMC/PMD [4]...PMC/PMD [7] pairs), and 4 performance monitor counter
- overflow status registers (PMC [0]... PMC [3]). Processor implementations may
- provide additional implementation-dependent PMC and PMD to increase the number
- of 'generic' performance counters (PMC/PMD pairs). The remainder of PMC and PMD
- register set is implementation dependent. No parameter checking is performed
- on Index. If the Index value is beyond the implemented PMD register range,
- zero value will be returned.
- This function is only available on Itanium processors.
-
- @param Index The 8-bit Performance Monitor Data Register index to read.
-
- @return The current value of Performance Monitor Data Register specified by Index.
-
-**/
-UINT64
-EFIAPI
-AsmReadPmd (
- IN UINT8 Index
- );
-
-
-/**
- Writes the current value of 64-bit Instruction Breakpoint Register (IBR).
-
- Writes current value of Instruction Breakpoint Register specified by Index.
- The Instruction Breakpoint Registers are used in pairs. The even numbered
- registers contain breakpoint addresses, and odd numbered registers contain
- breakpoint mask conditions. At least four instruction registers pairs are implemented
- on all processor models. Implemented registers are contiguous starting with
- register 0. No parameter checking is performed on Index. If the Index value
- is beyond the implemented IBR register range, a Reserved Register/Field fault may
- occur. The caller must either guarantee that Index is valid, or the caller must
- set up fault handlers to catch the faults.
- This function is only available on Itanium processors.
-
- @param Index The 8-bit Instruction Breakpoint Register index to write.
- @param Value The 64-bit value to write to IBR.
-
- @return The 64-bit value written to the IBR.
-
-**/
-UINT64
-EFIAPI
-AsmWriteIbr (
- IN UINT8 Index,
- IN UINT64 Value
- );
-
-
-/**
- Writes the current value of 64-bit Data Breakpoint Register (DBR).
-
- Writes current value of Data Breakpoint Register specified by Index.
- The Data Breakpoint Registers are used in pairs. The even numbered registers
- contain breakpoint addresses, and odd numbered registers contain breakpoint
- mask conditions. At least four data registers pairs are implemented on all processor
- models. Implemented registers are contiguous starting with register 0. No parameter
- checking is performed on Index. If the Index value is beyond the implemented
- DBR register range, a Reserved Register/Field fault may occur. The caller must
- either guarantee that Index is valid, or the caller must set up fault handlers to
- catch the faults.
- This function is only available on Itanium processors.
-
- @param Index The 8-bit Data Breakpoint Register index to write.
- @param Value The 64-bit value to write to DBR.
-
- @return The 64-bit value written to the DBR.
-
-**/
-UINT64
-EFIAPI
-AsmWriteDbr (
- IN UINT8 Index,
- IN UINT64 Value
- );
-
-
-/**
- Writes the current value of 64-bit Performance Monitor Configuration Register (PMC).
-
- Writes current value of Performance Monitor Configuration Register specified by Index.
- All processor implementations provide at least four performance counters
- (PMC/PMD [4]...PMC/PMD [7] pairs), and four performance monitor counter overflow status
- registers (PMC [0]... PMC [3]). Processor implementations may provide additional
- implementation-dependent PMC and PMD to increase the number of 'generic' performance
- counters (PMC/PMD pairs). The remainder of PMC and PMD register set is implementation
- dependent. No parameter checking is performed on Index. If the Index value is
- beyond the implemented PMC register range, the write is ignored.
- This function is only available on Itanium processors.
-
- @param Index The 8-bit Performance Monitor Configuration Register index to write.
- @param Value The 64-bit value to write to PMC.
-
- @return The 64-bit value written to the PMC.
-
-**/
-UINT64
-EFIAPI
-AsmWritePmc (
- IN UINT8 Index,
- IN UINT64 Value
- );
-
-
-/**
- Writes the current value of 64-bit Performance Monitor Data Register (PMD).
-
- Writes current value of Performance Monitor Data Register specified by Index.
- All processor implementations provide at least four performance counters
- (PMC/PMD [4]...PMC/PMD [7] pairs), and four performance monitor counter overflow
- status registers (PMC [0]... PMC [3]). Processor implementations may provide
- additional implementation-dependent PMC and PMD to increase the number of 'generic'
- performance counters (PMC/PMD pairs). The remainder of PMC and PMD register set
- is implementation dependent. No parameter checking is performed on Index. If the
- Index value is beyond the implemented PMD register range, the write is ignored.
- This function is only available on Itanium processors.
-
- @param Index The 8-bit Performance Monitor Data Register index to write.
- @param Value The 64-bit value to write to PMD.
-
- @return The 64-bit value written to the PMD.
-
-**/
-UINT64
-EFIAPI
-AsmWritePmd (
- IN UINT8 Index,
- IN UINT64 Value
- );
-
-
-/**
- Reads the current value of 64-bit Global Pointer (GP).
-
- Reads and returns the current value of GP.
- This function is only available on Itanium processors.
-
- @return The current value of GP.
-
-**/
-UINT64
-EFIAPI
-AsmReadGp (
- VOID
- );
-
-
-/**
- Write the current value of 64-bit Global Pointer (GP).
-
- Writes the current value of GP. The 64-bit value written to the GP is returned.
- No parameter checking is performed on Value.
- This function is only available on Itanium processors.
-
- @param Value The 64-bit value to write to GP.
-
- @return The 64-bit value written to the GP.
-
-**/
-UINT64
-EFIAPI
-AsmWriteGp (
- IN UINT64 Value
- );
-
-
-/**
- Reads the current value of 64-bit Stack Pointer (SP).
-
- Reads and returns the current value of SP.
- This function is only available on Itanium processors.
-
- @return The current value of SP.
-
-**/
-UINT64
-EFIAPI
-AsmReadSp (
- VOID
- );
-
-
-///
-/// Valid Index value for AsmReadControlRegister().
-///
-#define IPF_CONTROL_REGISTER_DCR 0
-#define IPF_CONTROL_REGISTER_ITM 1
-#define IPF_CONTROL_REGISTER_IVA 2
-#define IPF_CONTROL_REGISTER_PTA 8
-#define IPF_CONTROL_REGISTER_IPSR 16
-#define IPF_CONTROL_REGISTER_ISR 17
-#define IPF_CONTROL_REGISTER_IIP 19
-#define IPF_CONTROL_REGISTER_IFA 20
-#define IPF_CONTROL_REGISTER_ITIR 21
-#define IPF_CONTROL_REGISTER_IIPA 22
-#define IPF_CONTROL_REGISTER_IFS 23
-#define IPF_CONTROL_REGISTER_IIM 24
-#define IPF_CONTROL_REGISTER_IHA 25
-#define IPF_CONTROL_REGISTER_LID 64
-#define IPF_CONTROL_REGISTER_IVR 65
-#define IPF_CONTROL_REGISTER_TPR 66
-#define IPF_CONTROL_REGISTER_EOI 67
-#define IPF_CONTROL_REGISTER_IRR0 68
-#define IPF_CONTROL_REGISTER_IRR1 69
-#define IPF_CONTROL_REGISTER_IRR2 70
-#define IPF_CONTROL_REGISTER_IRR3 71
-#define IPF_CONTROL_REGISTER_ITV 72
-#define IPF_CONTROL_REGISTER_PMV 73
-#define IPF_CONTROL_REGISTER_CMCV 74
-#define IPF_CONTROL_REGISTER_LRR0 80
-#define IPF_CONTROL_REGISTER_LRR1 81
-
-/**
- Reads a 64-bit control register.
-
- Reads and returns the control register specified by Index. The valid Index valued
- are defined above in "Related Definitions".
- If Index is invalid then 0xFFFFFFFFFFFFFFFF is returned. This function is only
- available on Itanium processors.
-
- @param Index The index of the control register to read.
-
- @return The control register specified by Index.
-
-**/
-UINT64
-EFIAPI
-AsmReadControlRegister (
- IN UINT64 Index
- );
-
-
-///
-/// Valid Index value for AsmReadApplicationRegister().
-///
-#define IPF_APPLICATION_REGISTER_K0 0
-#define IPF_APPLICATION_REGISTER_K1 1
-#define IPF_APPLICATION_REGISTER_K2 2
-#define IPF_APPLICATION_REGISTER_K3 3
-#define IPF_APPLICATION_REGISTER_K4 4
-#define IPF_APPLICATION_REGISTER_K5 5
-#define IPF_APPLICATION_REGISTER_K6 6
-#define IPF_APPLICATION_REGISTER_K7 7
-#define IPF_APPLICATION_REGISTER_RSC 16
-#define IPF_APPLICATION_REGISTER_BSP 17
-#define IPF_APPLICATION_REGISTER_BSPSTORE 18
-#define IPF_APPLICATION_REGISTER_RNAT 19
-#define IPF_APPLICATION_REGISTER_FCR 21
-#define IPF_APPLICATION_REGISTER_EFLAG 24
-#define IPF_APPLICATION_REGISTER_CSD 25
-#define IPF_APPLICATION_REGISTER_SSD 26
-#define IPF_APPLICATION_REGISTER_CFLG 27
-#define IPF_APPLICATION_REGISTER_FSR 28
-#define IPF_APPLICATION_REGISTER_FIR 29
-#define IPF_APPLICATION_REGISTER_FDR 30
-#define IPF_APPLICATION_REGISTER_CCV 32
-#define IPF_APPLICATION_REGISTER_UNAT 36
-#define IPF_APPLICATION_REGISTER_FPSR 40
-#define IPF_APPLICATION_REGISTER_ITC 44
-#define IPF_APPLICATION_REGISTER_PFS 64
-#define IPF_APPLICATION_REGISTER_LC 65
-#define IPF_APPLICATION_REGISTER_EC 66
-
-/**
- Reads a 64-bit application register.
-
- Reads and returns the application register specified by Index. The valid Index
- valued are defined above in "Related Definitions".
- If Index is invalid then 0xFFFFFFFFFFFFFFFF is returned. This function is only
- available on Itanium processors.
-
- @param Index The index of the application register to read.
-
- @return The application register specified by Index.
-
-**/
-UINT64
-EFIAPI
-AsmReadApplicationRegister (
- IN UINT64 Index
- );
-
-
-/**
- Reads the current value of a Machine Specific Register (MSR).
-
- Reads and returns the current value of the Machine Specific Register specified by Index. No
- parameter checking is performed on Index, and if the Index value is beyond the implemented MSR
- register range, a Reserved Register/Field fault may occur. The caller must either guarantee that
- Index is valid, or the caller must set up fault handlers to catch the faults. This function is
- only available on Itanium processors.
-
- @param Index The 8-bit Machine Specific Register index to read.
-
- @return The current value of the Machine Specific Register specified by Index.
-
-**/
-UINT64
-EFIAPI
-AsmReadMsr (
- IN UINT8 Index
- );
-
-
-/**
- Writes the current value of a Machine Specific Register (MSR).
-
- Writes Value to the Machine Specific Register specified by Index. Value is returned. No
- parameter checking is performed on Index, and if the Index value is beyond the implemented MSR
- register range, a Reserved Register/Field fault may occur. The caller must either guarantee that
- Index is valid, or the caller must set up fault handlers to catch the faults. This function is
- only available on Itanium processors.
-
- @param Index The 8-bit Machine Specific Register index to write.
- @param Value The 64-bit value to write to the Machine Specific Register.
-
- @return The 64-bit value to write to the Machine Specific Register.
-
-**/
-UINT64
-EFIAPI
-AsmWriteMsr (
- IN UINT8 Index,
- IN UINT64 Value
- );
-
-
-/**
- Determines if the CPU is currently executing in virtual, physical, or mixed mode.
-
- Determines the current execution mode of the CPU.
- If the CPU is in virtual mode(PSR.RT=1, PSR.DT=1, PSR.IT=1), then 1 is returned.
- If the CPU is in physical mode(PSR.RT=0, PSR.DT=0, PSR.IT=0), then 0 is returned.
- If the CPU is not in physical mode or virtual mode, then it is in mixed mode,
- and -1 is returned.
- This function is only available on Itanium processors.
-
- @retval 1 The CPU is in virtual mode.
- @retval 0 The CPU is in physical mode.
- @retval -1 The CPU is in mixed mode.
-
-**/
-INT64
-EFIAPI
-AsmCpuVirtual (
- VOID
- );
-
-
-/**
- Makes a PAL procedure call.
-
- This is a wrapper function to make a PAL procedure call. Based on the Index
- value this API will make static or stacked PAL call. The following table
- describes the usage of PAL Procedure Index Assignment. Architected procedures
- may be designated as required or optional. If a PAL procedure is specified
- as optional, a unique return code of 0xFFFFFFFFFFFFFFFF is returned in the
- Status field of the PAL_CALL_RETURN structure.
- This indicates that the procedure is not present in this PAL implementation.
- It is the caller's responsibility to check for this return code after calling
- any optional PAL procedure.
- No parameter checking is performed on the 5 input parameters, but there are
- some common rules that the caller should follow when making a PAL call. Any
- address passed to PAL as buffers for return parameters must be 8-byte aligned.
- Unaligned addresses may cause undefined results. For those parameters defined
- as reserved or some fields defined as reserved must be zero filled or the invalid
- argument return value may be returned or undefined result may occur during the
- execution of the procedure. If the PalEntryPoint does not point to a valid
- PAL entry point then the system behavior is undefined. This function is only
- available on Itanium processors.
-
- @param PalEntryPoint The PAL procedure calls entry point.
- @param Index The PAL procedure Index number.
- @param Arg2 The 2nd parameter for PAL procedure calls.
- @param Arg3 The 3rd parameter for PAL procedure calls.
- @param Arg4 The 4th parameter for PAL procedure calls.
-
- @return structure returned from the PAL Call procedure, including the status and return value.
-
-**/
-PAL_CALL_RETURN
-EFIAPI
-AsmPalCall (
- IN UINT64 PalEntryPoint,
- IN UINT64 Index,
- IN UINT64 Arg2,
- IN UINT64 Arg3,
- IN UINT64 Arg4
- );
-#endif // defined (MDE_CPU_IPF)
#if defined (MDE_CPU_IA32) || defined (MDE_CPU_X64)
///
diff --git a/MdePkg/Include/Protocol/PxeBaseCode.h b/MdePkg/Include/Protocol/PxeBaseCode.h
index 7cef457374..bf9af68ab1 100644
--- a/MdePkg/Include/Protocol/PxeBaseCode.h
+++ b/MdePkg/Include/Protocol/PxeBaseCode.h
@@ -153,8 +153,6 @@ typedef UINT16 EFI_PXE_BASE_CODE_UDP_PORT;
//
#if defined (MDE_CPU_IA32)
#define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x0006
-#elif defined (MDE_CPU_IPF)
-#define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x0002
#elif defined (MDE_CPU_X64)
#define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x0007
#elif defined (MDE_CPU_ARM)
diff --git a/MdePkg/Include/Uefi/UefiBaseType.h b/MdePkg/Include/Uefi/UefiBaseType.h
index d9556cd2ec..fa5b36b565 100644
--- a/MdePkg/Include/Uefi/UefiBaseType.h
+++ b/MdePkg/Include/Uefi/UefiBaseType.h
@@ -254,13 +254,6 @@ typedef union {
#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) ((Machine) == EFI_IMAGE_MACHINE_X64)
-#elif defined (MDE_CPU_IPF)
-
-#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \
- (((Machine) == EFI_IMAGE_MACHINE_IA64) || ((Machine) == EFI_IMAGE_MACHINE_EBC))
-
-#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE)
-
#elif defined (MDE_CPU_X64)
#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \
diff --git a/MdePkg/Include/Uefi/UefiSpec.h b/MdePkg/Include/Uefi/UefiSpec.h
index ee016b48de..17b89416e5 100644
--- a/MdePkg/Include/Uefi/UefiSpec.h
+++ b/MdePkg/Include/Uefi/UefiSpec.h
@@ -2190,8 +2190,6 @@ typedef struct {
#if defined (MDE_CPU_IA32)
#define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_IA32
-#elif defined (MDE_CPU_IPF)
- #define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_IA64
#elif defined (MDE_CPU_X64)
#define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_X64
#elif defined (MDE_CPU_EBC)
diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
index d659161f33..df082eb413 100644
--- a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
@@ -28,7 +28,7 @@
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC ARM AARCH64
+# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64
#
[Sources.IA32]
@@ -37,9 +37,6 @@
[Sources.X64]
X86Cache.c
-[Sources.IPF]
- IpfCache.c
-
[Sources.EBC]
EbcCache.c
@@ -56,6 +53,3 @@
BaseLib
DebugLib
-[LibraryClasses.Ipf]
- PalLib
-
diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c b/MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c
deleted file mode 100644
index 24e985174e..0000000000
--- a/MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c
+++ /dev/null
@@ -1,242 +0,0 @@
-/** @file
- Cache Maintenance Functions.
-
- Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php.
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include <Base.h>
-#include <Library/CacheMaintenanceLib.h>
-#include <Library/BaseLib.h>
-#include <Library/DebugLib.h>
-#include <Library/PalLib.h>
-
-/**
- Invalidates the entire instruction cache in cache coherency domain of the
- calling CPU.
-
-**/
-VOID
-EFIAPI
-InvalidateInstructionCache (
- VOID
- )
-{
- PalCall (PAL_CACHE_FLUSH, PAL_CACHE_FLUSH_INSTRUCTION_ALL, PAL_CACHE_FLUSH_INVALIDATE_LINES | PAL_CACHE_FLUSH_NO_INTERRUPT, 0);
-}
-
-/**
- Invalidates a range of instruction cache lines in the cache coherency domain
- of the calling CPU.
-
- Invalidates the instruction cache lines specified by Address and Length. If
- Address is not aligned on a cache line boundary, then entire instruction
- cache line containing Address is invalidated. If Address + Length is not
- aligned on a cache line boundary, then the entire instruction cache line
- containing Address + Length -1 is invalidated. This function may choose to
- invalidate the entire instruction cache if that is more efficient than
- invalidating the specified range. If Length is 0, then no instruction cache
- lines are invalidated. Address is returned.
-
- If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
-
- @param Address The base address of the instruction cache lines to
- invalidate. If the CPU is in a physical addressing mode, then
- Address is a physical address. If the CPU is in a virtual
- addressing mode, then Address is a virtual address.
-
- @param Length The number of bytes to invalidate from the instruction cache.
-
- @return Address.
-
-**/
-VOID *
-EFIAPI
-InvalidateInstructionCacheRange (
- IN VOID *Address,
- IN UINTN Length
- )
-{
- return AsmFlushCacheRange (Address, Length);
-}
-
-/**
- Writes back and invalidates the entire data cache in cache coherency domain
- of the calling CPU.
-
- Writes back and invalidates the entire data cache in cache coherency domain
- of the calling CPU. This function guarantees that all dirty cache lines are
- written back to system memory, and also invalidates all the data cache lines
- in the cache coherency domain of the calling CPU.
-
-**/
-VOID
-EFIAPI
-WriteBackInvalidateDataCache (
- VOID
- )
-{
- PalCall (PAL_CACHE_FLUSH, PAL_CACHE_FLUSH_DATA_ALL, PAL_CACHE_FLUSH_INVALIDATE_LINES | PAL_CACHE_FLUSH_NO_INTERRUPT, 0);
-}
-
-/**
- Writes back and invalidates a range of data cache lines in the cache
- coherency domain of the calling CPU.
-
- Writes back and invalidates the data cache lines specified by Address and
- Length. If Address is not aligned on a cache line boundary, then entire data
- cache line containing Address is written back and invalidated. If Address +
- Length is not aligned on a cache line boundary, then the entire data cache
- line containing Address + Length -1 is written back and invalidated. This
- function may choose to write back and invalidate the entire data cache if
- that is more efficient than writing back and invalidating the specified
- range. If Length is 0, then no data cache lines are written back and
- invalidated. Address is returned.
-
- If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
-
- @param Address The base address of the data cache lines to write back and
- invalidate. If the CPU is in a physical addressing mode, then
- Address is a physical address. If the CPU is in a virtual
- addressing mode, then Address is a virtual address.
- @param Length The number of bytes to write back and invalidate from the
- data cache.
-
- @return Address of cache invalidation.
-
-**/
-VOID *
-EFIAPI
-WriteBackInvalidateDataCacheRange (
- IN VOID *Address,
- IN UINTN Length
- )
-{
- return AsmFlushCacheRange (Address, Length);
-}
-
-/**
- Writes Back the entire data cache in cache coherency domain of the calling
- CPU.
-
- Writes Back the entire data cache in cache coherency domain of the calling
- CPU. This function guarantees that all dirty cache lines are written back to
- system memory. This function may also invalidate all the data cache lines in
- the cache coherency domain of the calling CPU.
-
-**/
-VOID
-EFIAPI
-WriteBackDataCache (
- VOID
- )
-{
- PalCall (PAL_CACHE_FLUSH, PAL_CACHE_FLUSH_DATA_ALL, PAL_CACHE_FLUSH_NO_INVALIDATE_LINES | PAL_CACHE_FLUSH_NO_INTERRUPT, 0);
-}
-
-/**
- Writes Back a range of data cache lines in the cache coherency domain of the
- calling CPU.
-
- Writes Back the data cache lines specified by Address and Length. If Address
- is not aligned on a cache line boundary, then entire data cache line
- containing Address is written back. If Address + Length is not aligned on a
- cache line boundary, then the entire data cache line containing Address +
- Length -1 is written back. This function may choose to write back the entire
- data cache if that is more efficient than writing back the specified range.
- If Length is 0, then no data cache lines are written back. This function may
- also invalidate all the data cache lines in the specified range of the cache
- coherency domain of the calling CPU. Address is returned.
-
- If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
-
- @param Address The base address of the data cache lines to write back. If
- the CPU is in a physical addressing mode, then Address is a
- physical address. If the CPU is in a virtual addressing
- mode, then Address is a virtual address.
- @param Length The number of bytes to write back from the data cache.
-
- @return Address of cache written in main memory.
-
-**/
-VOID *
-EFIAPI
-WriteBackDataCacheRange (
- IN VOID *Address,
- IN UINTN Length
- )
-{
- return AsmFlushCacheRange (Address, Length);
-}
-
-/**
- Invalidates the entire data cache in cache coherency domain of the calling
- CPU.
-
- Invalidates the entire data cache in cache coherency domain of the calling
- CPU. This function must be used with care because dirty cache lines are not
- written back to system memory. It is typically used for cache diagnostics. If
- the CPU does not support invalidation of the entire data cache, then a write
- back and invalidate operation should be performed on the entire data cache.
-
-**/
-VOID
-EFIAPI
-InvalidateDataCache (
- VOID
- )
-{
- //
- // Invalidation of the entire data cache without writing back is not supported
- // on IPF architecture, so a write back and invalidate operation is performed.
- //
- WriteBackInvalidateDataCache ();
-}
-
-/**
- Invalidates a range of data cache lines in the cache coherency domain of the
- calling CPU.
-
- Invalidates the data cache lines specified by Address and Length. If Address
- is not aligned on a cache line boundary, then entire data cache line
- containing Address is invalidated. If Address + Length is not aligned on a
- cache line boundary, then the entire data cache line containing Address +
- Length -1 is invalidated. This function must never invalidate any cache lines
- outside the specified range. If Length is 0, then no data cache lines are
- invalidated. Address is returned. This function must be used with care
- because dirty cache lines are not written back to system memory. It is
- typically used for cache diagnostics. If the CPU does not support
- invalidation of a data cache range, then a write back and invalidate
- operation should be performed on the data cache range.
-
- If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
-
- @param Address The base address of the data cache lines to invalidate. If
- the CPU is in a physical addressing mode, then Address is a
- physical address. If the CPU is in a virtual addressing mode,
- then Address is a virtual address.
- @param Length The number of bytes to invalidate from the data cache.
-
- @return Address.
-
-**/
-VOID *
-EFIAPI
-InvalidateDataCacheRange (
- IN VOID *Address,
- IN UINTN Length
- )
-{
- //
- // Invalidation of a data cache range without writing back is not supported on
- // IPF architecture, so write back and invalidate operation is performed.
- //
- return AsmFlushCacheRange (Address, Length);
-}
diff --git a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf b/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
index 84564e00d7..2622fbeb9f 100644
--- a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
+++ b/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
@@ -29,7 +29,7 @@
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC ARM AARCH64
+# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64
#
[Sources.IA32]
@@ -51,10 +51,6 @@
X64/CpuFlushTlb.nasm| GCC
X64/CpuFlushTlb.S | GCC
-[Sources.IPF]
- Ipf/CpuFlushTlb.s
- Ipf/CpuSleep.c
-
[Sources.EBC]
Ebc/CpuSleepFlushTlb.c
@@ -76,7 +72,3 @@
MdePkg/MdePkg.dec
-[LibraryClasses.IPF]
- PalLib
- BaseLib
-
diff --git a/MdePkg/Library/BaseCpuLib/Ipf/CpuFlushTlb.s b/MdePkg/Library/BaseCpuLib/Ipf/CpuFlushTlb.s
deleted file mode 100644
index 911f7809a0..0000000000
--- a/MdePkg/Library/BaseCpuLib/Ipf/CpuFlushTlb.s
+++ /dev/null
@@ -1,58 +0,0 @@
-/// @file
-/// CpuFlushTlb() function for Itanium-based architecture.
-///
-/// Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
-/// This program and the accompanying materials
-/// are licensed and made available under the terms and conditions of the BSD License
-/// which accompanies this distribution. The full text of the license may be found at
-/// http://opensource.org/licenses/bsd-license.php.
-///
-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-///
-/// Module Name: CpuFlushTlb.s
-///
-///
-
-.auto
-.text
-
-ASM_GLOBAL PalCall
-.type PalCall, @function
-
-.proc CpuFlushTlb
-.type CpuFlushTlb, @function
-CpuFlushTlb::
- alloc loc0 = ar.pfs, 0, 3, 5, 0
- mov out0 = 0
- mov out1 = 6
- mov out2 = 0
- mov out3 = 0
- mov loc1 = b0
- mov out4 = 0
- brl.call.sptk b0 = PalCall
- mov loc2 = psr // save PSR
- mov ar.pfs = loc0
- extr.u r14 = r10, 32, 32 // r14 <- count1
- rsm 1 << 14 // Disable interrupts
- extr.u r15 = r11, 32, 32 // r15 <- stride1
- extr.u r10 = r10, 0, 32 // r10 <- count2
- add r10 = -1, r10
- extr.u r11 = r11, 0, 32 // r11 <- stride2
- br.cond.sptk LoopPredicate
-LoopOuter:
- mov ar.lc = r10 // LC <- count2
- mov ar.ec = r0 // EC <- 0
-Loop:
- ptc.e r9
- add r9 = r11, r9 // r9 += stride2
- br.ctop.sptk Loop
- add r9 = r15, r9 // r9 += stride1
-LoopPredicate:
- cmp.ne p6 = r0, r14 // count1 == 0?
- add r14 = -1, r14
-(p6) br.cond.sptk LoopOuter
- mov psr.l = loc2
- mov b0 = loc1
- br.ret.sptk.many b0
-.endp
diff --git a/MdePkg/Library/BaseCpuLib/Ipf/CpuSleep.c b/MdePkg/Library/BaseCpuLib/Ipf/CpuSleep.c
deleted file mode 100644
index 59c07cac72..0000000000
--- a/MdePkg/Library/BaseCpuLib/Ipf/CpuSleep.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/** @file
- Base Library CPU functions for Itanium
-
- Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php.
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include <Library/PalLib.h>
-#include <Library/BaseLib.h>
-
-/**
- Places the CPU in a sleep state until an interrupt is received.
-
- Places the CPU in a sleep state until an interrupt is received. If interrupts
- are disabled prior to calling this function, then the CPU will be placed in a
- sleep state indefinitely.
-
-**/
-VOID
-EFIAPI
-CpuSleep (
- VOID
- )
-{
- UINT64 Tpr;
-
- //
- // It is the TPR register that controls if external interrupt would bring processor in LIGHT HALT low-power state
- // back to normal state. PAL_HALT_LIGHT does not depend on PSR setting.
- // So here if interrupts are disabled (via PSR.i), TRP.mmi needs to be set to prevent processor being interrupted by external interrupts.
- // If interrupts are enabled, then just use current TRP setting.
- //
- if (GetInterruptState ()) {
- //
- // If interrupts are enabled, then call PAL_HALT_LIGHT with the current TPR setting.
- //
- PalCall (PAL_HALT_LIGHT, 0, 0, 0);
- } else {
- //
- // If interrupts are disabled on entry, then mask all interrupts in TPR before calling PAL_HALT_LIGHT.
- //
-
- //
- // Save TPR
- //
- Tpr = AsmReadTpr();
- //
- // Set TPR.mmi to mask all external interrupts
- //
- AsmWriteTpr (BIT16 | Tpr);
-
- PalCall (PAL_HALT_LIGHT, 0, 0, 0);
-
- //
- // Restore TPR
- //
- AsmWriteTpr (Tpr);
- }
-}
diff --git a/MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf b/MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
index a203e187cf..bea5fc8a73 100644
--- a/MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+++ b/MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
@@ -24,7 +24,7 @@
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]
diff --git a/MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf b/MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
index 823511b22f..761c35a8b1 100644
--- a/MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+++ b/MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
@@ -25,7 +25,7 @@
CONSTRUCTOR = BaseDebugLibSerialPortConstructor
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]
diff --git a/MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf b/MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
index 7f611b0b9b..93020e7101 100644
--- a/MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
+++ b/MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
@@ -23,7 +23,7 @@
LIBRARY_CLASS = DebugPrintErrorLevelLib
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]
diff --git a/MdePkg/Library/BaseExtractGuidedSectionLib/BaseExtractGuidedSectionLib.inf b/MdePkg/Library/BaseExtractGuidedSectionLib/BaseExtractGuidedSectionLib.inf
index f211b77a95..959785e3cd 100644
--- a/MdePkg/Library/BaseExtractGuidedSectionLib/BaseExtractGuidedSectionLib.inf
+++ b/MdePkg/Library/BaseExtractGuidedSectionLib/BaseExtractGuidedSectionLib.inf
@@ -34,7 +34,7 @@
#
# The following information is for reference only and not required by the build tools.
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC (EBC is for build only)
+# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only)
#
[Sources]
diff --git a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
index 6c4d7ccfb7..64844e4c7c 100644
--- a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+++ b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
@@ -30,7 +30,7 @@
#
-# VALID_ARCHITECTURES = IA32 X64 EBC IPF ARM AARCH64
+# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64
#
[Sources]
@@ -56,9 +56,6 @@
IoLibEbc.c
IoLib.c
-[Sources.IPF]
- IoLibIpf.c
-
[Sources.ARM]
IoLibArm.c
@@ -72,9 +69,3 @@
DebugLib
BaseLib
-[LibraryClasses.IPF]
- PcdLib
-
-[Pcd.IPF]
- gEfiMdePkgTokenSpaceGuid.PcdIoBlockBaseAddressForIpf ## SOMETIMES_CONSUMES
-
diff --git a/MdePkg/Library/BaseIoLibIntrinsic/IoLibIpf.c b/MdePkg/Library/BaseIoLibIntrinsic/IoLibIpf.c
deleted file mode 100644
index b84134b757..0000000000
--- a/MdePkg/Library/BaseIoLibIntrinsic/IoLibIpf.c
+++ /dev/null
@@ -1,736 +0,0 @@
-/** @file
- Common I/O Library routines.
-
- Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
- Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
-
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php.
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-
-#include "BaseIoLibIntrinsicInternal.h"
-#include <Library/PcdLib.h>
-
-#define MAP_PORT_BASE_TO_MEM(_Port) \
- ((((_Port) & 0xfffc) << 10) | ((_Port) & 0x0fff))
-
-/**
- Translates I/O port address to memory address.
-
- This function translates I/O port address to memory address by adding the 64MB
- aligned I/O Port space to the I/O address.
- If I/O Port space base is not 64MB aligned, then ASSERT ().
-
- @param Port The I/O port to read.
-
- @return The memory address.
-
-**/
-UINTN
-InternalGetMemoryMapAddress (
- IN UINTN Port
- )
-{
- UINTN Address;
- UINTN IoBlockBaseAddress;
-
- Address = MAP_PORT_BASE_TO_MEM (Port);
- IoBlockBaseAddress = PcdGet64(PcdIoBlockBaseAddressForIpf);
-
- //
- // Make sure that the I/O Port space base is 64MB aligned.
- //
- ASSERT ((IoBlockBaseAddress & 0x3ffffff) == 0);
- Address += IoBlockBaseAddress;
-
- return Address;
-}
-
-/**
- Reads an 8-bit I/O port.
-
- Reads the 8-bit I/O port specified by Port. The 8-bit read value is returned.
- This function must guarantee that all I/O read and write operations are
- serialized.
-
- If 8-bit I/O port operations are not supported, then ASSERT().
-
- @param Port The I/O port to read.
-
- @return The value read.
-
-**/
-UINT8
-EFIAPI
-IoRead8 (
- IN UINTN Port
- )
-{
- return MmioRead8 (InternalGetMemoryMapAddress (Port));
-}
-
-/**
- Reads a 16-bit I/O port.
-
- Reads the 16-bit I/O port specified by Port. The 16-bit read value is returned.
- This function must guarantee that all I/O read and write operations are
- serialized.
-
- If 16-bit I/O port operations are not supported, then ASSERT().
- If Port is not aligned on a 16-bit boundary, then ASSERT().
-
- @param Port The I/O port to read.
-
- @return The value read.
-
-**/
-UINT16
-EFIAPI
-IoRead16 (
- IN UINTN Port
- )
-{
- return MmioRead16 (InternalGetMemoryMapAddress (Port));
-}
-
-/**
- Reads a 32-bit I/O port.
-
- Reads the 32-bit I/O port specified by Port. The 32-bit read value is returned.
- This function must guarantee that all I/O read and write operations are
- serialized.
-
- If 32-bit I/O port operations are not supported, then ASSERT().
- If Port is not aligned on a 32-bit boundary, then ASSERT().
-
- @param Port The I/O port to read.
-
- @return The value read.
-
-**/
-UINT32
-EFIAPI
-IoRead32 (
- IN UINTN Port
- )
-{
- return MmioRead32 (InternalGetMemoryMapAddress (Port));
-}
-
-/**
- Reads a 64-bit I/O port.
-
- Reads the 64-bit I/O port specified by Port. The 64-bit read value is returned.
- This function must guarantee that all I/O read and write operations are
- serialized.
-
- If 64-bit I/O port operations are not supported, then ASSERT().
- If Port is not aligned on a 64-bit boundary, then ASSERT().
-
- @param Port The I/O port to read.
-
- @return The value read.
-
-**/
-UINT64
-EFIAPI
-IoRead64 (
- IN UINTN Port
- )
-{
- ASSERT (FALSE);
- return 0;
-}
-
-
-/**
- Writes an 8-bit I/O port.
-
- Writes the 8-bit I/O port specified by Port with the value specified by Value
- and returns Value. This function must guarantee that all I/O read and write
- operations are serialized.
-
- If 8-bit I/O port operations are not supported, then ASSERT().
-
- @param Port The I/O port to write.
- @param Value The value to write to the I/O port.
-
- @return The value written the I/O port.
-
-**/
-UINT8
-EFIAPI
-IoWrite8 (
- IN UINTN Port,
- IN UINT8 Value
- )
-{
- return MmioWrite8 (InternalGetMemoryMapAddress (Port), Value);
-}
-
-/**
- Writes a 16-bit I/O port.
-
- Writes the 16-bit I/O port specified by Port with the value specified by Value
- and returns Value. This function must guarantee that all I/O read and write
- operations are serialized.
-
- If 16-bit I/O port operations are not supported, then ASSERT().
- If Port is not aligned on a 16-bit boundary, then ASSERT().
-
- @param Port The I/O port to write.
- @param Value The value to write to the I/O port.
-
- @return The value written the I/O port.
-
-**/
-UINT16
-EFIAPI
-IoWrite16 (
- IN UINTN Port,
- IN UINT16 Value
- )
-{
- return MmioWrite16 (InternalGetMemoryMapAddress (Port), Value);
-}
-
-/**
- Writes a 32-bit I/O port.
-
- Writes the 32-bit I/O port specified by Port with the value specified by Value
- and returns Value. This function must guarantee that all I/O read and write
- operations are serialized.
-
- If 32-bit I/O port operations are not supported, then ASSERT().
- If Port is not aligned on a 32-bit boundary, then ASSERT().
-
- @param Port The I/O port to write.
- @param Value The value to write to the I/O port.
-
- @return The value written the I/O port.
-
-**/
-UINT32
-EFIAPI
-IoWrite32 (
- IN UINTN Port,
- IN UINT32 Value
- )
-{
- return MmioWrite32 (InternalGetMemoryMapAddress (Port), Value);
-}
-
-/**
- Writes a 64-bit I/O port.
-
- Writes the 64-bit I/O port specified by Port with the value specified by Value
- and returns Value. This function must guarantee that all I/O read and write
- operations are serialized.
-
- If 64-bit I/O port operations are not supported, then ASSERT().
- If Port is not aligned on a 64-bit boundary, then ASSERT().
-
- @param Port The I/O port to write.
- @param Value The value to write to the I/O port.
-
- @return The value written the I/O port.
-
-**/
-UINT64
-EFIAPI
-IoWrite64 (
- IN UINTN Port,
- IN UINT64 Value
- )
-{
- ASSERT (FALSE);
- return 0;
-}
-
-/**
- Reads an 8-bit I/O port fifo into a block of memory.
-
- Reads the 8-bit I/O fifo port specified by Port.
- The port is read Count times, and the read data is
- stored in the provided Buffer.
-
- This function must guarantee that all I/O read and write operations are
- serialized.
-
- If 8-bit I/O port operations are not supported, then ASSERT().
-
- @param Port The I/O port to read.
- @param Count The number of times to read I/O port.
- @param Buffer The buffer to store the read data into.
-
-**/
-VOID
-EFIAPI
-IoReadFifo8 (
- IN UINTN Port,
- IN UINTN Count,
- OUT VOID *Buffer
- )
-{
- UINT8 *Buffer8;
-
- Buffer8 = (UINT8 *)Buffer;
- while (Count-- > 0) {
- *Buffer8++ = IoRead8 (Port);
- }
-}
-
-/**
- Reads a 16-bit I/O port fifo into a block of memory.
-
- Reads the 16-bit I/O fifo port specified by Port.
- The port is read Count times, and the read data is
- stored in the provided Buffer.
-
- This function must guarantee that all I/O read and write operations are
- serialized.
-
- If 16-bit I/O port operations are not supported, then ASSERT().
-
- @param Port The I/O port to read.
- @param Count The number of times to read I/O port.
- @param Buffer The buffer to store the read data into.
-
-**/
-VOID
-EFIAPI
-IoReadFifo16 (
- IN UINTN Port,
- IN UINTN Count,
- OUT VOID *Buffer
- )
-{
- UINT16 *Buffer16;
-
- Buffer16 = (UINT16 *)Buffer;
- while (Count-- > 0) {
- *Buffer16++ = IoRead16 (Port);
- }
-}
-
-/**
- Reads a 32-bit I/O port fifo into a block of memory.
-
- Reads the 32-bit I/O fifo port specified by Port.
- The port is read Count times, and the read data is
- stored in the provided Buffer.
-
- This function must guarantee that all I/O read and write operations are
- serialized.
-
- If 32-bit I/O port operations are not supported, then ASSERT().
-
- @param Port The I/O port to read.
- @param Count The number of times to read I/O port.
- @param Buffer The buffer to store the read data into.
-
-**/
-VOID
-EFIAPI
-IoReadFifo32 (
- IN UINTN Port,
- IN UINTN Count,
- OUT VOID *Buffer
- )
-{
- UINT32 *Buffer32;
-
- Buffer32 = (UINT32 *)Buffer;
- while (Count-- > 0) {
- *Buffer32++ = IoRead32 (Port);
- }
-}
-
-/**
- Writes a block of memory into an 8-bit I/O port fifo.
-
- Writes the 8-bit I/O fifo port specified by Port.
- The port is written Count times, and the write data is
- retrieved from the provided Buffer.
-
- This function must guarantee that all I/O write and write operations are
- serialized.
-
- If 8-bit I/O port operations are not supported, then ASSERT().
-
- @param Port The I/O port to write.
- @param Count The number of times to write I/O port.
- @param Buffer The buffer to retrieve the write data from.
-
-**/
-VOID
-EFIAPI
-IoWriteFifo8 (
- IN UINTN Port,
- IN UINTN Count,
- IN VOID *Buffer
- )
-{
- UINT8 *Buffer8;
-
- Buffer8 = (UINT8 *)Buffer;
- while (Count-- > 0) {
- IoWrite8 (Port, *Buffer8++);
- }
-}
-
-/**
- Writes a block of memory into a 16-bit I/O port fifo.
-
- Writes the 16-bit I/O fifo port specified by Port.
- The port is written Count times, and the write data is
- retrieved from the provided Buffer.
-
- This function must guarantee that all I/O write and write operations are
- serialized.
-
- If 16-bit I/O port operations are not supported, then ASSERT().
-
- @param Port The I/O port to write.
- @param Count The number of times to write I/O port.
- @param Buffer The buffer to retrieve the write data from.
-
-**/
-VOID
-EFIAPI
-IoWriteFifo16 (
- IN UINTN Port,
- IN UINTN Count,
- IN VOID *Buffer
- )
-{
- UINT16 *Buffer16;
-
- Buffer16 = (UINT16 *)Buffer;
- while (Count-- > 0) {
- IoWrite16 (Port, *Buffer16++);
- }
-}
-
-/**
- Writes a block of memory into a 32-bit I/O port fifo.
-
- Writes the 32-bit I/O fifo port specified by Port.
- The port is written Count times, and the write data is
- retrieved from the provided Buffer.
-
- This function must guarantee that all I/O write and write operations are
- serialized.
-
- If 32-bit I/O port operations are not supported, then ASSERT().
-
- @param Port The I/O port to write.
- @param Count The number of times to write I/O port.
- @param Buffer The buffer to retrieve the write data from.
-
-**/
-VOID
-EFIAPI
-IoWriteFifo32 (
- IN UINTN Port,
- IN UINTN Count,
- IN VOID *Buffer
- )
-{
- UINT32 *Buffer32;
-
- Buffer32 = (UINT32 *)Buffer;
- while (Count-- > 0) {
- IoWrite32 (Port, *Buffer32++);
- }
-}
-
-/**
- Reads an 8-bit MMIO register.
-
- Reads the 8-bit MMIO register specified by Address. The 8-bit read value is
- returned. This function must guarantee that all MMIO read and write
- operations are serialized.
-
- If 8-bit MMIO register operations are not supported, then ASSERT().
-
- @param Address The MMIO register to read.
-
- @return The value read.
-
-**/
-UINT8
-EFIAPI
-MmioRead8 (
- IN UINTN Address
- )
-{
- UINT8 Data;
-
- Address |= BIT63;
-
- MemoryFence ();
- Data = *((volatile UINT8 *) Address);
- MemoryFence ();
-
- return Data;
-}
-
-/**
- Reads a 16-bit MMIO register.
-
- Reads the 16-bit MMIO register specified by Address. The 16-bit read value is
- returned. This function must guarantee that all MMIO read and write
- operations are serialized.
-
- If 16-bit MMIO register operations are not supported, then ASSERT().
- If Address is not aligned on a 16-bit boundary, then ASSERT().
-
- @param Address The MMIO register to read.
-
- @return The value read.
-
-**/
-UINT16
-EFIAPI
-MmioRead16 (
- IN UINTN Address
- )
-{
- UINT16 Data;
-
- //
- // Make sure that Address is 16-bit aligned.
- //
- ASSERT ((Address & 1) == 0);
-
- Address |= BIT63;
-
- MemoryFence ();
- Data = *((volatile UINT16 *) Address);
- MemoryFence ();
-
- return Data;
-}
-
-/**
- Reads a 32-bit MMIO register.
-
- Reads the 32-bit MMIO register specified by Address. The 32-bit read value is
- returned. This function must guarantee that all MMIO read and write
- operations are serialized.
-
- If 32-bit MMIO register operations are not supported, then ASSERT().
- If Address is not aligned on a 32-bit boundary, then ASSERT().
-
- @param Address The MMIO register to read.
-
- @return The value read.
-
-**/
-UINT32
-EFIAPI
-MmioRead32 (
- IN UINTN Address
- )
-{
- UINT32 Data;
-
- //
- // Make sure that Address is 32-bit aligned.
- //
- ASSERT ((Address & 3) == 0);
-
- Address |= BIT63;
-
- MemoryFence ();
- Data = *((volatile UINT32 *) Address);
- MemoryFence ();
-
- return Data;
-}
-
-/**
- Reads a 64-bit MMIO register.
-
- Reads the 64-bit MMIO register specified by Address. The 64-bit read value is
- returned. This function must guarantee that all MMIO read and write
- operations are serialized.
-
- If 64-bit MMIO register operations are not supported, then ASSERT().
- If Address is not aligned on a 64-bit boundary, then ASSERT().
-
- @param Address The MMIO register to read.
-
- @return The value read.
-
-**/
-UINT64
-EFIAPI
-MmioRead64 (
- IN UINTN Address
- )
-{
- UINT64 Data;
-
- //
- // Make sure that Address is 64-bit aligned.
- //
- ASSERT ((Address & 7) == 0);
-
- Address |= BIT63;
-
- MemoryFence ();
- Data = *((volatile UINT64 *) Address);
- MemoryFence ();
-
- return Data;
-
-}
-
-/**
- Writes an 8-bit MMIO register.
-
- Writes the 8-bit MMIO register specified by Address with the value specified
- by Value and returns Value. This function must guarantee that all MMIO read
- and write operations are serialized.
-
- If 8-bit MMIO register operations are not supported, then ASSERT().
-
- @param Address The MMIO register to write.
- @param Value The value to write to the MMIO register.
-
- @return Value.
-
-**/
-UINT8
-EFIAPI
-MmioWrite8 (
- IN UINTN Address,
- IN UINT8 Value
- )
-{
- Address |= BIT63;
-
- MemoryFence ();
- *((volatile UINT8 *) Address) = Value;
- MemoryFence ();
-
- return Value;
-}
-
-/**
- Writes a 16-bit MMIO register.
-
- Writes the 16-bit MMIO register specified by Address with the value specified
- by Value and returns Value. This function must guarantee that all MMIO read
- and write operations are serialized.
-
- If 16-bit MMIO register operations are not supported, then ASSERT().
- If Address is not aligned on a 16-bit boundary, then ASSERT().
-
- @param Address The MMIO register to write.
- @param Value The value to write to the MMIO register.
-
- @return Value.
-
-**/
-UINT16
-EFIAPI
-MmioWrite16 (
- IN UINTN Address,
- IN UINT16 Value
- )
-{
- //
- // Make sure that Address is 16-bit aligned.
- //
- ASSERT ((Address & 1) == 0);
-
- Address |= BIT63;
-
- MemoryFence ();
- *((volatile UINT16 *) Address) = Value;
- MemoryFence ();
-
- return Value;
-}
-
-/**
- Writes a 32-bit MMIO register.
-
- Writes the 32-bit MMIO register specified by Address with the value specified
- by Value and returns Value. This function must guarantee that all MMIO read
- and write operations are serialized.
-
- If 32-bit MMIO register operations are not supported, then ASSERT().
- If Address is not aligned on a 32-bit boundary, then ASSERT().
-
- @param Address The MMIO register to write.
- @param Value The value to write to the MMIO register.
-
- @return Value.
-
-**/
-UINT32
-EFIAPI
-MmioWrite32 (
- IN UINTN Address,
- IN UINT32 Value
- )
-{
- //
- // Make sure that Address is 32-bit aligned.
- //
- ASSERT ((Address & 3) == 0);
-
- Address |= BIT63;
-
- MemoryFence ();
- *((volatile UINT32 *) Address) = Value;
- MemoryFence ();
-
- return Value;
-}
-
-/**
- Writes a 64-bit MMIO register.
-
- Writes the 64-bit MMIO register specified by Address with the value specified
- by Value and returns Value. This function must guarantee that all MMIO read
- and write operations are serialized.
-
- If 64-bit MMIO register operations are not supported, then ASSERT().
- If Address is not aligned on a 64-bit boundary, then ASSERT().
-
- @param Address The MMIO register to write.
- @param Value The value to write to the MMIO register.
-
-**/
-UINT64
-EFIAPI
-MmioWrite64 (
- IN UINTN Address,
- IN UINT64 Value
- )
-{
- //
- // Make sure that Address is 64-bit aligned.
- //
- ASSERT ((Address & 7) == 0);
-
- Address |= BIT63;
-
- MemoryFence ();
- *((volatile UINT64 *) Address) = Value;
- MemoryFence ();
-
- return Value;
-}
diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf
index 12e883cbb8..e84470e10f 100644
--- a/MdePkg/Library/BaseLib/BaseLib.inf
+++ b/MdePkg/Library/BaseLib/BaseLib.inf
@@ -25,7 +25,7 @@
LIBRARY_CLASS = BaseLib
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC ARM AARCH64
+# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64
#
[Sources]
@@ -537,39 +537,6 @@
X64/RdRand.S | GCC
ChkStkGcc.c | GCC
-[Sources.IPF]
- Ipf/AccessGp.s
- Ipf/ReadCpuid.s
- Ipf/ExecFc.s
- Ipf/AsmPalCall.s
- Ipf/AccessPsr.s
- Ipf/AccessPmr.s
- Ipf/AccessKr.s
- Ipf/AccessKr7.s
- Ipf/AccessGcr.s
- Ipf/AccessEicr.s
- Ipf/AccessDbr.s
- Ipf/AccessMsr.s | INTEL
- Ipf/AccessMsr.s | GCC
- Ipf/AccessMsrDb.s | MSFT
- Ipf/InternalFlushCacheRange.s
- Ipf/FlushCacheRange.c
- Ipf/InternalSwitchStack.c
- Ipf/GetInterruptState.s
- Ipf/CpuPause.s
- Ipf/CpuBreakpoint.c | INTEL
- Ipf/CpuBreakpointMsc.c | MSFT
- Ipf/AsmCpuMisc.s | GCC
- Ipf/Unaligned.c
- Ipf/SwitchStack.s
- Ipf/LongJmp.s
- Ipf/SetJmp.s
- Ipf/ReadCr.s
- Ipf/ReadAr.s
- Ipf/Ia64gen.h
- Ipf/Asm.h
- Math64.c
-
[Sources.EBC]
Ebc/CpuBreakpoint.c
Ebc/SetJumpLongJump.c
diff --git a/MdePkg/Library/BaseLib/BaseLibInternals.h b/MdePkg/Library/BaseLib/BaseLibInternals.h
index 9dca97a0dc..e8ebd03834 100644
--- a/MdePkg/Library/BaseLib/BaseLibInternals.h
+++ b/MdePkg/Library/BaseLib/BaseLibInternals.h
@@ -910,926 +910,6 @@ InternalX86RdRand64 (
OUT UINT64 *Rand
);
-
-#elif defined (MDE_CPU_IPF)
-//
-//
-// IPF specific functions
-//
-
-/**
- Reads control register DCR.
-
- This is a worker function for AsmReadControlRegister()
- when its parameter Index is IPF_CONTROL_REGISTER_DCR.
-
- @return The 64-bit control register DCR.
-
-**/
-UINT64
-EFIAPI
-AsmReadControlRegisterDcr (
- VOID
- );
-
-
-/**
- Reads control register ITM.
-
- This is a worker function for AsmReadControlRegister()
- when its parameter Index is IPF_CONTROL_REGISTER_ITM.
-
- @return The 64-bit control register ITM.
-
-**/
-UINT64
-EFIAPI
-AsmReadControlRegisterItm (
- VOID
- );
-
-
-/**
- Reads control register IVA.
-
- This is a worker function for AsmReadControlRegister()
- when its parameter Index is IPF_CONTROL_REGISTER_IVA.
-
- @return The 64-bit control register IVA.
-
-**/
-UINT64
-EFIAPI
-AsmReadControlRegisterIva (
- VOID
- );
-
-
-/**
- Reads control register PTA.
-
- This is a worker function for AsmReadControlRegister()
- when its parameter Index is IPF_CONTROL_REGISTER_PTA.
-
- @return The 64-bit control register PTA.
-
-**/
-UINT64
-EFIAPI
-AsmReadControlRegisterPta (
- VOID
- );
-
-
-/**
- Reads control register IPSR.
-
- This is a worker function for AsmReadControlRegister()
- when its parameter Index is IPF_CONTROL_REGISTER_IPSR.
-
- @return The 64-bit control register IPSR.
-
-**/
-UINT64
-EFIAPI
-AsmReadControlRegisterIpsr (
- VOID
- );
-
-
-/**
- Reads control register ISR.
-
- This is a worker function for AsmReadControlRegister()
- when its parameter Index is IPF_CONTROL_REGISTER_ISR.
-
- @return The 64-bit control register ISR.
-
-**/
-UINT64
-EFIAPI
-AsmReadControlRegisterIsr (
- VOID
- );
-
-
-/**
- Reads control register IIP.
-
- This is a worker function for AsmReadControlRegister()
- when its parameter Index is IPF_CONTROL_REGISTER_IIP.
-
- @return The 64-bit control register IIP.
-
-**/
-UINT64
-EFIAPI
-AsmReadControlRegisterIip (
- VOID
- );
-
-
-/**
- Reads control register IFA.
-
- This is a worker function for AsmReadControlRegister()
- when its parameter Index is IPF_CONTROL_REGISTER_IFA.
-
- @return The 64-bit control register IFA.
-
-**/
-UINT64
-EFIAPI
-AsmReadControlRegisterIfa (
- VOID
- );
-
-
-/**
- Reads control register ITIR.
-
- This is a worker function for AsmReadControlRegister()
- when its parameter Index is IPF_CONTROL_REGISTER_ITIR.
-
- @return The 64-bit control register ITIR.
-
-**/
-UINT64
-EFIAPI
-AsmReadControlRegisterItir (
- VOID
- );
-
-
-/**
- Reads control register IIPA.
-
- This is a worker function for AsmReadControlRegister()
- when its parameter Index is IPF_CONTROL_REGISTER_IIPA.
-
- @return The 64-bit control register IIPA.
-
-**/
-UINT64
-EFIAPI
-AsmReadControlRegisterIipa (
- VOID
- );
-
-
-/**
- Reads control register IFS.
-
- This is a worker function for AsmReadControlRegister()
- when its parameter Index is IPF_CONTROL_REGISTER_IFS.
-
- @return The 64-bit control register IFS.
-
-**/
-UINT64
-EFIAPI
-AsmReadControlRegisterIfs (
- VOID
- );
-
-
-/**
- Reads control register IIM.
-
- This is a worker function for AsmReadControlRegister()
- when its parameter Index is IPF_CONTROL_REGISTER_IIM.
-
- @return The 64-bit control register IIM.
-
-**/
-UINT64
-EFIAPI
-AsmReadControlRegisterIim (
- VOID
- );
-
-
-/**
- Reads control register IHA.
-
- This is a worker function for AsmReadControlRegister()
- when its parameter Index is IPF_CONTROL_REGISTER_IHA.
-
- @return The 64-bit control register IHA.
-
-**/
-UINT64
-EFIAPI
-AsmReadControlRegisterIha (
- VOID
- );
-
-
-/**
- Reads control register LID.
-
- This is a worker function for AsmReadControlRegister()
- when its parameter Index is IPF_CONTROL_REGISTER_LID.
-
- @return The 64-bit control register LID.
-
-**/
-UINT64
-EFIAPI
-AsmReadControlRegisterLid (
- VOID
- );
-
-
-/**
- Reads control register IVR.
-
- This is a worker function for AsmReadControlRegister()
- when its parameter Index is IPF_CONTROL_REGISTER_IVR.
-
- @return The 64-bit control register IVR.
-
-**/
-UINT64
-EFIAPI
-AsmReadControlRegisterIvr (
- VOID
- );
-
-
-/**
- Reads control register TPR.
-
- This is a worker function for AsmReadControlRegister()
- when its parameter Index is IPF_CONTROL_REGISTER_TPR.
-
- @return The 64-bit control register TPR.
-
-**/
-UINT64
-EFIAPI
-AsmReadControlRegisterTpr (
- VOID
- );
-
-
-/**
- Reads control register EOI.
-
- This is a worker function for AsmReadControlRegister()
- when its parameter Index is IPF_CONTROL_REGISTER_EOI.
-
- @return The 64-bit control register EOI.
-
-**/
-UINT64
-EFIAPI
-AsmReadControlRegisterEoi (
- VOID
- );
-
-
-/**
- Reads control register IRR0.
-
- This is a worker function for AsmReadControlRegister()
- when its parameter Index is IPF_CONTROL_REGISTER_IRR0.
-
- @return The 64-bit control register IRR0.
-
-**/
-UINT64
-EFIAPI
-AsmReadControlRegisterIrr0 (
- VOID
- );
-
-
-/**
- Reads control register IRR1.
-
- This is a worker function for AsmReadControlRegister()
- when its parameter Index is IPF_CONTROL_REGISTER_IRR1.
-
- @return The 64-bit control register IRR1.
-
-**/
-UINT64
-EFIAPI
-AsmReadControlRegisterIrr1 (
- VOID
- );
-
-
-/**
- Reads control register IRR2.
-
- This is a worker function for AsmReadControlRegister()
- when its parameter Index is IPF_CONTROL_REGISTER_IRR2.
-
- @return The 64-bit control register IRR2.
-
-**/
-UINT64
-EFIAPI
-AsmReadControlRegisterIrr2 (
- VOID
- );
-
-
-/**
- Reads control register IRR3.
-
- This is a worker function for AsmReadControlRegister()
- when its parameter Index is IPF_CONTROL_REGISTER_IRR3.
-
- @return The 64-bit control register IRR3.
-
-**/
-UINT64
-EFIAPI
-AsmReadControlRegisterIrr3 (
- VOID
- );
-
-
-/**
- Reads control register ITV.
-
- This is a worker function for AsmReadControlRegister()
- when its parameter Index is IPF_CONTROL_REGISTER_ITV.
-
- @return The 64-bit control register ITV.
-
-**/
-UINT64
-EFIAPI
-AsmReadControlRegisterItv (
- VOID
- );
-
-
-/**
- Reads control register PMV.
-
- This is a worker function for AsmReadControlRegister()
- when its parameter Index is IPF_CONTROL_REGISTER_PMV.
-
- @return The 64-bit control register PMV.
-
-**/
-UINT64
-EFIAPI
-AsmReadControlRegisterPmv (
- VOID
- );
-
-
-/**
- Reads control register CMCV.
-
- This is a worker function for AsmReadControlRegister()
- when its parameter Index is IPF_CONTROL_REGISTER_CMCV.
-
- @return The 64-bit control register CMCV.
-
-**/
-UINT64
-EFIAPI
-AsmReadControlRegisterCmcv (
- VOID
- );
-
-
-/**
- Reads control register LRR0.
-
- This is a worker function for AsmReadControlRegister()
- when its parameter Index is IPF_CONTROL_REGISTER_LRR0.
-
- @return The 64-bit control register LRR0.
-
-**/
-UINT64
-EFIAPI
-AsmReadControlRegisterLrr0 (
- VOID
- );
-
-
-/**
- Reads control register LRR1.
-
- This is a worker function for AsmReadControlRegister()
- when its parameter Index is IPF_CONTROL_REGISTER_LRR1.
-
- @return The 64-bit control register LRR1.
-
-**/
-UINT64
-EFIAPI
-AsmReadControlRegisterLrr1 (
- VOID
- );
-
-
-/**
- Reads application register K0.
-
- This is a worker function for AsmReadApplicationRegister()
- when its parameter Index is IPF_APPLICATION_REGISTER_K0.
-
- @return The 64-bit application register K0.
-
-**/
-UINT64
-EFIAPI
-AsmReadApplicationRegisterK0 (
- VOID
- );
-
-
-
-/**
- Reads application register K1.
-
- This is a worker function for AsmReadApplicationRegister()
- when its parameter Index is IPF_APPLICATION_REGISTER_K1.
-
- @return The 64-bit application register K1.
-
-**/
-UINT64
-EFIAPI
-AsmReadApplicationRegisterK1 (
- VOID
- );
-
-
-/**
- Reads application register K2.
-
- This is a worker function for AsmReadApplicationRegister()
- when its parameter Index is IPF_APPLICATION_REGISTER_K2.
-
- @return The 64-bit application register K2.
-
-**/
-UINT64
-EFIAPI
-AsmReadApplicationRegisterK2 (
- VOID
- );
-
-
-/**
- Reads application register K3.
-
- This is a worker function for AsmReadApplicationRegister()
- when its parameter Index is IPF_APPLICATION_REGISTER_K3.
-
- @return The 64-bit application register K3.
-
-**/
-UINT64
-EFIAPI
-AsmReadApplicationRegisterK3 (
- VOID
- );
-
-
-/**
- Reads application register K4.
-
- This is a worker function for AsmReadApplicationRegister()
- when its parameter Index is IPF_APPLICATION_REGISTER_K4.
-
- @return The 64-bit application register K4.
-
-**/
-UINT64
-EFIAPI
-AsmReadApplicationRegisterK4 (
- VOID
- );
-
-
-/**
- Reads application register K5.
-
- This is a worker function for AsmReadApplicationRegister()
- when its parameter Index is IPF_APPLICATION_REGISTER_K5.
-
- @return The 64-bit application register K5.
-
-**/
-UINT64
-EFIAPI
-AsmReadApplicationRegisterK5 (
- VOID
- );
-
-
-/**
- Reads application register K6.
-
- This is a worker function for AsmReadApplicationRegister()
- when its parameter Index is IPF_APPLICATION_REGISTER_K6.
-
- @return The 64-bit application register K6.
-
-**/
-UINT64
-EFIAPI
-AsmReadApplicationRegisterK6 (
- VOID
- );
-
-
-/**
- Reads application register K7.
-
- This is a worker function for AsmReadApplicationRegister()
- when its parameter Index is IPF_APPLICATION_REGISTER_K7.
-
- @return The 64-bit application register K7.
-
-**/
-UINT64
-EFIAPI
-AsmReadApplicationRegisterK7 (
- VOID
- );
-
-
-/**
- Reads application register RSC.
-
- This is a worker function for AsmReadApplicationRegister()
- when its parameter Index is IPF_APPLICATION_REGISTER_RSC.
-
- @return The 64-bit application register RSC.
-
-**/
-UINT64
-EFIAPI
-AsmReadApplicationRegisterRsc (
- VOID
- );
-
-
-/**
- Reads application register BSP.
-
- This is a worker function for AsmReadApplicationRegister()
- when its parameter Index is IPF_APPLICATION_REGISTER_BSP.
-
- @return The 64-bit application register BSP.
-
-**/
-UINT64
-EFIAPI
-AsmReadApplicationRegisterBsp (
- VOID
- );
-
-
-/**
- Reads application register BSPSTORE.
-
- This is a worker function for AsmReadApplicationRegister()
- when its parameter Index is IPF_APPLICATION_REGISTER_BSPSTORE.
-
- @return The 64-bit application register BSPSTORE.
-
-**/
-UINT64
-EFIAPI
-AsmReadApplicationRegisterBspstore (
- VOID
- );
-
-
-/**
- Reads application register RNAT.
-
- This is a worker function for AsmReadApplicationRegister()
- when its parameter Index is IPF_APPLICATION_REGISTER_RNAT.
-
- @return The 64-bit application register RNAT.
-
-**/
-UINT64
-EFIAPI
-AsmReadApplicationRegisterRnat (
- VOID
- );
-
-
-/**
- Reads application register FCR.
-
- This is a worker function for AsmReadApplicationRegister()
- when its parameter Index is IPF_APPLICATION_REGISTER_FCR.
-
- @return The 64-bit application register FCR.
-
-**/
-UINT64
-EFIAPI
-AsmReadApplicationRegisterFcr (
- VOID
- );
-
-
-/**
- Reads application register EFLAG.
-
- This is a worker function for AsmReadApplicationRegister()
- when its parameter Index is IPF_APPLICATION_REGISTER_EFLAG.
-
- @return The 64-bit application register EFLAG.
-
-**/
-UINT64
-EFIAPI
-AsmReadApplicationRegisterEflag (
- VOID
- );
-
-
-/**
- Reads application register CSD.
-
- This is a worker function for AsmReadApplicationRegister()
- when its parameter Index is IPF_APPLICATION_REGISTER_CSD.
-
- @return The 64-bit application register CSD.
-
-**/
-UINT64
-EFIAPI
-AsmReadApplicationRegisterCsd (
- VOID
- );
-
-
-/**
- Reads application register SSD.
-
- This is a worker function for AsmReadApplicationRegister()
- when its parameter Index is IPF_APPLICATION_REGISTER_SSD.
-
- @return The 64-bit application register SSD.
-
-**/
-UINT64
-EFIAPI
-AsmReadApplicationRegisterSsd (
- VOID
- );
-
-
-/**
- Reads application register CFLG.
-
- This is a worker function for AsmReadApplicationRegister()
- when its parameter Index is IPF_APPLICATION_REGISTER_CFLG.
-
- @return The 64-bit application register CFLG.
-
-**/
-UINT64
-EFIAPI
-AsmReadApplicationRegisterCflg (
- VOID
- );
-
-
-/**
- Reads application register FSR.
-
- This is a worker function for AsmReadApplicationRegister()
- when its parameter Index is IPF_APPLICATION_REGISTER_FSR.
-
- @return The 64-bit application register FSR.
-
-**/
-UINT64
-EFIAPI
-AsmReadApplicationRegisterFsr (
- VOID
- );
-
-
-/**
- Reads application register FIR.
-
- This is a worker function for AsmReadApplicationRegister()
- when its parameter Index is IPF_APPLICATION_REGISTER_FIR.
-
- @return The 64-bit application register FIR.
-
-**/
-UINT64
-EFIAPI
-AsmReadApplicationRegisterFir (
- VOID
- );
-
-
-/**
- Reads application register FDR.
-
- This is a worker function for AsmReadApplicationRegister()
- when its parameter Index is IPF_APPLICATION_REGISTER_FDR.
-
- @return The 64-bit application register FDR.
-
-**/
-UINT64
-EFIAPI
-AsmReadApplicationRegisterFdr (
- VOID
- );
-
-
-/**
- Reads application register CCV.
-
- This is a worker function for AsmReadApplicationRegister()
- when its parameter Index is IPF_APPLICATION_REGISTER_CCV.
-
- @return The 64-bit application register CCV.
-
-**/
-UINT64
-EFIAPI
-AsmReadApplicationRegisterCcv (
- VOID
- );
-
-
-/**
- Reads application register UNAT.
-
- This is a worker function for AsmReadApplicationRegister()
- when its parameter Index is IPF_APPLICATION_REGISTER_UNAT.
-
- @return The 64-bit application register UNAT.
-
-**/
-UINT64
-EFIAPI
-AsmReadApplicationRegisterUnat (
- VOID
- );
-
-
-/**
- Reads application register FPSR.
-
- This is a worker function for AsmReadApplicationRegister()
- when its parameter Index is IPF_APPLICATION_REGISTER_FPSR.
-
- @return The 64-bit application register FPSR.
-
-**/
-UINT64
-EFIAPI
-AsmReadApplicationRegisterFpsr (
- VOID
- );
-
-
-/**
- Reads application register ITC.
-
- This is a worker function for AsmReadApplicationRegister()
- when its parameter Index is IPF_APPLICATION_REGISTER_ITC.
-
- @return The 64-bit application register ITC.
-
-**/
-UINT64
-EFIAPI
-AsmReadApplicationRegisterItc (
- VOID
- );
-
-
-/**
- Reads application register PFS.
-
- This is a worker function for AsmReadApplicationRegister()
- when its parameter Index is IPF_APPLICATION_REGISTER_PFS.
-
- @return The 64-bit application register PFS.
-
-**/
-UINT64
-EFIAPI
-AsmReadApplicationRegisterPfs (
- VOID
- );
-
-
-/**
- Reads application register LC.
-
- This is a worker function for AsmReadApplicationRegister()
- when its parameter Index is IPF_APPLICATION_REGISTER_LC.
-
- @return The 64-bit application register LC.
-
-**/
-UINT64
-EFIAPI
-AsmReadApplicationRegisterLc (
- VOID
- );
-
-
-/**
- Reads application register EC.
-
- This is a worker function for AsmReadApplicationRegister()
- when its parameter Index is IPF_APPLICATION_REGISTER_EC.
-
- @return The 64-bit application register EC.
-
-**/
-UINT64
-EFIAPI
-AsmReadApplicationRegisterEc (
- VOID
- );
-
-
-
-/**
- Transfers control to a function starting with a new stack.
-
- Transfers control to the function specified by EntryPoint using the new stack
- specified by NewStack and passing in the parameters specified by Context1 and
- Context2. Context1 and Context2 are optional and may be NULL. The function
- EntryPoint must never return.
-
- If EntryPoint is NULL, then ASSERT().
- If NewStack is NULL, then ASSERT().
-
- @param EntryPoint A pointer to function to call with the new stack.
- @param Context1 A pointer to the context to pass into the EntryPoint
- function.
- @param Context2 A pointer to the context to pass into the EntryPoint
- function.
- @param NewStack A pointer to the new stack to use for the EntryPoint
- function.
- @param NewBsp A pointer to the new memory location for RSE backing
- store.
-
-**/
-VOID
-EFIAPI
-AsmSwitchStackAndBackingStore (
- IN SWITCH_STACK_ENTRY_POINT EntryPoint,
- IN VOID *Context1, OPTIONAL
- IN VOID *Context2, OPTIONAL
- IN VOID *NewStack,
- IN VOID *NewBsp
- );
-
-/**
- Internal worker function to invalidate a range of instruction cache lines
- in the cache coherency domain of the calling CPU.
-
- Internal worker function to invalidate the instruction cache lines specified
- by Address and Length. If Address is not aligned on a cache line boundary,
- then entire instruction cache line containing Address is invalidated. If
- Address + Length is not aligned on a cache line boundary, then the entire
- instruction cache line containing Address + Length -1 is invalidated. This
- function may choose to invalidate the entire instruction cache if that is more
- efficient than invalidating the specified range. If Length is 0, the no instruction
- cache lines are invalidated. Address is returned.
- This function is only available on IPF.
-
- @param Address The base address of the instruction cache lines to
- invalidate. If the CPU is in a physical addressing mode, then
- Address is a physical address. If the CPU is in a virtual
- addressing mode, then Address is a virtual address.
-
- @param Length The number of bytes to invalidate from the instruction cache.
-
- @return Address
-
-**/
-VOID *
-EFIAPI
-InternalFlushCacheRange (
- IN VOID *Address,
- IN UINTN Length
- );
-
#else
#endif
diff --git a/MdePkg/Library/BaseLib/Ipf/AccessDbr.s b/MdePkg/Library/BaseLib/Ipf/AccessDbr.s
deleted file mode 100644
index c74737bbf1..0000000000
--- a/MdePkg/Library/BaseLib/Ipf/AccessDbr.s
+++ /dev/null
@@ -1,118 +0,0 @@
-/// @file
-/// IPF specific Debug Breakpoint Registers accessing functions
-///
-/// Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
-/// This program and the accompanying materials
-/// are licensed and made available under the terms and conditions of the BSD License
-/// which accompanies this distribution. The full text of the license may be found at
-/// http://opensource.org/licenses/bsd-license.php.
-///
-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-///
-/// Module Name: AccessDbr.s
-///
-///
-
-//---------------------------------------------------------------------------------
-//++
-// AsmReadDbr
-//
-// This routine is used to Reads the current value of Data Breakpoint Register (DBR).
-//
-// Arguments :
-//
-// On Entry : The 8-bit DBR index to read.
-//
-// Return Value: The current value of DBR by Index.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmReadDbr, @function
-.proc AsmReadDbr
-.regstk 1, 0, 0, 0
-
-AsmReadDbr::
- mov r8 = dbr[in0];;
- br.ret.dpnt b0;;
-.endp AsmReadDbr
-
-//---------------------------------------------------------------------------------
-//++
-// AsmWriteDbr
-//
-// This routine is used to write the current value to Data Breakpoint Register (DBR).
-//
-// Arguments :
-//
-// On Entry : The 8-bit DBR index to read.
-// The value should be written to DBR
-//
-// Return Value: The value written to DBR.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmWriteDbr, @function
-.proc AsmWriteDbr
-.regstk 2, 0, 0, 0
-
-AsmWriteDbr::
- mov dbr[in0] = in1
- mov r8 = in1;;
- srlz.d;;
- br.ret.dpnt b0;;
-.endp AsmWriteDbr
-
-
-//---------------------------------------------------------------------------------
-//++
-// AsmReadIbr
-//
-// This routine is used to Reads the current value of Instruction Breakpoint Register (IBR).
-//
-// Arguments :
-//
-// On Entry : The 8-bit IBR index.
-//
-// Return Value: The current value of IBR by Index.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmReadIbr, @function
-.proc AsmReadIbr
-.regstk 1, 0, 0, 0
-
-AsmReadIbr::
- mov r8 = ibr[in0];;
- br.ret.dpnt b0;;
-.endp AsmReadIbr
-
-//---------------------------------------------------------------------------------
-//++
-// AsmWriteIbr
-//
-// This routine is used to write the current value to Instruction Breakpoint Register (IBR).
-//
-// Arguments :
-//
-// On Entry : The 8-bit IBR index.
-// The value should be written to IBR
-//
-// Return Value: The value written to IBR.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmWriteIbr, @function
-.proc AsmWriteIbr
-.regstk 2, 0, 0, 0
-
-AsmWriteIbr::
- mov ibr[in0] = in1
- mov r8 = in1;;
- srlz.i;;
- br.ret.dpnt b0;;
-.endp AsmWriteIbr
diff --git a/MdePkg/Library/BaseLib/Ipf/AccessEicr.s b/MdePkg/Library/BaseLib/Ipf/AccessEicr.s
deleted file mode 100644
index c2f977e3a8..0000000000
--- a/MdePkg/Library/BaseLib/Ipf/AccessEicr.s
+++ /dev/null
@@ -1,512 +0,0 @@
-/// @file
-/// IPF specific External Interrupt Control Registers accessing functions
-///
-/// Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
-/// This program and the accompanying materials
-/// are licensed and made available under the terms and conditions of the BSD License
-/// which accompanies this distribution. The full text of the license may be found at
-/// http://opensource.org/licenses/bsd-license.php.
-///
-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-///
-/// Module Name: AccessEicr.s
-///
-///
-
-//---------------------------------------------------------------------------------
-//++
-// AsmReadLid
-//
-// This routine is used to read the value of Local Interrupt ID Register (LID).
-//
-// Arguments :
-//
-// On Entry :
-//
-// Return Value: The current value of LID.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmReadLid, @function
-.proc AsmReadLid
-
-AsmReadLid::
- mov r8 = cr.lid;;
- srlz.d;;
- br.ret.dpnt b0;;
-.endp AsmReadLid
-
-//---------------------------------------------------------------------------------
-//++
-// AsmWriteLid
-//
-// This routine is used to write the value to Local Interrupt ID Register (LID).
-//
-// Arguments :
-//
-// On Entry : The value need to be written to LID.
-//
-// Return Value: The value written to LID.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmWriteLid, @function
-.proc AsmWriteLid
-.regstk 1, 0, 0, 0
-
-AsmWriteLid::
- mov cr.lid = in0
- mov r8 = in0;;
- srlz.d;;
- br.ret.dpnt b0;;
-.endp AsmWriteLid
-
-
-//---------------------------------------------------------------------------------
-//++
-// AsmReadIvr
-//
-// This routine is used to read the value of External Interrupt Vector Register (IVR).
-//
-// Arguments :
-//
-// On Entry :
-//
-// Return Value: The current value of IVR.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmReadIvr, @function
-.proc AsmReadIvr
-
-AsmReadIvr::
- mov r8 = cr.ivr;;
- srlz.d;;
- br.ret.dpnt b0;;
-.endp AsmReadIvr
-
-
-//---------------------------------------------------------------------------------
-//++
-// AsmReadTpr
-//
-// This routine is used to read the value of Task Priority Register (TPR).
-//
-// Arguments :
-//
-// On Entry :
-//
-// Return Value: The current value of TPR.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmReadTpr, @function
-.proc AsmReadTpr
-
-AsmReadTpr::
- mov r8 = cr.tpr;;
- br.ret.dpnt b0;;
-.endp AsmReadTpr
-
-//---------------------------------------------------------------------------------
-//++
-// AsmWriteTpr
-//
-// This routine is used to write the value to Task Priority Register (TPR).
-//
-// Arguments :
-//
-// On Entry : The value need to be written to TPR.
-//
-// Return Value: The value written to TPR.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmWriteTpr, @function
-.proc AsmWriteTpr
-.regstk 1, 0, 0, 0
-
-AsmWriteTpr::
- mov cr.tpr = in0
- mov r8 = in0;;
- srlz.d;;
- br.ret.dpnt b0;;
-.endp AsmWriteTpr
-
-
-//---------------------------------------------------------------------------------
-//++
-// AsmWriteEoi
-//
-// This routine is used to write the value to End of External Interrupt Register (EOI).
-//
-// Arguments :
-//
-// On Entry : The value need to be written to EOI.
-//
-// Return Value: The value written to EOI.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmWriteEoi, @function
-.proc AsmWriteEoi
-
-AsmWriteEoi::
- mov cr.eoi = r0;;
- srlz.d;;
- br.ret.dpnt b0;;
-.endp AsmWriteEoi
-
-
-//---------------------------------------------------------------------------------
-//++
-// AsmReadIrr0
-//
-// This routine is used to Read the value of External Interrupt Request Register 0 (IRR0).
-//
-// Arguments :
-//
-// On Entry :
-//
-// Return Value: The current value of IRR0.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmReadIrr0, @function
-.proc AsmReadIrr0
-
-AsmReadIrr0::
- mov r8 = cr.irr0;;
- br.ret.dpnt b0;;
-.endp AsmReadIrr0
-
-
-//---------------------------------------------------------------------------------
-//++
-// AsmReadIrr1
-//
-// This routine is used to Read the value of External Interrupt Request Register 1 (IRR1).
-//
-// Arguments :
-//
-// On Entry :
-//
-// Return Value: The current value of IRR1.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmReadIrr1, @function
-.proc AsmReadIrr1
-
-AsmReadIrr1::
- mov r8 = cr.irr1;;
- br.ret.dpnt b0;;
-.endp AsmReadIrr1
-
-
-//---------------------------------------------------------------------------------
-//++
-// AsmReadIrr2
-//
-// This routine is used to Read the value of External Interrupt Request Register 2 (IRR2).
-//
-// Arguments :
-//
-// On Entry :
-//
-// Return Value: The current value of IRR2.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmReadIrr2, @function
-.proc AsmReadIrr2
-
-AsmReadIrr2::
- mov r8 = cr.irr2;;
- br.ret.dpnt b0;;
-.endp AsmReadIrr2
-
-
-//---------------------------------------------------------------------------------
-//++
-// AsmReadIrr3
-//
-// This routine is used to Read the value of External Interrupt Request Register 3 (IRR3).
-//
-// Arguments :
-//
-// On Entry :
-//
-// Return Value: The current value of IRR3.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmReadIrr3, @function
-.proc AsmReadIrr3
-
-AsmReadIrr3::
- mov r8 = cr.irr3;;
- br.ret.dpnt b0;;
-.endp AsmReadIrr3
-
-
-//---------------------------------------------------------------------------------
-//++
-// AsmReadItv
-//
-// This routine is used to Read the value of Interval Timer Vector Register (ITV).
-//
-// Arguments :
-//
-// On Entry :
-//
-// Return Value: The current value of ITV.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmReadItv, @function
-.proc AsmReadItv
-
-AsmReadItv::
- mov r8 = cr.itv;;
- br.ret.dpnt b0;;
-.endp AsmReadItv
-
-//---------------------------------------------------------------------------------
-//++
-// AsmWriteItv
-//
-// This routine is used to write the value to Interval Timer Vector Register (ITV).
-//
-// Arguments :
-//
-// On Entry : The value need to be written to ITV
-//
-// Return Value: The value written to ITV.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmWriteItv, @function
-.proc AsmWriteItv
-.regstk 1, 0, 0, 0
-
-AsmWriteItv::
- mov cr.itv = in0
- mov r8 = in0;;
- srlz.d;;
- br.ret.dpnt b0;;
-.endp AsmWriteItv
-
-
-//---------------------------------------------------------------------------------
-//++
-// AsmReadPmv
-//
-// This routine is used to Read the value of Performance Monitoring Vector Register (PMV).
-//
-// Arguments :
-//
-// On Entry :
-//
-// Return Value: The current value of PMV.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmReadPmv, @function
-.proc AsmReadPmv
-
-AsmReadPmv::
- mov r8 = cr.pmv;;
- br.ret.dpnt b0;;
-.endp AsmReadPmv
-
-//---------------------------------------------------------------------------------
-//++
-// AsmWritePmv
-//
-// This routine is used to write the value to Performance Monitoring Vector Register (PMV).
-//
-// Arguments :
-//
-// On Entry : The value need to be written to PMV
-//
-// Return Value: The value written to PMV.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmWritePmv, @function
-.proc AsmWritePmv
-.regstk 1, 0, 0, 0
-
-AsmWritePmv::
- mov cr.pmv = in0
- mov r8 = in0;;
- srlz.d;;
- br.ret.dpnt b0;;
-.endp AsmWritePmv
-
-
-//---------------------------------------------------------------------------------
-//++
-// AsmReadCmcv
-//
-// This routine is used to Read the value of Corrected Machine Check Vector Register (CMCV).
-//
-// Arguments :
-//
-// On Entry :
-//
-// Return Value: The current value of CMCV.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmReadCmcv, @function
-.proc AsmReadCmcv
-
-AsmReadCmcv::
- mov r8 = cr.cmcv;;
- br.ret.dpnt b0;;
-.endp AsmReadCmcv
-
-//---------------------------------------------------------------------------------
-//++
-// AsmWriteCmcv
-//
-// This routine is used to write the value to Corrected Machine Check Vector Register (CMCV).
-//
-// Arguments :
-//
-// On Entry : The value need to be written to CMCV
-//
-// Return Value: The value written to CMCV.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmWriteCmcv, @function
-.proc AsmWriteCmcv
-.regstk 1, 0, 0, 0
-
-AsmWriteCmcv::
- mov cr.cmcv = in0
- mov r8 = in0;;
- srlz.d;;
- br.ret.dpnt b0;;
-.endp AsmWriteCmcv
-
-
-//---------------------------------------------------------------------------------
-//++
-// AsmReadLrr0
-//
-// This routine is used to read the value of Local Redirection Register 0 (LRR0).
-//
-// Arguments :
-//
-// On Entry :
-//
-// Return Value: The current value of LRR0.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmReadLrr0, @function
-.proc AsmReadLrr0
-
-AsmReadLrr0::
- mov r8 = cr.lrr0;;
- br.ret.dpnt b0;;
-.endp AsmReadLrr0
-
-//---------------------------------------------------------------------------------
-//++
-// AsmWriteLrr0
-//
-// This routine is used to write the value to Local Redirection Register 0 (LRR0).
-//
-// Arguments :
-//
-// On Entry : The value need to be written to LRR0.
-//
-// Return Value: The value written to LRR0.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmWriteLrr0, @function
-.proc AsmWriteLrr0
-.regstk 1, 0, 0, 0
-
-AsmWriteLrr0::
- mov cr.lrr0 = in0
- mov r8 = in0;;
- srlz.d;;
- br.ret.dpnt b0;;
-.endp AsmWriteLrr0
-
-
-//---------------------------------------------------------------------------------
-//++
-// AsmReadLrr1
-//
-// This routine is used to read the value of Local Redirection Register 1 (LRR1).
-//
-// Arguments :
-//
-// On Entry :
-//
-// Return Value: The current value of LRR1.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmReadLrr1, @function
-.proc AsmReadLrr1
-
-AsmReadLrr1::
- mov r8 = cr.lrr1;;
- br.ret.dpnt b0;;
-.endp AsmReadLrr1
-
-//---------------------------------------------------------------------------------
-//++
-// AsmWriteLrr1
-//
-// This routine is used to write the value to Local Redirection Register 1 (LRR1).
-//
-// Arguments :
-//
-// On Entry : The value need to be written to LRR1.
-//
-// Return Value: The value written to LRR1.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmWriteLrr1, @function
-.proc AsmWriteLrr1
-.regstk 1, 0, 0, 0
-
-AsmWriteLrr1::
- mov cr.lrr1 = in0
- mov r8 = in0;;
- srlz.d;;
- br.ret.dpnt b0;;
-.endp AsmWriteLrr1
-
diff --git a/MdePkg/Library/BaseLib/Ipf/AccessGcr.s b/MdePkg/Library/BaseLib/Ipf/AccessGcr.s
deleted file mode 100644
index d519e7d0f5..0000000000
--- a/MdePkg/Library/BaseLib/Ipf/AccessGcr.s
+++ /dev/null
@@ -1,274 +0,0 @@
-/// @file
-/// IPF specific Global Control Registers accessing functions
-///
-/// Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-/// This program and the accompanying materials
-/// are licensed and made available under the terms and conditions of the BSD License
-/// which accompanies this distribution. The full text of the license may be found at
-/// http://opensource.org/licenses/bsd-license.php.
-///
-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-///
-/// Module Name: AccessGcr.s
-///
-///
-
-//---------------------------------------------------------------------------------
-//++
-// AsmReadDcr
-//
-// This routine is used to Read the value of Default Control Register (DCR).
-//
-// Arguments :
-//
-// On Entry :
-//
-// Return Value: The current value of DCR.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmReadDcr, @function
-.proc AsmReadDcr
-
-AsmReadDcr::
- mov r8 = cr.dcr;;
- br.ret.dpnt b0;;
-.endp AsmReadDcr
-
-//---------------------------------------------------------------------------------
-//++
-// AsmWriteDcr
-//
-// This routine is used to write the value to Default Control Register (DCR).
-//
-// Arguments :
-//
-// On Entry : The value need to be written to DCR
-//
-// Return Value: The value written to DCR.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmWriteDcr, @function
-.proc AsmWriteDcr
-.regstk 1, 0, 0, 0
-
-AsmWriteDcr::
- mov cr.dcr = in0
- mov r8 = in0;;
- srlz.i;;
- srlz.d;;
- br.ret.dpnt b0;;
-.endp AsmWriteDcr
-
-
-//---------------------------------------------------------------------------------
-//++
-// AsmReadItc
-//
-// This routine is used to Read the value of Interval Timer Counter Register (ITC).
-//
-// Arguments :
-//
-// On Entry :
-//
-// Return Value: The current value of ITC.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmReadItc, @function
-.proc AsmReadItc
-
-AsmReadItc::
- mov r8 = ar.itc;;
- br.ret.dpnt b0;;
-.endp AsmReadItc
-
-//---------------------------------------------------------------------------------
-//++
-// AsmWriteItc
-//
-// This routine is used to write the value to Interval Timer Counter Register (ITC).
-//
-// Arguments :
-//
-// On Entry : The value need to be written to the ITC
-//
-// Return Value: The value written to the ITC.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmWriteItc, @function
-.proc AsmWriteItc
-.regstk 1, 0, 0, 0
-
-AsmWriteItc::
- mov ar.itc = in0
- mov r8 = in0;;
- br.ret.dpnt b0;;
-.endp AsmWriteItc
-
-
-//---------------------------------------------------------------------------------
-//++
-// AsmReadItm
-//
-// This routine is used to Read the value of Interval Timer Match Register (ITM).
-//
-// Arguments :
-//
-// On Entry :
-//
-// Return Value: The current value of ITM.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmReadItm, @function
-.proc AsmReadItm
-
-AsmReadItm::
- mov r8 = cr.itm;;
- br.ret.dpnt b0;;
-.endp AsmReadItm
-
-//---------------------------------------------------------------------------------
-//++
-// AsmWriteItm
-//
-// This routine is used to write the value to Interval Timer Match Register (ITM).
-//
-// Arguments :
-//
-// On Entry : The value need to be written to ITM
-//
-// Return Value: The value written to ITM.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmWriteItm, @function
-.proc AsmWriteItm
-.regstk 1, 0, 0, 0
-
-AsmWriteItm::
- mov cr.itm = in0
- mov r8 = in0;;
- srlz.d;
- br.ret.dpnt b0;;
-.endp AsmWriteItm
-
-
-//---------------------------------------------------------------------------------
-//++
-// AsmReadIva
-//
-// This routine is used to read the value of Interruption Vector Address Register (IVA).
-//
-// Arguments :
-//
-// On Entry :
-//
-// Return Value: The current value of IVA.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmReadIva, @function
-.proc AsmReadIva
-
-AsmReadIva::
- mov r8 = cr.iva;;
- br.ret.dpnt b0;;
-.endp AsmReadIva
-
-//---------------------------------------------------------------------------------
-//++
-// AsmWriteIva
-//
-// This routine is used to write the value to Interruption Vector Address Register (IVA).
-//
-// Arguments :
-//
-// On Entry : The value need to be written to IVA
-//
-// Return Value: The value written to IVA.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmWriteIva, @function
-.proc AsmWriteIva
-.regstk 1, 3, 0, 0
-
-AsmWriteIva::
- alloc loc1=ar.pfs,1,4,0,0 ;;
-
- mov loc2 = psr
- rsm 0x6000 // Make sure interrupts are masked
-
- mov cr.iva = in0
- srlz.i;;
- mov psr.l = loc2;;
- srlz.i;;
- srlz.d;;
- mov ar.pfs=loc1 ;;
- mov r8 = in0;;
- br.ret.dpnt b0;;
-.endp AsmWriteIva
-
-
-//---------------------------------------------------------------------------------
-//++
-// AsmReadPta
-//
-// This routine is used to read the value of Page Table Address Register (PTA).
-//
-// Arguments :
-//
-// On Entry :
-//
-// Return Value: The current value of PTA.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmReadPta, @function
-.proc AsmReadPta
-
-AsmReadPta::
- mov r8 = cr.pta;;
- br.ret.dpnt b0;;
-.endp AsmReadPta
-
-//---------------------------------------------------------------------------------
-//++
-// AsmWritePta
-//
-// This routine is used to write the value to Page Table Address Register (PTA)).
-//
-// Arguments :
-//
-// On Entry : The value need to be written to PTA
-//
-// Return Value: The value written to PTA.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmWritePta, @function
-.proc AsmWritePta
-.regstk 1, 0, 0, 0
-
-AsmWritePta::
- mov cr.pta = in0
- mov r8 = in0;;
- srlz.i;;
- srlz.d;;
- br.ret.dpnt b0;;
-.endp AsmWritePta
diff --git a/MdePkg/Library/BaseLib/Ipf/AccessGp.s b/MdePkg/Library/BaseLib/Ipf/AccessGp.s
deleted file mode 100644
index a0e3d3fb55..0000000000
--- a/MdePkg/Library/BaseLib/Ipf/AccessGp.s
+++ /dev/null
@@ -1,86 +0,0 @@
-/// @file
-/// IPF specific Global Pointer and Stack Pointer accessing functions
-///
-/// Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
-/// This program and the accompanying materials
-/// are licensed and made available under the terms and conditions of the BSD License
-/// which accompanies this distribution. The full text of the license may be found at
-/// http://opensource.org/licenses/bsd-license.php.
-///
-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-///
-/// Module Name: AccessGp.s
-///
-///
-
-//---------------------------------------------------------------------------------
-//++
-// AsmReadGp
-//
-// This routine is used to read the current value of 64-bit Global Pointer (GP).
-//
-// Arguments :
-//
-// On Entry :
-//
-// Return Value: The current GP value.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmReadGp, @function
-.proc AsmReadGp
-
-AsmReadGp::
- mov r8 = gp;;
- br.ret.dpnt b0;;
-.endp AsmReadGp
-
-//---------------------------------------------------------------------------------
-//++
-// AsmWriteGp
-//
-// This routine is used to write the current value of 64-bit Global Pointer (GP).
-//
-// Arguments :
-//
-// On Entry : The value need to be written.
-//
-// Return Value: The value have been written.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmWriteGp, @function
-.proc AsmWriteGp
-.regstk 1, 0, 0, 0
-
-AsmWriteGp::
- mov gp = in0
- mov r8 = in0;;
- br.ret.dpnt b0;;
-.endp AsmWriteGp
-
-//---------------------------------------------------------------------------------
-//++
-// AsmReadSp
-//
-// This routine is used to read the current value of 64-bit Stack Pointer (SP).
-//
-// Arguments :
-//
-// On Entry :
-//
-// Return Value: The current SP value.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmReadSp, @function
-.proc AsmReadSp
-
-AsmReadSp::
- mov r8 = sp;;
- br.ret.dpnt b0;;
-.endp AsmReadSp
diff --git a/MdePkg/Library/BaseLib/Ipf/AccessKr.s b/MdePkg/Library/BaseLib/Ipf/AccessKr.s
deleted file mode 100644
index 4d4798de76..0000000000
--- a/MdePkg/Library/BaseLib/Ipf/AccessKr.s
+++ /dev/null
@@ -1,360 +0,0 @@
-/// @file
-/// IPF specific AsmReadKrX() and AsmWriteKrX() functions, 'X' is from '0' to '6'
-///
-/// Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
-/// This program and the accompanying materials
-/// are licensed and made available under the terms and conditions of the BSD License
-/// which accompanies this distribution. The full text of the license may be found at
-/// http://opensource.org/licenses/bsd-license.php.
-///
-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-///
-/// Module Name: AccessKr.s
-///
-///
-
-//---------------------------------------------------------------------------------
-//++
-// AsmReadKr0
-//
-// This routine is used to get KR0.
-//
-// Arguments :
-//
-// On Entry : None.
-//
-// Return Value: The value store in KR0.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmReadKr0, @function
-.proc AsmReadKr0
-
-AsmReadKr0::
- mov r8 = ar.k0;;
- br.ret.dpnt b0;;
-.endp AsmReadKr0
-
-//---------------------------------------------------------------------------------
-//++
-// AsmWriteKr0
-//
-// This routine is used to Write KR0.
-//
-// Arguments :
-//
-// On Entry : None.
-//
-// Return Value: The value written to the KR0.
-//
-//--
-//----------------------------------------------------------------------------------
-
-.text
-.type AsmWriteKr0, @function
-.proc AsmWriteKr0
-.regstk 1, 3, 0, 0
-
-AsmWriteKr0::
- alloc loc1=ar.pfs,1,4,0,0 ;;
- mov loc2 = psr;;
- rsm 0x6000;; // Masking interrupts
- mov ar.k0 = in0
- srlz.i;;
- mov psr.l = loc2;;
- srlz.i;;
- srlz.d;;
- mov r8 = in0;;
- mov ar.pfs=loc1 ;;
- br.ret.dpnt b0;;
-.endp AsmWriteKr0
-
-
-//---------------------------------------------------------------------------------
-//++
-// AsmReadKr1
-//
-// This routine is used to get KR1.
-//
-// Arguments :
-//
-// On Entry : None.
-//
-// Return Value: The value store in KR1.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmReadKr1, @function
-.proc AsmReadKr1
-
-AsmReadKr1::
- mov r8 = ar.k1;;
- br.ret.dpnt b0;;
-.endp AsmReadKr1
-
-//---------------------------------------------------------------------------------
-//++
-// AsmWriteKr1
-//
-// This routine is used to Write KR1.
-//
-// Arguments :
-//
-// On Entry : None.
-//
-// Return Value: The value written to the KR1.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmWriteKr1, @function
-.proc AsmWriteKr1
-
-AsmWriteKr1::
- mov ar.k1 = in0
- mov r8 = in0;;
- br.ret.dpnt b0;;
-.endp AsmWriteKr1
-
-
-//---------------------------------------------------------------------------------
-//++
-// AsmReadKr2
-//
-// This routine is used to get KR2.
-//
-// Arguments :
-//
-// On Entry : None.
-//
-// Return Value: The value store in KR2.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmReadKr2, @function
-.proc AsmReadKr2
-
-AsmReadKr2::
- mov r8 = ar.k2;;
- br.ret.dpnt b0;;
-.endp AsmReadKr2
-
-//---------------------------------------------------------------------------------
-//++
-// AsmWriteKr2
-//
-// This routine is used to Write KR2.
-//
-// Arguments :
-//
-// On Entry : None.
-//
-// Return Value: The value written to the KR2.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmWriteKr2, @function
-.proc AsmWriteKr2
-
-AsmWriteKr2::
- mov ar.k2 = in0
- mov r8 = in0;;
- br.ret.dpnt b0;;
-.endp AsmWriteKr2
-
-
-//---------------------------------------------------------------------------------
-//++
-// AsmReadKr3
-//
-// This routine is used to get KR3.
-//
-// Arguments :
-//
-// On Entry : None.
-//
-// Return Value: The value store in KR3.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmReadKr3, @function
-.proc AsmReadKr3
-
-AsmReadKr3::
- mov r8 = ar.k3;;
- br.ret.dpnt b0;;
-.endp AsmReadKr3
-
-//---------------------------------------------------------------------------------
-//++
-// AsmWriteKr3
-//
-// This routine is used to Write KR3.
-//
-// Arguments :
-//
-// On Entry : None.
-//
-// Return Value: The value written to the KR3.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmWriteKr3, @function
-.proc AsmWriteKr3
-
-AsmWriteKr3::
- mov ar.k3 = in0
- mov r8 = in0;;
- br.ret.dpnt b0;;
-.endp AsmWriteKr3
-
-
-//---------------------------------------------------------------------------------
-//++
-// AsmReadKr4
-//
-// This routine is used to get KR4.
-//
-// Arguments :
-//
-// On Entry : None.
-//
-// Return Value: The value store in KR4.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmReadKr4, @function
-.proc AsmReadKr4
-
-AsmReadKr4::
- mov r8 = ar.k4;;
- br.ret.dpnt b0;;
-.endp AsmReadKr4
-
-//---------------------------------------------------------------------------------
-//++
-// AsmWriteKr4
-//
-// This routine is used to Write KR4.
-//
-// Arguments :
-//
-// On Entry : None.
-//
-// Return Value: The value written to the KR4.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmWriteKr4, @function
-.proc AsmWriteKr4
-
-AsmWriteKr4::
- mov ar.k4 = in0
- mov r8 = in0;;
- br.ret.dpnt b0;;
-.endp AsmWriteKr4
-
-
-//---------------------------------------------------------------------------------
-//++
-// AsmReadKr5
-//
-// This routine is used to get KR5.
-//
-// Arguments :
-//
-// On Entry : None.
-//
-// Return Value: The value store in KR5.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmReadKr5, @function
-.proc AsmReadKr5
-
-AsmReadKr5::
- mov r8 = ar.k5;;
- br.ret.dpnt b0;;
-.endp AsmReadKr5
-
-//---------------------------------------------------------------------------------
-//++
-// AsmWriteKr5
-//
-// This routine is used to Write KR5.
-//
-// Arguments :
-//
-// On Entry : None.
-//
-// Return Value: The value written to the KR5.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmWriteKr5, @function
-.proc AsmWriteKr5
-
-AsmWriteKr5::
- mov ar.k5 = in0
- mov r8 = in0;;
- br.ret.dpnt b0;;
-.endp AsmWriteKr5
-
-
-//---------------------------------------------------------------------------------
-//++
-// AsmReadKr6
-//
-// This routine is used to get KR6.
-//
-// Arguments :
-//
-// On Entry : None.
-//
-// Return Value: The value store in KR6.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmReadKr6, @function
-.proc AsmReadKr6
-
-AsmReadKr6::
- mov r8 = ar.k6;;
- br.ret.dpnt b0;;
-.endp AsmReadKr6
-
-//---------------------------------------------------------------------------------
-//++
-// AsmWriteKr6
-//
-// This routine is used to write KR6.
-//
-// Arguments :
-//
-// On Entry : None.
-//
-// Return Value: The value written to the KR6.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmWriteKr6, @function
-.proc AsmWriteKr6
-
-AsmWriteKr6::
- mov ar.k6 = in0
- mov r8 = in0;;
- br.ret.dpnt b0;;
-.endp AsmWriteKr6
diff --git a/MdePkg/Library/BaseLib/Ipf/AccessKr7.s b/MdePkg/Library/BaseLib/Ipf/AccessKr7.s
deleted file mode 100644
index 66a3dbfd35..0000000000
--- a/MdePkg/Library/BaseLib/Ipf/AccessKr7.s
+++ /dev/null
@@ -1,63 +0,0 @@
-/// @file
-/// IPF specific AsmReadKr7() and AsmWriteKr7()
-///
-/// Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
-/// This program and the accompanying materials
-/// are licensed and made available under the terms and conditions of the BSD License
-/// which accompanies this distribution. The full text of the license may be found at
-/// http://opensource.org/licenses/bsd-license.php.
-///
-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-///
-/// Module Name: AccessKr7.s
-///
-///
-
-//---------------------------------------------------------------------------------
-//++
-// AsmReadKr7
-//
-// This routine is used to get KR7.
-//
-// Arguments :
-//
-// On Entry : None.
-//
-// Return Value: The value store in KR7.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmReadKr7, @function
-.proc AsmReadKr7
-
-AsmReadKr7::
- mov r8 = ar.k7;;
- br.ret.dpnt b0;;
-.endp AsmReadKr7
-
-//---------------------------------------------------------------------------------
-//++
-// AsmWriteKr7
-//
-// This routine is used to write KR7.
-//
-// Arguments :
-//
-// On Entry : None.
-//
-// Return Value: The value written to the KR7.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmWriteKr7, @function
-.proc AsmWriteKr7
-.regstk 1, 3, 0, 0
-
-AsmWriteKr7::
- mov ar.k7 = in0
- mov r8 = in0;;
- br.ret.dpnt b0;;
-.endp AsmWriteKr7
diff --git a/MdePkg/Library/BaseLib/Ipf/AccessMsr.s b/MdePkg/Library/BaseLib/Ipf/AccessMsr.s
deleted file mode 100644
index 11b3f1eafb..0000000000
--- a/MdePkg/Library/BaseLib/Ipf/AccessMsr.s
+++ /dev/null
@@ -1,79 +0,0 @@
-/// @file
-/// IPF specific Machine Specific Registers accessing functions.
-///
-/// Copyright (c) 2008, Intel Corporation. All rights reserved.<BR>
-/// This program and the accompanying materials
-/// are licensed and made available under the terms and conditions of the BSD License
-/// which accompanies this distribution. The full text of the license may be found at
-/// http://opensource.org/licenses/bsd-license.php.
-///
-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-///
-///
-///
-
-
-//---------------------------------------------------------------------------------
-//++
-// AsmReadMsr
-//
-// Reads the current value of a Machine Specific Register (MSR).
-//
-// Reads and returns the current value of the Machine Specific Register specified by Index. No
-// parameter checking is performed on Index, and if the Index value is beyond the implemented MSR
-// register range, a Reserved Register/Field fault may occur. The caller must either guarantee that
-// Index is valid, or the caller must set up fault handlers to catch the faults. This function is
-// only available on IPF.
-//
-// Arguments :
-//
-// On Entry : The 8-bit Machine Specific Register index to read.
-//
-// Return Value: The current value of the Machine Specific Register specified by Index.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmReadMsr, @function
-.proc AsmReadMsr
-.regstk 1, 0, 0, 0
-
-AsmReadMsr::
- mov r8=msr[in0];;
- br.ret.sptk b0;;
-.endp AsmReadMsr
-
-//---------------------------------------------------------------------------------
-//++
-// AsmWriteMsr
-//
-// Writes the current value of a Machine Specific Register (MSR).
-//
-// Writes Value to the Machine Specific Register specified by Index. Value is returned. No
-// parameter checking is performed on Index, and if the Index value is beyond the implemented MSR
-// register range, a Reserved Register/Field fault may occur. The caller must either guarantee that
-// Index is valid, or the caller must set up fault handlers to catch the faults. This function is
-// only available on IPF.
-//
-// Arguments :
-//
-// On Entry : The 8-bit Machine Specific Register index to write.
-// The 64-bit value to write to the Machine Specific Register.
-//
-// Return Value: The 64-bit value to write to the Machine Specific Register.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmWriteMsr, @function
-.proc AsmWriteMsr
-.regstk 2, 0, 0, 0
-
-AsmWriteMsr::
- mov msr[in0] = in1
- mov r8 = in1;;
- srlz.d;;
- br.ret.sptk b0;;
-.endp AsmWriteMsr
-
diff --git a/MdePkg/Library/BaseLib/Ipf/AccessMsrDb.s b/MdePkg/Library/BaseLib/Ipf/AccessMsrDb.s
deleted file mode 100644
index 79468e0500..0000000000
--- a/MdePkg/Library/BaseLib/Ipf/AccessMsrDb.s
+++ /dev/null
@@ -1,121 +0,0 @@
-/// @file
-/// IPF specific Machine Specific Registers accessing functions.
-/// This implementation uses raw data to prepresent the assembly instruction of
-/// mov msr[]= and mov =msr[].
-///
-/// Copyright (c) 2008, Intel Corporation. All rights reserved.<BR>
-/// This program and the accompanying materials
-/// are licensed and made available under the terms and conditions of the BSD License
-/// which accompanies this distribution. The full text of the license may be found at
-/// http://opensource.org/licenses/bsd-license.php.
-///
-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-///
-///
-///
-
-
-//---------------------------------------------------------------------------------
-//++
-// AsmReadMsr
-//
-// Reads the current value of a Machine Specific Register (MSR).
-//
-// Reads and returns the current value of the Machine Specific Register specified by Index. No
-// parameter checking is performed on Index, and if the Index value is beyond the implemented MSR
-// register range, a Reserved Register/Field fault may occur. The caller must either guarantee that
-// Index is valid, or the caller must set up fault handlers to catch the faults. This function is
-// only available on IPF.
-//
-// Arguments :
-//
-// On Entry : The 8-bit Machine Specific Register index to read.
-//
-// Return Value: The current value of the Machine Specific Register specified by Index.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmReadMsr, @function
-.proc AsmReadMsr
-.regstk 1, 0, 0, 0
-
-AsmReadMsr::
-//
-// The follow 16 bytes stand for the bundle of
-// mov r8=msr[in0];;
-// since MSFT tool chain does not support mov =msr[] instruction
-//
- data1 0x0D
- data1 0x40
- data1 0x00
- data1 0x40
- data1 0x16
- data1 0x04
- data1 0x00
- data1 0x00
- data1 0x00
- data1 0x02
- data1 0x00
- data1 0x00
- data1 0x00
- data1 0x00
- data1 0x04
- data1 0x00
- br.ret.sptk b0;;
-.endp AsmReadMsr
-
-//---------------------------------------------------------------------------------
-//++
-// AsmWriteMsr
-//
-// Writes the current value of a Machine Specific Register (MSR).
-//
-// Writes Value to the Machine Specific Register specified by Index. Value is returned. No
-// parameter checking is performed on Index, and if the Index value is beyond the implemented MSR
-// register range, a Reserved Register/Field fault may occur. The caller must either guarantee that
-// Index is valid, or the caller must set up fault handlers to catch the faults. This function is
-// only available on IPF.
-//
-// Arguments :
-//
-// On Entry : The 8-bit Machine Specific Register index to write.
-// The 64-bit value to write to the Machine Specific Register.
-//
-// Return Value: The 64-bit value to write to the Machine Specific Register.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmWriteMsr, @function
-.proc AsmWriteMsr
-.regstk 2, 0, 0, 0
-
-AsmWriteMsr::
-//
-// The follow 16 bytes stand for the bundle of
-// mov msr[in0] = in1
-// mov r8 = in1;;
-// since MSFT tool chain does not support mov msr[]= instruction
-//
- data1 0x0D
- data1 0x00
- data1 0x84
- data1 0x40
- data1 0x06
- data1 0x04
- data1 0x00
- data1 0x00
- data1 0x00
- data1 0x02
- data1 0x00
- data1 0x00
- data1 0x01
- data1 0x08
- data1 0x01
- data1 0x84
- srlz.d;;
- br.ret.sptk b0;;
-.endp AsmWriteMsr
-
diff --git a/MdePkg/Library/BaseLib/Ipf/AccessPmr.s b/MdePkg/Library/BaseLib/Ipf/AccessPmr.s
deleted file mode 100644
index cc75b4f263..0000000000
--- a/MdePkg/Library/BaseLib/Ipf/AccessPmr.s
+++ /dev/null
@@ -1,124 +0,0 @@
-/// @file
-/// IPF specific Performance Monitor Configuration/Data Registers accessing functions
-///
-/// Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
-/// This program and the accompanying materials
-/// are licensed and made available under the terms and conditions of the BSD License
-/// which accompanies this distribution. The full text of the license may be found at
-/// http://opensource.org/licenses/bsd-license.php.
-///
-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-///
-/// Module Name: AccessPmr.s
-///
-///
-
-//---------------------------------------------------------------------------------
-//++
-// AsmReadPmc
-//
-// This routine is used to Reads the current value of Performance Monitor Configuration Register (PMC).
-//
-// Arguments :
-//
-// On Entry : The 8-bit PMC index.
-//
-// Return Value: The current value of PMC by Index.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmReadPmc, @function
-.proc AsmReadPmc
-.regstk 1, 0, 0, 0
-
-AsmReadPmc::
- srlz.i;;
- srlz.d;;
- mov r8 = pmc[in0];;
- br.ret.dpnt b0;;
-.endp AsmReadPmc
-
-//---------------------------------------------------------------------------------
-//++
-// AsmWritePmc
-//
-// This routine is used to write the current value to a Performance Monitor Configuration Register (PMC).
-//
-// Arguments :
-//
-// On Entry : The 8-bit PMC index.
-// The value should be written to PMC
-//
-// Return Value: The value written to PMC.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmWritePmc, @function
-.proc AsmWritePmc
-.regstk 2, 0, 0, 0
-
-AsmWritePmc::
- mov pmc[in0] = in1
- mov r8 = in1;;
- srlz.i;;
- srlz.d;;
- br.ret.dpnt b0;;
-.endp AsmWritePmc
-
-
-//---------------------------------------------------------------------------------
-//++
-// AsmReadPmd
-//
-// This routine is used to Reads the current value of Performance Monitor Data Register (PMD).
-//
-// Arguments :
-//
-// On Entry : The 8-bit PMD index.
-//
-// Return Value: The current value of PMD by Index.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmReadPmd, @function
-.proc AsmReadPmd
-.regstk 1, 0, 0, 0
-
-AsmReadPmd::
- srlz.i;;
- srlz.d;;
- mov r8 = pmd[in0];;
- br.ret.dpnt b0;;
-.endp AsmReadPmd
-
-//---------------------------------------------------------------------------------
-//++
-// AsmWritePmd
-//
-// This routine is used to write the current value to Performance Monitor Data Register (PMD).
-//
-// Arguments :
-//
-// On Entry : The 8-bit PMD index.
-// The value should be written to PMD
-//
-// Return Value: The value written to PMD.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmWritePmd, @function
-.proc AsmWritePmd
-.regstk 2, 0, 0, 0
-
-AsmWritePmd::
- mov pmd[in0] = in1
- mov r8 = in1;;
- srlz.i;;
- srlz.d;;
- br.ret.dpnt b0;;
-.endp AsmWritePmd
diff --git a/MdePkg/Library/BaseLib/Ipf/AccessPsr.s b/MdePkg/Library/BaseLib/Ipf/AccessPsr.s
deleted file mode 100644
index b183ba01b1..0000000000
--- a/MdePkg/Library/BaseLib/Ipf/AccessPsr.s
+++ /dev/null
@@ -1,111 +0,0 @@
-/// @file
-/// IPF specific Processor Status Register accessing functions
-///
-/// Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
-/// This program and the accompanying materials
-/// are licensed and made available under the terms and conditions of the BSD License
-/// which accompanies this distribution. The full text of the license may be found at
-/// http://opensource.org/licenses/bsd-license.php.
-///
-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-///
-/// Module Name: AccessPsr.s
-///
-///
-
-#define CpuModeMask 0x0000001008020000
-
-#define CpuInVirtualMode 0x1
-#define CpuInPhysicalMode 0x0
-#define CpuInMixMode (0x0 - 0x1)
-
-//---------------------------------------------------------------------------------
-//++
-// AsmReadPsr
-//
-// This routine is used to read the current value of Processor Status Register (PSR).
-//
-// Arguments :
-//
-// On Entry :
-//
-// Return Value: The current PSR value.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmReadPsr, @function
-.proc AsmReadPsr
-
-AsmReadPsr::
- mov r8 = psr;;
- br.ret.dpnt b0;;
-.endp AsmReadPsr
-
-//---------------------------------------------------------------------------------
-//++
-// AsmWritePsr
-//
-// This routine is used to write the value of Processor Status Register (PSR).
-//
-// Arguments :
-//
-// On Entry : The value need to be written.
-//
-// Return Value: The value have been written.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmWritePsr, @function
-.proc AsmWritePsr
-.regstk 1, 0, 0, 0
-
-AsmWritePsr::
- mov psr.l = in0
- mov r8 = in0;;
- srlz.d;;
- srlz.i;;
- br.ret.dpnt b0;;
-.endp AsmWritePsr
-
-//---------------------------------------------------------------------------------
-//++
-// AsmCpuVirtual
-//
-// This routine is used to determines if the CPU is currently executing
-// in virtual, physical, or mixed mode.
-//
-// If the CPU is in virtual mode(PSR.RT=1, PSR.DT=1, PSR.IT=1), then 1 is returned.
-// If the CPU is in physical mode(PSR.RT=0, PSR.DT=0, PSR.IT=0), then 0 is returned.
-// If the CPU is not in physical mode or virtual mode, then it is in mixed mode,
-// and -1 is returned.
-//
-// Arguments:
-//
-// On Entry: None
-//
-// Return Value: The CPU mode flag
-// return 1 The CPU is in virtual mode.
-// return 0 The CPU is in physical mode.
-// return -1 The CPU is in mixed mode.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmCpuVirtual, @function
-.proc AsmCpuVirtual
-
-AsmCpuVirtual::
- mov r29 = psr
- movl r30 = CpuModeMask;;
- and r28 = r30, r29;;
- cmp.eq p6, p7 = r30, r28;;
-(p6) mov r8 = CpuInVirtualMode;;
-(p6) br.ret.dpnt b0;;
-(p7) cmp.eq p6, p7 = 0x0, r28;;
-(p6) mov r8 = CpuInPhysicalMode;;
-(p7) mov r8 = CpuInMixMode;;
- br.ret.dpnt b0;;
-.endp AsmCpuVirtual
diff --git a/MdePkg/Library/BaseLib/Ipf/Asm.h b/MdePkg/Library/BaseLib/Ipf/Asm.h
deleted file mode 100644
index 54345734f1..0000000000
--- a/MdePkg/Library/BaseLib/Ipf/Asm.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/** @file
-
- This module contains generic macros for an assembly writer.
-
-Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution. The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-**/
-
-#ifndef _ASM_H_
-#define _ASM_H_
-
-#define TRUE 1
-#define FALSE 0
-#define PROCEDURE_ENTRY(name) .##text; \
- .##type name, @function; \
- .##proc name; \
- name::
-
-#define PROCEDURE_EXIT(name) .##endp name
-
-#endif // _ASM_H
diff --git a/MdePkg/Library/BaseLib/Ipf/AsmCpuMisc.s b/MdePkg/Library/BaseLib/Ipf/AsmCpuMisc.s
deleted file mode 100644
index 91075bf7b3..0000000000
--- a/MdePkg/Library/BaseLib/Ipf/AsmCpuMisc.s
+++ /dev/null
@@ -1,79 +0,0 @@
-/// @file
-/// Contains an implementation of CallPalProcStacked on Itanium-based
-/// architecture.
-///
-/// Copyright (c) 2008, Intel Corporation. All rights reserved.<BR>
-/// This program and the accompanying materials
-/// are licensed and made available under the terms and conditions of the BSD License
-/// which accompanies this distribution. The full text of the license may be found at
-/// http://opensource.org/licenses/bsd-license.php.
-///
-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-///
-/// Module Name: AsmCpuMisc.s
-///
-///
-
-
-.text
-.proc CpuBreakpoint
-.type CpuBreakpoint, @function
-
-CpuBreakpoint::
- break.i 0;;
- br.ret.dpnt b0;;
-
-.endp CpuBreakpoint
-
-.proc MemoryFence
-.type MemoryFence, @function
-
-MemoryFence::
- mf;; // memory access ordering
-
- // do we need the mf.a also here?
- mf.a // wait for any IO to complete?
-
- // not sure if we need serialization here, just put it, in case...
-
- srlz.d;;
- srlz.i;;
-
- br.ret.dpnt b0;;
-.endp MemoryFence
-
-.proc DisableInterrupts
-.type DisableInterrupts, @function
-
-DisableInterrupts::
- rsm 0x4000
- srlz.d;;
- br.ret.dpnt b0;;
-
-.endp DisableInterrupts
-
-.proc EnableInterrupts
-.type EnableInterrupts, @function
-
-EnableInterrupts::
- ssm 0x4000
- srlz.d;;
- br.ret.dpnt b0;;
-
-.endp EnableInterrupts
-
-.proc EnableDisableInterrupts
-.type EnableDisableInterrupts, @function
-
-EnableDisableInterrupts::
- ssm 0x4000
- srlz.d;;
- srlz.i;;
- rsm 0x4000
- srlz.d;;
-
- br.ret.dpnt b0;;
-
-.endp EnableDisableInterrupts
-
diff --git a/MdePkg/Library/BaseLib/Ipf/AsmPalCall.s b/MdePkg/Library/BaseLib/Ipf/AsmPalCall.s
deleted file mode 100644
index 7fd40aa2b4..0000000000
--- a/MdePkg/Library/BaseLib/Ipf/AsmPalCall.s
+++ /dev/null
@@ -1,158 +0,0 @@
-/// @file
-/// Contains an implementation of CallPalProcStacked on Itanium-based
-/// architecture.
-///
-/// Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-/// This program and the accompanying materials
-/// are licensed and made available under the terms and conditions of the BSD License
-/// which accompanies this distribution. The full text of the license may be found at
-/// http://opensource.org/licenses/bsd-license.php.
-///
-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-///
-/// Module Name: AsmPalCall.s
-///
-///
-
-
-//-----------------------------------------------------------------------------
-//++
-// AsmPalCall
-//
-// Makes a PAL procedure call.
-// This is function to make a PAL procedure call. Based on the Index
-// value this API will make static or stacked PAL call. The following table
-// describes the usage of PAL Procedure Index Assignment. Architected procedures
-// may be designated as required or optional. If a PAL procedure is specified
-// as optional, a unique return code of 0xFFFFFFFFFFFFFFFF is returned in the
-// Status field of the PAL_CALL_RETURN structure.
-// This indicates that the procedure is not present in this PAL implementation.
-// It is the caller's responsibility to check for this return code after calling
-// any optional PAL procedure.
-// No parameter checking is performed on the 5 input parameters, but there are
-// some common rules that the caller should follow when making a PAL call. Any
-// address passed to PAL as buffers for return parameters must be 8-byte aligned.
-// Unaligned addresses may cause undefined results. For those parameters defined
-// as reserved or some fields defined as reserved must be zero filled or the invalid
-// argument return value may be returned or undefined result may occur during the
-// execution of the procedure. If the PalEntryPoint does not point to a valid
-// PAL entry point then the system behavior is undefined. This function is only
-// available on IPF.
-//
-// On Entry :
-// in0: PAL_PROC entrypoint
-// in1-in4 : PAL_PROC arguments
-//
-// Return Value:
-//
-// As per stacked calling conventions.
-//
-//--
-//---------------------------------------------------------------------------
-
-//
-// PAL function calls
-//
-#define PAL_MC_CLEAR_LOG 0x0015
-#define PAL_MC_DYNAMIC_STATE 0x0018
-#define PAL_MC_ERROR_INFO 0x0019
-#define PAL_MC_RESUME 0x001a
-
-
-.text
-.proc AsmPalCall
-.type AsmPalCall, @function
-
-AsmPalCall::
- alloc loc1 = ar.pfs,5,8,4,0
- mov loc0 = b0
- mov loc3 = b5
- mov loc4 = r2
- mov loc7 = r1
- mov r2 = psr;;
- mov r28 = in1
- mov loc5 = r2;;
-
- movl loc6 = 0x100;;
- cmp.ge p6,p7 = r28,loc6;;
-
-(p6) movl loc6 = 0x1FF;;
-(p7) br.dpnt.few PalCallStatic;; // 0 ~ 255 make a static Pal Call
-(p6) cmp.le p6,p7 = r28,loc6;;
-(p6) br.dpnt.few PalCallStacked;; // 256 ~ 511 make a stacked Pal Call
-(p7) movl loc6 = 0x300;;
-(p7) cmp.ge p6,p7 = r28,loc6;;
-(p7) br.dpnt.few PalCallStatic;; // 512 ~ 767 make a static Pal Call
-(p6) movl loc6 = 0x3FF;;
-(p6) cmp.le p6,p7 = r28,loc6;;
-(p6) br.dpnt.few PalCallStacked;; // 768 ~ 1023 make a stacked Pal Call
-
-(p7) mov r8 = 0xFFFFFFFFFFFFFFFF;; // > 1024 return invalid
-(p7) br.dpnt.few ComeBackFromPALCall;;
-
-PalCallStatic:
- movl loc6 = PAL_MC_CLEAR_LOG;;
- cmp.eq p6,p7 = r28,loc6;;
-
-(p7) movl loc6 = PAL_MC_DYNAMIC_STATE;;
-(p7) cmp.eq p6,p7 = r28,loc6;;
-
-(p7) movl loc6 = PAL_MC_ERROR_INFO;;
-(p7) cmp.eq p6,p7 = r28,loc6;;
-
-(p7) movl loc6 = PAL_MC_RESUME;;
-(p7) cmp.eq p6,p7 = r28,loc6 ;;
-
- mov loc6 = 0x1;;
-(p7) dep r2 = loc6,r2,13,1;; // psr.ic = 1
-
-// p6 will be true, if it is one of the MCHK calls. There has been lots of debate
-// on psr.ic for these values. For now, do not do any thing to psr.ic
-
- dep r2 = r0,r2,14,1;; // psr.i = 0
-
- mov psr.l = r2
- srlz.d // Needs data serailization.
- srlz.i // Needs instruction serailization.
-
-StaticGetPALLocalIP:
- mov loc2 = ip;;
- add loc2 = ComeBackFromPALCall - StaticGetPALLocalIP,loc2;;
- mov b0 = loc2 // return address after Pal call
-
- mov r29 = in2
- mov r30 = in3
- mov r31 = in4
- mov b5 = in0;; // get the PalProcEntrypt from input
- br.sptk b5;; // Take the plunge.
-
-PalCallStacked:
- dep r2 = r0,r2,14,1;; // psr.i = 0
- mov psr.l = r2;;
- srlz.d // Needs data serailization.
- srlz.i // Needs instruction serailization.
-
-StackedGetPALLocalIP:
- mov out0 = in1
- mov out1 = in2
- mov out2 = in3
- mov out3 = in4
- mov b5 = in0 ;; // get the PalProcEntrypt from input
- br.call.dpnt b0 = b5 ;; // Take the plunge.
-
-ComeBackFromPALCall:
- mov psr.l = loc5 ;;
- srlz.d // Needs data serailization.
- srlz.i // Needs instruction serailization.
-
- mov b5 = loc3
- mov r2 = loc4
- mov r1 = loc7
-
- mov b0 = loc0
- mov ar.pfs = loc1;;
- br.ret.dpnt b0;;
-
-.endp AsmPalCall
-
diff --git a/MdePkg/Library/BaseLib/Ipf/CpuBreakpoint.c b/MdePkg/Library/BaseLib/Ipf/CpuBreakpoint.c
deleted file mode 100644
index 302974bd5c..0000000000
--- a/MdePkg/Library/BaseLib/Ipf/CpuBreakpoint.c
+++ /dev/null
@@ -1,96 +0,0 @@
-/** @file
- Base Library CPU functions for Itanium
-
- Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php.
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-
-#include "BaseLibInternals.h"
-
-/**
- Generates a breakpoint on the CPU.
-
- Generates a breakpoint on the CPU. The breakpoint must be implemented such
- that code can resume normal execution after the breakpoint.
-
-**/
-VOID
-EFIAPI
-CpuBreakpoint (
- VOID
- )
-{
- __break (0);
-}
-
-/**
- Used to serialize load and store operations.
-
- All loads and stores that proceed calls to this function are guaranteed to be
- globally visible when this function returns.
-
-**/
-VOID
-EFIAPI
-MemoryFence (
- VOID
- )
-{
- __mfa ();
-}
-
-/**
- Disables CPU interrupts.
-
- Disables CPU interrupts.
-
-**/
-VOID
-EFIAPI
-DisableInterrupts (
- VOID
- )
-{
- _disable ();
-}
-
-/**
- Enables CPU interrupts.
-
- Enables CPU interrupts.
-
-**/
-VOID
-EFIAPI
-EnableInterrupts (
- VOID
- )
-{
- _enable ();
-}
-
-/**
- Enables CPU interrupts for the smallest window required to capture any
- pending interrupts.
-
- Enables CPU interrupts for the smallest window required to capture any
- pending interrupts.
-
-**/
-VOID
-EFIAPI
-EnableDisableInterrupts (
- VOID
- )
-{
- EnableInterrupts ();
- DisableInterrupts ();
-}
diff --git a/MdePkg/Library/BaseLib/Ipf/CpuBreakpointMsc.c b/MdePkg/Library/BaseLib/Ipf/CpuBreakpointMsc.c
deleted file mode 100644
index 89b0acfd80..0000000000
--- a/MdePkg/Library/BaseLib/Ipf/CpuBreakpointMsc.c
+++ /dev/null
@@ -1,102 +0,0 @@
-/** @file
- Base Library CPU functions for Itanium
-
- Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php.
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-
-#include "BaseLibInternals.h"
-
-#pragma intrinsic (_enable)
-#pragma intrinsic (_disable)
-#pragma intrinsic (__break)
-#pragma intrinsic (__mfa)
-
-/**
- Generates a breakpoint on the CPU.
-
- Generates a breakpoint on the CPU. The breakpoint must be implemented such
- that code can resume normal execution after the breakpoint.
-
-**/
-VOID
-EFIAPI
-CpuBreakpoint (
- VOID
- )
-{
- __break (0);
-}
-
-/**
- Used to serialize load and store operations.
-
- All loads and stores that proceed calls to this function are guaranteed to be
- globally visible when this function returns.
-
-**/
-VOID
-EFIAPI
-MemoryFence (
- VOID
- )
-{
- __mfa ();
-}
-
-/**
- Disables CPU interrupts.
-
- Disables CPU interrupts.
-
-**/
-VOID
-EFIAPI
-DisableInterrupts (
- VOID
- )
-{
- _disable ();
-}
-
-/**
- Enables CPU interrupts.
-
- Enables CPU interrupts.
-
-**/
-VOID
-EFIAPI
-EnableInterrupts (
- VOID
- )
-{
- _enable ();
-}
-
-/**
- Enables CPU interrupts for the smallest window required to capture any
- pending interrupts.
-
- Enables CPU interrupts for the smallest window required to capture any
- pending interrupts.
-
-**/
-VOID
-EFIAPI
-EnableDisableInterrupts (
- VOID
- )
-{
- EnableInterrupts ();
- DisableInterrupts ();
-}
-
diff --git a/MdePkg/Library/BaseLib/Ipf/CpuPause.s b/MdePkg/Library/BaseLib/Ipf/CpuPause.s
deleted file mode 100644
index d881aaa3a0..0000000000
--- a/MdePkg/Library/BaseLib/Ipf/CpuPause.s
+++ /dev/null
@@ -1,25 +0,0 @@
-/// @file
-/// CpuPause() function for Itanium-based architecture.
-///
-/// Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
-/// This program and the accompanying materials
-/// are licensed and made available under the terms and conditions of the BSD License
-/// which accompanies this distribution. The full text of the license may be found at
-/// http://opensource.org/licenses/bsd-license.php.
-///
-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-///
-/// Module Name: CpuPause.s
-///
-///
-
-.auto
-.text
-
-.proc CpuPause
-.type CpuPause, @function
-CpuPause::
- hint.i @pause
- br.ret.sptk.many b0
-.endp
diff --git a/MdePkg/Library/BaseLib/Ipf/ExecFc.s b/MdePkg/Library/BaseLib/Ipf/ExecFc.s
deleted file mode 100644
index a7c4e30e9c..0000000000
--- a/MdePkg/Library/BaseLib/Ipf/ExecFc.s
+++ /dev/null
@@ -1,66 +0,0 @@
-/// @file
-/// IPF specific AsmFc() and AsmFci () functions
-///
-/// Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-/// This program and the accompanying materials
-/// are licensed and made available under the terms and conditions of the BSD License
-/// which accompanies this distribution. The full text of the license may be found at
-/// http://opensource.org/licenses/bsd-license.php.
-///
-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-///
-/// Module Name: ExecFc.s
-///
-///
-
-//---------------------------------------------------------------------------------
-//++
-// AsmFc
-//
-// This routine is used to execute a FC instruction on the specific address.
-//
-// Arguments :
-//
-// On Entry : The specific address need to execute FC instruction.
-//
-// Return Value: The specific address have been execute FC instruction.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmFc, @function
-.proc AsmFc
-.regstk 1, 0, 0, 0
-
-AsmFc::
- fc in0
- mov r8 = in0;;
- br.ret.dpnt b0;;
-.endp AsmFc
-
-
-//---------------------------------------------------------------------------------
-//++
-// AsmFci
-//
-// This routine is used to execute a FC.i instruction on the specific address.
-//
-// Arguments :
-//
-// On Entry : The specific address need to execute FC.i instruction.
-//
-// Return Value: The specific address have been execute FC.i instruction.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmFci, @function
-.proc AsmFci
-.regstk 1, 0, 0, 0
-
-AsmFci::
- fc.i in0
- mov r8 = in0;;
- br.ret.dpnt b0;;
-.endp AsmFci
diff --git a/MdePkg/Library/BaseLib/Ipf/FlushCacheRange.c b/MdePkg/Library/BaseLib/Ipf/FlushCacheRange.c
deleted file mode 100644
index 5286bebcab..0000000000
--- a/MdePkg/Library/BaseLib/Ipf/FlushCacheRange.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/** @file
- AsmFlushCacheRange() function for IPF.
-
- Copyright (c) 2009, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php.
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-
-#include "BaseLibInternals.h"
-
-/**
- Flush a range of cache lines in the cache coherency domain of the calling
- CPU.
-
- Flushes the cache lines specified by Address and Length. If Address is not aligned
- on a cache line boundary, then entire cache line containing Address is flushed.
- If Address + Length is not aligned on a cache line boundary, then the entire cache
- line containing Address + Length - 1 is flushed. This function may choose to flush
- the entire cache if that is more efficient than flushing the specified range. If
- Length is 0, the no cache lines are flushed. Address is returned.
- This function is only available on IPF.
-
- If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
-
- @param Address The base address of the instruction lines to invalidate. If
- the CPU is in a physical addressing mode, then Address is a
- physical address. If the CPU is in a virtual addressing mode,
- then Address is a virtual address.
-
- @param Length The number of bytes to invalidate from the instruction cache.
-
- @return Address.
-
-**/
-VOID *
-EFIAPI
-AsmFlushCacheRange (
- IN VOID *Address,
- IN UINTN Length
- )
-{
- ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
- return InternalFlushCacheRange (Address, Length);
-}
diff --git a/MdePkg/Library/BaseLib/Ipf/GetInterruptState.s b/MdePkg/Library/BaseLib/Ipf/GetInterruptState.s
deleted file mode 100644
index eed6794f77..0000000000
--- a/MdePkg/Library/BaseLib/Ipf/GetInterruptState.s
+++ /dev/null
@@ -1,27 +0,0 @@
-/// @file
-/// Retrieve of the interrupt state of the running processor for the Itanium
-/// architecture.
-///
-/// Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
-/// This program and the accompanying materials
-/// are licensed and made available under the terms and conditions of the BSD License
-/// which accompanies this distribution. The full text of the license may be found at
-/// http://opensource.org/licenses/bsd-license.php.
-///
-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-///
-/// Module Name: GetInterruptState.s
-///
-///
-
-.auto
-.text
-
-.proc GetInterruptState
-.type GetInterruptState, @function
-GetInterruptState::
- mov r8 = psr
- extr.u r8 = r8, 14, 1
- br.ret.sptk.many b0
-.endp GetInterruptState
diff --git a/MdePkg/Library/BaseLib/Ipf/Ia64gen.h b/MdePkg/Library/BaseLib/Ipf/Ia64gen.h
deleted file mode 100644
index 3439f9e670..0000000000
--- a/MdePkg/Library/BaseLib/Ipf/Ia64gen.h
+++ /dev/null
@@ -1,205 +0,0 @@
-/** @file
-
- Register Definition for IPF.
-
-Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-This program and the accompanying materials
-are licensed and made available under the terms and conditions of the BSD License
-which accompanies this distribution. The full text of the license may be found at
-http://opensource.org/licenses/bsd-license.php.
-
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-#ifndef _IA64GEN_H_
-#define _IA64GEN_H_
-
-#define TT_UNAT 0
-#define C_PSR 0
-#define J_UNAT 0
-#define T_TYPE 0
-#define T_IPSR 0x8
-#define T_ISR 0x10
-#define T_IIP 0x18
-#define T_IFA 0x20
-#define T_IIPA 0x28
-#define T_IFS 0x30
-#define T_IIM 0x38
-#define T_RSC 0x40
-#define T_BSP 0x48
-#define T_BSPSTORE 0x50
-#define T_RNAT 0x58
-#define T_PFS 0x60
-#define T_KBSPSTORE 0x68
-#define T_UNAT 0x70
-#define T_CCV 0x78
-#define T_DCR 0x80
-#define T_PREDS 0x88
-#define T_NATS 0x90
-#define T_R1 0x98
-#define T_GP 0x98
-#define T_R2 0xa0
-#define T_R3 0xa8
-#define T_R4 0xb0
-#define T_R5 0xb8
-#define T_R6 0xc0
-#define T_R7 0xc8
-#define T_R8 0xd0
-#define T_R9 0xd8
-#define T_R10 0xe0
-#define T_R11 0xe8
-#define T_R12 0xf0
-#define T_SP 0xf0
-#define T_R13 0xf8
-#define T_R14 0x100
-#define T_R15 0x108
-#define T_R16 0x110
-#define T_R17 0x118
-#define T_R18 0x120
-#define T_R19 0x128
-#define T_R20 0x130
-#define T_R21 0x138
-#define T_R22 0x140
-#define T_R23 0x148
-#define T_R24 0x150
-#define T_R25 0x158
-#define T_R26 0x160
-#define T_R27 0x168
-#define T_R28 0x170
-#define T_R29 0x178
-#define T_R30 0x180
-#define T_R31 0x188
-#define T_F2 0x1f0
-#define T_F3 0x200
-#define T_F4 0x210
-#define T_F5 0x220
-#define T_F6 0x230
-#define T_F7 0x240
-#define T_F8 0x250
-#define T_F9 0x260
-#define T_F10 0x270
-#define T_F11 0x280
-#define T_F12 0x290
-#define T_F13 0x2a0
-#define T_F14 0x2b0
-#define T_F15 0x2c0
-#define T_F16 0x2d0
-#define T_F17 0x2e0
-#define T_F18 0x2f0
-#define T_F19 0x300
-#define T_F20 0x310
-#define T_F21 0x320
-#define T_F22 0x330
-#define T_F23 0x340
-#define T_F24 0x350
-#define T_F25 0x360
-#define T_F26 0x370
-#define T_F27 0x380
-#define T_F28 0x390
-#define T_F29 0x3a0
-#define T_F30 0x3b0
-#define T_F31 0x3c0
-#define T_FPSR 0x1e0
-#define T_B0 0x190
-#define T_B1 0x198
-#define T_B2 0x1a0
-#define T_B3 0x1a8
-#define T_B4 0x1b0
-#define T_B5 0x1b8
-#define T_B6 0x1c0
-#define T_B7 0x1c8
-#define T_EC 0x1d0
-#define T_LC 0x1d8
-#define J_NATS 0x8
-#define J_PFS 0x10
-#define J_BSP 0x18
-#define J_RNAT 0x20
-#define J_PREDS 0x28
-#define J_LC 0x30
-#define J_R4 0x38
-#define J_R5 0x40
-#define J_R6 0x48
-#define J_R7 0x50
-#define J_SP 0x58
-#define J_F2 0x60
-#define J_F3 0x70
-#define J_F4 0x80
-#define J_F5 0x90
-#define J_F16 0xa0
-#define J_F17 0xb0
-#define J_F18 0xc0
-#define J_F19 0xd0
-#define J_F20 0xe0
-#define J_F21 0xf0
-#define J_F22 0x100
-#define J_F23 0x110
-#define J_F24 0x120
-#define J_F25 0x130
-#define J_F26 0x140
-#define J_F27 0x150
-#define J_F28 0x160
-#define J_F29 0x170
-#define J_F30 0x180
-#define J_F31 0x190
-#define J_FPSR 0x1a0
-#define J_B0 0x1a8
-#define J_B1 0x1b0
-#define J_B2 0x1b8
-#define J_B3 0x1c0
-#define J_B4 0x1c8
-#define J_B5 0x1d0
-#define TRAP_FRAME_LENGTH 0x3d0
-#define C_UNAT 0x28
-#define C_NATS 0x30
-#define C_PFS 0x8
-#define C_BSPSTORE 0x10
-#define C_RNAT 0x18
-#define C_RSC 0x20
-#define C_PREDS 0x38
-#define C_LC 0x40
-#define C_DCR 0x48
-#define C_R1 0x50
-#define C_GP 0x50
-#define C_R4 0x58
-#define C_R5 0x60
-#define C_R6 0x68
-#define C_R7 0x70
-#define C_SP 0x78
-#define C_R13 0x80
-#define C_F2 0x90
-#define C_F3 0xa0
-#define C_F4 0xb0
-#define C_F5 0xc0
-#define C_F16 0xd0
-#define C_F17 0xe0
-#define C_F18 0xf0
-#define C_F19 0x100
-#define C_F20 0x110
-#define C_F21 0x120
-#define C_F22 0x130
-#define C_F23 0x140
-#define C_F24 0x150
-#define C_F25 0x160
-#define C_F26 0x170
-#define C_F27 0x180
-#define C_F28 0x190
-#define C_F29 0x1a0
-#define C_F30 0x1b0
-#define C_F31 0x1c0
-#define C_FPSR 0x1d0
-#define C_B0 0x1d8
-#define C_B1 0x1e0
-#define C_B2 0x1e8
-#define C_B3 0x1f0
-#define C_B4 0x1f8
-#define C_B5 0x200
-#define TT_R2 0x8
-#define TT_R3 0x10
-#define TT_R8 0x18
-#define TT_R9 0x20
-#define TT_R10 0x28
-#define TT_R11 0x30
-#define TT_R14 0x38
-
-#endif _IA64GEN_H
diff --git a/MdePkg/Library/BaseLib/Ipf/InternalFlushCacheRange.s b/MdePkg/Library/BaseLib/Ipf/InternalFlushCacheRange.s
deleted file mode 100644
index 7a0b747965..0000000000
--- a/MdePkg/Library/BaseLib/Ipf/InternalFlushCacheRange.s
+++ /dev/null
@@ -1,94 +0,0 @@
-//++
-// Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
-// This program and the accompanying materials
-// are licensed and made available under the terms and conditions of the BSD License
-// which accompanies this distribution. The full text of the license may be found at
-// http://opensource.org/licenses/bsd-license.php.
-//
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-//
-// Module Name:
-// InternalFlushCacheRange.s
-//
-// Abstract:
-// Assemble routine to flush cache lines
-//
-// Revision History:
-//
-//--
-.file "IpfCpuCache.s"
-
-#include <IpfMacro.i>
-
-//
-// Internal worker function to invalidate a range of instruction cache lines
-// in the cache coherency domain of the calling CPU.
-//
-// Internal worker function to invalidate the instruction cache lines specified
-// by Address and Length. If Address is not aligned on a cache line boundary,
-// then entire instruction cache line containing Address is invalidated. If
-// Address + Length is not aligned on a cache line boundary, then the entire
-// instruction cache line containing Address + Length -1 is invalidated. This
-// function may choose to invalidate the entire instruction cache if that is more
-// efficient than invalidating the specified range. If Length is 0, the no instruction
-// cache lines are invalidated. Address is returned.
-// This function is only available on IPF.
-//
-// @param Address The base address of the instruction cache lines to
-// invalidate. If the CPU is in a physical addressing mode, then
-// Address is a physical address. If the CPU is in a virtual
-// addressing mode, then Address is a virtual address.
-//
-// @param Length The number of bytes to invalidate from the instruction cache.
-//
-// @return Address
-//
-// VOID *
-// EFIAPI
-// InternalFlushCacheRange (
-// IN VOID *Address,
-// IN UINTN Length
-// );
-//
-PROCEDURE_ENTRY (InternalFlushCacheRange)
-
- NESTED_SETUP (5,8,0,0)
-
- mov loc2 = ar.lc
-
- mov loc3 = in0 // Start address.
- mov loc4 = in1;; // Length in bytes.
-
- cmp.eq p6,p7 = loc4, r0;; // If Length is zero then don't flush any cache
- (p6) br.spnt.many DoneFlushingC;;
-
- add loc4 = loc4,loc3
- mov loc5 = 1;;
- sub loc4 = loc4, loc5 ;; // the End address to flush
-
- dep loc3 = r0,loc3,0,5
- dep loc4 = r0,loc4,0,5;;
- shr loc3 = loc3,5
- shr loc4 = loc4,5;; // 32 byte cache line
-
- sub loc4 = loc4,loc3;; // total flush count, It should be add 1 but
- // the br.cloop will first execute one time
- mov loc3 = in0
- mov loc5 = 32
- mov ar.lc = loc4;;
-
-StillFlushingC:
- fc loc3;;
- sync.i;;
- srlz.i;;
- add loc3 = loc5,loc3;;
- br.cloop.sptk.few StillFlushingC;;
-
-DoneFlushingC:
- mov ar.lc = loc2
- mov r8 = in0 // return *Address
- NESTED_RETURN
-
-PROCEDURE_EXIT (InternalFlushCacheRange)
-
diff --git a/MdePkg/Library/BaseLib/Ipf/InternalSwitchStack.c b/MdePkg/Library/BaseLib/Ipf/InternalSwitchStack.c
deleted file mode 100644
index 35a0905aff..0000000000
--- a/MdePkg/Library/BaseLib/Ipf/InternalSwitchStack.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/** @file
- SwitchStack() function for IPF.
-
- Copyright (c) 2007 - 2010, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php.
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include "BaseLibInternals.h"
-
-/**
- Transfers control to a function starting with a new stack.
-
- Transfers control to the function specified by EntryPoint using the
- new stack specified by NewStack and passing in the parameters specified
- by Context1 and Context2. Context1 and Context2 are optional and may
- be NULL. The function EntryPoint must never return.
- Marker will be ignored on IA-32, x64, and EBC.
- IPF CPUs expect one additional parameter of type VOID * that specifies
- the new backing store pointer.
-
- If EntryPoint is NULL, then ASSERT().
- If NewStack is NULL, then ASSERT().
-
- @param EntryPoint A pointer to function to call with the new stack.
- @param Context1 A pointer to the context to pass into the EntryPoint
- function.
- @param Context2 A pointer to the context to pass into the EntryPoint
- function.
- @param NewStack A pointer to the new stack to use for the EntryPoint
- function.
- @param Marker VA_LIST marker for the variable argument list.
-
-**/
-VOID
-EFIAPI
-InternalSwitchStack (
- IN SWITCH_STACK_ENTRY_POINT EntryPoint,
- IN VOID *Context1, OPTIONAL
- IN VOID *Context2, OPTIONAL
- IN VOID *NewStack,
- IN VA_LIST Marker
- )
-{
- VOID *NewBsp;
-
- //
- // Get new backing store pointer from variable list
- //
- NewBsp = VA_ARG (Marker, VOID *);
-
- //
- // New backing store pointer should be aligned with CPU_STACK_ALIGNMENT
- //
- ASSERT (((UINTN)NewBsp & (CPU_STACK_ALIGNMENT - 1)) == 0);
-
- AsmSwitchStackAndBackingStore (EntryPoint, Context1, Context2, NewStack, NewBsp);
-}
diff --git a/MdePkg/Library/BaseLib/Ipf/LongJmp.s b/MdePkg/Library/BaseLib/Ipf/LongJmp.s
deleted file mode 100644
index 8b5eb6408b..0000000000
--- a/MdePkg/Library/BaseLib/Ipf/LongJmp.s
+++ /dev/null
@@ -1,121 +0,0 @@
-/// @file
-/// Contains an implementation of longjmp for the Itanium-based architecture.
-///
-/// Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-/// This program and the accompanying materials
-/// are licensed and made available under the terms and conditions of the BSD License
-/// which accompanies this distribution. The full text of the license may be found at
-/// http://opensource.org/licenses/bsd-license.php.
-///
-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-///
-/// Module Name: longjmp.s
-///
-///
-
-.auto
-.text
-
-.proc InternalLongJump
-.type InternalLongJump, @function
-.regstk 2, 0, 0, 0
-InternalLongJump::
- add r10 = 0x10*20 + 8*14, in0
- movl r2 = ~((((1 << 14) - 1) << 16) | 3)
-
- ld8.nt1 r14 = [r10], -8*2 // BSP, skip PFS
- mov r15 = ar.bspstore // BSPSTORE
-
- ld8.nt1 r17 = [r10], -8 // UNAT after spill
- mov r16 = ar.rsc // RSC
- cmp.leu p6 = r14, r15
-
- ld8.nt1 r18 = [r10], -8 // UNAT
- ld8.nt1 r25 = [r10], -8 // b5
- and r2 = r16, r2
-
- ldf.fill.nt1 f2 = [in0], 0x10
- ld8.nt1 r24 = [r10], -8 // b4
- mov b5 = r25
-
- mov ar.rsc = r2
- ld8.nt1 r23 = [r10], -8 // b3
- mov b4 = r24
-
- ldf.fill.nt1 f3 = [in0], 0x10
- mov ar.unat = r17
-(p6) br.spnt.many _skip_flushrs
-
- flushrs
- mov r15 = ar.bsp // New BSPSTORE
-
-_skip_flushrs:
- mov r31 = ar.rnat // RNAT
- loadrs
-
- ldf.fill.nt1 f4 = [in0], 0x10
- ld8.nt1 r22 = [r10], -8
- dep r2 = -1, r14, 3, 6
-
- ldf.fill.nt1 f5 = [in0], 0x10
- ld8.nt1 r21 = [r10], -8
- cmp.ltu p6 = r2, r15
-
- ld8.nt1 r20 = [r10], -0x10 // skip sp
-(p6) ld8.nta r31 = [r2]
- mov b3 = r23
-
- ldf.fill.nt1 f16 = [in0], 0x10
- ld8.fill.nt1 r7 = [r10], -8
- mov b2 = r22
-
- ldf.fill.nt1 f17 = [in0], 0x10
- ld8.fill.nt1 r6 = [r10], -8
- mov b1 = r21
-
- ldf.fill.nt1 f18 = [in0], 0x10
- ld8.fill.nt1 r5 = [r10], -8
- mov b0 = r20
-
- ldf.fill.nt1 f19 = [in0], 0x10
- ld8.fill.nt1 r4 = [r10], 8*13
-
- ldf.fill.nt1 f20 = [in0], 0x10
- ld8.nt1 r19 = [r10], 0x10 // PFS
-
- ldf.fill.nt1 f21 = [in0], 0x10
- ld8.nt1 r26 = [r10], 8 // Predicate
- mov ar.pfs = r19
-
- ldf.fill.nt1 f22 = [in0], 0x10
- ld8.nt1 r27 = [r10], 8 // LC
- mov pr = r26, -1
-
- ldf.fill.nt1 f23 = [in0], 0x10
- ld8.nt1 r28 = [r10], -17*8 - 0x10
- mov ar.lc = r27
-
- ldf.fill.nt1 f24 = [in0], 0x10
- ldf.fill.nt1 f25 = [in0], 0x10
- mov r8 = in1
-
- ldf.fill.nt1 f26 = [in0], 0x10
- ldf.fill.nt1 f31 = [r10], -0x10
-
- ldf.fill.nt1 f27 = [in0], 0x10
- ldf.fill.nt1 f30 = [r10], -0x10
-
- ldf.fill.nt1 f28 = [in0]
- ldf.fill.nt1 f29 = [r10], 0x10*3 + 8*4
-
- ld8.fill.nt1 sp = [r10]
- mov ar.unat = r18
-
- mov ar.bspstore = r14
- mov ar.rnat = r31
-
- invala
- mov ar.rsc = r16
- br.ret.sptk b0
-.endp
diff --git a/MdePkg/Library/BaseLib/Ipf/ReadAr.s b/MdePkg/Library/BaseLib/Ipf/ReadAr.s
deleted file mode 100644
index 36efe8b3da..0000000000
--- a/MdePkg/Library/BaseLib/Ipf/ReadAr.s
+++ /dev/null
@@ -1,109 +0,0 @@
-/// @file
-/// IPF specific application register reading functions
-///
-/// Copyright (c) 2008, Intel Corporation. All rights reserved.<BR>
-/// This program and the accompanying materials
-/// are licensed and made available under the terms and conditions of the BSD License
-/// which accompanies this distribution. The full text of the license may be found at
-/// http://opensource.org/licenses/bsd-license.php.
-///
-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-///
-///
-///
-
-
-
-//---------------------------------------------------------------------------------
-//++
-// AsmReadApplicationRegister
-//
-// Reads a 64-bit application register.
-//
-// Reads and returns the application register specified by Index.
-// If Index is invalid then 0xFFFFFFFFFFFFFFFF is returned. This function is only available on IPF.
-//
-// Arguments :
-//
-// On Entry : The index of the application register to read.
-//
-// Return Value: The application register specified by Index.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmReadApplicationRegister, @function
-.proc AsmReadApplicationRegister
-.regstk 1, 0, 0, 0
-
-AsmReadApplicationRegister::
- //
- // ARs are defined in the ranges 0-44 and 64-66 (with some holes).
- // Compact this list by subtracting 16 from the top range.
- // 0-44, 64-66 -> 0-44, 48-50
- //
- mov r15=2
- mov r14=pr // save predicates
- cmp.leu p6,p7=64,in0 // p6 = AR# >= 64
- ;;
- (p7) cmp.leu p7,p0=48,in0 // p7 = 32 <= AR# < 64
- (p6) add in0=-16,in0 // if (AR >= 64) AR# -= 16
- ;;
- (p7) mov r15=0 // if bad range (48-63)
- ;;
- mov ret0=-1 // in case of illegal AR #
- shl r15=r15,in0 // r15 = 0x2 << AR#
- ;;
- mov pr=r15,-1
- ;;
- //
- // At this point the predicates contain a bit field of the
- // AR desired. (The bit is the AR+1, since pr0 is always 1.)
- //
- .pred.rel "mutex",p1,p2,p3,p4,p5,p6,p7,p8,p17,p18,p19,p20,p22,p25,\
- p26,p27,p28,p29,p30,p31,p33,p37,p41,p45,p49,p50,p51
- (p1) mov ret0=ar.k0 // ar0
- (p2) mov ret0=ar.k1 // ar1
- (p3) mov ret0=ar.k2 // ar2
- (p4) mov ret0=ar.k3 // ar3
- (p5) mov ret0=ar.k4 // ar4
- (p6) mov ret0=ar.k5 // ar5
- (p7) mov ret0=ar.k6 // ar6
- (p8) mov ret0=ar.k7 // ar7
-
- (p17) mov ret0=ar.rsc // ar16
- (p18) mov ret0=ar.bsp // ar17
- (p19) mov ret0=ar.bspstore // ar18
- (p20) mov ret0=ar.rnat // ar19
-
- (p22) mov ret0=ar.fcr // ar21 [iA32]
-
- (p25) mov ret0=ar.eflag // ar24 [iA32]
- (p26) mov ret0=ar.csd // ar25 [iA32]
- (p27) mov ret0=ar.ssd // ar26 [iA32]
- (p28) mov ret0=ar.cflg // ar27 [iA32]
- (p29) mov ret0=ar.fsr // ar28 [iA32]
- (p30) mov ret0=ar.fir // ar29 [iA32]
- (p31) mov ret0=ar.fdr // ar30 [iA32]
-
- (p33) mov ret0=ar.ccv // ar32
-
- (p37) mov ret0=ar.unat // ar36
-
- (p41) mov ret0=ar.fpsr // ar40
-
- (p45) mov ret0=ar.itc // ar44
-
- //
- // This is the translated (-16) range.
- //
- (p49) mov ret0=ar.pfs // ar64
- (p50) mov ret0=ar.lc // ar65
- (p51) mov ret0=ar.ec // ar66
-
- // Restore predicates and return.
-
- mov pr=r14,-1
- br.ret.sptk b0
- .endp
diff --git a/MdePkg/Library/BaseLib/Ipf/ReadCpuid.s b/MdePkg/Library/BaseLib/Ipf/ReadCpuid.s
deleted file mode 100644
index 31023847c9..0000000000
--- a/MdePkg/Library/BaseLib/Ipf/ReadCpuid.s
+++ /dev/null
@@ -1,40 +0,0 @@
-/// @file
-/// IPF specific AsmReadCpuid()function
-///
-/// Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
-/// This program and the accompanying materials
-/// are licensed and made available under the terms and conditions of the BSD License
-/// which accompanies this distribution. The full text of the license may be found at
-/// http://opensource.org/licenses/bsd-license.php.
-///
-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-///
-/// Module Name: ReadCpuid.s
-///
-///
-
-//---------------------------------------------------------------------------------
-//++
-// AsmReadCpuid
-//
-// This routine is used to Reads the current value of Processor Identifier Register (CPUID).
-//
-// Arguments :
-//
-// On Entry : The 8-bit Processor Identifier Register index to read.
-//
-// Return Value: The current value of Processor Identifier Register specified by Index.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmReadCpuid, @function
-.proc AsmReadCpuid
-.regstk 1, 0, 0, 0
-
-AsmReadCpuid::
- mov r8 = cpuid[in0];;
- br.ret.dpnt b0;;
-.endp AsmReadCpuid
-
diff --git a/MdePkg/Library/BaseLib/Ipf/ReadCr.s b/MdePkg/Library/BaseLib/Ipf/ReadCr.s
deleted file mode 100644
index ef52964e5c..0000000000
--- a/MdePkg/Library/BaseLib/Ipf/ReadCr.s
+++ /dev/null
@@ -1,102 +0,0 @@
-/// @file
-/// IPF specific control register reading functions
-///
-/// Copyright (c) 2008, Intel Corporation. All rights reserved.<BR>
-/// This program and the accompanying materials
-/// are licensed and made available under the terms and conditions of the BSD License
-/// which accompanies this distribution. The full text of the license may be found at
-/// http://opensource.org/licenses/bsd-license.php.
-///
-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-///
-///
-///
-
-
-
-//---------------------------------------------------------------------------------
-//++
-// AsmReadControlRegister
-//
-// Reads a 64-bit control register.
-//
-// Reads and returns the control register specified by Index.
-// If Index is invalid then 0xFFFFFFFFFFFFFFFF is returned. This function is only available on IPF.
-//
-// Arguments :
-//
-// On Entry : The index of the control register to read.
-//
-// Return Value: The control register specified by Index.
-//
-//--
-//----------------------------------------------------------------------------------
-.text
-.type AsmReadControlRegister, @function
-.proc AsmReadControlRegister
-.regstk 1, 0, 0, 0
-
-AsmReadControlRegister::
- //
- // CRs are defined in the ranges 0-25 and 64-81 (with some holes).
- // Compact this list by subtracting 32 from the top range.
- // 0-25, 64-81 -> 0-25, 32-49
- //
- mov r15=2
- mov r14=pr // save predicates
- cmp.leu p6,p7=64,in0 // p6 = CR# >= 64
- ;;
- (p7) cmp.leu p7,p0=32,in0 // p7 = 32 <= CR# < 64
- (p6) add in0=-32,in0 // if (CR >= 64) CR# -= 32
- ;;
- (p7) mov r15=0 // if bad range (32-63)
- ;;
- mov ret0=-1 // in case of illegal CR #
- shl r15=r15,in0 // r15 = 0x2 << CR#
- ;;
- mov pr=r15,-1
- ;;
-
- //
- // At this point the predicates contain a bit field of the
- // CR desired. (The bit is the CR+1, since pr0 is always 1.)
- //
- .pred.rel "mutex",p1,p2,p3,p9,p17,p18,p20,p21,p22,p23,p24,p25,p26,\
- p33,p34,p35,p36,p37,p38,p39,p40,p41,p42,p43,p49,p50
- (p1) mov ret0=cr.dcr // cr0
- (p2) mov ret0=cr.itm // cr1
- (p3) mov ret0=cr.iva // cr2
- (p9) mov ret0=cr.pta // cr8
- (p17) mov ret0=cr.ipsr // cr16
- (p18) mov ret0=cr.isr // cr17
- (p20) mov ret0=cr.iip // cr19
- (p21) mov ret0=cr.ifa // cr20
- (p22) mov ret0=cr.itir // cr21
- (p23) mov ret0=cr.iipa // cr22
- (p24) mov ret0=cr.ifs // cr23
- (p25) mov ret0=cr.iim // cr24
- (p26) mov ret0=cr.iha // cr25
-
- // This is the translated (-32) range.
-
- (p33) mov ret0=cr.lid // cr64
- (p34) mov ret0=cr.ivr // cr65
- (p35) mov ret0=cr.tpr // cr66
- (p36) mov ret0=cr.eoi // cr67
- (p37) mov ret0=cr.irr0 // cr68
- (p38) mov ret0=cr.irr1 // cr69
- (p39) mov ret0=cr.irr2 // cr70
- (p40) mov ret0=cr.irr3 // cr71
- (p41) mov ret0=cr.itv // cr72
- (p42) mov ret0=cr.pmv // cr73
- (p43) mov ret0=cr.cmcv // cr74
- (p49) mov ret0=cr.lrr0 // cr80
- (p50) mov ret0=cr.lrr1 // cr81
-
- //
- // Restore predicates and return.
- //
- mov pr=r14,-1
- br.ret.sptk b0
- .endp
diff --git a/MdePkg/Library/BaseLib/Ipf/SetJmp.s b/MdePkg/Library/BaseLib/Ipf/SetJmp.s
deleted file mode 100644
index 71467f5ce4..0000000000
--- a/MdePkg/Library/BaseLib/Ipf/SetJmp.s
+++ /dev/null
@@ -1,108 +0,0 @@
-/// @file
-/// Contains an implementation of longjmp for the Itanium-based architecture.
-///
-/// Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-/// This program and the accompanying materials
-/// are licensed and made available under the terms and conditions of the BSD License
-/// which accompanies this distribution. The full text of the license may be found at
-/// http://opensource.org/licenses/bsd-license.php.
-///
-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-///
-/// Module Name: longjmp.s
-///
-///
-
-.auto
-.text
-
-ASM_GLOBAL InternalAssertJumpBuffer
-.type InternalAssertJumpBuffer, @function
-
-.proc SetJump
-.type SetJump, @function
-SetJump::
- alloc loc0 = ar.pfs, 1, 2, 1, 0
- mov loc1 = b0
- mov out0 = in0
-
- brl.call.sptk.many b0 = InternalAssertJumpBuffer
-
- mov r14 = ar.unat
- mov r15 = ar.bsp
- add r10 = 0x10*20, in0
-
- stf.spill.nta [in0] = f2, 0x10
- st8.spill.nta [r10] = r4, 8
- mov r21 = b1
-
- stf.spill.nta [in0] = f3, 0x10
- st8.spill.nta [r10] = r5, 8
- mov r22 = b2
-
- stf.spill.nta [in0] = f4, 0x10
- st8.spill.nta [r10] = r6, 8
- mov r23 = b3
-
- stf.spill.nta [in0] = f5, 0x10
- st8.spill.nta [r10] = r7, 8
- mov r24 = b4
-
- stf.spill.nta [in0] = f16, 0x10
- st8.spill.nta [r10] = sp, 8
- mov r25 = b5
-
- stf.spill.nta [in0] = f17, 0x10
- st8.nta [r10] = loc1, 8
- mov r16 = pr
-
- stf.spill.nta [in0] = f18, 0x10
- st8.nta [r10] = r21, 8
- mov r17 = ar.lc
-
- stf.spill.nta [in0] = f19, 0x10
- st8.nta [r10] = r22, 8
-
- stf.spill.nta [in0] = f20, 0x10
- st8.nta [r10] = r23, 8
-
- stf.spill.nta [in0] = f21, 0x10
- st8.nta [r10] = r24, 8
-
- stf.spill.nta [in0] = f22, 0x10
- st8.nta [r10] = r25, 8
-
- stf.spill.nta [in0] = f23, 0x10
- mov r18 = ar.unat
-
- stf.spill.nta [in0] = f24, 0x10
- st8.nta [r10] = r14, 8 // UNAT
-
- stf.spill.nta [in0] = f25, 0x10
- st8.nta [r10] = r18, 8 // UNAT after spill
-
- stf.spill.nta [in0] = f26, 0x10
- st8.nta [r10] = loc0, 8 // PFS
-
- stf.spill.nta [in0] = f27, 0x10
- st8.nta [r10] = r15, 8 // BSP
- mov r8 = 0
-
- stf.spill.nta [in0] = f28, 0x10
- mov r19 = ar.fpsr
-
- stf.spill.nta [in0] = f29, 0x10
- st8.nta [r10] = r16, 8 // PR
- mov ar.pfs = loc0
-
- stf.spill.nta [in0] = f30, 0x10
- st8.nta [r10] = r17, 8 // LC
- mov b0 = loc1
-
- stf.spill.nta [in0] = f31, 0x10
- st8.nta [r10] = r19 // FPSR
-
- mov ar.unat = r14
- br.ret.sptk b0
-.endp SetJump
diff --git a/MdePkg/Library/BaseLib/Ipf/SwitchStack.s b/MdePkg/Library/BaseLib/Ipf/SwitchStack.s
deleted file mode 100644
index 1236bbe947..0000000000
--- a/MdePkg/Library/BaseLib/Ipf/SwitchStack.s
+++ /dev/null
@@ -1,52 +0,0 @@
-/// @file
-/// IPF specific SwitchStack() function
-///
-/// Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
-/// This program and the accompanying materials
-/// are licensed and made available under the terms and conditions of the BSD License
-/// which accompanies this distribution. The full text of the license may be found at
-/// http://opensource.org/licenses/bsd-license.php.
-///
-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-///
-/// Module Name: SwitchStack.s
-///
-///
-
-.auto
-.text
-
-.proc AsmSwitchStackAndBackingStore
-.type AsmSwitchStackAndBackingStore, @function
-.regstk 5, 0, 0, 0
-AsmSwitchStackAndBackingStore::
- mov r14 = ar.rsc
- movl r2 = ~((((1 << 14) - 1) << 16) | 3)
-
- mov r17 = in1
- mov r18 = in2
- and r2 = r14, r2
-
- flushrs
-
- mov ar.rsc = r2
- mov sp = in3
- mov r19 = in4
-
- ld8.nt1 r16 = [in0], 8
- ld8.nta gp = [in0]
- mov r3 = -1
-
- loadrs
- mov ar.bspstore = r19
- mov b7 = r16
-
- alloc r2 = ar.pfs, 0, 0, 2, 0
- mov out0 = r17
- mov out1 = r18
-
- mov ar.rnat = r3
- mov ar.rsc = r14
- br.call.sptk.many b0 = b7
-.endp AsmSwitchStackAndBackingStore
diff --git a/MdePkg/Library/BaseLib/Ipf/Unaligned.c b/MdePkg/Library/BaseLib/Ipf/Unaligned.c
deleted file mode 100644
index 7d0d8ddc02..0000000000
--- a/MdePkg/Library/BaseLib/Ipf/Unaligned.c
+++ /dev/null
@@ -1,243 +0,0 @@
-/** @file
- Unaligned access functions of BaseLib for IPF.
-
- Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php.
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include "BaseLibInternals.h"
-
-/**
- Reads a 16-bit value from memory that may be unaligned.
-
- This function returns the 16-bit value pointed to by Buffer. The function
- guarantees that the read operation does not produce an alignment fault.
-
- If the Buffer is NULL, then ASSERT().
-
- @param Buffer The pointer to a 16-bit value that may be unaligned.
-
- @return The 16-bit value read from Buffer.
-
-**/
-UINT16
-EFIAPI
-ReadUnaligned16 (
- IN CONST UINT16 *Buffer
- )
-{
- ASSERT (Buffer != NULL);
-
- return (UINT16)(((UINT8*)Buffer)[0] | (((UINT8*)Buffer)[1] << 8));
-}
-
-/**
- Writes a 16-bit value to memory that may be unaligned.
-
- This function writes the 16-bit value specified by Value to Buffer. Value is
- returned. The function guarantees that the write operation does not produce
- an alignment fault.
-
- If the Buffer is NULL, then ASSERT().
-
- @param Buffer The pointer to a 16-bit value that may be unaligned.
- @param Value The 16-bit value to write to Buffer.
-
- @return The 16-bit value to write to Buffer.
-
-**/
-UINT16
-EFIAPI
-WriteUnaligned16 (
- OUT UINT16 *Buffer,
- IN UINT16 Value
- )
-{
- ASSERT (Buffer != NULL);
-
- ((UINT8*)Buffer)[0] = (UINT8)Value;
- ((UINT8*)Buffer)[1] = (UINT8)(Value >> 8);
-
- return Value;
-}
-
-/**
- Reads a 24-bit value from memory that may be unaligned.
-
- This function returns the 24-bit value pointed to by Buffer. The function
- guarantees that the read operation does not produce an alignment fault.
-
- If the Buffer is NULL, then ASSERT().
-
- @param Buffer The pointer to a 24-bit value that may be unaligned.
-
- @return The 24-bit value read from Buffer.
-
-**/
-UINT32
-EFIAPI
-ReadUnaligned24 (
- IN CONST UINT32 *Buffer
- )
-{
- ASSERT (Buffer != NULL);
-
- return (UINT32)(
- ReadUnaligned16 ((UINT16*)Buffer) |
- (((UINT8*)Buffer)[2] << 16)
- );
-}
-
-/**
- Writes a 24-bit value to memory that may be unaligned.
-
- This function writes the 24-bit value specified by Value to Buffer. Value is
- returned. The function guarantees that the write operation does not produce
- an alignment fault.
-
- If the Buffer is NULL, then ASSERT().
-
- @param Buffer The pointer to a 24-bit value that may be unaligned.
- @param Value The 24-bit value to write to Buffer.
-
- @return The 24-bit value to write to Buffer.
-
-**/
-UINT32
-EFIAPI
-WriteUnaligned24 (
- OUT UINT32 *Buffer,
- IN UINT32 Value
- )
-{
- ASSERT (Buffer != NULL);
-
- WriteUnaligned16 ((UINT16*)Buffer, (UINT16)Value);
- *(UINT8*)((UINT16*)Buffer + 1) = (UINT8)(Value >> 16);
- return Value;
-}
-
-/**
- Reads a 32-bit value from memory that may be unaligned.
-
- This function returns the 32-bit value pointed to by Buffer. The function
- guarantees that the read operation does not produce an alignment fault.
-
- If the Buffer is NULL, then ASSERT().
-
- @param Buffer The pointer to a 32-bit value that may be unaligned.
-
- @return The 32-bit value read from Buffer.
-
-**/
-UINT32
-EFIAPI
-ReadUnaligned32 (
- IN CONST UINT32 *Buffer
- )
-{
- UINT16 LowerBytes;
- UINT16 HigherBytes;
-
- ASSERT (Buffer != NULL);
-
- LowerBytes = ReadUnaligned16 ((UINT16*) Buffer);
- HigherBytes = ReadUnaligned16 ((UINT16*) Buffer + 1);
-
- return (UINT32) (LowerBytes | (HigherBytes << 16));
-}
-
-/**
- Writes a 32-bit value to memory that may be unaligned.
-
- This function writes the 32-bit value specified by Value to Buffer. Value is
- returned. The function guarantees that the write operation does not produce
- an alignment fault.
-
- If the Buffer is NULL, then ASSERT().
-
- @param Buffer The pointer to a 32-bit value that may be unaligned.
- @param Value The 32-bit value to write to Buffer.
-
- @return The 32-bit value to write to Buffer.
-
-**/
-UINT32
-EFIAPI
-WriteUnaligned32 (
- OUT UINT32 *Buffer,
- IN UINT32 Value
- )
-{
- ASSERT (Buffer != NULL);
-
- WriteUnaligned16 ((UINT16*)Buffer, (UINT16)Value);
- WriteUnaligned16 ((UINT16*)Buffer + 1, (UINT16)(Value >> 16));
- return Value;
-}
-
-/**
- Reads a 64-bit value from memory that may be unaligned.
-
- This function returns the 64-bit value pointed to by Buffer. The function
- guarantees that the read operation does not produce an alignment fault.
-
- If the Buffer is NULL, then ASSERT().
-
- @param Buffer The pointer to a 64-bit value that may be unaligned.
-
- @return The 64-bit value read from Buffer.
-
-**/
-UINT64
-EFIAPI
-ReadUnaligned64 (
- IN CONST UINT64 *Buffer
- )
-{
- UINT32 LowerBytes;
- UINT32 HigherBytes;
-
- ASSERT (Buffer != NULL);
-
- LowerBytes = ReadUnaligned32 ((UINT32*) Buffer);
- HigherBytes = ReadUnaligned32 ((UINT32*) Buffer + 1);
-
- return (UINT64) (LowerBytes | LShiftU64 (HigherBytes, 32));
-}
-
-/**
- Writes a 64-bit value to memory that may be unaligned.
-
- This function writes the 64-bit value specified by Value to Buffer. Value is
- returned. The function guarantees that the write operation does not produce
- an alignment fault.
-
- If the Buffer is NULL, then ASSERT().
-
- @param Buffer The pointer to a 64-bit value that may be unaligned.
- @param Value The 64-bit value to write to Buffer.
-
- @return The 64-bit value to write to Buffer.
-
-**/
-UINT64
-EFIAPI
-WriteUnaligned64 (
- OUT UINT64 *Buffer,
- IN UINT64 Value
- )
-{
- ASSERT (Buffer != NULL);
-
- WriteUnaligned32 ((UINT32*)Buffer, (UINT32)Value);
- WriteUnaligned32 ((UINT32*)Buffer + 1, (UINT32)RShiftU64 (Value, 32));
- return Value;
-}
diff --git a/MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf b/MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
index 358eeed4f4..7c82ca9a19 100644
--- a/MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+++ b/MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
@@ -26,7 +26,7 @@
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC ARM AARCH64
+# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64
#
[Sources]
diff --git a/MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib/BaseOrderedCollectionRedBlackTreeLib.inf b/MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib/BaseOrderedCollectionRedBlackTreeLib.inf
index a68afc8861..eaad44257f 100644
--- a/MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib/BaseOrderedCollectionRedBlackTreeLib.inf
+++ b/MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib/BaseOrderedCollectionRedBlackTreeLib.inf
@@ -33,7 +33,7 @@
LIBRARY_CLASS = OrderedCollectionLib
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]
diff --git a/MdePkg/Library/BasePalLibNull/BasePalLibNull.inf b/MdePkg/Library/BasePalLibNull/BasePalLibNull.inf
deleted file mode 100644
index 927c6d34c4..0000000000
--- a/MdePkg/Library/BasePalLibNull/BasePalLibNull.inf
+++ /dev/null
@@ -1,40 +0,0 @@
-## @file
-# Null instance of PAL Library with empty functions.
-#
-# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php.
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#
-##
-
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = BasePalLibNull
- MODULE_UNI_FILE = BasePalLibNull.uni
- FILE_GUID = 632D5625-B73D-43b8-AF30-8D225D96168E
- MODULE_TYPE = BASE
- VERSION_STRING = 1.0
- LIBRARY_CLASS = PalLib
-
-
-#
-# VALID_ARCHITECTURES = IPF
-#
-
-[Sources]
- PalCall.c
-
-
-[Packages]
- MdePkg/MdePkg.dec
-
-
-[LibraryClasses]
- DebugLib
-
diff --git a/MdePkg/Library/BasePalLibNull/PalCall.c b/MdePkg/Library/BasePalLibNull/PalCall.c
deleted file mode 100644
index 174c28ee67..0000000000
--- a/MdePkg/Library/BasePalLibNull/PalCall.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/** @file
-
- Template and Sample instance of PalCallLib.
-
- Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php.
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include <Base.h>
-#include <Library/PalLib.h>
-#include <Library/DebugLib.h>
-
-/**
- Makes a PAL procedure call.
-
- This is a wrapper function to make a PAL procedure call. Based on the Index value,
- this API will make static or stacked PAL call. Architected procedures may be designated
- as required or optional. If a PAL procedure is specified as optional, a unique return
- code of 0xFFFFFFFFFFFFFFFF is returned in the Status field of the PAL_CALL_RETURN structure.
- This indicates that the procedure is not present in this PAL implementation. It is the
- caller's responsibility to check for this return code after calling any optional PAL
- procedure. No parameter checking is performed on the 4 input parameters, but there are
- some common rules that the caller should follow when making a PAL call. Any address
- passed to PAL as buffers for return parameters must be 8-byte aligned. Unaligned addresses
- may cause undefined results. For those parameters defined as reserved or some fields
- defined as reserved must be zero filled or the invalid argument return value may be
- returned or undefined result may occur during the execution of the procedure.
- This function is only available on IPF.
-
- @param Index The PAL procedure Index number.
- @param Arg2 The 2nd parameter for PAL procedure calls.
- @param Arg3 The 3rd parameter for PAL procedure calls.
- @param Arg4 The 4th parameter for PAL procedure calls.
-
- @return The structure returned from the PAL Call procedure, including the status and return value.
-
-**/
-PAL_CALL_RETURN
-EFIAPI
-PalCall (
- IN UINT64 Index,
- IN UINT64 Arg2,
- IN UINT64 Arg3,
- IN UINT64 Arg4
- )
-{
- PAL_CALL_RETURN Ret;
-
- Ret.Status = (UINT64) -1;
- ASSERT (!RETURN_ERROR (RETURN_UNSUPPORTED));
- return Ret;
-}
diff --git a/MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf b/MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
index 4b511b336c..15e19a7454 100644
--- a/MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+++ b/MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
@@ -27,7 +27,7 @@
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]
diff --git a/MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf b/MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf
index 17b81e076a..e39ea3e5b8 100644
--- a/MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf
+++ b/MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf
@@ -26,7 +26,7 @@
LIBRARY_CLASS = PciCf8Lib
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]
diff --git a/MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf b/MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
index 4b14b5d89e..db817409c2 100644
--- a/MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
+++ b/MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
@@ -26,7 +26,7 @@
LIBRARY_CLASS = PciExpressLib
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]
diff --git a/MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf b/MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf
index 9409332cb5..443534d2b8 100644
--- a/MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf
+++ b/MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf
@@ -26,7 +26,7 @@
LIBRARY_CLASS = PciLib
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]
diff --git a/MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf b/MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
index 6ccd54ff9d..05c82d1bcf 100644
--- a/MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
+++ b/MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
@@ -27,7 +27,7 @@
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC ARM AARCH64
+# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64
#
[Sources]
diff --git a/MdePkg/Library/BasePciSegmentInfoLibNull/BasePciSegmentInfoLibNull.inf b/MdePkg/Library/BasePciSegmentInfoLibNull/BasePciSegmentInfoLibNull.inf
index 5ae59fb2be..0d759fb8cd 100644
--- a/MdePkg/Library/BasePciSegmentInfoLibNull/BasePciSegmentInfoLibNull.inf
+++ b/MdePkg/Library/BasePciSegmentInfoLibNull/BasePciSegmentInfoLibNull.inf
@@ -27,7 +27,7 @@
#
# The following information is for reference only and not required by the build tools.
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]
diff --git a/MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf b/MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
index 7dbb22282e..67a308fe71 100644
--- a/MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
+++ b/MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
@@ -28,7 +28,7 @@
#
# The following information is for reference only and not required by the build tools.
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]
diff --git a/MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf b/MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
index ecc770aca7..f24bd01c3a 100644
--- a/MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
+++ b/MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
@@ -24,7 +24,7 @@
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]
diff --git a/MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf b/MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
index b6eed82d5f..d30347ca57 100644
--- a/MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+++ b/MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
@@ -24,7 +24,7 @@
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]
diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
index ff0580fbdf..fa6613241a 100644
--- a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+++ b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
@@ -33,7 +33,7 @@
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC ARM AARCH64
+# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64
#
[Sources]
@@ -43,9 +43,6 @@
[Sources.IA32, Sources.X64, Sources.EBC, Sources.AARCH64]
PeCoffLoaderEx.c
-[Sources.IPF]
- Ipf/PeCoffLoaderEx.c
-
[Sources.ARM]
Arm/PeCoffLoaderEx.c
diff --git a/MdePkg/Library/BasePeCoffLib/Ipf/PeCoffLoaderEx.c b/MdePkg/Library/BasePeCoffLib/Ipf/PeCoffLoaderEx.c
deleted file mode 100644
index 96e122b698..0000000000
--- a/MdePkg/Library/BasePeCoffLib/Ipf/PeCoffLoaderEx.c
+++ /dev/null
@@ -1,422 +0,0 @@
-/** @file
- Fixes Intel Itanium(TM) specific relocation types.
-
- Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php.
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include "BasePeCoffLibInternals.h"
-
-
-
-#define EXT_IMM64(Value, Address, Size, InstPos, ValPos) \
- Value |= (((UINT64)((*(Address) >> InstPos) & (((UINT64)1 << Size) - 1))) << ValPos)
-
-#define INS_IMM64(Value, Address, Size, InstPos, ValPos) \
- *(UINT32*)Address = (*(UINT32*)Address & ~(((1 << Size) - 1) << InstPos)) | \
- ((UINT32)((((UINT64)Value >> ValPos) & (((UINT64)1 << Size) - 1))) << InstPos)
-
-#define IMM64_IMM7B_INST_WORD_X 3
-#define IMM64_IMM7B_SIZE_X 7
-#define IMM64_IMM7B_INST_WORD_POS_X 4
-#define IMM64_IMM7B_VAL_POS_X 0
-
-#define IMM64_IMM9D_INST_WORD_X 3
-#define IMM64_IMM9D_SIZE_X 9
-#define IMM64_IMM9D_INST_WORD_POS_X 18
-#define IMM64_IMM9D_VAL_POS_X 7
-
-#define IMM64_IMM5C_INST_WORD_X 3
-#define IMM64_IMM5C_SIZE_X 5
-#define IMM64_IMM5C_INST_WORD_POS_X 13
-#define IMM64_IMM5C_VAL_POS_X 16
-
-#define IMM64_IC_INST_WORD_X 3
-#define IMM64_IC_SIZE_X 1
-#define IMM64_IC_INST_WORD_POS_X 12
-#define IMM64_IC_VAL_POS_X 21
-
-#define IMM64_IMM41A_INST_WORD_X 1
-#define IMM64_IMM41A_SIZE_X 10
-#define IMM64_IMM41A_INST_WORD_POS_X 14
-#define IMM64_IMM41A_VAL_POS_X 22
-
-#define IMM64_IMM41B_INST_WORD_X 1
-#define IMM64_IMM41B_SIZE_X 8
-#define IMM64_IMM41B_INST_WORD_POS_X 24
-#define IMM64_IMM41B_VAL_POS_X 32
-
-#define IMM64_IMM41C_INST_WORD_X 2
-#define IMM64_IMM41C_SIZE_X 23
-#define IMM64_IMM41C_INST_WORD_POS_X 0
-#define IMM64_IMM41C_VAL_POS_X 40
-
-#define IMM64_SIGN_INST_WORD_X 3
-#define IMM64_SIGN_SIZE_X 1
-#define IMM64_SIGN_INST_WORD_POS_X 27
-#define IMM64_SIGN_VAL_POS_X 63
-
-/**
- Performs an Itanium-based specific relocation fixup.
-
- @param Reloc The pointer to the relocation record.
- @param Fixup The pointer to the address to fix up.
- @param FixupData The pointer to a buffer to log the fixups.
- @param Adjust The offset to adjust the fixup.
-
- @retval RETURN_SUCCESS Succeed to fix the relocation entry.
- @retval RETURN_UNSUPPOTED Unrecoganized relocation entry.
-
-**/
-RETURN_STATUS
-PeCoffLoaderRelocateImageEx (
- IN UINT16 *Reloc,
- IN OUT CHAR8 *Fixup,
- IN OUT CHAR8 **FixupData,
- IN UINT64 Adjust
- )
-{
- UINT64 *Fixup64;
- UINT64 FixupVal;
-
- switch ((*Reloc) >> 12) {
- case EFI_IMAGE_REL_BASED_IA64_IMM64:
-
- //
- // Align it to bundle address before fixing up the
- // 64-bit immediate value of the movl instruction.
- //
-
- Fixup = (CHAR8 *)((UINTN) Fixup & (UINTN) ~(15));
- FixupVal = (UINT64)0;
-
- //
- // Extract the lower 32 bits of IMM64 from bundle
- //
- EXT_IMM64(FixupVal,
- (UINT32 *)Fixup + IMM64_IMM7B_INST_WORD_X,
- IMM64_IMM7B_SIZE_X,
- IMM64_IMM7B_INST_WORD_POS_X,
- IMM64_IMM7B_VAL_POS_X
- );
-
- EXT_IMM64(FixupVal,
- (UINT32 *)Fixup + IMM64_IMM9D_INST_WORD_X,
- IMM64_IMM9D_SIZE_X,
- IMM64_IMM9D_INST_WORD_POS_X,
- IMM64_IMM9D_VAL_POS_X
- );
-
- EXT_IMM64(FixupVal,
- (UINT32 *)Fixup + IMM64_IMM5C_INST_WORD_X,
- IMM64_IMM5C_SIZE_X,
- IMM64_IMM5C_INST_WORD_POS_X,
- IMM64_IMM5C_VAL_POS_X
- );
-
- EXT_IMM64(FixupVal,
- (UINT32 *)Fixup + IMM64_IC_INST_WORD_X,
- IMM64_IC_SIZE_X,
- IMM64_IC_INST_WORD_POS_X,
- IMM64_IC_VAL_POS_X
- );
-
- EXT_IMM64(FixupVal,
- (UINT32 *)Fixup + IMM64_IMM41A_INST_WORD_X,
- IMM64_IMM41A_SIZE_X,
- IMM64_IMM41A_INST_WORD_POS_X,
- IMM64_IMM41A_VAL_POS_X
- );
-
- //
- // Update 64-bit address
- //
- FixupVal += Adjust;
-
- //
- // Insert IMM64 into bundle
- //
- INS_IMM64(FixupVal,
- ((UINT32 *)Fixup + IMM64_IMM7B_INST_WORD_X),
- IMM64_IMM7B_SIZE_X,
- IMM64_IMM7B_INST_WORD_POS_X,
- IMM64_IMM7B_VAL_POS_X
- );
-
- INS_IMM64(FixupVal,
- ((UINT32 *)Fixup + IMM64_IMM9D_INST_WORD_X),
- IMM64_IMM9D_SIZE_X,
- IMM64_IMM9D_INST_WORD_POS_X,
- IMM64_IMM9D_VAL_POS_X
- );
-
- INS_IMM64(FixupVal,
- ((UINT32 *)Fixup + IMM64_IMM5C_INST_WORD_X),
- IMM64_IMM5C_SIZE_X,
- IMM64_IMM5C_INST_WORD_POS_X,
- IMM64_IMM5C_VAL_POS_X
- );
-
- INS_IMM64(FixupVal,
- ((UINT32 *)Fixup + IMM64_IC_INST_WORD_X),
- IMM64_IC_SIZE_X,
- IMM64_IC_INST_WORD_POS_X,
- IMM64_IC_VAL_POS_X
- );
-
- INS_IMM64(FixupVal,
- ((UINT32 *)Fixup + IMM64_IMM41A_INST_WORD_X),
- IMM64_IMM41A_SIZE_X,
- IMM64_IMM41A_INST_WORD_POS_X,
- IMM64_IMM41A_VAL_POS_X
- );
-
- INS_IMM64(FixupVal,
- ((UINT32 *)Fixup + IMM64_IMM41B_INST_WORD_X),
- IMM64_IMM41B_SIZE_X,
- IMM64_IMM41B_INST_WORD_POS_X,
- IMM64_IMM41B_VAL_POS_X
- );
-
- INS_IMM64(FixupVal,
- ((UINT32 *)Fixup + IMM64_IMM41C_INST_WORD_X),
- IMM64_IMM41C_SIZE_X,
- IMM64_IMM41C_INST_WORD_POS_X,
- IMM64_IMM41C_VAL_POS_X
- );
-
- INS_IMM64(FixupVal,
- ((UINT32 *)Fixup + IMM64_SIGN_INST_WORD_X),
- IMM64_SIGN_SIZE_X,
- IMM64_SIGN_INST_WORD_POS_X,
- IMM64_SIGN_VAL_POS_X
- );
-
- Fixup64 = (UINT64 *) Fixup;
- if (*FixupData != NULL) {
- *FixupData = ALIGN_POINTER(*FixupData, sizeof(UINT64));
- *(UINT64 *)(*FixupData) = *Fixup64;
- *FixupData = *FixupData + sizeof(UINT64);
- }
- break;
-
- default:
- return RETURN_UNSUPPORTED;
- }
-
- return RETURN_SUCCESS;
-}
-
-/**
- Returns TRUE if the machine type of PE/COFF image is supported. Supported
- does not mean the image can be executed it means the PE/COFF loader supports
- loading and relocating of the image type. It's up to the caller to support
- the entry point.
-
- The itanium version PE/COFF loader/relocater supports itanium and EBC image.
-
- @param Machine Machine type from the PE Header.
-
- @return TRUE if this PE/COFF loader can load the image
- @return FALSE unrecoganized machine type of image.
-
-**/
-BOOLEAN
-PeCoffLoaderImageFormatSupported (
- IN UINT16 Machine
- )
-{
- if ((Machine == IMAGE_FILE_MACHINE_IA64) || (Machine == IMAGE_FILE_MACHINE_EBC)) {
- return TRUE;
- }
-
- return FALSE;
-}
-
-
-/**
- ImageRead function that operates on a memory buffer whos base is passed into
- FileHandle.
-
- @param Reloc Ponter to baes of the input stream
- @param Fixup Offset to the start of the buffer
- @param FixupData The number of bytes to copy into the buffer
- @param Adjust Location to place results of read
-
- @retval RETURN_SUCCESS Data is read from FileOffset from the Handle into
- the buffer.
- @retval RETURN_UNSUPPORTED Un-recoganized relocation entry
- type.
-**/
-RETURN_STATUS
-PeHotRelocateImageEx (
- IN UINT16 *Reloc,
- IN OUT CHAR8 *Fixup,
- IN OUT CHAR8 **FixupData,
- IN UINT64 Adjust
- )
-{
- UINT64 *Fixup64;
- UINT64 FixupVal;
-
- switch ((*Reloc) >> 12) {
- case EFI_IMAGE_REL_BASED_DIR64:
- Fixup64 = (UINT64 *) Fixup;
- *FixupData = ALIGN_POINTER (*FixupData, sizeof (UINT64));
- if (*(UINT64 *) (*FixupData) == *Fixup64) {
- *Fixup64 = *Fixup64 + (UINT64) Adjust;
- }
-
- *FixupData = *FixupData + sizeof (UINT64);
- break;
-
- case EFI_IMAGE_REL_BASED_IA64_IMM64:
- Fixup64 = (UINT64 *) Fixup;
- *FixupData = ALIGN_POINTER (*FixupData, sizeof (UINT64));
- if (*(UINT64 *) (*FixupData) == *Fixup64) {
- //
- // Align it to bundle address before fixing up the
- // 64-bit immediate value of the movl instruction.
- //
- //
- Fixup = (CHAR8 *) ((UINT64) Fixup & (UINT64)~(15));
- FixupVal = (UINT64) 0;
-
- //
- // Extract the lower 32 bits of IMM64 from bundle
- //
- EXT_IMM64 (
- FixupVal,
- (UINT32 *) Fixup + IMM64_IMM7B_INST_WORD_X,
- IMM64_IMM7B_SIZE_X,
- IMM64_IMM7B_INST_WORD_POS_X,
- IMM64_IMM7B_VAL_POS_X
- );
-
- EXT_IMM64 (
- FixupVal,
- (UINT32 *) Fixup + IMM64_IMM9D_INST_WORD_X,
- IMM64_IMM9D_SIZE_X,
- IMM64_IMM9D_INST_WORD_POS_X,
- IMM64_IMM9D_VAL_POS_X
- );
-
- EXT_IMM64 (
- FixupVal,
- (UINT32 *) Fixup + IMM64_IMM5C_INST_WORD_X,
- IMM64_IMM5C_SIZE_X,
- IMM64_IMM5C_INST_WORD_POS_X,
- IMM64_IMM5C_VAL_POS_X
- );
-
- EXT_IMM64 (
- FixupVal,
- (UINT32 *) Fixup + IMM64_IC_INST_WORD_X,
- IMM64_IC_SIZE_X,
- IMM64_IC_INST_WORD_POS_X,
- IMM64_IC_VAL_POS_X
- );
-
- EXT_IMM64 (
- FixupVal,
- (UINT32 *) Fixup + IMM64_IMM41A_INST_WORD_X,
- IMM64_IMM41A_SIZE_X,
- IMM64_IMM41A_INST_WORD_POS_X,
- IMM64_IMM41A_VAL_POS_X
- );
-
- //
- // Update 64-bit address
- //
- FixupVal += Adjust;
-
- //
- // Insert IMM64 into bundle
- //
- INS_IMM64 (
- FixupVal,
- ((UINT32 *) Fixup + IMM64_IMM7B_INST_WORD_X),
- IMM64_IMM7B_SIZE_X,
- IMM64_IMM7B_INST_WORD_POS_X,
- IMM64_IMM7B_VAL_POS_X
- );
-
- INS_IMM64 (
- FixupVal,
- ((UINT32 *) Fixup + IMM64_IMM9D_INST_WORD_X),
- IMM64_IMM9D_SIZE_X,
- IMM64_IMM9D_INST_WORD_POS_X,
- IMM64_IMM9D_VAL_POS_X
- );
-
- INS_IMM64 (
- FixupVal,
- ((UINT32 *) Fixup + IMM64_IMM5C_INST_WORD_X),
- IMM64_IMM5C_SIZE_X,
- IMM64_IMM5C_INST_WORD_POS_X,
- IMM64_IMM5C_VAL_POS_X
- );
-
- INS_IMM64 (
- FixupVal,
- ((UINT32 *) Fixup + IMM64_IC_INST_WORD_X),
- IMM64_IC_SIZE_X,
- IMM64_IC_INST_WORD_POS_X,
- IMM64_IC_VAL_POS_X
- );
-
- INS_IMM64 (
- FixupVal,
- ((UINT32 *) Fixup + IMM64_IMM41A_INST_WORD_X),
- IMM64_IMM41A_SIZE_X,
- IMM64_IMM41A_INST_WORD_POS_X,
- IMM64_IMM41A_VAL_POS_X
- );
-
- INS_IMM64 (
- FixupVal,
- ((UINT32 *) Fixup + IMM64_IMM41B_INST_WORD_X),
- IMM64_IMM41B_SIZE_X,
- IMM64_IMM41B_INST_WORD_POS_X,
- IMM64_IMM41B_VAL_POS_X
- );
-
- INS_IMM64 (
- FixupVal,
- ((UINT32 *) Fixup + IMM64_IMM41C_INST_WORD_X),
- IMM64_IMM41C_SIZE_X,
- IMM64_IMM41C_INST_WORD_POS_X,
- IMM64_IMM41C_VAL_POS_X
- );
-
- INS_IMM64 (
- FixupVal,
- ((UINT32 *) Fixup + IMM64_SIGN_INST_WORD_X),
- IMM64_SIGN_SIZE_X,
- IMM64_SIGN_INST_WORD_POS_X,
- IMM64_SIGN_VAL_POS_X
- );
-
- *(UINT64 *) (*FixupData) = *Fixup64;
- }
-
- *FixupData = *FixupData + sizeof (UINT64);
- break;
-
- default:
- DEBUG ((EFI_D_ERROR, "PeHotRelocateEx:unknown fixed type\n"));
- return RETURN_UNSUPPORTED;
- }
-
- return RETURN_SUCCESS;
-}
-
-
-
diff --git a/MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf b/MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
index d29b532c08..f8d468dbe3 100644
--- a/MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
+++ b/MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
@@ -24,7 +24,7 @@
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]
diff --git a/MdePkg/Library/BasePostCodeLibDebug/BasePostCodeLibDebug.inf b/MdePkg/Library/BasePostCodeLibDebug/BasePostCodeLibDebug.inf
index 1b9c8ad2c8..076cb410af 100644
--- a/MdePkg/Library/BasePostCodeLibDebug/BasePostCodeLibDebug.inf
+++ b/MdePkg/Library/BasePostCodeLibDebug/BasePostCodeLibDebug.inf
@@ -27,7 +27,7 @@
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+# VALID_ARCHITECTURES = IA32 X64 EBC
#
diff --git a/MdePkg/Library/BasePostCodeLibPort80/BasePostCodeLibPort80.inf b/MdePkg/Library/BasePostCodeLibPort80/BasePostCodeLibPort80.inf
index ebe1158728..c411faa37f 100644
--- a/MdePkg/Library/BasePostCodeLibPort80/BasePostCodeLibPort80.inf
+++ b/MdePkg/Library/BasePostCodeLibPort80/BasePostCodeLibPort80.inf
@@ -26,7 +26,7 @@
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]
diff --git a/MdePkg/Library/BasePrintLib/BasePrintLib.inf b/MdePkg/Library/BasePrintLib/BasePrintLib.inf
index 069b80d5e4..9b993ba906 100644
--- a/MdePkg/Library/BasePrintLib/BasePrintLib.inf
+++ b/MdePkg/Library/BasePrintLib/BasePrintLib.inf
@@ -24,7 +24,7 @@
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+# VALID_ARCHITECTURES = IA32 X64 EBC
#
diff --git a/MdePkg/Library/BaseReportStatusCodeLibNull/BaseReportStatusCodeLibNull.inf b/MdePkg/Library/BaseReportStatusCodeLibNull/BaseReportStatusCodeLibNull.inf
index 8ca96aab61..28b85f3636 100644
--- a/MdePkg/Library/BaseReportStatusCodeLibNull/BaseReportStatusCodeLibNull.inf
+++ b/MdePkg/Library/BaseReportStatusCodeLibNull/BaseReportStatusCodeLibNull.inf
@@ -25,7 +25,7 @@
#
# The following information is for reference only and not required by the build tools.
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]
diff --git a/MdePkg/Library/BaseS3BootScriptLibNull/BaseS3BootScriptLibNull.inf b/MdePkg/Library/BaseS3BootScriptLibNull/BaseS3BootScriptLibNull.inf
index 41e966c475..2e3f28e846 100644
--- a/MdePkg/Library/BaseS3BootScriptLibNull/BaseS3BootScriptLibNull.inf
+++ b/MdePkg/Library/BaseS3BootScriptLibNull/BaseS3BootScriptLibNull.inf
@@ -31,7 +31,7 @@
#
# The following information is for reference only and not required by the build tools.
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]
diff --git a/MdePkg/Library/BaseS3IoLib/BaseS3IoLib.inf b/MdePkg/Library/BaseS3IoLib/BaseS3IoLib.inf
index b6c10941ff..359d427c6b 100644
--- a/MdePkg/Library/BaseS3IoLib/BaseS3IoLib.inf
+++ b/MdePkg/Library/BaseS3IoLib/BaseS3IoLib.inf
@@ -29,7 +29,7 @@
#
# The following information is for reference only and not required by the build tools.
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]
diff --git a/MdePkg/Library/BaseS3PciLib/BaseS3PciLib.inf b/MdePkg/Library/BaseS3PciLib/BaseS3PciLib.inf
index 561c504d7a..6f996796e7 100644
--- a/MdePkg/Library/BaseS3PciLib/BaseS3PciLib.inf
+++ b/MdePkg/Library/BaseS3PciLib/BaseS3PciLib.inf
@@ -29,7 +29,7 @@
#
# The following information is for reference only and not required by the build tools.
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]
diff --git a/MdePkg/Library/BaseS3PciSegmentLib/BaseS3PciSegmentLib.inf b/MdePkg/Library/BaseS3PciSegmentLib/BaseS3PciSegmentLib.inf
index 20214f7f2b..b6684cffa0 100644
--- a/MdePkg/Library/BaseS3PciSegmentLib/BaseS3PciSegmentLib.inf
+++ b/MdePkg/Library/BaseS3PciSegmentLib/BaseS3PciSegmentLib.inf
@@ -29,7 +29,7 @@
#
# The following information is for reference only and not required by the build tools.
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]
diff --git a/MdePkg/Library/BaseS3SmbusLib/BaseS3SmbusLib.inf b/MdePkg/Library/BaseS3SmbusLib/BaseS3SmbusLib.inf
index 553662471f..5be1b19e28 100644
--- a/MdePkg/Library/BaseS3SmbusLib/BaseS3SmbusLib.inf
+++ b/MdePkg/Library/BaseS3SmbusLib/BaseS3SmbusLib.inf
@@ -29,7 +29,7 @@
#
# The following information is for reference only and not required by the build tools.
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]
diff --git a/MdePkg/Library/BaseS3StallLib/BaseS3StallLib.inf b/MdePkg/Library/BaseS3StallLib/BaseS3StallLib.inf
index a77eec512d..ad480f622f 100644
--- a/MdePkg/Library/BaseS3StallLib/BaseS3StallLib.inf
+++ b/MdePkg/Library/BaseS3StallLib/BaseS3StallLib.inf
@@ -29,7 +29,7 @@
#
# The following information is for reference only and not required by the build tools.
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]
diff --git a/MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf b/MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf
index 8fbdafe748..b5b1880a52 100644
--- a/MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf
+++ b/MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf
@@ -48,7 +48,7 @@
[Sources.Ia32, Sources.ARM]
SafeIntLib32.c
-[Sources.X64, Sources.IPF, Sources.AARCH64]
+[Sources.X64, Sources.AARCH64]
SafeIntLib64.c
[Sources.EBC]
diff --git a/MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf b/MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf
index 28a7988274..4c4739ed19 100644
--- a/MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf
+++ b/MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf
@@ -24,7 +24,7 @@
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]
diff --git a/MdePkg/Library/BaseSmbusLibNull/BaseSmbusLibNull.inf b/MdePkg/Library/BaseSmbusLibNull/BaseSmbusLibNull.inf
index 512db33f9f..dbd9b8b6e1 100644
--- a/MdePkg/Library/BaseSmbusLibNull/BaseSmbusLibNull.inf
+++ b/MdePkg/Library/BaseSmbusLibNull/BaseSmbusLibNull.inf
@@ -22,7 +22,7 @@
LIBRARY_CLASS = SmbusLib
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]
diff --git a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
index 03562c6e56..a26de76d7e 100755
--- a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
+++ b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
@@ -24,7 +24,7 @@
LIBRARY_CLASS = SynchronizationLib
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC ARM AARCH64
+# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64
#
[Sources]
BaseSynchronizationLibInternals.h
@@ -71,19 +71,6 @@
X64/GccInline.c | GCC
SynchronizationGcc.c | GCC
-[Sources.IPF]
- Ipf/Synchronization.c
- Ipf/InterlockedCompareExchange64.s
- Ipf/InterlockedCompareExchange32.s
- Ipf/InterlockedCompareExchange16.s
-
- Ipf/InternalGetSpinLockProperties.c | MSFT
- Ipf/InternalGetSpinLockProperties.c | GCC
-
- Synchronization.c | INTEL
- SynchronizationMsc.c | MSFT
- SynchronizationGcc.c | GCC
-
[Sources.EBC]
Synchronization.c
Ebc/Synchronization.c
diff --git a/MdePkg/Library/BaseSynchronizationLib/Ipf/InterlockedCompareExchange16.s b/MdePkg/Library/BaseSynchronizationLib/Ipf/InterlockedCompareExchange16.s
deleted file mode 100644
index b72a1f33dd..0000000000
--- a/MdePkg/Library/BaseSynchronizationLib/Ipf/InterlockedCompareExchange16.s
+++ /dev/null
@@ -1,30 +0,0 @@
-/// @file
-/// Contains an implementation of InterlockedCompareExchange16 on Itanium-
-/// based architecture.
-///
-/// Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-/// Copyright (c) 2015, Linaro Ltd. All rights reserved.<BR>
-/// This program and the accompanying materials
-/// are licensed and made available under the terms and conditions of the BSD License
-/// which accompanies this distribution. The full text of the license may be found at
-/// http://opensource.org/licenses/bsd-license.php.
-///
-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-///
-/// Module Name: InterlockedCompareExchange16.s
-///
-///
-
-.auto
-.text
-
-.proc InternalSyncCompareExchange16
-.type InternalSyncCompareExchange16, @function
-InternalSyncCompareExchange16::
- zxt2 r33 = r33
- mov ar.ccv = r33
- cmpxchg2.rel r8 = [r32], r34
- mf
- br.ret.sptk.many b0
-.endp InternalSyncCompareExchange16
diff --git a/MdePkg/Library/BaseSynchronizationLib/Ipf/InterlockedCompareExchange32.s b/MdePkg/Library/BaseSynchronizationLib/Ipf/InterlockedCompareExchange32.s
deleted file mode 100644
index 48273c9cfd..0000000000
--- a/MdePkg/Library/BaseSynchronizationLib/Ipf/InterlockedCompareExchange32.s
+++ /dev/null
@@ -1,29 +0,0 @@
-/// @file
-/// Contains an implementation of InterlockedCompareExchange32 on Itanium-
-/// based architecture.
-///
-/// Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-/// This program and the accompanying materials
-/// are licensed and made available under the terms and conditions of the BSD License
-/// which accompanies this distribution. The full text of the license may be found at
-/// http://opensource.org/licenses/bsd-license.php.
-///
-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-///
-/// Module Name: InterlockedCompareExchange32.s
-///
-///
-
-.auto
-.text
-
-.proc InternalSyncCompareExchange32
-.type InternalSyncCompareExchange32, @function
-InternalSyncCompareExchange32::
- zxt4 r33 = r33
- mov ar.ccv = r33
- cmpxchg4.rel r8 = [r32], r34
- mf
- br.ret.sptk.many b0
-.endp InternalSyncCompareExchange32
diff --git a/MdePkg/Library/BaseSynchronizationLib/Ipf/InterlockedCompareExchange64.s b/MdePkg/Library/BaseSynchronizationLib/Ipf/InterlockedCompareExchange64.s
deleted file mode 100644
index b6ee19694e..0000000000
--- a/MdePkg/Library/BaseSynchronizationLib/Ipf/InterlockedCompareExchange64.s
+++ /dev/null
@@ -1,28 +0,0 @@
-/// @file
-/// Contains an implementation of InterlockedCompareExchange64 on Itanium-
-/// based architecture.
-///
-/// Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
-/// This program and the accompanying materials
-/// are licensed and made available under the terms and conditions of the BSD License
-/// which accompanies this distribution. The full text of the license may be found at
-/// http://opensource.org/licenses/bsd-license.php.
-///
-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-///
-/// Module Name: InterlockedCompareExchange64.s
-///
-///
-
-.auto
-.text
-
-.proc InternalSyncCompareExchange64
-.type InternalSyncCompareExchange64, @function
-InternalSyncCompareExchange64::
- mov ar.ccv = r33
- cmpxchg8.rel r8 = [r32], r34
- mf
- br.ret.sptk.many b0
-.endp InternalSyncCompareExchange64
diff --git a/MdePkg/Library/BaseSynchronizationLib/Ipf/InternalGetSpinLockProperties.c b/MdePkg/Library/BaseSynchronizationLib/Ipf/InternalGetSpinLockProperties.c
deleted file mode 100644
index f6464c2db7..0000000000
--- a/MdePkg/Library/BaseSynchronizationLib/Ipf/InternalGetSpinLockProperties.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/** @file
- Internal function to get spin lock alignment.
-
- Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php.
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-/**
- Internal function to retrieve the architecture specific spin lock alignment
- requirements for optimal spin lock performance.
-
- @return The architecture specific spin lock alignment.
-
-**/
-UINTN
-InternalGetSpinLockProperties (
- VOID
- )
-{
- return 32;
-}
-
diff --git a/MdePkg/Library/BaseSynchronizationLib/Ipf/Synchronization.c b/MdePkg/Library/BaseSynchronizationLib/Ipf/Synchronization.c
deleted file mode 100644
index 3e316e7140..0000000000
--- a/MdePkg/Library/BaseSynchronizationLib/Ipf/Synchronization.c
+++ /dev/null
@@ -1,77 +0,0 @@
-/** @file
- Implementation of synchronization functions on Itanium.
-
- Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php.
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include "BaseSynchronizationLibInternals.h"
-
-/**
- Performs an atomic increment of an 32-bit unsigned integer.
-
- Performs an atomic increment of the 32-bit unsigned integer specified by
- Value and returns the incremented value. The increment operation must be
- performed using MP safe mechanisms. The state of the return value is not
- guaranteed to be MP safe.
-
- @param Value A pointer to the 32-bit value to increment.
-
- @return The incremented value.
-
-**/
-UINT32
-EFIAPI
-InternalSyncIncrement (
- IN volatile UINT32 *Value
- )
-{
- UINT32 OriginalValue;
-
- do {
- OriginalValue = *Value;
- } while (OriginalValue != InternalSyncCompareExchange32 (
- Value,
- OriginalValue,
- OriginalValue + 1
- ));
- return OriginalValue + 1;
-}
-
-/**
- Performs an atomic decrement of an 32-bit unsigned integer.
-
- Performs an atomic decrement of the 32-bit unsigned integer specified by
- Value and returns the decrement value. The decrement operation must be
- performed using MP safe mechanisms. The state of the return value is not
- guaranteed to be MP safe.
-
- @param Value A pointer to the 32-bit value to decrement.
-
- @return The decrement value.
-
-**/
-UINT32
-EFIAPI
-InternalSyncDecrement (
- IN volatile UINT32 *Value
- )
-{
- UINT32 OriginalValue;
-
- do {
- OriginalValue = *Value;
- } while (OriginalValue != InternalSyncCompareExchange32 (
- Value,
- OriginalValue,
- OriginalValue - 1
- ));
- return OriginalValue - 1;
-}
diff --git a/MdePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTemplate.inf b/MdePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTemplate.inf
index e72abdd818..99625dd0a8 100644
--- a/MdePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTemplate.inf
+++ b/MdePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTemplate.inf
@@ -29,7 +29,7 @@
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]
diff --git a/MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf b/MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
index 36d7a240c1..f0730fb7ec 100644
--- a/MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+++ b/MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
@@ -24,7 +24,7 @@
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]
diff --git a/MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf b/MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
index 01f64c34c7..1aa6e23619 100644
--- a/MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
+++ b/MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
@@ -24,7 +24,7 @@
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC (EBC is for build only)
+# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only)
#
[Sources]
diff --git a/MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf b/MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
index ae48d9279f..0a4bfdcb99 100644
--- a/MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
+++ b/MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
@@ -27,7 +27,7 @@
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC (EBC is for build only)
+# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only)
#
[Sources]
diff --git a/MdePkg/Library/DxeExtendedSalLib/DxeExtendedSalLib.inf b/MdePkg/Library/DxeExtendedSalLib/DxeExtendedSalLib.inf
deleted file mode 100644
index 2c4e28b039..0000000000
--- a/MdePkg/Library/DxeExtendedSalLib/DxeExtendedSalLib.inf
+++ /dev/null
@@ -1,46 +0,0 @@
-## @file
-# The library implements the Extended SAL Library Class for boot service only modules.
-#
-# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php.
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-##
-
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = DxeExtendedSalLib
- MODULE_UNI_FILE = DxeExtendedSalLib.uni
- FILE_GUID = 8FDED21D-7AB5-4c26-8CF7-20EC4DB9861D
- MODULE_TYPE = DXE_DRIVER
- VERSION_STRING = 1.0
- LIBRARY_CLASS = ExtendedSalLib|DXE_DRIVER UEFI_DRIVER UEFI_APPLICATION
- CONSTRUCTOR = DxeExtendedSalLibConstruct
-
-#
-# The following information is for reference only and not required by the build tools.
-#
-# VALID_ARCHITECTURES = IPF
-#
-
-[Sources.IPF]
- ExtendedSalLib.c
- Ipf/AsmExtendedSalLib.s
-
-[Packages]
- MdePkg/MdePkg.dec
-
-[LibraryClasses]
- UefiBootServicesTableLib
-
-[Protocols]
- gEfiExtendedSalBootServiceProtocolGuid ## CONSUMES
-
-[Depex.common.DXE_DRIVER]
- gEfiExtendedSalBootServiceProtocolGuid
-
diff --git a/MdePkg/Library/DxeExtendedSalLib/ExtendedSalLib.c b/MdePkg/Library/DxeExtendedSalLib/ExtendedSalLib.c
deleted file mode 100644
index 0f48c63f7b..0000000000
--- a/MdePkg/Library/DxeExtendedSalLib/ExtendedSalLib.c
+++ /dev/null
@@ -1,1001 +0,0 @@
-/** @file
- The library implements the Extended SAL Library Class for boot service only modules.
-
- Copyright (c) 2007 - 2012, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php.
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include <PiDxe.h>
-
-#include <Protocol/ExtendedSalBootService.h>
-#include <Protocol/ExtendedSalServiceClasses.h>
-
-#include <Library/ExtendedSalLib.h>
-#include <Library/UefiBootServicesTableLib.h>
-#include <Library/DebugLib.h>
-
-/**
- Stores the physical plabel of ESAL entrypoint.
-
- This assembly function stores the physical plabel of ESAL entrypoint
- where GetEsalEntryPoint() can easily retrieve.
-
- @param EntryPoint Physical address of ESAL entrypoint
- @param Gp Physical GP of ESAL entrypoint
-
- @return r8 = EFI_SAL_SUCCESS
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-SetEsalPhysicalEntryPoint (
- IN UINT64 EntryPoint,
- IN UINT64 Gp
- );
-
-/**
- Retrieves plabel of ESAL entrypoint.
-
- This function retrives plabel of ESAL entrypoint stored by
- SetEsalPhysicalEntryPoint().
-
- @return r8 = EFI_SAL_SUCCESS
- r9 = Physical Plabel
- r10 = Virtual Plabel
- r11 = PSR
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-GetEsalEntryPoint (
- VOID
- );
-
-EXTENDED_SAL_BOOT_SERVICE_PROTOCOL *mEsalBootService = NULL;
-EFI_PLABEL mPlabel;
-
-/**
- Constructor function to get Extended SAL Boot Service Protocol, and initializes
- physical plabel of ESAL entrypoint.
-
- This function first locates Extended SAL Boot Service Protocol and caches it in global variable.
- Then it initializes the physical plable of ESAL entrypoint, and stores
- it where GetEsalEntryPoint() can easily retrieve.
-
- @param ImageHandle The firmware allocated handle for the EFI image.
- @param SystemTable A pointer to the EFI System Table.
-
- @retval EFI_SUCCESS Plable of ESAL entrypoint successfully stored.
-
-**/
-EFI_STATUS
-EFIAPI
-DxeExtendedSalLibConstruct (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
- )
-{
- EFI_PLABEL *Plabel;
- EFI_STATUS Status;
-
- //
- // The protocol contains a function pointer, which is an indirect procedure call.
- // An indirect procedure call goes through a plabel, and pointer to a function is
- // a pointer to a plabel. To implement indirect procedure calls that can work in
- // both physical and virtual mode, two plabels are required (one physical and one
- // virtual). So lets grap the physical PLABEL for the EsalEntryPoint and store it
- // away. We cache it in a module global, so we can register the vitrual version.
- //
- Status = gBS->LocateProtocol (&gEfiExtendedSalBootServiceProtocolGuid, NULL, (VOID **) &mEsalBootService);
- ASSERT_EFI_ERROR (Status);
-
- Plabel = (EFI_PLABEL *) (UINTN) mEsalBootService->ExtendedSalProc;
- mPlabel.EntryPoint = Plabel->EntryPoint;
- mPlabel.GP = Plabel->GP;
- //
- // Stores the physical plabel of ESAL entrypoint where GetEsalEntryPoint() can easily retrieve.
- //
- SetEsalPhysicalEntryPoint (mPlabel.EntryPoint, mPlabel.GP);
-
- return EFI_SUCCESS;
-}
-
-/**
- Registers function of ESAL class and it's associated global.
-
- This function registers function of ESAL class, together with its associated global.
- It is worker function for RegisterEsalClass().
- It is only for boot time.
-
- @param FunctionId ID of function to register
- @param ClassGuidLo GUID of ESAL class, lower 64-bits
- @param ClassGuidHi GUID of ESAL class, upper 64-bits
- @param Function Function to register with ClassGuid/FunctionId pair
- @param ModuleGlobal Module global for the function.
-
- @return Status returned by RegisterExtendedSalProc() of Extended SAL Boot Service Protocol
-
-**/
-EFI_STATUS
-RegisterEsalFunction (
- IN UINT64 FunctionId,
- IN UINT64 ClassGuidLo,
- IN UINT64 ClassGuidHi,
- IN SAL_INTERNAL_EXTENDED_SAL_PROC Function,
- IN VOID *ModuleGlobal
- )
-{
- return mEsalBootService->RegisterExtendedSalProc (
- mEsalBootService,
- ClassGuidLo,
- ClassGuidHi,
- FunctionId,
- Function,
- ModuleGlobal
- );
-}
-
-/**
- Registers ESAL Class and it's associated global.
-
- This function registers one or more Extended SAL services in a given
- class along with the associated global context.
- This function is only available prior to ExitBootServices().
-
- @param ClassGuidLo GUID of function class, lower 64-bits
- @param ClassGuidHi GUID of function class, upper 64-bits
- @param ModuleGlobal Module global for the class.
- @param ... List of Function/FunctionId pairs, ended by NULL
-
- @retval EFI_SUCCESS The Extended SAL services were registered.
- @retval EFI_UNSUPPORTED This function was called after ExitBootServices().
- @retval EFI_OUT_OF_RESOURCES There are not enough resources available to register one or more of the specified services.
- @retval Other ClassGuid could not be installed onto a new handle.
-
-**/
-EFI_STATUS
-EFIAPI
-RegisterEsalClass (
- IN CONST UINT64 ClassGuidLo,
- IN CONST UINT64 ClassGuidHi,
- IN VOID *ModuleGlobal, OPTIONAL
- ...
- )
-{
- VA_LIST Args;
- EFI_STATUS Status;
- SAL_INTERNAL_EXTENDED_SAL_PROC Function;
- UINT64 FunctionId;
- EFI_HANDLE NewHandle;
- EFI_GUID ClassGuid;
-
- VA_START (Args, ModuleGlobal);
-
- //
- // Register all functions of the class to register.
- //
- Status = EFI_SUCCESS;
- while (!EFI_ERROR (Status)) {
- Function = (SAL_INTERNAL_EXTENDED_SAL_PROC) VA_ARG (Args, SAL_INTERNAL_EXTENDED_SAL_PROC);
- //
- // NULL serves as the end mark of function list
- //
- if (Function == NULL) {
- break;
- }
-
- FunctionId = VA_ARG (Args, UINT64);
-
- Status = RegisterEsalFunction (FunctionId, ClassGuidLo, ClassGuidHi, Function, ModuleGlobal);
- }
-
- VA_END (Args);
-
- if (EFI_ERROR (Status)) {
- return Status;
- }
-
- NewHandle = NULL;
- *((UINT64 *)(&ClassGuid) + 0) = ClassGuidLo;
- *((UINT64 *)(&ClassGuid) + 1) = ClassGuidHi;
- return gBS->InstallProtocolInterface (
- &NewHandle,
- &ClassGuid,
- EFI_NATIVE_INTERFACE,
- NULL
- );
-}
-
-/**
- Calls an Extended SAL Class service that was previously registered with RegisterEsalClass().
-
- This function gets the entrypoint of Extended SAL, and calls an Extended SAL Class service
- that was previously registered with RegisterEsalClass() through this entrypoint.
-
- @param ClassGuidLo GUID of function, lower 64-bits
- @param ClassGuidHi GUID of function, upper 64-bits
- @param FunctionId Function in ClassGuid to call
- @param Arg2 Argument 2 ClassGuid/FunctionId defined
- @param Arg3 Argument 3 ClassGuid/FunctionId defined
- @param Arg4 Argument 4 ClassGuid/FunctionId defined
- @param Arg5 Argument 5 ClassGuid/FunctionId defined
- @param Arg6 Argument 6 ClassGuid/FunctionId defined
- @param Arg7 Argument 7 ClassGuid/FunctionId defined
- @param Arg8 Argument 8 ClassGuid/FunctionId defined
-
- @retval EFI_SAL_SUCCESS ESAL procedure successfully called.
- @retval EFI_SAL_ERROR The address of ExtendedSalProc() can not be correctly
- initialized.
- @retval Other Status returned from ExtendedSalProc() service of
- EXTENDED_SAL_BOOT_SERVICE_PROTOCOL.
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-EsalCall (
- IN UINT64 ClassGuidLo,
- IN UINT64 ClassGuidHi,
- IN UINT64 FunctionId,
- IN UINT64 Arg2,
- IN UINT64 Arg3,
- IN UINT64 Arg4,
- IN UINT64 Arg5,
- IN UINT64 Arg6,
- IN UINT64 Arg7,
- IN UINT64 Arg8
- )
-{
- SAL_RETURN_REGS ReturnReg;
- EXTENDED_SAL_PROC EsalProc;
-
- //
- // Get the entrypoint of Extended SAL
- //
- ReturnReg = GetEsalEntryPoint ();
- if (*(UINT64 *)ReturnReg.r9 == 0 && *(UINT64 *)(ReturnReg.r9 + 8) == 0) {
- //
- // The ESAL Entry Point could not be initialized
- //
- ReturnReg.Status = EFI_SAL_ERROR;
- return ReturnReg;
- }
-
- //
- // Test PSR.it which is BIT36
- //
- if ((ReturnReg.r11 & BIT36) != 0) {
- //
- // Virtual mode plabel to entry point
- //
- EsalProc = (EXTENDED_SAL_PROC) ReturnReg.r10;
- } else {
- //
- // Physical mode plabel to entry point
- //
- EsalProc = (EXTENDED_SAL_PROC) ReturnReg.r9;
- }
-
- return EsalProc (
- ClassGuidLo,
- ClassGuidHi,
- FunctionId,
- Arg2,
- Arg3,
- Arg4,
- Arg5,
- Arg6,
- Arg7,
- Arg8
- );
-}
-
-/**
- Wrapper for the EsalStallFunctionId service of Extended SAL Stall Services Class.
-
- This function is a wrapper for the EsalStallFunctionId service of Extended SAL
- Stall Services Class. See EsalStallFunctionId of Extended SAL Specification.
-
- @param Microseconds The number of microseconds to delay.
-
- @retval EFI_SAL_SUCCESS Call completed without error.
- @retval EFI_SAL_INVALID_ARGUMENT Invalid argument.
- @retval EFI_SAL_VIRTUAL_ADDRESS_ERROR Virtual address not registered
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-EsalStall (
- IN UINTN Microseconds
- )
-{
- return EsalCall (
- EFI_EXTENDED_SAL_STALL_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_STALL_SERVICES_PROTOCOL_GUID_HI,
- StallFunctionId,
- Microseconds,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0
- );
-}
-
-/**
- Wrapper for the EsalSetNewPalEntryFunctionId service of Extended SAL PAL Services Services Class.
-
- This function is a wrapper for the EsalSetNewPalEntryFunctionId service of Extended SAL
- PAL Services Services Class. See EsalSetNewPalEntryFunctionId of Extended SAL Specification.
-
- @param PhysicalAddress If TRUE, then PalEntryPoint is a physical address.
- If FALSE, then PalEntryPoint is a virtual address.
- @param PalEntryPoint The PAL Entry Point being set.
-
- @retval EFI_SAL_SUCCESS The PAL Entry Point was set.
- @retval EFI_SAL_VIRTUAL_ADDRESS_ERROR This function was called in virtual mode before
- virtual mappings for the specified Extended SAL
- Procedure are available.
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-EsalSetNewPalEntry (
- IN BOOLEAN PhysicalAddress,
- IN UINT64 PalEntryPoint
- )
-{
- return EsalCall (
- EFI_EXTENDED_SAL_PAL_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_PAL_SERVICES_PROTOCOL_GUID_HI,
- SetNewPalEntryFunctionId,
- PhysicalAddress,
- PalEntryPoint,
- 0,
- 0,
- 0,
- 0,
- 0
- );
-}
-
-/**
- Wrapper for the EsalGetNewPalEntryFunctionId service of Extended SAL PAL Services Services Class.
-
- This function is a wrapper for the EsalGetNewPalEntryFunctionId service of Extended SAL
- PAL Services Services Class. See EsalGetNewPalEntryFunctionId of Extended SAL Specification.
-
- @param PhysicalAddress If TRUE, then PalEntryPoint is a physical address.
- If FALSE, then PalEntryPoint is a virtual address.
-
- @retval EFI_SAL_SUCCESS The PAL Entry Point was retrieved and returned in
- SAL_RETURN_REGS.r9.
- @retval EFI_SAL_VIRTUAL_ADDRESS_ERROR This function was called in virtual mode before
- virtual mappings for the specified Extended SAL
- Procedure are available.
- @return r9 PAL entry point retrieved.
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-EsalGetNewPalEntry (
- IN BOOLEAN PhysicalAddress
- )
-{
- return EsalCall (
- EFI_EXTENDED_SAL_PAL_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_PAL_SERVICES_PROTOCOL_GUID_HI,
- GetNewPalEntryFunctionId,
- PhysicalAddress,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0
- );
-}
-
-/**
- Wrapper for the EsalGetStateBufferFunctionId service of Extended SAL MCA Log Services Class.
-
- This function is a wrapper for the EsalGetStateBufferFunctionId service of Extended SAL
- MCA Log Services Class. See EsalGetStateBufferFunctionId of Extended SAL Specification.
-
- @param McaType See type parameter of SAL Procedure SAL_GET_STATE_INFO.
- @param McaBuffer A pointer to the base address of the returned buffer.
- Copied from SAL_RETURN_REGS.r9.
- @param BufferSize A pointer to the size, in bytes, of the returned buffer.
- Copied from SAL_RETURN_REGS.r10.
-
- @retval EFI_SAL_SUCCESS The memory buffer to store error records was returned in r9 and r10.
- @retval EFI_OUT_OF_RESOURCES A memory buffer for string error records in not available
- @return r9 Base address of the returned buffer
- @return r10 Size of the returned buffer in bytes
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-EsalGetStateBuffer (
- IN UINT64 McaType,
- OUT UINT8 **McaBuffer,
- OUT UINTN *BufferSize
- )
-{
- SAL_RETURN_REGS Regs;
-
- Regs = EsalCall (
- EFI_EXTENDED_SAL_MCA_LOG_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_MCA_LOG_SERVICES_PROTOCOL_GUID_HI,
- EsalGetStateBufferFunctionId,
- McaType,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0
- );
-
- *McaBuffer = (UINT8 *) Regs.r9;
- *BufferSize = Regs.r10;
-
- return Regs;
-}
-
-/**
- Wrapper for the EsalSaveStateBufferFunctionId service of Extended SAL MCA Log Services Class.
-
- This function is a wrapper for the EsalSaveStateBufferFunctionId service of Extended SAL
- MCA Log Services Class. See EsalSaveStateBufferFunctionId of Extended SAL Specification.
-
- @param McaType See type parameter of SAL Procedure SAL_GET_STATE_INFO.
-
- @retval EFI_SUCCESS The memory buffer containing the error record was written to nonvolatile storage.
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-EsalSaveStateBuffer (
- IN UINT64 McaType
- )
-{
- return EsalCall (
- EFI_EXTENDED_SAL_MCA_LOG_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_MCA_LOG_SERVICES_PROTOCOL_GUID_HI,
- EsalSaveStateBufferFunctionId,
- McaType,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0
- );
-}
-
-/**
- Wrapper for the EsalGetVectorsFunctionId service of Extended SAL Base Services Class.
-
- This function is a wrapper for the EsalGetVectorsFunctionId service of Extended SAL
- Base Services Class. See EsalGetVectorsFunctionId of Extended SAL Specification.
-
- @param VectorType The vector type to retrieve.
- 0 - MCA, 1 - BSP INIT, 2 - BOOT_RENDEZ, 3 - AP INIT.
-
- @retval EFI_SAL_SUCCESS Call completed without error.
- @retval EFI_SAL_INVALID_ARGUMENT Invalid argument.
- @retval EFI_SAL_NO_INFORMATION The requested vector has not been registered
- with the SAL Procedure SAL_SET_VECTORS.
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-EsalGetVectors (
- IN UINT64 VectorType
- )
-{
- return EsalCall (
- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_HI,
- EsalGetVectorsFunctionId,
- VectorType,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0
- );
-}
-
-/**
- Wrapper for the EsalMcGetParamsFunctionId service of Extended SAL Base Services Class.
-
- This function is a wrapper for the EsalMcGetParamsFunctionId service of Extended SAL
- Base Services Class. See EsalMcGetParamsFunctionId of Extended SAL Specification.
-
- @param ParamInfoType The parameter type to retrieve.
- 1 - rendezvous interrupt
- 2 - wake up
- 3 - Corrected Platform Error Vector.
-
- @retval EFI_SAL_SUCCESS Call completed without error.
- @retval EFI_SAL_INVALID_ARGUMENT Invalid argument.
- @retval EFI_SAL_NO_INFORMATION The requested vector has not been registered
- with the SAL Procedure SAL_MC_SET_PARAMS.
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-EsalMcGetParams (
- IN UINT64 ParamInfoType
- )
-{
- return EsalCall (
- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_HI,
- EsalMcGetParamsFunctionId,
- ParamInfoType,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0
- );
-}
-
-/**
- Wrapper for the EsalMcGetParamsFunctionId service of Extended SAL Base Services Class.
-
- This function is a wrapper for the EsalMcGetParamsFunctionId service of Extended SAL
- Base Services Class. See EsalMcGetParamsFunctionId of Extended SAL Specification.
-
- @retval EFI_SAL_SUCCESS Call completed without error.
- @retval EFI_SAL_NO_INFORMATION The requested vector has not been registered
- with the SAL Procedure SAL_MC_SET_PARAMS.
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-EsalMcGetMcParams (
- VOID
- )
-{
- return EsalCall (
- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_HI,
- EsalMcGetMcParamsFunctionId,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0
- );
-}
-
-/**
- Wrapper for the EsalGetMcCheckinFlagsFunctionId service of Extended SAL Base Services Class.
-
- This function is a wrapper for the EsalGetMcCheckinFlagsFunctionId service of Extended SAL
- Base Services Class. See EsalGetMcCheckinFlagsFunctionId of Extended SAL Specification.
-
- @param CpuIndex The index of the CPU of set of enabled CPUs to check.
-
- @retval EFI_SAL_SUCCESS The checkin status of the requested CPU was returned.
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-EsalGetMcCheckinFlags (
- IN UINT64 CpuIndex
- )
-{
- return EsalCall (
- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_HI,
- EsalGetMcCheckinFlagsFunctionId,
- CpuIndex,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0
- );
-}
-
-/**
- Wrapper for the EsalAddCpuDataFunctionId service of Extended SAL MP Services Class.
-
- This function is a wrapper for the EsalAddCpuDataFunctionId service of Extended SAL
- MP Services Class. See EsalAddCpuDataFunctionId of Extended SAL Specification.
-
- @param CpuGlobalId The Global ID for the CPU being added.
- @param Enabled The enable flag for the CPU being added.
- TRUE means the CPU is enabled.
- FALSE means the CPU is disabled.
- @param PalCompatibility The PAL Compatibility value for the CPU being added.
-
- @retval EFI_SAL_SUCCESS The CPU was added to the database.
- @retval EFI_SAL_NOT_ENOUGH_SCRATCH There are not enough resource available to add the CPU.
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-EsalAddCpuData (
- IN UINT64 CpuGlobalId,
- IN BOOLEAN Enabled,
- IN UINT64 PalCompatibility
- )
-{
- return EsalCall (
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_HI,
- AddCpuDataFunctionId,
- CpuGlobalId,
- Enabled,
- PalCompatibility,
- 0,
- 0,
- 0,
- 0
- );
-}
-
-/**
- Wrapper for the EsalRemoveCpuDataFunctionId service of Extended SAL MP Services Class.
-
- This function is a wrapper for the EsalRemoveCpuDataFunctionId service of Extended SAL
- MP Services Class. See EsalRemoveCpuDataFunctionId of Extended SAL Specification.
-
- @param CpuGlobalId The Global ID for the CPU being removed.
-
- @retval EFI_SAL_SUCCESS The CPU was removed from the database.
- @retval EFI_SAL_NO_INFORMATION The specified CPU is not in the database.
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-EsalRemoveCpuData (
- IN UINT64 CpuGlobalId
- )
-{
- return EsalCall (
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_HI,
- RemoveCpuDataFunctionId,
- CpuGlobalId,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0
- );
-}
-
-/**
- Wrapper for the EsalModifyCpuDataFunctionId service of Extended SAL MP Services Class.
-
- This function is a wrapper for the EsalModifyCpuDataFunctionId service of Extended SAL
- MP Services Class. See EsalModifyCpuDataFunctionId of Extended SAL Specification.
-
- @param CpuGlobalId The Global ID for the CPU being modified.
- @param Enabled The enable flag for the CPU being modified.
- TRUE means the CPU is enabled.
- FALSE means the CPU is disabled.
- @param PalCompatibility The PAL Compatibility value for the CPU being modified.
-
- @retval EFI_SAL_SUCCESS The CPU database was updated.
- @retval EFI_SAL_NO_INFORMATION The specified CPU is not in the database.
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-EsalModifyCpuData (
- IN UINT64 CpuGlobalId,
- IN BOOLEAN Enabled,
- IN UINT64 PalCompatibility
- )
-{
- return EsalCall (
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_HI,
- ModifyCpuDataFunctionId,
- CpuGlobalId,
- Enabled,
- PalCompatibility,
- 0,
- 0,
- 0,
- 0
- );
-}
-
-/**
- Wrapper for the EsalGetCpuDataByIdFunctionId service of Extended SAL MP Services Class.
-
- This function is a wrapper for the EsalGetCpuDataByIdFunctionId service of Extended SAL
- MP Services Class. See EsalGetCpuDataByIdFunctionId of Extended SAL Specification.
-
- @param CpuGlobalId The Global ID for the CPU being looked up.
- @param IndexByEnabledCpu If TRUE, then the index of set of enabled CPUs of database is returned.
- If FALSE, then the index of set of all CPUs of database is returned.
-
- @retval EFI_SAL_SUCCESS The information on the specified CPU was returned.
- @retval EFI_SAL_NO_INFORMATION The specified CPU is not in the database.
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-EsalGetCpuDataById (
- IN UINT64 CpuGlobalId,
- IN BOOLEAN IndexByEnabledCpu
- )
-{
- return EsalCall (
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_HI,
- GetCpuDataByIDFunctionId,
- CpuGlobalId,
- IndexByEnabledCpu,
- 0,
- 0,
- 0,
- 0,
- 0
- );
-}
-
-/**
- Wrapper for the EsalGetCpuDataByIndexFunctionId service of Extended SAL MP Services Class.
-
- This function is a wrapper for the EsalGetCpuDataByIndexFunctionId service of Extended SAL
- MP Services Class. See EsalGetCpuDataByIndexFunctionId of Extended SAL Specification.
-
- @param Index The Global ID for the CPU being modified.
- @param IndexByEnabledCpu If TRUE, then the index of set of enabled CPUs of database is returned.
- If FALSE, then the index of set of all CPUs of database is returned.
-
- @retval EFI_SAL_SUCCESS The information on the specified CPU was returned.
- @retval EFI_SAL_NO_INFORMATION The specified CPU is not in the database.
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-EsalGetCpuDataByIndex (
- IN UINT64 Index,
- IN BOOLEAN IndexByEnabledCpu
- )
-{
- return EsalCall (
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_HI,
- GetCpuDataByIndexFunctionId,
- Index,
- IndexByEnabledCpu,
- 0,
- 0,
- 0,
- 0,
- 0
- );
-}
-
-/**
- Wrapper for the EsalWhoAmIFunctionId service of Extended SAL MP Services Class.
-
- This function is a wrapper for the EsalWhoAmIFunctionId service of Extended SAL
- MP Services Class. See EsalWhoAmIFunctionId of Extended SAL Specification.
-
- @param IndexByEnabledCpu If TRUE, then the index of set of enabled CPUs of database is returned.
- If FALSE, then the index of set of all CPUs of database is returned.
-
- @retval EFI_SAL_SUCCESS The Global ID for the calling CPU was returned.
- @retval EFI_SAL_NO_INFORMATION The calling CPU is not in the database.
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-EsalWhoAmI (
- IN BOOLEAN IndexByEnabledCpu
- )
-{
- return EsalCall (
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_HI,
- CurrentProcInfoFunctionId,
- IndexByEnabledCpu,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0
- );
-}
-
-/**
- Wrapper for the EsalNumProcessors service of Extended SAL MP Services Class.
-
- This function is a wrapper for the EsalNumProcessors service of Extended SAL
- MP Services Class. See EsalNumProcessors of Extended SAL Specification.
-
- @retval EFI_SAL_SUCCESS The information on the number of CPUs in the platform
- was returned.
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-EsalNumProcessors (
- VOID
- )
-{
- return EsalCall (
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_HI,
- NumProcessorsFunctionId,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0
- );
-}
-
-/**
- Wrapper for the EsalSetMinStateFnctionId service of Extended SAL MP Services Class.
-
- This function is a wrapper for the EsalSetMinStateFnctionId service of Extended SAL
- MP Services Class. See EsalSetMinStateFnctionId of Extended SAL Specification.
-
- @param CpuGlobalId The Global ID for the CPU whose MINSTATE pointer is being set.
- @param MinStatePointer The physical address of the MINSTATE buffer for the CPU
- specified by CpuGlobalId.
-
- @retval EFI_SAL_SUCCESS The MINSTATE pointer was set for the specified CPU.
- @retval EFI_SAL_NO_INFORMATION The specified CPU is not in the database.
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-EsalSetMinState (
- IN UINT64 CpuGlobalId,
- IN EFI_PHYSICAL_ADDRESS MinStatePointer
- )
-{
- return EsalCall (
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_HI,
- SetMinStateFunctionId,
- CpuGlobalId,
- MinStatePointer,
- 0,
- 0,
- 0,
- 0,
- 0
- );
-}
-
-/**
- Wrapper for the EsalGetMinStateFunctionId service of Extended SAL MP Services Class.
-
- This function is a wrapper for the EsalGetMinStateFunctionId service of Extended SAL
- MP Services Class. See EsalGetMinStateFunctionId of Extended SAL Specification.
-
- @param CpuGlobalId The Global ID for the CPU whose MINSTATE pointer is being retrieved.
-
- @retval EFI_SAL_SUCCESS The MINSTATE pointer for the specified CPU was retrieved.
- @retval EFI_SAL_NO_INFORMATION The specified CPU is not in the database.
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-EsalGetMinState (
- IN UINT64 CpuGlobalId
- )
-{
- return EsalCall (
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_HI,
- GetMinStateFunctionId,
- CpuGlobalId,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0
- );
-}
-
-/**
- Wrapper for the EsalMcsGetStateInfoFunctionId service of Extended SAL MCA Services Class.
-
- This function is a wrapper for the EsalMcsGetStateInfoFunctionId service of Extended SAL
- MCA Services Class. See EsalMcsGetStateInfoFunctionId of Extended SAL Specification.
-
- @param CpuGlobalId The Global ID for the CPU whose MCA state buffer is being retrieved.
- @param StateBufferPointer A pointer to the returned MCA state buffer.
- @param RequiredStateBufferSize A pointer to the size, in bytes, of the returned MCA state buffer.
-
- @retval EFI_SUCCESS MINSTATE successfully got and size calculated.
- @retval EFI_SAL_NO_INFORMATION Fail to get MINSTATE.
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-EsalMcaGetStateInfo (
- IN UINT64 CpuGlobalId,
- OUT EFI_PHYSICAL_ADDRESS *StateBufferPointer,
- OUT UINT64 *RequiredStateBufferSize
- )
-{
- SAL_RETURN_REGS Regs;
-
- Regs = EsalCall (
- EFI_EXTENDED_SAL_MCA_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_MCA_SERVICES_PROTOCOL_GUID_HI,
- McaGetStateInfoFunctionId,
- CpuGlobalId,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0
- );
-
- *StateBufferPointer = (EFI_PHYSICAL_ADDRESS) Regs.r9;
- *RequiredStateBufferSize = (UINT64) Regs.r10;
-
- return Regs;
-}
-
-/**
- Wrapper for the EsalMcaRegisterCpuFunctionId service of Extended SAL MCA Services Class.
-
- This function is a wrapper for the EsalMcaRegisterCpuFunctionId service of Extended SAL
- MCA Services Class. See EsalMcaRegisterCpuFunctionId of Extended SAL Specification.
-
- @param CpuGlobalId The Global ID for the CPU whose MCA state buffer is being set.
- @param StateBufferPointer A pointer to the MCA state buffer.
-
- @retval EFI_SAL_NO_INFORMATION Cannot get the processor info with the CpuId
- @retval EFI_SUCCESS Save the processor's state info successfully
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-EsalMcaRegisterCpu (
- IN UINT64 CpuGlobalId,
- IN EFI_PHYSICAL_ADDRESS StateBufferPointer
- )
-{
- return EsalCall (
- EFI_EXTENDED_SAL_MCA_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_MCA_SERVICES_PROTOCOL_GUID_HI,
- McaRegisterCpuFunctionId,
- CpuGlobalId,
- StateBufferPointer,
- 0,
- 0,
- 0,
- 0,
- 0
- );
-}
diff --git a/MdePkg/Library/DxeExtendedSalLib/Ipf/AsmExtendedSalLib.s b/MdePkg/Library/DxeExtendedSalLib/Ipf/AsmExtendedSalLib.s
deleted file mode 100644
index f1c4366f1b..0000000000
--- a/MdePkg/Library/DxeExtendedSalLib/Ipf/AsmExtendedSalLib.s
+++ /dev/null
@@ -1,97 +0,0 @@
-/// @file
-/// Assembly procedures to get and set ESAL entry point.
-///
-/// Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
-/// This program and the accompanying materials
-/// are licensed and made available under the terms and conditions of the BSD License
-/// which accompanies this distribution. The full text of the license may be found at
-/// http://opensource.org/licenses/bsd-license.php.
-///
-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-///
-
-.auto
-.text
-
-#include "IpfMacro.i"
-
-//
-// Exports
-//
-ASM_GLOBAL GetEsalEntryPoint
-
-//-----------------------------------------------------------------------------
-//++
-// GetEsalEntryPoint
-//
-// Return Esal global and PSR register.
-//
-// On Entry :
-//
-//
-// Return Value:
-// r8 = EFI_SAL_SUCCESS
-// r9 = Physical Plabel
-// r10 = Virtual Plabel
-// r11 = psr
-//
-// As per static calling conventions.
-//
-//--
-//---------------------------------------------------------------------------
-PROCEDURE_ENTRY (GetEsalEntryPoint)
-
- NESTED_SETUP (0,8,0,0)
-
-EsalCalcStart:
- mov r8 = ip;;
- add r8 = (EsalEntryPoint - EsalCalcStart), r8;;
- mov r9 = r8;;
- add r10 = 0x10, r8;;
- mov r11 = psr;;
- mov r8 = r0;;
-
- NESTED_RETURN
-
-PROCEDURE_EXIT (GetEsalEntryPoint)
-
-//-----------------------------------------------------------------------------
-//++
-// SetEsalPhysicalEntryPoint
-//
-// Set the dispatcher entry point
-//
-// On Entry:
-// in0 = Physical address of Esal Dispatcher
-// in1 = Physical GP
-//
-// Return Value:
-// r8 = EFI_SAL_SUCCESS
-//
-// As per static calling conventions.
-//
-//--
-//---------------------------------------------------------------------------
-PROCEDURE_ENTRY (SetEsalPhysicalEntryPoint)
-
- NESTED_SETUP (2,8,0,0)
-
-EsalCalcStart1:
- mov r8 = ip;;
- add r8 = (EsalEntryPoint - EsalCalcStart1), r8;;
- st8 [r8] = in0;;
- add r8 = 0x08, r8;;
- st8 [r8] = in1;;
- mov r8 = r0;;
-
- NESTED_RETURN
-
-PROCEDURE_EXIT (SetEsalPhysicalEntryPoint)
-
-.align 32
-EsalEntryPoint:
- data8 0 // Physical Entry
- data8 0 // GP
- data8 0 // Virtual Entry
- data8 0 // GP
diff --git a/MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf b/MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
index c66a26b168..b46764197b 100644
--- a/MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
+++ b/MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
@@ -22,14 +22,14 @@
FILE_GUID = f773469b-e265-4b0c-b0a6-2f971fbfe72b
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
- LIBRARY_CLASS = ExtractGuidedSectionLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER
+ LIBRARY_CLASS = ExtractGuidedSectionLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER
CONSTRUCTOR = DxeExtractGuidedSectionLibConstructor
#
# The following information is for reference only and not required by the build tools.
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]
diff --git a/MdePkg/Library/DxeHobLib/DxeHobLib.inf b/MdePkg/Library/DxeHobLib/DxeHobLib.inf
index 32cd5546ab..329aec24a3 100644
--- a/MdePkg/Library/DxeHobLib/DxeHobLib.inf
+++ b/MdePkg/Library/DxeHobLib/DxeHobLib.inf
@@ -23,11 +23,11 @@
FILE_GUID = f12b59c9-76d0-4661-ad7c-f04d1bef0558
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
- LIBRARY_CLASS = HobLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER SMM_CORE DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER
+ LIBRARY_CLASS = HobLib|DXE_DRIVER DXE_RUNTIME_DRIVER SMM_CORE DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER
CONSTRUCTOR = HobLibConstructor
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]
diff --git a/MdePkg/Library/DxeHstiLib/DxeHstiLib.inf b/MdePkg/Library/DxeHstiLib/DxeHstiLib.inf
index a694c2c8ae..44039d116d 100644
--- a/MdePkg/Library/DxeHstiLib/DxeHstiLib.inf
+++ b/MdePkg/Library/DxeHstiLib/DxeHstiLib.inf
@@ -19,7 +19,7 @@
FILE_GUID = 7DE1C620-F587-4116-A36D-40F3467B9A0C
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
- LIBRARY_CLASS = HstiLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER
+ LIBRARY_CLASS = HstiLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER
[Sources]
HstiAip.c
diff --git a/MdePkg/Library/DxeIoLibCpuIo2/DxeIoLibCpuIo2.inf b/MdePkg/Library/DxeIoLibCpuIo2/DxeIoLibCpuIo2.inf
index 65031d0bd3..585d1cdda2 100644
--- a/MdePkg/Library/DxeIoLibCpuIo2/DxeIoLibCpuIo2.inf
+++ b/MdePkg/Library/DxeIoLibCpuIo2/DxeIoLibCpuIo2.inf
@@ -22,13 +22,13 @@
FILE_GUID = 33D33BF3-349E-4768-9459-836A9F7558FB
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
- LIBRARY_CLASS = IoLib|DXE_DRIVER DXE_SAL_DRIVER
+ LIBRARY_CLASS = IoLib|DXE_DRIVER
CONSTRUCTOR = IoLibConstructor
#
# The following information is for reference only and not required by the build tools.
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]
diff --git a/MdePkg/Library/DxeIoLibEsal/DxeIoLibEsal.inf b/MdePkg/Library/DxeIoLibEsal/DxeIoLibEsal.inf
deleted file mode 100644
index fdfc12b945..0000000000
--- a/MdePkg/Library/DxeIoLibEsal/DxeIoLibEsal.inf
+++ /dev/null
@@ -1,49 +0,0 @@
-## @file
-# I/O Library instance that layers on top of Itanium ESAL services.
-#
-# I/O Library implementation that uses Itanium ESAL services for I/O
-# and MMIO operations.
-#
-# Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
-# This program and the accompanying materials are licensed and made available
-# under the terms and conditions of the BSD License which accompanies this
-# distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php.
-#
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-##
-
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = DxeIoLibEsal
- MODULE_UNI_FILE = DxeIoLibEsal.uni
- FILE_GUID = 0D8E6E4E-B029-475f-9122-60A3FEDBA8C0
- MODULE_TYPE = DXE_DRIVER
- VERSION_STRING = 1.0
- LIBRARY_CLASS = IoLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER
-
-#
-# The following information is for reference only and not required by the build tools.
-#
-# VALID_ARCHITECTURES = IPF
-#
-
-[Sources]
- IoHighLevel.c
- IoLib.c
- IoLibMmioBuffer.c
- DxeIoLibEsalInternal.h
-
-[Packages]
- MdePkg/MdePkg.dec
-
-[LibraryClasses]
- ExtendedSalLib
- BaseLib
- DebugLib
-
-[Depex]
- gEfiExtendedSalBaseIoServicesProtocolGuid
-
diff --git a/MdePkg/Library/DxeIoLibEsal/DxeIoLibEsalInternal.h b/MdePkg/Library/DxeIoLibEsal/DxeIoLibEsalInternal.h
deleted file mode 100644
index c6dd4af543..0000000000
--- a/MdePkg/Library/DxeIoLibEsal/DxeIoLibEsalInternal.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/** @file
- Internal include file for the I/O Library using ESAL services.
-
- Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials are licensed and made available
- under the terms and conditions of the BSD License which accompanies this
- distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php.
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#ifndef __DXE_IO_LIB_ESAL_INTERNAL_H_
-#define __DXE_IO_LIB_ESAL_INTERNAL_H_
-
-#include <PiDxe.h>
-
-#include <Protocol/CpuIo2.h>
-#include <Protocol/ExtendedSalServiceClasses.h>
-
-#include <Library/IoLib.h>
-#include <Library/DebugLib.h>
-#include <Library/BaseLib.h>
-#include <Library/ExtendedSalLib.h>
-
-#endif
diff --git a/MdePkg/Library/DxeIoLibEsal/IoHighLevel.c b/MdePkg/Library/DxeIoLibEsal/IoHighLevel.c
deleted file mode 100644
index 7b602192a4..0000000000
--- a/MdePkg/Library/DxeIoLibEsal/IoHighLevel.c
+++ /dev/null
@@ -1,2303 +0,0 @@
-/** @file
- High-level Io/Mmio functions.
-
- Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php.
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include "DxeIoLibEsalInternal.h"
-
-/**
- Reads an 8-bit I/O port, performs a bitwise OR, and writes the
- result back to the 8-bit I/O port.
-
- Reads the 8-bit I/O port specified by Port, performs a bitwise OR
- between the read result and the value specified by OrData, and writes the
- result to the 8-bit I/O port specified by Port. The value written to the I/O
- port is returned. This function must guarantee that all I/O read and write
- operations are serialized.
-
- If 8-bit I/O port operations are not supported, then ASSERT().
-
- @param Port The I/O port to write.
- @param OrData The value to OR with the value read from the I/O port.
-
- @return The value written back to the I/O port.
-
-**/
-UINT8
-EFIAPI
-IoOr8 (
- IN UINTN Port,
- IN UINT8 OrData
- )
-{
- return IoWrite8 (Port, (UINT8)(IoRead8 (Port) | OrData));
-}
-
-/**
- Reads an 8-bit I/O port, performs a bitwise AND, and writes the result back
- to the 8-bit I/O port.
-
- Reads the 8-bit I/O port specified by Port, performs a bitwise AND between
- the read result and the value specified by AndData, and writes the result to
- the 8-bit I/O port specified by Port. The value written to the I/O port is
- returned. This function must guarantee that all I/O read and write operations
- are serialized.
-
- If 8-bit I/O port operations are not supported, then ASSERT().
-
- @param Port The I/O port to write.
- @param AndData The value to AND with the value read from the I/O port.
-
- @return The value written back to the I/O port.
-
-**/
-UINT8
-EFIAPI
-IoAnd8 (
- IN UINTN Port,
- IN UINT8 AndData
- )
-{
- return IoWrite8 (Port, (UINT8)(IoRead8 (Port) & AndData));
-}
-
-/**
- Reads an 8-bit I/O port, performs a bitwise AND followed by a bitwise
- inclusive OR, and writes the result back to the 8-bit I/O port.
-
- Reads the 8-bit I/O port specified by Port, performs a bitwise AND between
- the read result and the value specified by AndData, performs a bitwise OR
- between the result of the AND operation and the value specified by OrData,
- and writes the result to the 8-bit I/O port specified by Port. The value
- written to the I/O port is returned. This function must guarantee that all
- I/O read and write operations are serialized.
-
- If 8-bit I/O port operations are not supported, then ASSERT().
-
- @param Port The I/O port to write.
- @param AndData The value to AND with the value read from the I/O port.
- @param OrData The value to OR with the result of the AND operation.
-
- @return The value written back to the I/O port.
-
-**/
-UINT8
-EFIAPI
-IoAndThenOr8 (
- IN UINTN Port,
- IN UINT8 AndData,
- IN UINT8 OrData
- )
-{
- return IoWrite8 (Port, (UINT8)((IoRead8 (Port) & AndData) | OrData));
-}
-
-/**
- Reads a bit field of an I/O register.
-
- Reads the bit field in an 8-bit I/O register. The bit field is specified by
- the StartBit and the EndBit. The value of the bit field is returned.
-
- If 8-bit I/O port operations are not supported, then ASSERT().
- If StartBit is greater than 7, then ASSERT().
- If EndBit is greater than 7, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
-
- @param Port The I/O port to read.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..7.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..7.
-
- @return The value read.
-
-**/
-UINT8
-EFIAPI
-IoBitFieldRead8 (
- IN UINTN Port,
- IN UINTN StartBit,
- IN UINTN EndBit
- )
-{
- return BitFieldRead8 (IoRead8 (Port), StartBit, EndBit);
-}
-
-/**
- Writes a bit field to an I/O register.
-
- Writes Value to the bit field of the I/O register. The bit field is specified
- by the StartBit and the EndBit. All other bits in the destination I/O
- register are preserved. The value written to the I/O port is returned. Extra
- left bits in Value are stripped.
-
- If 8-bit I/O port operations are not supported, then ASSERT().
- If StartBit is greater than 7, then ASSERT().
- If EndBit is greater than 7, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Port The I/O port to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..7.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..7.
- @param Value New value of the bit field.
-
- @return The value written back to the I/O port.
-
-**/
-UINT8
-EFIAPI
-IoBitFieldWrite8 (
- IN UINTN Port,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 Value
- )
-{
- return IoWrite8 (
- Port,
- BitFieldWrite8 (IoRead8 (Port), StartBit, EndBit, Value)
- );
-}
-
-/**
- Reads a bit field in an 8-bit port, performs a bitwise OR, and writes the
- result back to the bit field in the 8-bit port.
-
- Reads the 8-bit I/O port specified by Port, performs a bitwise OR
- between the read result and the value specified by OrData, and writes the
- result to the 8-bit I/O port specified by Port. The value written to the I/O
- port is returned. This function must guarantee that all I/O read and write
- operations are serialized. Extra left bits in OrData are stripped.
-
- If 8-bit I/O port operations are not supported, then ASSERT().
- If StartBit is greater than 7, then ASSERT().
- If EndBit is greater than 7, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Port The I/O port to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..7.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..7.
- @param OrData The value to OR with the value read from the I/O port.
-
- @return The value written back to the I/O port.
-
-**/
-UINT8
-EFIAPI
-IoBitFieldOr8 (
- IN UINTN Port,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 OrData
- )
-{
- return IoWrite8 (
- Port,
- BitFieldOr8 (IoRead8 (Port), StartBit, EndBit, OrData)
- );
-}
-
-/**
- Reads a bit field in an 8-bit port, performs a bitwise AND, and writes the
- result back to the bit field in the 8-bit port.
-
- Reads the 8-bit I/O port specified by Port, performs a bitwise AND between
- the read result and the value specified by AndData, and writes the result to
- the 8-bit I/O port specified by Port. The value written to the I/O port is
- returned. This function must guarantee that all I/O read and write operations
- are serialized. Extra left bits in AndData are stripped.
-
- If 8-bit I/O port operations are not supported, then ASSERT().
- If StartBit is greater than 7, then ASSERT().
- If EndBit is greater than 7, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Port The I/O port to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..7.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..7.
- @param AndData The value to AND with the value read from the I/O port.
-
- @return The value written back to the I/O port.
-
-**/
-UINT8
-EFIAPI
-IoBitFieldAnd8 (
- IN UINTN Port,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 AndData
- )
-{
- return IoWrite8 (
- Port,
- BitFieldAnd8 (IoRead8 (Port), StartBit, EndBit, AndData)
- );
-}
-
-/**
- Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
- bitwise OR, and writes the result back to the bit field in the
- 8-bit port.
-
- Reads the 8-bit I/O port specified by Port, performs a bitwise AND followed
- by a bitwise OR between the read result and the value specified by
- AndData, and writes the result to the 8-bit I/O port specified by Port. The
- value written to the I/O port is returned. This function must guarantee that
- all I/O read and write operations are serialized. Extra left bits in both
- AndData and OrData are stripped.
-
- If 8-bit I/O port operations are not supported, then ASSERT().
- If StartBit is greater than 7, then ASSERT().
- If EndBit is greater than 7, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Port The I/O port to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..7.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..7.
- @param AndData The value to AND with the value read from the I/O port.
- @param OrData The value to OR with the result of the AND operation.
-
- @return The value written back to the I/O port.
-
-**/
-UINT8
-EFIAPI
-IoBitFieldAndThenOr8 (
- IN UINTN Port,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 AndData,
- IN UINT8 OrData
- )
-{
- return IoWrite8 (
- Port,
- BitFieldAndThenOr8 (IoRead8 (Port), StartBit, EndBit, AndData, OrData)
- );
-}
-
-/**
- Reads a 16-bit I/O port, performs a bitwise OR, and writes the
- result back to the 16-bit I/O port.
-
- Reads the 16-bit I/O port specified by Port, performs a bitwise OR
- between the read result and the value specified by OrData, and writes the
- result to the 16-bit I/O port specified by Port. The value written to the I/O
- port is returned. This function must guarantee that all I/O read and write
- operations are serialized.
-
- If 16-bit I/O port operations are not supported, then ASSERT().
-
- @param Port The I/O port to write.
- @param OrData The value to OR with the value read from the I/O port.
-
- @return The value written back to the I/O port.
-
-**/
-UINT16
-EFIAPI
-IoOr16 (
- IN UINTN Port,
- IN UINT16 OrData
- )
-{
- return IoWrite16 (Port, (UINT16)(IoRead16 (Port) | OrData));
-}
-
-/**
- Reads a 16-bit I/O port, performs a bitwise AND, and writes the result back
- to the 16-bit I/O port.
-
- Reads the 16-bit I/O port specified by Port, performs a bitwise AND between
- the read result and the value specified by AndData, and writes the result to
- the 16-bit I/O port specified by Port. The value written to the I/O port is
- returned. This function must guarantee that all I/O read and write operations
- are serialized.
-
- If 16-bit I/O port operations are not supported, then ASSERT().
-
- @param Port The I/O port to write.
- @param AndData The value to AND with the value read from the I/O port.
-
- @return The value written back to the I/O port.
-
-**/
-UINT16
-EFIAPI
-IoAnd16 (
- IN UINTN Port,
- IN UINT16 AndData
- )
-{
- return IoWrite16 (Port, (UINT16)(IoRead16 (Port) & AndData));
-}
-
-/**
- Reads a 16-bit I/O port, performs a bitwise AND followed by a bitwise
- inclusive OR, and writes the result back to the 16-bit I/O port.
-
- Reads the 16-bit I/O port specified by Port, performs a bitwise AND between
- the read result and the value specified by AndData, performs a bitwise OR
- between the result of the AND operation and the value specified by OrData,
- and writes the result to the 16-bit I/O port specified by Port. The value
- written to the I/O port is returned. This function must guarantee that all
- I/O read and write operations are serialized.
-
- If 16-bit I/O port operations are not supported, then ASSERT().
-
- @param Port The I/O port to write.
- @param AndData The value to AND with the value read from the I/O port.
- @param OrData The value to OR with the result of the AND operation.
-
- @return The value written back to the I/O port.
-
-**/
-UINT16
-EFIAPI
-IoAndThenOr16 (
- IN UINTN Port,
- IN UINT16 AndData,
- IN UINT16 OrData
- )
-{
- return IoWrite16 (Port, (UINT16)((IoRead16 (Port) & AndData) | OrData));
-}
-
-/**
- Reads a bit field of an I/O register.
-
- Reads the bit field in a 16-bit I/O register. The bit field is specified by
- the StartBit and the EndBit. The value of the bit field is returned.
-
- If 16-bit I/O port operations are not supported, then ASSERT().
- If StartBit is greater than 15, then ASSERT().
- If EndBit is greater than 15, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
-
- @param Port The I/O port to read.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..15.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..15.
-
- @return The value read.
-
-**/
-UINT16
-EFIAPI
-IoBitFieldRead16 (
- IN UINTN Port,
- IN UINTN StartBit,
- IN UINTN EndBit
- )
-{
- return BitFieldRead16 (IoRead16 (Port), StartBit, EndBit);
-}
-
-/**
- Writes a bit field to an I/O register.
-
- Writes Value to the bit field of the I/O register. The bit field is specified
- by the StartBit and the EndBit. All other bits in the destination I/O
- register are preserved. The value written to the I/O port is returned. Extra
- left bits in Value are stripped.
-
- If 16-bit I/O port operations are not supported, then ASSERT().
- If StartBit is greater than 15, then ASSERT().
- If EndBit is greater than 15, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Port The I/O port to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..15.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..15.
- @param Value New value of the bit field.
-
- @return The value written back to the I/O port.
-
-**/
-UINT16
-EFIAPI
-IoBitFieldWrite16 (
- IN UINTN Port,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 Value
- )
-{
- return IoWrite16 (
- Port,
- BitFieldWrite16 (IoRead16 (Port), StartBit, EndBit, Value)
- );
-}
-
-/**
- Reads a bit field in a 16-bit port, performs a bitwise OR, and writes the
- result back to the bit field in the 16-bit port.
-
- Reads the 16-bit I/O port specified by Port, performs a bitwise OR
- between the read result and the value specified by OrData, and writes the
- result to the 16-bit I/O port specified by Port. The value written to the I/O
- port is returned. This function must guarantee that all I/O read and write
- operations are serialized. Extra left bits in OrData are stripped.
-
- If 16-bit I/O port operations are not supported, then ASSERT().
- If StartBit is greater than 15, then ASSERT().
- If EndBit is greater than 15, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Port The I/O port to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..15.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..15.
- @param OrData The value to OR with the value read from the I/O port.
-
- @return The value written back to the I/O port.
-
-**/
-UINT16
-EFIAPI
-IoBitFieldOr16 (
- IN UINTN Port,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 OrData
- )
-{
- return IoWrite16 (
- Port,
- BitFieldOr16 (IoRead16 (Port), StartBit, EndBit, OrData)
- );
-}
-
-/**
- Reads a bit field in a 16-bit port, performs a bitwise AND, and writes the
- result back to the bit field in the 16-bit port.
-
- Reads the 16-bit I/O port specified by Port, performs a bitwise AND between
- the read result and the value specified by AndData, and writes the result to
- the 16-bit I/O port specified by Port. The value written to the I/O port is
- returned. This function must guarantee that all I/O read and write operations
- are serialized. Extra left bits in AndData are stripped.
-
- If 16-bit I/O port operations are not supported, then ASSERT().
- If StartBit is greater than 15, then ASSERT().
- If EndBit is greater than 15, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Port The I/O port to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..15.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..15.
- @param AndData The value to AND with the value read from the I/O port.
-
- @return The value written back to the I/O port.
-
-**/
-UINT16
-EFIAPI
-IoBitFieldAnd16 (
- IN UINTN Port,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 AndData
- )
-{
- return IoWrite16 (
- Port,
- BitFieldAnd16 (IoRead16 (Port), StartBit, EndBit, AndData)
- );
-}
-
-/**
- Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
- bitwise OR, and writes the result back to the bit field in the
- 16-bit port.
-
- Reads the 16-bit I/O port specified by Port, performs a bitwise AND followed
- by a bitwise OR between the read result and the value specified by
- AndData, and writes the result to the 16-bit I/O port specified by Port. The
- value written to the I/O port is returned. This function must guarantee that
- all I/O read and write operations are serialized. Extra left bits in both
- AndData and OrData are stripped.
-
- If 16-bit I/O port operations are not supported, then ASSERT().
- If StartBit is greater than 15, then ASSERT().
- If EndBit is greater than 15, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Port The I/O port to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..15.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..15.
- @param AndData The value to AND with the value read from the I/O port.
- @param OrData The value to OR with the result of the AND operation.
-
- @return The value written back to the I/O port.
-
-**/
-UINT16
-EFIAPI
-IoBitFieldAndThenOr16 (
- IN UINTN Port,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 AndData,
- IN UINT16 OrData
- )
-{
- return IoWrite16 (
- Port,
- BitFieldAndThenOr16 (IoRead16 (Port), StartBit, EndBit, AndData, OrData)
- );
-}
-
-/**
- Reads a 32-bit I/O port, performs a bitwise OR, and writes the
- result back to the 32-bit I/O port.
-
- Reads the 32-bit I/O port specified by Port, performs a bitwise OR
- between the read result and the value specified by OrData, and writes the
- result to the 32-bit I/O port specified by Port. The value written to the I/O
- port is returned. This function must guarantee that all I/O read and write
- operations are serialized.
-
- If 32-bit I/O port operations are not supported, then ASSERT().
-
- @param Port The I/O port to write.
- @param OrData The value to OR with the value read from the I/O port.
-
- @return The value written back to the I/O port.
-
-**/
-UINT32
-EFIAPI
-IoOr32 (
- IN UINTN Port,
- IN UINT32 OrData
- )
-{
- return IoWrite32 (Port, IoRead32 (Port) | OrData);
-}
-
-/**
- Reads a 32-bit I/O port, performs a bitwise AND, and writes the result back
- to the 32-bit I/O port.
-
- Reads the 32-bit I/O port specified by Port, performs a bitwise AND between
- the read result and the value specified by AndData, and writes the result to
- the 32-bit I/O port specified by Port. The value written to the I/O port is
- returned. This function must guarantee that all I/O read and write operations
- are serialized.
-
- If 32-bit I/O port operations are not supported, then ASSERT().
-
- @param Port The I/O port to write.
- @param AndData The value to AND with the value read from the I/O port.
-
- @return The value written back to the I/O port.
-
-**/
-UINT32
-EFIAPI
-IoAnd32 (
- IN UINTN Port,
- IN UINT32 AndData
- )
-{
- return IoWrite32 (Port, IoRead32 (Port) & AndData);
-}
-
-/**
- Reads a 32-bit I/O port, performs a bitwise AND followed by a bitwise
- inclusive OR, and writes the result back to the 32-bit I/O port.
-
- Reads the 32-bit I/O port specified by Port, performs a bitwise AND between
- the read result and the value specified by AndData, performs a bitwise OR
- between the result of the AND operation and the value specified by OrData,
- and writes the result to the 32-bit I/O port specified by Port. The value
- written to the I/O port is returned. This function must guarantee that all
- I/O read and write operations are serialized.
-
- If 32-bit I/O port operations are not supported, then ASSERT().
-
- @param Port The I/O port to write.
- @param AndData The value to AND with the value read from the I/O port.
- @param OrData The value to OR with the result of the AND operation.
-
- @return The value written back to the I/O port.
-
-**/
-UINT32
-EFIAPI
-IoAndThenOr32 (
- IN UINTN Port,
- IN UINT32 AndData,
- IN UINT32 OrData
- )
-{
- return IoWrite32 (Port, (IoRead32 (Port) & AndData) | OrData);
-}
-
-/**
- Reads a bit field of an I/O register.
-
- Reads the bit field in a 32-bit I/O register. The bit field is specified by
- the StartBit and the EndBit. The value of the bit field is returned.
-
- If 32-bit I/O port operations are not supported, then ASSERT().
- If StartBit is greater than 31, then ASSERT().
- If EndBit is greater than 31, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
-
- @param Port The I/O port to read.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..31.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..31.
-
- @return The value read.
-
-**/
-UINT32
-EFIAPI
-IoBitFieldRead32 (
- IN UINTN Port,
- IN UINTN StartBit,
- IN UINTN EndBit
- )
-{
- return BitFieldRead32 (IoRead32 (Port), StartBit, EndBit);
-}
-
-/**
- Writes a bit field to an I/O register.
-
- Writes Value to the bit field of the I/O register. The bit field is specified
- by the StartBit and the EndBit. All other bits in the destination I/O
- register are preserved. The value written to the I/O port is returned. Extra
- left bits in Value are stripped.
-
- If 32-bit I/O port operations are not supported, then ASSERT().
- If StartBit is greater than 31, then ASSERT().
- If EndBit is greater than 31, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Port The I/O port to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..31.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..31.
- @param Value New value of the bit field.
-
- @return The value written back to the I/O port.
-
-**/
-UINT32
-EFIAPI
-IoBitFieldWrite32 (
- IN UINTN Port,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 Value
- )
-{
- return IoWrite32 (
- Port,
- BitFieldWrite32 (IoRead32 (Port), StartBit, EndBit, Value)
- );
-}
-
-/**
- Reads a bit field in a 32-bit port, performs a bitwise OR, and writes the
- result back to the bit field in the 32-bit port.
-
- Reads the 32-bit I/O port specified by Port, performs a bitwise OR
- between the read result and the value specified by OrData, and writes the
- result to the 32-bit I/O port specified by Port. The value written to the I/O
- port is returned. This function must guarantee that all I/O read and write
- operations are serialized. Extra left bits in OrData are stripped.
-
- If 32-bit I/O port operations are not supported, then ASSERT().
- If StartBit is greater than 31, then ASSERT().
- If EndBit is greater than 31, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Port The I/O port to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..31.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..31.
- @param OrData The value to OR with the value read from the I/O port.
-
- @return The value written back to the I/O port.
-
-**/
-UINT32
-EFIAPI
-IoBitFieldOr32 (
- IN UINTN Port,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 OrData
- )
-{
- return IoWrite32 (
- Port,
- BitFieldOr32 (IoRead32 (Port), StartBit, EndBit, OrData)
- );
-}
-
-/**
- Reads a bit field in a 32-bit port, performs a bitwise AND, and writes the
- result back to the bit field in the 32-bit port.
-
- Reads the 32-bit I/O port specified by Port, performs a bitwise AND between
- the read result and the value specified by AndData, and writes the result to
- the 32-bit I/O port specified by Port. The value written to the I/O port is
- returned. This function must guarantee that all I/O read and write operations
- are serialized. Extra left bits in AndData are stripped.
-
- If 32-bit I/O port operations are not supported, then ASSERT().
- If StartBit is greater than 31, then ASSERT().
- If EndBit is greater than 31, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Port The I/O port to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..31.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..31.
- @param AndData The value to AND with the value read from the I/O port.
-
- @return The value written back to the I/O port.
-
-**/
-UINT32
-EFIAPI
-IoBitFieldAnd32 (
- IN UINTN Port,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 AndData
- )
-{
- return IoWrite32 (
- Port,
- BitFieldAnd32 (IoRead32 (Port), StartBit, EndBit, AndData)
- );
-}
-
-/**
- Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
- bitwise OR, and writes the result back to the bit field in the
- 32-bit port.
-
- Reads the 32-bit I/O port specified by Port, performs a bitwise AND followed
- by a bitwise OR between the read result and the value specified by
- AndData, and writes the result to the 32-bit I/O port specified by Port. The
- value written to the I/O port is returned. This function must guarantee that
- all I/O read and write operations are serialized. Extra left bits in both
- AndData and OrData are stripped.
-
- If 32-bit I/O port operations are not supported, then ASSERT().
- If StartBit is greater than 31, then ASSERT().
- If EndBit is greater than 31, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Port The I/O port to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..31.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..31.
- @param AndData The value to AND with the value read from the I/O port.
- @param OrData The value to OR with the result of the AND operation.
-
- @return The value written back to the I/O port.
-
-**/
-UINT32
-EFIAPI
-IoBitFieldAndThenOr32 (
- IN UINTN Port,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 AndData,
- IN UINT32 OrData
- )
-{
- return IoWrite32 (
- Port,
- BitFieldAndThenOr32 (IoRead32 (Port), StartBit, EndBit, AndData, OrData)
- );
-}
-
-/**
- Reads a 64-bit I/O port, performs a bitwise OR, and writes the
- result back to the 64-bit I/O port.
-
- Reads the 64-bit I/O port specified by Port, performs a bitwise OR
- between the read result and the value specified by OrData, and writes the
- result to the 64-bit I/O port specified by Port. The value written to the I/O
- port is returned. This function must guarantee that all I/O read and write
- operations are serialized.
-
- If 64-bit I/O port operations are not supported, then ASSERT().
-
- @param Port The I/O port to write.
- @param OrData The value to OR with the value read from the I/O port.
-
- @return The value written back to the I/O port.
-
-**/
-UINT64
-EFIAPI
-IoOr64 (
- IN UINTN Port,
- IN UINT64 OrData
- )
-{
- return IoWrite64 (Port, IoRead64 (Port) | OrData);
-}
-
-/**
- Reads a 64-bit I/O port, performs a bitwise AND, and writes the result back
- to the 64-bit I/O port.
-
- Reads the 64-bit I/O port specified by Port, performs a bitwise AND between
- the read result and the value specified by AndData, and writes the result to
- the 64-bit I/O port specified by Port. The value written to the I/O port is
- returned. This function must guarantee that all I/O read and write operations
- are serialized.
-
- If 64-bit I/O port operations are not supported, then ASSERT().
-
- @param Port The I/O port to write.
- @param AndData The value to AND with the value read from the I/O port.
-
- @return The value written back to the I/O port.
-
-**/
-UINT64
-EFIAPI
-IoAnd64 (
- IN UINTN Port,
- IN UINT64 AndData
- )
-{
- return IoWrite64 (Port, IoRead64 (Port) & AndData);
-}
-
-/**
- Reads a 64-bit I/O port, performs a bitwise AND followed by a bitwise
- inclusive OR, and writes the result back to the 64-bit I/O port.
-
- Reads the 64-bit I/O port specified by Port, performs a bitwise AND between
- the read result and the value specified by AndData, performs a bitwise OR
- between the result of the AND operation and the value specified by OrData,
- and writes the result to the 64-bit I/O port specified by Port. The value
- written to the I/O port is returned. This function must guarantee that all
- I/O read and write operations are serialized.
-
- If 64-bit I/O port operations are not supported, then ASSERT().
-
- @param Port The I/O port to write.
- @param AndData The value to AND with the value read from the I/O port.
- @param OrData The value to OR with the result of the AND operation.
-
- @return The value written back to the I/O port.
-
-**/
-UINT64
-EFIAPI
-IoAndThenOr64 (
- IN UINTN Port,
- IN UINT64 AndData,
- IN UINT64 OrData
- )
-{
- return IoWrite64 (Port, (IoRead64 (Port) & AndData) | OrData);
-}
-
-/**
- Reads a bit field of an I/O register.
-
- Reads the bit field in a 64-bit I/O register. The bit field is specified by
- the StartBit and the EndBit. The value of the bit field is returned.
-
- If 64-bit I/O port operations are not supported, then ASSERT().
- If StartBit is greater than 63, then ASSERT().
- If EndBit is greater than 63, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
-
- @param Port The I/O port to read.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..63.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..63.
-
- @return The value read.
-
-**/
-UINT64
-EFIAPI
-IoBitFieldRead64 (
- IN UINTN Port,
- IN UINTN StartBit,
- IN UINTN EndBit
- )
-{
- return BitFieldRead64 (IoRead64 (Port), StartBit, EndBit);
-}
-
-/**
- Writes a bit field to an I/O register.
-
- Writes Value to the bit field of the I/O register. The bit field is specified
- by the StartBit and the EndBit. All other bits in the destination I/O
- register are preserved. The value written to the I/O port is returned. Extra
- left bits in Value are stripped.
-
- If 64-bit I/O port operations are not supported, then ASSERT().
- If StartBit is greater than 63, then ASSERT().
- If EndBit is greater than 63, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Port The I/O port to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..63.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..63.
- @param Value New value of the bit field.
-
- @return The value written back to the I/O port.
-
-**/
-UINT64
-EFIAPI
-IoBitFieldWrite64 (
- IN UINTN Port,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT64 Value
- )
-{
- return IoWrite64 (
- Port,
- BitFieldWrite64 (IoRead64 (Port), StartBit, EndBit, Value)
- );
-}
-
-/**
- Reads a bit field in a 64-bit port, performs a bitwise OR, and writes the
- result back to the bit field in the 64-bit port.
-
- Reads the 64-bit I/O port specified by Port, performs a bitwise OR
- between the read result and the value specified by OrData, and writes the
- result to the 64-bit I/O port specified by Port. The value written to the I/O
- port is returned. This function must guarantee that all I/O read and write
- operations are serialized. Extra left bits in OrData are stripped.
-
- If 64-bit I/O port operations are not supported, then ASSERT().
- If StartBit is greater than 63, then ASSERT().
- If EndBit is greater than 63, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Port The I/O port to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..63.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..63.
- @param OrData The value to OR with the value read from the I/O port.
-
- @return The value written back to the I/O port.
-
-**/
-UINT64
-EFIAPI
-IoBitFieldOr64 (
- IN UINTN Port,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT64 OrData
- )
-{
- return IoWrite64 (
- Port,
- BitFieldOr64 (IoRead64 (Port), StartBit, EndBit, OrData)
- );
-}
-
-/**
- Reads a bit field in a 64-bit port, performs a bitwise AND, and writes the
- result back to the bit field in the 64-bit port.
-
- Reads the 64-bit I/O port specified by Port, performs a bitwise AND between
- the read result and the value specified by AndData, and writes the result to
- the 64-bit I/O port specified by Port. The value written to the I/O port is
- returned. This function must guarantee that all I/O read and write operations
- are serialized. Extra left bits in AndData are stripped.
-
- If 64-bit I/O port operations are not supported, then ASSERT().
- If StartBit is greater than 63, then ASSERT().
- If EndBit is greater than 63, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Port The I/O port to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..63.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..63.
- @param AndData The value to AND with the value read from the I/O port.
-
- @return The value written back to the I/O port.
-
-**/
-UINT64
-EFIAPI
-IoBitFieldAnd64 (
- IN UINTN Port,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT64 AndData
- )
-{
- return IoWrite64 (
- Port,
- BitFieldAnd64 (IoRead64 (Port), StartBit, EndBit, AndData)
- );
-}
-
-/**
- Reads a bit field in a 64-bit port, performs a bitwise AND followed by a
- bitwise OR, and writes the result back to the bit field in the
- 64-bit port.
-
- Reads the 64-bit I/O port specified by Port, performs a bitwise AND followed
- by a bitwise OR between the read result and the value specified by
- AndData, and writes the result to the 64-bit I/O port specified by Port. The
- value written to the I/O port is returned. This function must guarantee that
- all I/O read and write operations are serialized. Extra left bits in both
- AndData and OrData are stripped.
-
- If 64-bit I/O port operations are not supported, then ASSERT().
- If StartBit is greater than 63, then ASSERT().
- If EndBit is greater than 63, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Port The I/O port to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..63.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..63.
- @param AndData The value to AND with the value read from the I/O port.
- @param OrData The value to OR with the result of the AND operation.
-
- @return The value written back to the I/O port.
-
-**/
-UINT64
-EFIAPI
-IoBitFieldAndThenOr64 (
- IN UINTN Port,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT64 AndData,
- IN UINT64 OrData
- )
-{
- return IoWrite64 (
- Port,
- BitFieldAndThenOr64 (IoRead64 (Port), StartBit, EndBit, AndData, OrData)
- );
-}
-
-/**
- Reads an 8-bit MMIO register, performs a bitwise OR, and writes the
- result back to the 8-bit MMIO register.
-
- Reads the 8-bit MMIO register specified by Address, performs a bitwise
- inclusive OR between the read result and the value specified by OrData, and
- writes the result to the 8-bit MMIO register specified by Address. The value
- written to the MMIO register is returned. This function must guarantee that
- all MMIO read and write operations are serialized.
-
- If 8-bit MMIO register operations are not supported, then ASSERT().
-
- @param Address The MMIO register to write.
- @param OrData The value to OR with the value read from the MMIO register.
-
- @return The value written back to the MMIO register.
-
-**/
-UINT8
-EFIAPI
-MmioOr8 (
- IN UINTN Address,
- IN UINT8 OrData
- )
-{
- return MmioWrite8 (Address, (UINT8)(MmioRead8 (Address) | OrData));
-}
-
-/**
- Reads an 8-bit MMIO register, performs a bitwise AND, and writes the result
- back to the 8-bit MMIO register.
-
- Reads the 8-bit MMIO register specified by Address, performs a bitwise AND
- between the read result and the value specified by AndData, and writes the
- result to the 8-bit MMIO register specified by Address. The value written to
- the MMIO register is returned. This function must guarantee that all MMIO
- read and write operations are serialized.
-
- If 8-bit MMIO register operations are not supported, then ASSERT().
-
- @param Address The MMIO register to write.
- @param AndData The value to AND with the value read from the MMIO register.
-
- @return The value written back to the MMIO register.
-
-**/
-UINT8
-EFIAPI
-MmioAnd8 (
- IN UINTN Address,
- IN UINT8 AndData
- )
-{
- return MmioWrite8 (Address, (UINT8)(MmioRead8 (Address) & AndData));
-}
-
-/**
- Reads an 8-bit MMIO register, performs a bitwise AND followed by a bitwise
- inclusive OR, and writes the result back to the 8-bit MMIO register.
-
- Reads the 8-bit MMIO register specified by Address, performs a bitwise AND
- between the read result and the value specified by AndData, performs a
- bitwise OR between the result of the AND operation and the value specified by
- OrData, and writes the result to the 8-bit MMIO register specified by
- Address. The value written to the MMIO register is returned. This function
- must guarantee that all MMIO read and write operations are serialized.
-
- If 8-bit MMIO register operations are not supported, then ASSERT().
-
-
- @param Address The MMIO register to write.
- @param AndData The value to AND with the value read from the MMIO register.
- @param OrData The value to OR with the result of the AND operation.
-
- @return The value written back to the MMIO register.
-
-**/
-UINT8
-EFIAPI
-MmioAndThenOr8 (
- IN UINTN Address,
- IN UINT8 AndData,
- IN UINT8 OrData
- )
-{
- return MmioWrite8 (Address, (UINT8)((MmioRead8 (Address) & AndData) | OrData));
-}
-
-/**
- Reads a bit field of a MMIO register.
-
- Reads the bit field in an 8-bit MMIO register. The bit field is specified by
- the StartBit and the EndBit. The value of the bit field is returned.
-
- If 8-bit MMIO register operations are not supported, then ASSERT().
- If StartBit is greater than 7, then ASSERT().
- If EndBit is greater than 7, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
-
- @param Address MMIO register to read.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..7.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..7.
-
- @return The value read.
-
-**/
-UINT8
-EFIAPI
-MmioBitFieldRead8 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit
- )
-{
- return BitFieldRead8 (MmioRead8 (Address), StartBit, EndBit);
-}
-
-/**
- Writes a bit field to a MMIO register.
-
- Writes Value to the bit field of the MMIO register. The bit field is
- specified by the StartBit and the EndBit. All other bits in the destination
- MMIO register are preserved. The new value of the 8-bit register is returned.
-
- If 8-bit MMIO register operations are not supported, then ASSERT().
- If StartBit is greater than 7, then ASSERT().
- If EndBit is greater than 7, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Address MMIO register to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..7.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..7.
- @param Value New value of the bit field.
-
- @return The value written back to the MMIO register.
-
-**/
-UINT8
-EFIAPI
-MmioBitFieldWrite8 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 Value
- )
-{
- return MmioWrite8 (
- Address,
- BitFieldWrite8 (MmioRead8 (Address), StartBit, EndBit, Value)
- );
-}
-
-/**
- Reads a bit field in an 8-bit MMIO register, performs a bitwise OR, and
- writes the result back to the bit field in the 8-bit MMIO register.
-
- Reads the 8-bit MMIO register specified by Address, performs a bitwise
- inclusive OR between the read result and the value specified by OrData, and
- writes the result to the 8-bit MMIO register specified by Address. The value
- written to the MMIO register is returned. This function must guarantee that
- all MMIO read and write operations are serialized. Extra left bits in OrData
- are stripped.
-
- If 8-bit MMIO register operations are not supported, then ASSERT().
- If StartBit is greater than 7, then ASSERT().
- If EndBit is greater than 7, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Address MMIO register to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..7.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..7.
- @param OrData The value to OR with value read from the MMIO register.
-
- @return The value written back to the MMIO register.
-
-**/
-UINT8
-EFIAPI
-MmioBitFieldOr8 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 OrData
- )
-{
- return MmioWrite8 (
- Address,
- BitFieldOr8 (MmioRead8 (Address), StartBit, EndBit, OrData)
- );
-}
-
-/**
- Reads a bit field in an 8-bit MMIO register, performs a bitwise AND, and
- writes the result back to the bit field in the 8-bit MMIO register.
-
- Reads the 8-bit MMIO register specified by Address, performs a bitwise AND
- between the read result and the value specified by AndData, and writes the
- result to the 8-bit MMIO register specified by Address. The value written to
- the MMIO register is returned. This function must guarantee that all MMIO
- read and write operations are serialized. Extra left bits in AndData are
- stripped.
-
- If 8-bit MMIO register operations are not supported, then ASSERT().
- If StartBit is greater than 7, then ASSERT().
- If EndBit is greater than 7, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Address MMIO register to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..7.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..7.
- @param AndData The value to AND with value read from the MMIO register.
-
- @return The value written back to the MMIO register.
-
-**/
-UINT8
-EFIAPI
-MmioBitFieldAnd8 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 AndData
- )
-{
- return MmioWrite8 (
- Address,
- BitFieldAnd8 (MmioRead8 (Address), StartBit, EndBit, AndData)
- );
-}
-
-/**
- Reads a bit field in an 8-bit MMIO register, performs a bitwise AND followed
- by a bitwise OR, and writes the result back to the bit field in the
- 8-bit MMIO register.
-
- Reads the 8-bit MMIO register specified by Address, performs a bitwise AND
- followed by a bitwise OR between the read result and the value
- specified by AndData, and writes the result to the 8-bit MMIO register
- specified by Address. The value written to the MMIO register is returned.
- This function must guarantee that all MMIO read and write operations are
- serialized. Extra left bits in both AndData and OrData are stripped.
-
- If 8-bit MMIO register operations are not supported, then ASSERT().
- If StartBit is greater than 7, then ASSERT().
- If EndBit is greater than 7, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Address MMIO register to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..7.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..7.
- @param AndData The value to AND with value read from the MMIO register.
- @param OrData The value to OR with the result of the AND operation.
-
- @return The value written back to the MMIO register.
-
-**/
-UINT8
-EFIAPI
-MmioBitFieldAndThenOr8 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 AndData,
- IN UINT8 OrData
- )
-{
- return MmioWrite8 (
- Address,
- BitFieldAndThenOr8 (MmioRead8 (Address), StartBit, EndBit, AndData, OrData)
- );
-}
-
-/**
- Reads a 16-bit MMIO register, performs a bitwise OR, and writes the
- result back to the 16-bit MMIO register.
-
- Reads the 16-bit MMIO register specified by Address, performs a bitwise
- inclusive OR between the read result and the value specified by OrData, and
- writes the result to the 16-bit MMIO register specified by Address. The value
- written to the MMIO register is returned. This function must guarantee that
- all MMIO read and write operations are serialized.
-
- If 16-bit MMIO register operations are not supported, then ASSERT().
-
- @param Address The MMIO register to write.
- @param OrData The value to OR with the value read from the MMIO register.
-
- @return The value written back to the MMIO register.
-
-**/
-UINT16
-EFIAPI
-MmioOr16 (
- IN UINTN Address,
- IN UINT16 OrData
- )
-{
- return MmioWrite16 (Address, (UINT16)(MmioRead16 (Address) | OrData));
-}
-
-/**
- Reads a 16-bit MMIO register, performs a bitwise AND, and writes the result
- back to the 16-bit MMIO register.
-
- Reads the 16-bit MMIO register specified by Address, performs a bitwise AND
- between the read result and the value specified by AndData, and writes the
- result to the 16-bit MMIO register specified by Address. The value written to
- the MMIO register is returned. This function must guarantee that all MMIO
- read and write operations are serialized.
-
- If 16-bit MMIO register operations are not supported, then ASSERT().
-
- @param Address The MMIO register to write.
- @param AndData The value to AND with the value read from the MMIO register.
-
- @return The value written back to the MMIO register.
-
-**/
-UINT16
-EFIAPI
-MmioAnd16 (
- IN UINTN Address,
- IN UINT16 AndData
- )
-{
- return MmioWrite16 (Address, (UINT16)(MmioRead16 (Address) & AndData));
-}
-
-/**
- Reads a 16-bit MMIO register, performs a bitwise AND followed by a bitwise
- inclusive OR, and writes the result back to the 16-bit MMIO register.
-
- Reads the 16-bit MMIO register specified by Address, performs a bitwise AND
- between the read result and the value specified by AndData, performs a
- bitwise OR between the result of the AND operation and the value specified by
- OrData, and writes the result to the 16-bit MMIO register specified by
- Address. The value written to the MMIO register is returned. This function
- must guarantee that all MMIO read and write operations are serialized.
-
- If 16-bit MMIO register operations are not supported, then ASSERT().
-
-
- @param Address The MMIO register to write.
- @param AndData The value to AND with the value read from the MMIO register.
- @param OrData The value to OR with the result of the AND operation.
-
- @return The value written back to the MMIO register.
-
-**/
-UINT16
-EFIAPI
-MmioAndThenOr16 (
- IN UINTN Address,
- IN UINT16 AndData,
- IN UINT16 OrData
- )
-{
- return MmioWrite16 (Address, (UINT16)((MmioRead16 (Address) & AndData) | OrData));
-}
-
-/**
- Reads a bit field of a MMIO register.
-
- Reads the bit field in a 16-bit MMIO register. The bit field is specified by
- the StartBit and the EndBit. The value of the bit field is returned.
-
- If 16-bit MMIO register operations are not supported, then ASSERT().
- If StartBit is greater than 15, then ASSERT().
- If EndBit is greater than 15, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
-
- @param Address MMIO register to read.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..15.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..15.
-
- @return The value read.
-
-**/
-UINT16
-EFIAPI
-MmioBitFieldRead16 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit
- )
-{
- return BitFieldRead16 (MmioRead16 (Address), StartBit, EndBit);
-}
-
-/**
- Writes a bit field to a MMIO register.
-
- Writes Value to the bit field of the MMIO register. The bit field is
- specified by the StartBit and the EndBit. All other bits in the destination
- MMIO register are preserved. The new value of the 16-bit register is returned.
-
- If 16-bit MMIO register operations are not supported, then ASSERT().
- If StartBit is greater than 15, then ASSERT().
- If EndBit is greater than 15, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Address MMIO register to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..15.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..15.
- @param Value New value of the bit field.
-
- @return The value written back to the MMIO register.
-
-**/
-UINT16
-EFIAPI
-MmioBitFieldWrite16 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 Value
- )
-{
- return MmioWrite16 (
- Address,
- BitFieldWrite16 (MmioRead16 (Address), StartBit, EndBit, Value)
- );
-}
-
-/**
- Reads a bit field in a 16-bit MMIO register, performs a bitwise OR, and
- writes the result back to the bit field in the 16-bit MMIO register.
-
- Reads the 16-bit MMIO register specified by Address, performs a bitwise
- inclusive OR between the read result and the value specified by OrData, and
- writes the result to the 16-bit MMIO register specified by Address. The value
- written to the MMIO register is returned. This function must guarantee that
- all MMIO read and write operations are serialized. Extra left bits in OrData
- are stripped.
-
- If 16-bit MMIO register operations are not supported, then ASSERT().
- If StartBit is greater than 15, then ASSERT().
- If EndBit is greater than 15, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Address MMIO register to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..15.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..15.
- @param OrData The value to OR with value read from the MMIO register.
-
- @return The value written back to the MMIO register.
-
-**/
-UINT16
-EFIAPI
-MmioBitFieldOr16 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 OrData
- )
-{
- return MmioWrite16 (
- Address,
- BitFieldOr16 (MmioRead16 (Address), StartBit, EndBit, OrData)
- );
-}
-
-/**
- Reads a bit field in a 16-bit MMIO register, performs a bitwise AND, and
- writes the result back to the bit field in the 16-bit MMIO register.
-
- Reads the 16-bit MMIO register specified by Address, performs a bitwise AND
- between the read result and the value specified by AndData, and writes the
- result to the 16-bit MMIO register specified by Address. The value written to
- the MMIO register is returned. This function must guarantee that all MMIO
- read and write operations are serialized. Extra left bits in AndData are
- stripped.
-
- If 16-bit MMIO register operations are not supported, then ASSERT().
- If StartBit is greater than 15, then ASSERT().
- If EndBit is greater than 15, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Address MMIO register to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..15.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..15.
- @param AndData The value to AND with value read from the MMIO register.
-
- @return The value written back to the MMIO register.
-
-**/
-UINT16
-EFIAPI
-MmioBitFieldAnd16 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 AndData
- )
-{
- return MmioWrite16 (
- Address,
- BitFieldAnd16 (MmioRead16 (Address), StartBit, EndBit, AndData)
- );
-}
-
-/**
- Reads a bit field in a 16-bit MMIO register, performs a bitwise AND followed
- by a bitwise OR, and writes the result back to the bit field in the
- 16-bit MMIO register.
-
- Reads the 16-bit MMIO register specified by Address, performs a bitwise AND
- followed by a bitwise OR between the read result and the value
- specified by AndData, and writes the result to the 16-bit MMIO register
- specified by Address. The value written to the MMIO register is returned.
- This function must guarantee that all MMIO read and write operations are
- serialized. Extra left bits in both AndData and OrData are stripped.
-
- If 16-bit MMIO register operations are not supported, then ASSERT().
- If StartBit is greater than 15, then ASSERT().
- If EndBit is greater than 15, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Address MMIO register to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..15.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..15.
- @param AndData The value to AND with value read from the MMIO register.
- @param OrData The value to OR with the result of the AND operation.
-
- @return The value written back to the MMIO register.
-
-**/
-UINT16
-EFIAPI
-MmioBitFieldAndThenOr16 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 AndData,
- IN UINT16 OrData
- )
-{
- return MmioWrite16 (
- Address,
- BitFieldAndThenOr16 (MmioRead16 (Address), StartBit, EndBit, AndData, OrData)
- );
-}
-
-/**
- Reads a 32-bit MMIO register, performs a bitwise OR, and writes the
- result back to the 32-bit MMIO register.
-
- Reads the 32-bit MMIO register specified by Address, performs a bitwise
- inclusive OR between the read result and the value specified by OrData, and
- writes the result to the 32-bit MMIO register specified by Address. The value
- written to the MMIO register is returned. This function must guarantee that
- all MMIO read and write operations are serialized.
-
- If 32-bit MMIO register operations are not supported, then ASSERT().
-
- @param Address The MMIO register to write.
- @param OrData The value to OR with the value read from the MMIO register.
-
- @return The value written back to the MMIO register.
-
-**/
-UINT32
-EFIAPI
-MmioOr32 (
- IN UINTN Address,
- IN UINT32 OrData
- )
-{
- return MmioWrite32 (Address, MmioRead32 (Address) | OrData);
-}
-
-/**
- Reads a 32-bit MMIO register, performs a bitwise AND, and writes the result
- back to the 32-bit MMIO register.
-
- Reads the 32-bit MMIO register specified by Address, performs a bitwise AND
- between the read result and the value specified by AndData, and writes the
- result to the 32-bit MMIO register specified by Address. The value written to
- the MMIO register is returned. This function must guarantee that all MMIO
- read and write operations are serialized.
-
- If 32-bit MMIO register operations are not supported, then ASSERT().
-
- @param Address The MMIO register to write.
- @param AndData The value to AND with the value read from the MMIO register.
-
- @return The value written back to the MMIO register.
-
-**/
-UINT32
-EFIAPI
-MmioAnd32 (
- IN UINTN Address,
- IN UINT32 AndData
- )
-{
- return MmioWrite32 (Address, MmioRead32 (Address) & AndData);
-}
-
-/**
- Reads a 32-bit MMIO register, performs a bitwise AND followed by a bitwise
- inclusive OR, and writes the result back to the 32-bit MMIO register.
-
- Reads the 32-bit MMIO register specified by Address, performs a bitwise AND
- between the read result and the value specified by AndData, performs a
- bitwise OR between the result of the AND operation and the value specified by
- OrData, and writes the result to the 32-bit MMIO register specified by
- Address. The value written to the MMIO register is returned. This function
- must guarantee that all MMIO read and write operations are serialized.
-
- If 32-bit MMIO register operations are not supported, then ASSERT().
-
-
- @param Address The MMIO register to write.
- @param AndData The value to AND with the value read from the MMIO register.
- @param OrData The value to OR with the result of the AND operation.
-
- @return The value written back to the MMIO register.
-
-**/
-UINT32
-EFIAPI
-MmioAndThenOr32 (
- IN UINTN Address,
- IN UINT32 AndData,
- IN UINT32 OrData
- )
-{
- return MmioWrite32 (Address, (MmioRead32 (Address) & AndData) | OrData);
-}
-
-/**
- Reads a bit field of a MMIO register.
-
- Reads the bit field in a 32-bit MMIO register. The bit field is specified by
- the StartBit and the EndBit. The value of the bit field is returned.
-
- If 32-bit MMIO register operations are not supported, then ASSERT().
- If StartBit is greater than 31, then ASSERT().
- If EndBit is greater than 31, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
-
- @param Address MMIO register to read.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..31.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..31.
-
- @return The value read.
-
-**/
-UINT32
-EFIAPI
-MmioBitFieldRead32 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit
- )
-{
- return BitFieldRead32 (MmioRead32 (Address), StartBit, EndBit);
-}
-
-/**
- Writes a bit field to a MMIO register.
-
- Writes Value to the bit field of the MMIO register. The bit field is
- specified by the StartBit and the EndBit. All other bits in the destination
- MMIO register are preserved. The new value of the 32-bit register is returned.
-
- If 32-bit MMIO register operations are not supported, then ASSERT().
- If StartBit is greater than 31, then ASSERT().
- If EndBit is greater than 31, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Address MMIO register to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..31.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..31.
- @param Value New value of the bit field.
-
- @return The value written back to the MMIO register.
-
-**/
-UINT32
-EFIAPI
-MmioBitFieldWrite32 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 Value
- )
-{
- return MmioWrite32 (
- Address,
- BitFieldWrite32 (MmioRead32 (Address), StartBit, EndBit, Value)
- );
-}
-
-/**
- Reads a bit field in a 32-bit MMIO register, performs a bitwise OR, and
- writes the result back to the bit field in the 32-bit MMIO register.
-
- Reads the 32-bit MMIO register specified by Address, performs a bitwise
- inclusive OR between the read result and the value specified by OrData, and
- writes the result to the 32-bit MMIO register specified by Address. The value
- written to the MMIO register is returned. This function must guarantee that
- all MMIO read and write operations are serialized. Extra left bits in OrData
- are stripped.
-
- If 32-bit MMIO register operations are not supported, then ASSERT().
- If StartBit is greater than 31, then ASSERT().
- If EndBit is greater than 31, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Address MMIO register to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..31.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..31.
- @param OrData The value to OR with value read from the MMIO register.
-
- @return The value written back to the MMIO register.
-
-**/
-UINT32
-EFIAPI
-MmioBitFieldOr32 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 OrData
- )
-{
- return MmioWrite32 (
- Address,
- BitFieldOr32 (MmioRead32 (Address), StartBit, EndBit, OrData)
- );
-}
-
-/**
- Reads a bit field in a 32-bit MMIO register, performs a bitwise AND, and
- writes the result back to the bit field in the 32-bit MMIO register.
-
- Reads the 32-bit MMIO register specified by Address, performs a bitwise AND
- between the read result and the value specified by AndData, and writes the
- result to the 32-bit MMIO register specified by Address. The value written to
- the MMIO register is returned. This function must guarantee that all MMIO
- read and write operations are serialized. Extra left bits in AndData are
- stripped.
-
- If 32-bit MMIO register operations are not supported, then ASSERT().
- If StartBit is greater than 31, then ASSERT().
- If EndBit is greater than 31, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Address MMIO register to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..31.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..31.
- @param AndData The value to AND with value read from the MMIO register.
-
- @return The value written back to the MMIO register.
-
-**/
-UINT32
-EFIAPI
-MmioBitFieldAnd32 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 AndData
- )
-{
- return MmioWrite32 (
- Address,
- BitFieldAnd32 (MmioRead32 (Address), StartBit, EndBit, AndData)
- );
-}
-
-/**
- Reads a bit field in a 32-bit MMIO register, performs a bitwise AND followed
- by a bitwise OR, and writes the result back to the bit field in the
- 32-bit MMIO register.
-
- Reads the 32-bit MMIO register specified by Address, performs a bitwise AND
- followed by a bitwise OR between the read result and the value
- specified by AndData, and writes the result to the 32-bit MMIO register
- specified by Address. The value written to the MMIO register is returned.
- This function must guarantee that all MMIO read and write operations are
- serialized. Extra left bits in both AndData and OrData are stripped.
-
- If 32-bit MMIO register operations are not supported, then ASSERT().
- If StartBit is greater than 31, then ASSERT().
- If EndBit is greater than 31, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Address MMIO register to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..31.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..31.
- @param AndData The value to AND with value read from the MMIO register.
- @param OrData The value to OR with the result of the AND operation.
-
- @return The value written back to the MMIO register.
-
-**/
-UINT32
-EFIAPI
-MmioBitFieldAndThenOr32 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 AndData,
- IN UINT32 OrData
- )
-{
- return MmioWrite32 (
- Address,
- BitFieldAndThenOr32 (MmioRead32 (Address), StartBit, EndBit, AndData, OrData)
- );
-}
-
-/**
- Reads a 64-bit MMIO register, performs a bitwise OR, and writes the
- result back to the 64-bit MMIO register.
-
- Reads the 64-bit MMIO register specified by Address, performs a bitwise
- inclusive OR between the read result and the value specified by OrData, and
- writes the result to the 64-bit MMIO register specified by Address. The value
- written to the MMIO register is returned. This function must guarantee that
- all MMIO read and write operations are serialized.
-
- If 64-bit MMIO register operations are not supported, then ASSERT().
-
- @param Address The MMIO register to write.
- @param OrData The value to OR with the value read from the MMIO register.
-
- @return The value written back to the MMIO register.
-
-**/
-UINT64
-EFIAPI
-MmioOr64 (
- IN UINTN Address,
- IN UINT64 OrData
- )
-{
- return MmioWrite64 (Address, MmioRead64 (Address) | OrData);
-}
-
-/**
- Reads a 64-bit MMIO register, performs a bitwise AND, and writes the result
- back to the 64-bit MMIO register.
-
- Reads the 64-bit MMIO register specified by Address, performs a bitwise AND
- between the read result and the value specified by AndData, and writes the
- result to the 64-bit MMIO register specified by Address. The value written to
- the MMIO register is returned. This function must guarantee that all MMIO
- read and write operations are serialized.
-
- If 64-bit MMIO register operations are not supported, then ASSERT().
-
- @param Address The MMIO register to write.
- @param AndData The value to AND with the value read from the MMIO register.
-
- @return The value written back to the MMIO register.
-
-**/
-UINT64
-EFIAPI
-MmioAnd64 (
- IN UINTN Address,
- IN UINT64 AndData
- )
-{
- return MmioWrite64 (Address, MmioRead64 (Address) & AndData);
-}
-
-/**
- Reads a 64-bit MMIO register, performs a bitwise AND followed by a bitwise
- inclusive OR, and writes the result back to the 64-bit MMIO register.
-
- Reads the 64-bit MMIO register specified by Address, performs a bitwise AND
- between the read result and the value specified by AndData, performs a
- bitwise OR between the result of the AND operation and the value specified by
- OrData, and writes the result to the 64-bit MMIO register specified by
- Address. The value written to the MMIO register is returned. This function
- must guarantee that all MMIO read and write operations are serialized.
-
- If 64-bit MMIO register operations are not supported, then ASSERT().
-
-
- @param Address The MMIO register to write.
- @param AndData The value to AND with the value read from the MMIO register.
- @param OrData The value to OR with the result of the AND operation.
-
- @return The value written back to the MMIO register.
-
-**/
-UINT64
-EFIAPI
-MmioAndThenOr64 (
- IN UINTN Address,
- IN UINT64 AndData,
- IN UINT64 OrData
- )
-{
- return MmioWrite64 (Address, (MmioRead64 (Address) & AndData) | OrData);
-}
-
-/**
- Reads a bit field of a MMIO register.
-
- Reads the bit field in a 64-bit MMIO register. The bit field is specified by
- the StartBit and the EndBit. The value of the bit field is returned.
-
- If 64-bit MMIO register operations are not supported, then ASSERT().
- If StartBit is greater than 63, then ASSERT().
- If EndBit is greater than 63, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
-
- @param Address MMIO register to read.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..63.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..63.
-
- @return The value read.
-
-**/
-UINT64
-EFIAPI
-MmioBitFieldRead64 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit
- )
-{
- return BitFieldRead64 (MmioRead64 (Address), StartBit, EndBit);
-}
-
-/**
- Writes a bit field to a MMIO register.
-
- Writes Value to the bit field of the MMIO register. The bit field is
- specified by the StartBit and the EndBit. All other bits in the destination
- MMIO register are preserved. The new value of the 64-bit register is returned.
-
- If 64-bit MMIO register operations are not supported, then ASSERT().
- If StartBit is greater than 63, then ASSERT().
- If EndBit is greater than 63, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Address MMIO register to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..63.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..63.
- @param Value New value of the bit field.
-
- @return The value written back to the MMIO register.
-
-**/
-UINT64
-EFIAPI
-MmioBitFieldWrite64 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT64 Value
- )
-{
- return MmioWrite64 (
- Address,
- BitFieldWrite64 (MmioRead64 (Address), StartBit, EndBit, Value)
- );
-}
-
-/**
- Reads a bit field in a 64-bit MMIO register, performs a bitwise OR, and
- writes the result back to the bit field in the 64-bit MMIO register.
-
- Reads the 64-bit MMIO register specified by Address, performs a bitwise
- inclusive OR between the read result and the value specified by OrData, and
- writes the result to the 64-bit MMIO register specified by Address. The value
- written to the MMIO register is returned. This function must guarantee that
- all MMIO read and write operations are serialized. Extra left bits in OrData
- are stripped.
-
- If 64-bit MMIO register operations are not supported, then ASSERT().
- If StartBit is greater than 63, then ASSERT().
- If EndBit is greater than 63, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Address MMIO register to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..63.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..63.
- @param OrData The value to OR with value read from the MMIO register.
-
- @return The value written back to the MMIO register.
-
-**/
-UINT64
-EFIAPI
-MmioBitFieldOr64 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT64 OrData
- )
-{
- return MmioWrite64 (
- Address,
- BitFieldOr64 (MmioRead64 (Address), StartBit, EndBit, OrData)
- );
-}
-
-/**
- Reads a bit field in a 64-bit MMIO register, performs a bitwise AND, and
- writes the result back to the bit field in the 64-bit MMIO register.
-
- Reads the 64-bit MMIO register specified by Address, performs a bitwise AND
- between the read result and the value specified by AndData, and writes the
- result to the 64-bit MMIO register specified by Address. The value written to
- the MMIO register is returned. This function must guarantee that all MMIO
- read and write operations are serialized. Extra left bits in AndData are
- stripped.
-
- If 64-bit MMIO register operations are not supported, then ASSERT().
- If StartBit is greater than 63, then ASSERT().
- If EndBit is greater than 63, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Address MMIO register to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..63.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..63.
- @param AndData The value to AND with value read from the MMIO register.
-
- @return The value written back to the MMIO register.
-
-**/
-UINT64
-EFIAPI
-MmioBitFieldAnd64 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT64 AndData
- )
-{
- return MmioWrite64 (
- Address,
- BitFieldAnd64 (MmioRead64 (Address), StartBit, EndBit, AndData)
- );
-}
-
-/**
- Reads a bit field in a 64-bit MMIO register, performs a bitwise AND followed
- by a bitwise OR, and writes the result back to the bit field in the
- 64-bit MMIO register.
-
- Reads the 64-bit MMIO register specified by Address, performs a bitwise AND
- followed by a bitwise OR between the read result and the value
- specified by AndData, and writes the result to the 64-bit MMIO register
- specified by Address. The value written to the MMIO register is returned.
- This function must guarantee that all MMIO read and write operations are
- serialized. Extra left bits in both AndData and OrData are stripped.
-
- If 64-bit MMIO register operations are not supported, then ASSERT().
- If StartBit is greater than 63, then ASSERT().
- If EndBit is greater than 63, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Address MMIO register to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..63.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..63.
- @param AndData The value to AND with value read from the MMIO register.
- @param OrData The value to OR with the result of the AND operation.
-
- @return The value written back to the MMIO register.
-
-**/
-UINT64
-EFIAPI
-MmioBitFieldAndThenOr64 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT64 AndData,
- IN UINT64 OrData
- )
-{
- return MmioWrite64 (
- Address,
- BitFieldAndThenOr64 (MmioRead64 (Address), StartBit, EndBit, AndData, OrData)
- );
-}
diff --git a/MdePkg/Library/DxeIoLibEsal/IoLib.c b/MdePkg/Library/DxeIoLibEsal/IoLib.c
deleted file mode 100644
index ab186a6d32..0000000000
--- a/MdePkg/Library/DxeIoLibEsal/IoLib.c
+++ /dev/null
@@ -1,879 +0,0 @@
-/** @file
- I/O Library basic function implementation and worker functions.
-
- Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
- Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
-
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php.
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include "DxeIoLibEsalInternal.h"
-
-/**
- Reads registers in the EFI CPU I/O space.
-
- Reads the I/O port specified by Port with registers width specified by Width.
- The read value is returned.
-
- This function must guarantee that all I/O read and write operations are serialized.
- If such operations are not supported, then ASSERT().
-
- @param Port The base address of the I/O operation.
- The caller is responsible for aligning the Address if required.
- @param Width The width of the I/O operation.
-
- @return Data read from registers in the EFI CPU I/O space.
-
-**/
-UINT64
-EFIAPI
-IoReadWorker (
- IN UINTN Port,
- IN EFI_CPU_IO_PROTOCOL_WIDTH Width
- )
-{
- SAL_RETURN_REGS ReturnReg;
- UINT64 Data;
-
- Data = 0;
-
- ReturnReg = EsalCall (
- EFI_EXTENDED_SAL_BASE_IO_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_BASE_IO_SERVICES_PROTOCOL_GUID_HI,
- IoReadFunctionId,
- (UINT64)Width,
- Port,
- 1,
- (UINT64)&Data,
- 0,
- 0,
- 0
- );
- ASSERT (ReturnReg.Status == EFI_SAL_SUCCESS);
- return Data;
-}
-
-/**
- Writes registers in the EFI CPU I/O space.
-
- Writes the I/O port specified by Port with registers width and value specified by Width
- and Data respectively. Data is returned.
-
- This function must guarantee that all I/O read and write operations are serialized.
- If such operations are not supported, then ASSERT().
-
- @param Port The base address of the I/O operation.
- The caller is responsible for aligning the Address if required.
- @param Width The width of the I/O operation.
- @param Data The value to write to the I/O port.
-
- @return The parameter of Data.
-
-**/
-UINT64
-EFIAPI
-IoWriteWorker (
- IN UINTN Port,
- IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
- IN UINT64 Data
- )
-{
- SAL_RETURN_REGS ReturnReg;
-
- ReturnReg = EsalCall (
- EFI_EXTENDED_SAL_BASE_IO_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_BASE_IO_SERVICES_PROTOCOL_GUID_HI,
- IoWriteFunctionId,
- (UINT64)Width,
- Port,
- 1,
- (UINT64)&Data,
- 0,
- 0,
- 0
- );
- ASSERT (ReturnReg.Status == EFI_SAL_SUCCESS);
- return Data;
-}
-
-/**
- Reads registers in the EFI CPU I/O space.
-
- Reads the I/O port specified by Port with registers width specified by Width.
- The port is read Count times, and the read data is stored in the provided Buffer.
-
- This function must guarantee that all I/O read and write operations are serialized.
- If such operations are not supported, then ASSERT().
-
- @param Port The base address of the I/O operation.
- The caller is responsible for aligning the Address if required.
- @param Width The width of the I/O operation.
- @param Count The number of times to read I/O port.
- @param Buffer The buffer to store the read data into.
-
-**/
-VOID
-EFIAPI
-IoReadFifoWorker (
- IN UINTN Port,
- IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
- IN UINTN Count,
- IN VOID *Buffer
- )
-{
- SAL_RETURN_REGS ReturnReg;
-
- ReturnReg = EsalCall (
- EFI_EXTENDED_SAL_BASE_IO_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_BASE_IO_SERVICES_PROTOCOL_GUID_HI,
- IoReadFunctionId,
- (UINT64)Width,
- Port,
- Count,
- (UINT64)Buffer,
- 0,
- 0,
- 0
- );
- ASSERT (ReturnReg.Status == EFI_SAL_SUCCESS);
-}
-
-/**
- Writes registers in the EFI CPU I/O space.
-
- Writes the I/O port specified by Port with registers width specified by Width.
- The port is written Count times, and the write data is retrieved from the provided Buffer.
-
- This function must guarantee that all I/O read and write operations are serialized.
- If such operations are not supported, then ASSERT().
-
- @param Port The base address of the I/O operation.
- The caller is responsible for aligning the Address if required.
- @param Width The width of the I/O operation.
- @param Count The number of times to write I/O port.
- @param Buffer The buffer to store the read data into.
-
-**/
-VOID
-EFIAPI
-IoWriteFifoWorker (
- IN UINTN Port,
- IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
- IN UINTN Count,
- IN VOID *Buffer
- )
-{
- SAL_RETURN_REGS ReturnReg;
-
- ReturnReg = EsalCall (
- EFI_EXTENDED_SAL_BASE_IO_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_BASE_IO_SERVICES_PROTOCOL_GUID_HI,
- IoWriteFunctionId,
- (UINT64)Width,
- Port,
- Count,
- (UINT64)Buffer,
- 0,
- 0,
- 0
- );
- ASSERT (ReturnReg.Status == EFI_SAL_SUCCESS);
-}
-
-/**
- Reads memory-mapped registers in the EFI system memory space.
-
- Reads the MMIO registers specified by Address with registers width specified by Width.
- The read value is returned. If such operations are not supported, then ASSERT().
- This function must guarantee that all MMIO read and write operations are serialized.
-
- @param Address The MMIO register to read.
- The caller is responsible for aligning the Address if required.
- @param Width The width of the I/O operation.
-
- @return Data read from registers in the EFI system memory space.
-
-**/
-UINT64
-EFIAPI
-MmioReadWorker (
- IN UINTN Address,
- IN EFI_CPU_IO_PROTOCOL_WIDTH Width
- )
-{
- SAL_RETURN_REGS ReturnReg;
- UINT64 Data;
-
- Data = 0;
-
- ReturnReg = EsalCall (
- EFI_EXTENDED_SAL_BASE_IO_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_BASE_IO_SERVICES_PROTOCOL_GUID_HI,
- MemReadFunctionId,
- (UINT64)Width,
- Address,
- 1,
- (UINT64)&Data,
- 0,
- 0,
- 0
- );
- ASSERT (ReturnReg.Status == EFI_SAL_SUCCESS);
- return Data;
-}
-
-/**
- Writes memory-mapped registers in the EFI system memory space.
-
- Writes the MMIO registers specified by Address with registers width and value specified by Width
- and Data respectively. Data is returned. If such operations are not supported, then ASSERT().
- This function must guarantee that all MMIO read and write operations are serialized.
-
- @param Address The MMIO register to read.
- The caller is responsible for aligning the Address if required.
- @param Width The width of the I/O operation.
- @param Data The value to write to memory-mapped registers
-
- @return Data read from registers in the EFI system memory space.
-
-**/
-UINT64
-EFIAPI
-MmioWriteWorker (
- IN UINTN Address,
- IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
- IN UINT64 Data
- )
-{
- SAL_RETURN_REGS ReturnReg;
-
- ReturnReg = EsalCall (
- EFI_EXTENDED_SAL_BASE_IO_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_BASE_IO_SERVICES_PROTOCOL_GUID_HI,
- MemWriteFunctionId,
- (UINT64)Width,
- Address,
- 1,
- (UINT64)&Data,
- 0,
- 0,
- 0
- );
- ASSERT (ReturnReg.Status == EFI_SAL_SUCCESS);
- return Data;
-}
-
-/**
- Reads an 8-bit I/O port.
-
- Reads the 8-bit I/O port specified by Port. The 8-bit read value is returned.
- This function must guarantee that all I/O read and write operations are
- serialized.
-
- If 8-bit I/O port operations are not supported, then ASSERT().
-
- @param Port The I/O port to read.
-
- @return The value read.
-
-**/
-UINT8
-EFIAPI
-IoRead8 (
- IN UINTN Port
- )
-{
- return (UINT8)IoReadWorker (Port, EfiCpuIoWidthUint8);
-}
-
-/**
- Writes an 8-bit I/O port.
-
- Writes the 8-bit I/O port specified by Port with the value specified by Value
- and returns Value. This function must guarantee that all I/O read and write
- operations are serialized.
-
- If 8-bit I/O port operations are not supported, then ASSERT().
-
- @param Port The I/O port to write.
- @param Value The value to write to the I/O port.
-
- @return The value written the I/O port.
-
-**/
-UINT8
-EFIAPI
-IoWrite8 (
- IN UINTN Port,
- IN UINT8 Value
- )
-{
- return (UINT8)IoWriteWorker (Port, EfiCpuIoWidthUint8, Value);
-}
-
-/**
- Reads a 16-bit I/O port.
-
- Reads the 16-bit I/O port specified by Port. The 16-bit read value is returned.
- This function must guarantee that all I/O read and write operations are
- serialized.
-
- If 16-bit I/O port operations are not supported, then ASSERT().
-
- @param Port The I/O port to read.
-
- @return The value read.
-
-**/
-UINT16
-EFIAPI
-IoRead16 (
- IN UINTN Port
- )
-{
- //
- // Make sure Port is aligned on a 16-bit boundary.
- //
- ASSERT ((Port & 1) == 0);
- return (UINT16)IoReadWorker (Port, EfiCpuIoWidthUint16);
-}
-
-/**
- Writes a 16-bit I/O port.
-
- Writes the 16-bit I/O port specified by Port with the value specified by Value
- and returns Value. This function must guarantee that all I/O read and write
- operations are serialized.
-
- If 16-bit I/O port operations are not supported, then ASSERT().
-
- @param Port The I/O port to write.
- @param Value The value to write to the I/O port.
-
- @return The value written the I/O port.
-
-**/
-UINT16
-EFIAPI
-IoWrite16 (
- IN UINTN Port,
- IN UINT16 Value
- )
-{
- //
- // Make sure Port is aligned on a 16-bit boundary.
- //
- ASSERT ((Port & 1) == 0);
- return (UINT16)IoWriteWorker (Port, EfiCpuIoWidthUint16, Value);
-}
-
-/**
- Reads a 32-bit I/O port.
-
- Reads the 32-bit I/O port specified by Port. The 32-bit read value is returned.
- This function must guarantee that all I/O read and write operations are
- serialized.
-
- If 32-bit I/O port operations are not supported, then ASSERT().
-
- @param Port The I/O port to read.
-
- @return The value read.
-
-**/
-UINT32
-EFIAPI
-IoRead32 (
- IN UINTN Port
- )
-{
- //
- // Make sure Port is aligned on a 32-bit boundary.
- //
- ASSERT ((Port & 3) == 0);
- return (UINT32)IoReadWorker (Port, EfiCpuIoWidthUint32);
-}
-
-/**
- Writes a 32-bit I/O port.
-
- Writes the 32-bit I/O port specified by Port with the value specified by Value
- and returns Value. This function must guarantee that all I/O read and write
- operations are serialized.
-
- If 32-bit I/O port operations are not supported, then ASSERT().
-
- @param Port The I/O port to write.
- @param Value The value to write to the I/O port.
-
- @return The value written the I/O port.
-
-**/
-UINT32
-EFIAPI
-IoWrite32 (
- IN UINTN Port,
- IN UINT32 Value
- )
-{
- //
- // Make sure Port is aligned on a 32-bit boundary.
- //
- ASSERT ((Port & 3) == 0);
- return (UINT32)IoWriteWorker (Port, EfiCpuIoWidthUint32, Value);
-}
-
-/**
- Reads a 64-bit I/O port.
-
- Reads the 64-bit I/O port specified by Port. The 64-bit read value is returned.
- This function must guarantee that all I/O read and write operations are
- serialized.
-
- If 64-bit I/O port operations are not supported, then ASSERT().
-
- @param Port The I/O port to read.
-
- @return The value read.
-
-**/
-UINT64
-EFIAPI
-IoRead64 (
- IN UINTN Port
- )
-{
- //
- // Make sure Port is aligned on a 64-bit boundary.
- //
- ASSERT ((Port & 7) == 0);
- return IoReadWorker (Port, EfiCpuIoWidthUint64);
-}
-
-/**
- Writes a 64-bit I/O port.
-
- Writes the 64-bit I/O port specified by Port with the value specified by Value
- and returns Value. This function must guarantee that all I/O read and write
- operations are serialized.
-
- If 64-bit I/O port operations are not supported, then ASSERT().
-
- @param Port The I/O port to write.
- @param Value The value to write to the I/O port.
-
- @return The value written the I/O port.
-
-**/
-UINT64
-EFIAPI
-IoWrite64 (
- IN UINTN Port,
- IN UINT64 Value
- )
-{
- //
- // Make sure Port is aligned on a 64-bit boundary.
- //
- ASSERT ((Port & 7) == 0);
- return IoWriteWorker (Port, EfiCpuIoWidthUint64, Value);
-}
-
-/**
- Reads an 8-bit I/O port fifo into a block of memory.
-
- Reads the 8-bit I/O fifo port specified by Port.
- The port is read Count times, and the read data is
- stored in the provided Buffer.
-
- This function must guarantee that all I/O read and write operations are
- serialized.
-
- If 8-bit I/O port operations are not supported, then ASSERT().
-
- @param Port The I/O port to read.
- @param Count The number of times to read I/O port.
- @param Buffer The buffer to store the read data into.
-
-**/
-VOID
-EFIAPI
-IoReadFifo8 (
- IN UINTN Port,
- IN UINTN Count,
- OUT VOID *Buffer
- )
-{
- IoReadFifoWorker (Port, EfiCpuIoWidthFifoUint8, Count, Buffer);
-}
-
-/**
- Writes a block of memory into an 8-bit I/O port fifo.
-
- Writes the 8-bit I/O fifo port specified by Port.
- The port is written Count times, and the write data is
- retrieved from the provided Buffer.
-
- This function must guarantee that all I/O write and write operations are
- serialized.
-
- If 8-bit I/O port operations are not supported, then ASSERT().
-
- @param Port The I/O port to write.
- @param Count The number of times to write I/O port.
- @param Buffer The buffer to retrieve the write data from.
-
-**/
-VOID
-EFIAPI
-IoWriteFifo8 (
- IN UINTN Port,
- IN UINTN Count,
- IN VOID *Buffer
- )
-{
- IoWriteFifoWorker (Port, EfiCpuIoWidthFifoUint8, Count, Buffer);
-}
-
-/**
- Reads a 16-bit I/O port fifo into a block of memory.
-
- Reads the 16-bit I/O fifo port specified by Port.
- The port is read Count times, and the read data is
- stored in the provided Buffer.
-
- This function must guarantee that all I/O read and write operations are
- serialized.
-
- If 16-bit I/O port operations are not supported, then ASSERT().
-
- @param Port The I/O port to read.
- @param Count The number of times to read I/O port.
- @param Buffer The buffer to store the read data into.
-
-**/
-VOID
-EFIAPI
-IoReadFifo16 (
- IN UINTN Port,
- IN UINTN Count,
- OUT VOID *Buffer
- )
-{
- //
- // Make sure Port is aligned on a 16-bit boundary.
- //
- ASSERT ((Port & 1) == 0);
- IoReadFifoWorker (Port, EfiCpuIoWidthFifoUint16, Count, Buffer);
-}
-
-/**
- Writes a block of memory into a 16-bit I/O port fifo.
-
- Writes the 16-bit I/O fifo port specified by Port.
- The port is written Count times, and the write data is
- retrieved from the provided Buffer.
-
- This function must guarantee that all I/O write and write operations are
- serialized.
-
- If 16-bit I/O port operations are not supported, then ASSERT().
-
- @param Port The I/O port to write.
- @param Count The number of times to write I/O port.
- @param Buffer The buffer to retrieve the write data from.
-
-**/
-VOID
-EFIAPI
-IoWriteFifo16 (
- IN UINTN Port,
- IN UINTN Count,
- IN VOID *Buffer
- )
-{
- //
- // Make sure Port is aligned on a 16-bit boundary.
- //
- ASSERT ((Port & 1) == 0);
- IoWriteFifoWorker (Port, EfiCpuIoWidthFifoUint16, Count, Buffer);
-}
-
-/**
- Reads a 32-bit I/O port fifo into a block of memory.
-
- Reads the 32-bit I/O fifo port specified by Port.
- The port is read Count times, and the read data is
- stored in the provided Buffer.
-
- This function must guarantee that all I/O read and write operations are
- serialized.
-
- If 32-bit I/O port operations are not supported, then ASSERT().
-
- @param Port The I/O port to read.
- @param Count The number of times to read I/O port.
- @param Buffer The buffer to store the read data into.
-
-**/
-VOID
-EFIAPI
-IoReadFifo32 (
- IN UINTN Port,
- IN UINTN Count,
- OUT VOID *Buffer
- )
-{
- //
- // Make sure Port is aligned on a 32-bit boundary.
- //
- ASSERT ((Port & 3) == 0);
- IoReadFifoWorker (Port, EfiCpuIoWidthFifoUint32, Count, Buffer);
-}
-
-/**
- Writes a block of memory into a 32-bit I/O port fifo.
-
- Writes the 32-bit I/O fifo port specified by Port.
- The port is written Count times, and the write data is
- retrieved from the provided Buffer.
-
- This function must guarantee that all I/O write and write operations are
- serialized.
-
- If 32-bit I/O port operations are not supported, then ASSERT().
-
- @param Port The I/O port to write.
- @param Count The number of times to write I/O port.
- @param Buffer The buffer to retrieve the write data from.
-
-**/
-VOID
-EFIAPI
-IoWriteFifo32 (
- IN UINTN Port,
- IN UINTN Count,
- IN VOID *Buffer
- )
-{
- //
- // Make sure Port is aligned on a 32-bit boundary.
- //
- ASSERT ((Port & 3) == 0);
- IoWriteFifoWorker (Port, EfiCpuIoWidthFifoUint32, Count, Buffer);
-}
-
-/**
- Reads an 8-bit MMIO register.
-
- Reads the 8-bit MMIO register specified by Address. The 8-bit read value is
- returned. This function must guarantee that all MMIO read and write
- operations are serialized.
-
- If 8-bit MMIO register operations are not supported, then ASSERT().
-
- @param Address The MMIO register to read.
-
- @return The value read.
-
-**/
-UINT8
-EFIAPI
-MmioRead8 (
- IN UINTN Address
- )
-{
- return (UINT8)MmioReadWorker (Address, EfiCpuIoWidthUint8);
-}
-
-/**
- Writes an 8-bit MMIO register.
-
- Writes the 8-bit MMIO register specified by Address with the value specified
- by Value and returns Value. This function must guarantee that all MMIO read
- and write operations are serialized.
-
- If 8-bit MMIO register operations are not supported, then ASSERT().
-
- @param Address The MMIO register to write.
- @param Value The value to write to the MMIO register.
-
-**/
-UINT8
-EFIAPI
-MmioWrite8 (
- IN UINTN Address,
- IN UINT8 Value
- )
-{
- return (UINT8)MmioWriteWorker (Address, EfiCpuIoWidthUint8, Value);
-}
-
-/**
- Reads a 16-bit MMIO register.
-
- Reads the 16-bit MMIO register specified by Address. The 16-bit read value is
- returned. This function must guarantee that all MMIO read and write
- operations are serialized.
-
- If 16-bit MMIO register operations are not supported, then ASSERT().
-
- @param Address The MMIO register to read.
-
- @return The value read.
-
-**/
-UINT16
-EFIAPI
-MmioRead16 (
- IN UINTN Address
- )
-{
- //
- // Make sure Address is aligned on a 16-bit boundary.
- //
- ASSERT ((Address & 1) == 0);
- return (UINT16)MmioReadWorker (Address, EfiCpuIoWidthUint16);
-}
-
-/**
- Writes a 16-bit MMIO register.
-
- Writes the 16-bit MMIO register specified by Address with the value specified
- by Value and returns Value. This function must guarantee that all MMIO read
- and write operations are serialized.
-
- If 16-bit MMIO register operations are not supported, then ASSERT().
-
- @param Address The MMIO register to write.
- @param Value The value to write to the MMIO register.
-
-**/
-UINT16
-EFIAPI
-MmioWrite16 (
- IN UINTN Address,
- IN UINT16 Value
- )
-{
- //
- // Make sure Address is aligned on a 16-bit boundary.
- //
- ASSERT ((Address & 1) == 0);
- return (UINT16)MmioWriteWorker (Address, EfiCpuIoWidthUint16, Value);
-}
-
-/**
- Reads a 32-bit MMIO register.
-
- Reads the 32-bit MMIO register specified by Address. The 32-bit read value is
- returned. This function must guarantee that all MMIO read and write
- operations are serialized.
-
- If 32-bit MMIO register operations are not supported, then ASSERT().
-
- @param Address The MMIO register to read.
-
- @return The value read.
-
-**/
-UINT32
-EFIAPI
-MmioRead32 (
- IN UINTN Address
- )
-{
- //
- // Make sure Address is aligned on a 32-bit boundary.
- //
- ASSERT ((Address & 3) == 0);
- return (UINT32)MmioReadWorker (Address, EfiCpuIoWidthUint32);
-}
-
-/**
- Writes a 32-bit MMIO register.
-
- Writes the 32-bit MMIO register specified by Address with the value specified
- by Value and returns Value. This function must guarantee that all MMIO read
- and write operations are serialized.
-
- If 32-bit MMIO register operations are not supported, then ASSERT().
-
- @param Address The MMIO register to write.
- @param Value The value to write to the MMIO register.
-
-**/
-UINT32
-EFIAPI
-MmioWrite32 (
- IN UINTN Address,
- IN UINT32 Value
- )
-{
- //
- // Make sure Address is aligned on a 32-bit boundary.
- //
- ASSERT ((Address & 3) == 0);
- return (UINT32)MmioWriteWorker (Address, EfiCpuIoWidthUint32, Value);
-}
-
-/**
- Reads a 64-bit MMIO register.
-
- Reads the 64-bit MMIO register specified by Address. The 64-bit read value is
- returned. This function must guarantee that all MMIO read and write
- operations are serialized.
-
- If 64-bit MMIO register operations are not supported, then ASSERT().
-
- @param Address The MMIO register to read.
-
- @return The value read.
-
-**/
-UINT64
-EFIAPI
-MmioRead64 (
- IN UINTN Address
- )
-{
- //
- // Make sure Address is aligned on a 64-bit boundary.
- //
- ASSERT ((Address & 7) == 0);
- return (UINT64)MmioReadWorker (Address, EfiCpuIoWidthUint64);
-}
-
-/**
- Writes a 64-bit MMIO register.
-
- Writes the 64-bit MMIO register specified by Address with the value specified
- by Value and returns Value. This function must guarantee that all MMIO read
- and write operations are serialized.
-
- If 64-bit MMIO register operations are not supported, then ASSERT().
-
- @param Address The MMIO register to write.
- @param Value The value to write to the MMIO register.
-
-**/
-UINT64
-EFIAPI
-MmioWrite64 (
- IN UINTN Address,
- IN UINT64 Value
- )
-{
- //
- // Make sure Address is aligned on a 64-bit boundary.
- //
- ASSERT ((Address & 7) == 0);
- return (UINT64)MmioWriteWorker (Address, EfiCpuIoWidthUint64, Value);
-}
diff --git a/MdePkg/Library/DxeIoLibEsal/IoLibMmioBuffer.c b/MdePkg/Library/DxeIoLibEsal/IoLibMmioBuffer.c
deleted file mode 100644
index 5addef2291..0000000000
--- a/MdePkg/Library/DxeIoLibEsal/IoLibMmioBuffer.c
+++ /dev/null
@@ -1,411 +0,0 @@
-/** @file
- I/O Library MMIO Buffer Functions.
-
- Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php.
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include "DxeIoLibEsalInternal.h"
-
-/**
- Copy data from MMIO region to system memory by using 8-bit access.
-
- Copy data from MMIO region specified by starting address StartAddress
- to system memory specified by Buffer by using 8-bit access. The total
- number of byte to be copied is specified by Length. Buffer is returned.
-
- If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().
- If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
-
-
- @param StartAddress Starting address for the MMIO region to be copied from.
- @param Length Size in bytes of the copy.
- @param Buffer Pointer to a system memory buffer receiving the data read.
-
- @return Buffer
-
-**/
-UINT8 *
-EFIAPI
-MmioReadBuffer8 (
- IN UINTN StartAddress,
- IN UINTN Length,
- OUT UINT8 *Buffer
- )
-{
- UINT8 *ReturnBuffer;
-
- ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));
- ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));
-
- ReturnBuffer = Buffer;
-
- while (Length-- > 0) {
- *(Buffer++) = MmioRead8 (StartAddress++);
- }
-
- return ReturnBuffer;
-}
-
-/**
- Copy data from MMIO region to system memory by using 16-bit access.
-
- Copy data from MMIO region specified by starting address StartAddress
- to system memory specified by Buffer by using 16-bit access. The total
- number of byte to be copied is specified by Length. Buffer is returned.
-
- If StartAddress is not aligned on a 16-bit boundary, then ASSERT().
-
- If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().
- If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
-
- If Length is not aligned on a 16-bit boundary, then ASSERT().
- If Buffer is not aligned on a 16-bit boundary, then ASSERT().
-
- @param StartAddress Starting address for the MMIO region to be copied from.
- @param Length Size in bytes of the copy.
- @param Buffer Pointer to a system memory buffer receiving the data read.
-
- @return Buffer
-
-**/
-UINT16 *
-EFIAPI
-MmioReadBuffer16 (
- IN UINTN StartAddress,
- IN UINTN Length,
- OUT UINT16 *Buffer
- )
-{
- UINT16 *ReturnBuffer;
-
- ASSERT ((StartAddress & (sizeof (UINT16) - 1)) == 0);
-
- ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));
- ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));
-
- ASSERT ((Length & (sizeof (UINT16) - 1)) == 0);
- ASSERT (((UINTN) Buffer & (sizeof (UINT16) - 1)) == 0);
-
- ReturnBuffer = Buffer;
-
- while (Length > 0) {
- *(Buffer++) = MmioRead16 (StartAddress);
- StartAddress += sizeof (UINT16);
- Length -= sizeof (UINT16);
- }
-
- return ReturnBuffer;
-}
-
-/**
- Copy data from MMIO region to system memory by using 32-bit access.
-
- Copy data from MMIO region specified by starting address StartAddress
- to system memory specified by Buffer by using 32-bit access. The total
- number of byte to be copied is specified by Length. Buffer is returned.
-
- If StartAddress is not aligned on a 32-bit boundary, then ASSERT().
-
- If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().
- If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
-
- If Length is not aligned on a 32-bit boundary, then ASSERT().
- If Buffer is not aligned on a 32-bit boundary, then ASSERT().
-
- @param StartAddress Starting address for the MMIO region to be copied from.
- @param Length Size in bytes of the copy.
- @param Buffer Pointer to a system memory buffer receiving the data read.
-
- @return Buffer
-
-**/
-UINT32 *
-EFIAPI
-MmioReadBuffer32 (
- IN UINTN StartAddress,
- IN UINTN Length,
- OUT UINT32 *Buffer
- )
-{
- UINT32 *ReturnBuffer;
-
- ASSERT ((StartAddress & (sizeof (UINT32) - 1)) == 0);
-
- ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));
- ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));
-
- ASSERT ((Length & (sizeof (UINT32) - 1)) == 0);
- ASSERT (((UINTN) Buffer & (sizeof (UINT32) - 1)) == 0);
-
- ReturnBuffer = Buffer;
-
- while (Length > 0) {
- *(Buffer++) = MmioRead32 (StartAddress);
- StartAddress += sizeof (UINT32);
- Length -= sizeof (UINT32);
- }
-
- return ReturnBuffer;
-}
-
-/**
- Copy data from MMIO region to system memory by using 64-bit access.
-
- Copy data from MMIO region specified by starting address StartAddress
- to system memory specified by Buffer by using 64-bit access. The total
- number of byte to be copied is specified by Length. Buffer is returned.
-
- If StartAddress is not aligned on a 64-bit boundary, then ASSERT().
-
- If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().
- If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
-
- If Length is not aligned on a 64-bit boundary, then ASSERT().
- If Buffer is not aligned on a 64-bit boundary, then ASSERT().
-
- @param StartAddress Starting address for the MMIO region to be copied from.
- @param Length Size in bytes of the copy.
- @param Buffer Pointer to a system memory buffer receiving the data read.
-
- @return Buffer
-
-**/
-UINT64 *
-EFIAPI
-MmioReadBuffer64 (
- IN UINTN StartAddress,
- IN UINTN Length,
- OUT UINT64 *Buffer
- )
-{
- UINT64 *ReturnBuffer;
-
- ASSERT ((StartAddress & (sizeof (UINT64) - 1)) == 0);
-
- ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));
- ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));
-
- ASSERT ((Length & (sizeof (UINT64) - 1)) == 0);
- ASSERT (((UINTN) Buffer & (sizeof (UINT64) - 1)) == 0);
-
- ReturnBuffer = Buffer;
-
- while (Length > 0) {
- *(Buffer++) = MmioRead64 (StartAddress);
- StartAddress += sizeof (UINT64);
- Length -= sizeof (UINT64);
- }
-
- return ReturnBuffer;
-}
-
-
-/**
- Copy data from system memory to MMIO region by using 8-bit access.
-
- Copy data from system memory specified by Buffer to MMIO region specified
- by starting address StartAddress by using 8-bit access. The total number
- of byte to be copied is specified by Length. Buffer is returned.
-
- If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().
- If Length is greater than (MAX_ADDRESS -Buffer + 1), then ASSERT().
-
-
- @param StartAddress Starting address for the MMIO region to be copied to.
- @param Length Size in bytes of the copy.
- @param Buffer Pointer to a system memory buffer containing the data to write.
-
- @return Buffer
-
-**/
-UINT8 *
-EFIAPI
-MmioWriteBuffer8 (
- IN UINTN StartAddress,
- IN UINTN Length,
- IN CONST UINT8 *Buffer
- )
-{
- VOID* ReturnBuffer;
-
- ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));
- ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));
-
- ReturnBuffer = (UINT8 *) Buffer;
-
- while (Length-- > 0) {
- MmioWrite8 (StartAddress++, *(Buffer++));
- }
-
- return ReturnBuffer;
-
-}
-
-/**
- Copy data from system memory to MMIO region by using 16-bit access.
-
- Copy data from system memory specified by Buffer to MMIO region specified
- by starting address StartAddress by using 16-bit access. The total number
- of byte to be copied is specified by Length. Buffer is returned.
-
- If StartAddress is not aligned on a 16-bit boundary, then ASSERT().
-
- If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().
- If Length is greater than (MAX_ADDRESS -Buffer + 1), then ASSERT().
-
- If Length is not aligned on a 16-bit boundary, then ASSERT().
-
- If Buffer is not aligned on a 16-bit boundary, then ASSERT().
-
- @param StartAddress Starting address for the MMIO region to be copied to.
- @param Length Size in bytes of the copy.
- @param Buffer Pointer to a system memory buffer containing the data to write.
-
- @return Buffer
-
-**/
-UINT16 *
-EFIAPI
-MmioWriteBuffer16 (
- IN UINTN StartAddress,
- IN UINTN Length,
- IN CONST UINT16 *Buffer
- )
-{
- UINT16 *ReturnBuffer;
-
- ASSERT ((StartAddress & (sizeof (UINT16) - 1)) == 0);
-
- ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));
- ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));
-
- ASSERT ((Length & (sizeof (UINT16) - 1)) == 0);
- ASSERT (((UINTN) Buffer & (sizeof (UINT16) - 1)) == 0);
-
- ReturnBuffer = (UINT16 *) Buffer;
-
- while (Length > 0) {
- MmioWrite16 (StartAddress, *(Buffer++));
-
- StartAddress += sizeof (UINT16);
- Length -= sizeof (UINT16);
- }
-
- return ReturnBuffer;
-}
-
-
-/**
- Copy data from system memory to MMIO region by using 32-bit access.
-
- Copy data from system memory specified by Buffer to MMIO region specified
- by starting address StartAddress by using 32-bit access. The total number
- of byte to be copied is specified by Length. Buffer is returned.
-
- If StartAddress is not aligned on a 32-bit boundary, then ASSERT().
-
- If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().
- If Length is greater than (MAX_ADDRESS -Buffer + 1), then ASSERT().
-
- If Length is not aligned on a 32-bit boundary, then ASSERT().
-
- If Buffer is not aligned on a 32-bit boundary, then ASSERT().
-
- @param StartAddress Starting address for the MMIO region to be copied to.
- @param Length Size in bytes of the copy.
- @param Buffer Pointer to a system memory buffer containing the data to write.
-
- @return Buffer
-
-**/
-UINT32 *
-EFIAPI
-MmioWriteBuffer32 (
- IN UINTN StartAddress,
- IN UINTN Length,
- IN CONST UINT32 *Buffer
- )
-{
- UINT32 *ReturnBuffer;
-
- ASSERT ((StartAddress & (sizeof (UINT32) - 1)) == 0);
-
- ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));
- ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));
-
- ASSERT ((Length & (sizeof (UINT32) - 1)) == 0);
- ASSERT (((UINTN) Buffer & (sizeof (UINT32) - 1)) == 0);
-
- ReturnBuffer = (UINT32 *) Buffer;
-
- while (Length > 0) {
- MmioWrite32 (StartAddress, *(Buffer++));
-
- StartAddress += sizeof (UINT32);
- Length -= sizeof (UINT32);
- }
-
- return ReturnBuffer;
-}
-
-/**
- Copy data from system memory to MMIO region by using 64-bit access.
-
- Copy data from system memory specified by Buffer to MMIO region specified
- by starting address StartAddress by using 64-bit access. The total number
- of byte to be copied is specified by Length. Buffer is returned.
-
- If StartAddress is not aligned on a 64-bit boundary, then ASSERT().
-
- If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().
- If Length is greater than (MAX_ADDRESS -Buffer + 1), then ASSERT().
-
- If Length is not aligned on a 64-bit boundary, then ASSERT().
-
- If Buffer is not aligned on a 64-bit boundary, then ASSERT().
-
- @param StartAddress Starting address for the MMIO region to be copied to.
- @param Length Size in bytes of the copy.
- @param Buffer Pointer to a system memory buffer containing the data to write.
-
- @return Buffer
-
-**/
-UINT64 *
-EFIAPI
-MmioWriteBuffer64 (
- IN UINTN StartAddress,
- IN UINTN Length,
- IN CONST UINT64 *Buffer
- )
-{
- UINT64 *ReturnBuffer;
-
- ASSERT ((StartAddress & (sizeof (UINT64) - 1)) == 0);
-
- ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));
- ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));
-
- ASSERT ((Length & (sizeof (UINT64) - 1)) == 0);
- ASSERT (((UINTN) Buffer & (sizeof (UINT64) - 1)) == 0);
-
- ReturnBuffer = (UINT64 *) Buffer;
-
- while (Length > 0) {
- MmioWrite64 (StartAddress, *(Buffer++));
-
- StartAddress += sizeof (UINT64);
- Length -= sizeof (UINT64);
- }
-
- return ReturnBuffer;
-}
-
diff --git a/MdePkg/Library/DxePalLibEsal/DxePalLibEsal.c b/MdePkg/Library/DxePalLibEsal/DxePalLibEsal.c
deleted file mode 100644
index 6500320456..0000000000
--- a/MdePkg/Library/DxePalLibEsal/DxePalLibEsal.c
+++ /dev/null
@@ -1,73 +0,0 @@
-/** @file
- PAL Library Class implementation built upon Extended SAL Procedures.
-
- Copyright (c) 2007 - 2011, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php.
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include <PiDxe.h>
-
-#include <Protocol/ExtendedSalServiceClasses.h>
-
-#include <Library/PalLib.h>
-#include <Library/ExtendedSalLib.h>
-
-/**
- Makes a PAL procedure call.
-
- This is a wrapper function to make a PAL procedure call. Based on the Index value,
- this API will make static or stacked PAL call. Architected procedures may be designated
- as required or optional. If a PAL procedure is specified as optional, a unique return
- code of 0xFFFFFFFFFFFFFFFF is returned in the Status field of the PAL_CALL_RETURN structure.
- This indicates that the procedure is not present in this PAL implementation. It is the
- caller's responsibility to check for this return code after calling any optional PAL
- procedure. No parameter checking is performed on the 4 input parameters, but there are
- some common rules that the caller should follow when making a PAL call. Any address
- passed to PAL as buffers for return parameters must be 8-byte aligned. Unaligned addresses
- may cause undefined results. For those parameters defined as reserved or some fields
- defined as reserved must be zero filled or the invalid argument return value may be
- returned or undefined result may occur during the execution of the procedure.
- This function is only available on IPF.
-
- @param Index - The PAL procedure Index number.
- @param Arg2 - The 2nd parameter for PAL procedure calls.
- @param Arg3 - The 3rd parameter for PAL procedure calls.
- @param Arg4 - The 4th parameter for PAL procedure calls.
-
- @return structure returned from the PAL Call procedure, including the status and return value.
-
-**/
-PAL_CALL_RETURN
-EFIAPI
-PalCall (
- IN UINT64 Index,
- IN UINT64 Arg2,
- IN UINT64 Arg3,
- IN UINT64 Arg4
- )
-{
- SAL_RETURN_REGS SalReturn;
- PAL_CALL_RETURN *PalReturn;
-
- SalReturn = EsalCall (
- EFI_EXTENDED_SAL_PAL_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_PAL_SERVICES_PROTOCOL_GUID_HI,
- PalProcFunctionId,
- Index,
- Arg2,
- Arg3,
- Arg4,
- 0,
- 0,
- 0
- );
- PalReturn = (PAL_CALL_RETURN *) (UINTN) (&SalReturn);
- return *PalReturn;
-}
diff --git a/MdePkg/Library/DxePalLibEsal/DxePalLibEsal.inf b/MdePkg/Library/DxePalLibEsal/DxePalLibEsal.inf
deleted file mode 100644
index 1340d2902b..0000000000
--- a/MdePkg/Library/DxePalLibEsal/DxePalLibEsal.inf
+++ /dev/null
@@ -1,41 +0,0 @@
-## @file
-# Instance of PAL Library Class using Extended SAL functions
-#
-# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php.
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-##
-
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = DxePalLibEsal
- MODULE_UNI_FILE = DxePalLibEsal.uni
- FILE_GUID = 8BA65DE3-39E1-4afd-A8FE-7DD0BAFEFCC0
- MODULE_TYPE = DXE_DRIVER
- VERSION_STRING = 1.0
- LIBRARY_CLASS = PalLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
-
-#
-# The following information is for reference only and not required by the build tools.
-#
-# VALID_ARCHITECTURES = IPF
-#
-
-[Sources.IPF]
- DxePalLibEsal.c
-
-[Packages]
- MdePkg/MdePkg.dec
-
-[LibraryClasses]
- ExtendedSalLib
-
-[Depex.common.DXE_DRIVER, Depex.common.DXE_RUNTIME_DRIVER, Depex.common.DXE_SAL_DRIVER, Depex.common.DXE_SMM_DRIVER]
- gEfiExtendedSalPalServicesProtocolGuid
-
diff --git a/MdePkg/Library/DxePcdLib/DxePcdLib.inf b/MdePkg/Library/DxePcdLib/DxePcdLib.inf
index 23cd5d6e70..9c6d76669b 100644
--- a/MdePkg/Library/DxePcdLib/DxePcdLib.inf
+++ b/MdePkg/Library/DxePcdLib/DxePcdLib.inf
@@ -37,10 +37,10 @@
FILE_GUID = af97eb89-4cc6-45f8-a514-ca025b346480
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
- LIBRARY_CLASS = PcdLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER SMM_CORE UEFI_APPLICATION UEFI_DRIVER
+ LIBRARY_CLASS = PcdLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER SMM_CORE UEFI_APPLICATION UEFI_DRIVER
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]
diff --git a/MdePkg/Library/DxePciLibEsal/DxePciLibEsal.inf b/MdePkg/Library/DxePciLibEsal/DxePciLibEsal.inf
deleted file mode 100644
index da7772d9c3..0000000000
--- a/MdePkg/Library/DxePciLibEsal/DxePciLibEsal.inf
+++ /dev/null
@@ -1,40 +0,0 @@
-## @file
-# PCI Library that uses ESAL services to perform PCI Configuration cycles.
-#
-# Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php.
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-##
-
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = DxePciLibEsal
- MODULE_UNI_FILE = DxePciLibEsal.uni
- FILE_GUID = E3441740-3B41-4c90-9C9D-964056C7417D
- MODULE_TYPE = DXE_DRIVER
- VERSION_STRING = 1.0
- LIBRARY_CLASS = PciLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
-
-#
-# The following information is for reference only and not required by the build tools.
-#
-# VALID_ARCHITECTURES = IPF
-#
-
-[Sources]
- PciLib.c
-
-[Packages]
- MdePkg/MdePkg.dec
-
-[LibraryClasses]
- ExtendedSalLib
- DebugLib
- BaseLib
-
diff --git a/MdePkg/Library/DxePciLibEsal/PciLib.c b/MdePkg/Library/DxePciLibEsal/PciLib.c
deleted file mode 100644
index 28b01c905e..0000000000
--- a/MdePkg/Library/DxePciLibEsal/PciLib.c
+++ /dev/null
@@ -1,1464 +0,0 @@
-/** @file
- DXE PCI Library instance layered on top of ESAL services.
-
- Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php.
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include <PiDxe.h>
-
-#include <Protocol/ExtendedSalServiceClasses.h>
-
-#include <Library/PciLib.h>
-#include <Library/BaseLib.h>
-#include <Library/DebugLib.h>
-#include <Library/ExtendedSalLib.h>
-
-/**
- Assert the validity of a PCI address. A valid PCI address should contain 1's
- only in the low 28 bits.
-
- @param A The address to validate.
- @param M Additional bits to assert to be zero.
-
-**/
-#define ASSERT_INVALID_PCI_ADDRESS(A,M) \
- ASSERT (((A) & (~0xfffffff | (M))) == 0)
-
-/**
- Converts a PCI Library Address to a ESAL PCI Service Address.
- Based on SAL Spec 3.2, there are two SAL PCI Address:
-
- If address type = 0
- Bits 0..7 - Register address
- Bits 8..10 - Function number
- Bits 11..15 - Device number
- Bits 16..23 - Bus number
- Bits 24..31 - PCI segment group
- Bits 32..63 - Reserved (0)
-
- If address type = 1
- Bits 0..7 - Register address
- Bits 8..11 - Extended Register address
- Bits 12..14 - Function number
- Bits 15..19 - Device number
- Bits 20..27 - Bus number
- Bits 28..43 - PCI segment group
- Bits 44..63 - Reserved (0)
-
- @param A The PCI Library Address to convert.
-
-**/
-#define CONVERT_PCI_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS0(Address) ((((Address) >> 4) & 0x00ffff00) | ((Address) & 0xff))
-#define CONVERT_PCI_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS1(Address) (Address)
-
-/**
- Check a PCI Library Address is a PCI Compatible Address or not.
-**/
-#define IS_PCI_COMPATIBLE_ADDRESS(Address) (((Address) & 0xf00) == 0)
-
-/**
- Internal worker function to read a PCI configuration register.
-
- This function wraps EsalPciConfigRead function of Extended SAL PCI
- Services Class.
- It reads and returns the PCI configuration register specified by Address,
- the width of data is specified by Width.
-
- @param Address Address that encodes the PCI Bus, Device, Function and
- Register.
- @param Width Width of data to read
-
- @return The value read from the PCI configuration register.
-
-**/
-UINT32
-DxePciLibEsalReadWorker (
- IN UINTN Address,
- IN UINTN Width
- )
-{
- SAL_RETURN_REGS Return;
-
- if (IS_PCI_COMPATIBLE_ADDRESS(Address)) {
- Return = EsalCall (
- EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_HI,
- SalPciConfigReadFunctionId,
- CONVERT_PCI_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS0 (Address),
- Width,
- EFI_SAL_PCI_COMPATIBLE_ADDRESS,
- 0,
- 0,
- 0,
- 0
- );
- } else {
- Return = EsalCall (
- EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_HI,
- SalPciConfigReadFunctionId,
- CONVERT_PCI_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS1 (Address),
- Width,
- EFI_SAL_PCI_EXTENDED_REGISTER_ADDRESS,
- 0,
- 0,
- 0,
- 0
- );
- }
-
- return (UINT32) Return.r9;
-}
-
-/**
- Internal worker function to writes a PCI configuration register.
-
- This function wraps EsalPciConfigWrite function of Extended SAL PCI
- Services Class.
- It writes the PCI configuration register specified by Address with the
- value specified by Data. The width of data is specified by Width.
- Data is returned.
-
- @param Address Address that encodes the PCI Bus, Device, Function and
- Register.
- @param Width Width of data to write
- @param Data The value to write.
-
- @return The value written to the PCI configuration register.
-
-**/
-UINT32
-DxePciLibEsalWriteWorker (
- IN UINTN Address,
- IN UINTN Width,
- IN UINT32 Data
- )
-{
- if (IS_PCI_COMPATIBLE_ADDRESS(Address)) {
- EsalCall (
- EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_HI,
- SalPciConfigWriteFunctionId,
- CONVERT_PCI_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS0 (Address),
- Width,
- Data,
- EFI_SAL_PCI_COMPATIBLE_ADDRESS,
- 0,
- 0,
- 0
- );
- } else {
- EsalCall (
- EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_HI,
- SalPciConfigWriteFunctionId,
- CONVERT_PCI_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS1 (Address),
- Width,
- Data,
- EFI_SAL_PCI_EXTENDED_REGISTER_ADDRESS,
- 0,
- 0,
- 0
- );
- }
-
- return Data;
-}
-
-/**
- Register a PCI device so PCI configuration registers may be accessed after
- SetVirtualAddressMap().
-
- If Address > 0x0FFFFFFF, then ASSERT().
-
- @param Address Address that encodes the PCI Bus, Device, Function and
- Register.
-
- @retval RETURN_SUCCESS The PCI device was registered for runtime access.
- @retval RETURN_UNSUPPORTED An attempt was made to call this function
- after ExitBootServices().
- @retval RETURN_UNSUPPORTED The resources required to access the PCI device
- at runtime could not be mapped.
- @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
- complete the registration.
-
-**/
-RETURN_STATUS
-EFIAPI
-PciRegisterForRuntimeAccess (
- IN UINTN Address
- )
-{
- ASSERT_INVALID_PCI_ADDRESS (Address, 0);
- return RETURN_SUCCESS;
-}
-
-/**
- Reads an 8-bit PCI configuration register.
-
- Reads and returns the 8-bit PCI configuration register specified by Address.
- This function must guarantee that all PCI read and write operations are
- serialized.
-
- If Address > 0x0FFFFFFF, then ASSERT().
-
- @param Address Address that encodes the PCI Bus, Device, Function and
- Register.
-
- @return The value read from the PCI configuration register.
-
-**/
-UINT8
-EFIAPI
-PciRead8 (
- IN UINTN Address
- )
-{
- ASSERT_INVALID_PCI_ADDRESS (Address, 0);
-
- return (UINT8) DxePciLibEsalReadWorker (Address, 1);
-}
-
-/**
- Writes an 8-bit PCI configuration register.
-
- Writes the 8-bit PCI configuration register specified by Address with the
- value specified by Value. Value is returned. This function must guarantee
- that all PCI read and write operations are serialized.
-
- If Address > 0x0FFFFFFF, then ASSERT().
-
- @param Address Address that encodes the PCI Bus, Device, Function and
- Register.
- @param Data The value to write.
-
- @return The value written to the PCI configuration register.
-
-**/
-UINT8
-EFIAPI
-PciWrite8 (
- IN UINTN Address,
- IN UINT8 Data
- )
-{
- ASSERT_INVALID_PCI_ADDRESS (Address, 0);
-
- return (UINT8) DxePciLibEsalWriteWorker (Address, 1, Data);
-}
-
-/**
- Performs a bitwise OR of an 8-bit PCI configuration register with
- an 8-bit value.
-
- Reads the 8-bit PCI configuration register specified by Address, performs a
- bitwise OR between the read result and the value specified by
- OrData, and writes the result to the 8-bit PCI configuration register
- specified by Address. The value written to the PCI configuration register is
- returned. This function must guarantee that all PCI read and write operations
- are serialized.
-
- If Address > 0x0FFFFFFF, then ASSERT().
-
- @param Address Address that encodes the PCI Bus, Device, Function and
- Register.
- @param OrData The value to OR with the PCI configuration register.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT8
-EFIAPI
-PciOr8 (
- IN UINTN Address,
- IN UINT8 OrData
- )
-{
- return PciWrite8 (Address, (UINT8)(PciRead8 (Address) | OrData));
-}
-
-/**
- Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
- value.
-
- Reads the 8-bit PCI configuration register specified by Address, performs a
- bitwise AND between the read result and the value specified by AndData, and
- writes the result to the 8-bit PCI configuration register specified by
- Address. The value written to the PCI configuration register is returned.
- This function must guarantee that all PCI read and write operations are
- serialized.
-
- If Address > 0x0FFFFFFF, then ASSERT().
-
- @param Address Address that encodes the PCI Bus, Device, Function and
- Register.
- @param AndData The value to AND with the PCI configuration register.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT8
-EFIAPI
-PciAnd8 (
- IN UINTN Address,
- IN UINT8 AndData
- )
-{
- return PciWrite8 (Address, (UINT8)(PciRead8 (Address) & AndData));
-}
-
-/**
- Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
- value, followed a bitwise OR with another 8-bit value.
-
- Reads the 8-bit PCI configuration register specified by Address, performs a
- bitwise AND between the read result and the value specified by AndData,
- performs a bitwise OR between the result of the AND operation and
- the value specified by OrData, and writes the result to the 8-bit PCI
- configuration register specified by Address. The value written to the PCI
- configuration register is returned. This function must guarantee that all PCI
- read and write operations are serialized.
-
- If Address > 0x0FFFFFFF, then ASSERT().
-
- @param Address Address that encodes the PCI Bus, Device, Function and
- Register.
- @param AndData The value to AND with the PCI configuration register.
- @param OrData The value to OR with the result of the AND operation.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT8
-EFIAPI
-PciAndThenOr8 (
- IN UINTN Address,
- IN UINT8 AndData,
- IN UINT8 OrData
- )
-{
- return PciWrite8 (Address, (UINT8)((PciRead8 (Address) & AndData) | OrData));
-}
-
-/**
- Reads a bit field of a PCI configuration register.
-
- Reads the bit field in an 8-bit PCI configuration register. The bit field is
- specified by the StartBit and the EndBit. The value of the bit field is
- returned.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If StartBit is greater than 7, then ASSERT().
- If EndBit is greater than 7, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
-
- @param Address PCI configuration register to read.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..7.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..7.
-
- @return The value of the bit field read from the PCI configuration register.
-
-**/
-UINT8
-EFIAPI
-PciBitFieldRead8 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit
- )
-{
- return BitFieldRead8 (PciRead8 (Address), StartBit, EndBit);
-}
-
-/**
- Writes a bit field to a PCI configuration register.
-
- Writes Value to the bit field of the PCI configuration register. The bit
- field is specified by the StartBit and the EndBit. All other bits in the
- destination PCI configuration register are preserved. The new value of the
- 8-bit register is returned.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If StartBit is greater than 7, then ASSERT().
- If EndBit is greater than 7, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Address PCI configuration register to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..7.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..7.
- @param Value New value of the bit field.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT8
-EFIAPI
-PciBitFieldWrite8 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 Value
- )
-{
- return PciWrite8 (
- Address,
- BitFieldWrite8 (PciRead8 (Address), StartBit, EndBit, Value)
- );
-}
-
-/**
- Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
- writes the result back to the bit field in the 8-bit port.
-
- Reads the 8-bit PCI configuration register specified by Address, performs a
- bitwise OR between the read result and the value specified by
- OrData, and writes the result to the 8-bit PCI configuration register
- specified by Address. The value written to the PCI configuration register is
- returned. This function must guarantee that all PCI read and write operations
- are serialized. Extra left bits in OrData are stripped.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If StartBit is greater than 7, then ASSERT().
- If EndBit is greater than 7, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Address PCI configuration register to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..7.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..7.
- @param OrData The value to OR with the PCI configuration register.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT8
-EFIAPI
-PciBitFieldOr8 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 OrData
- )
-{
- return PciWrite8 (
- Address,
- BitFieldOr8 (PciRead8 (Address), StartBit, EndBit, OrData)
- );
-}
-
-/**
- Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
- AND, and writes the result back to the bit field in the 8-bit register.
-
- Reads the 8-bit PCI configuration register specified by Address, performs a
- bitwise AND between the read result and the value specified by AndData, and
- writes the result to the 8-bit PCI configuration register specified by
- Address. The value written to the PCI configuration register is returned.
- This function must guarantee that all PCI read and write operations are
- serialized. Extra left bits in AndData are stripped.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If StartBit is greater than 7, then ASSERT().
- If EndBit is greater than 7, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Address PCI configuration register to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..7.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..7.
- @param AndData The value to AND with the PCI configuration register.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT8
-EFIAPI
-PciBitFieldAnd8 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 AndData
- )
-{
- return PciWrite8 (
- Address,
- BitFieldAnd8 (PciRead8 (Address), StartBit, EndBit, AndData)
- );
-}
-
-/**
- Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
- bitwise OR, and writes the result back to the bit field in the
- 8-bit port.
-
- Reads the 8-bit PCI configuration register specified by Address, performs a
- bitwise AND followed by a bitwise OR between the read result and
- the value specified by AndData, and writes the result to the 8-bit PCI
- configuration register specified by Address. The value written to the PCI
- configuration register is returned. This function must guarantee that all PCI
- read and write operations are serialized. Extra left bits in both AndData and
- OrData are stripped.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If StartBit is greater than 7, then ASSERT().
- If EndBit is greater than 7, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Address PCI configuration register to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..7.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..7.
- @param AndData The value to AND with the PCI configuration register.
- @param OrData The value to OR with the result of the AND operation.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT8
-EFIAPI
-PciBitFieldAndThenOr8 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 AndData,
- IN UINT8 OrData
- )
-{
- return PciWrite8 (
- Address,
- BitFieldAndThenOr8 (PciRead8 (Address), StartBit, EndBit, AndData, OrData)
- );
-}
-
-/**
- Reads a 16-bit PCI configuration register.
-
- Reads and returns the 16-bit PCI configuration register specified by Address.
- This function must guarantee that all PCI read and write operations are
- serialized.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If Address is not aligned on a 16-bit boundary, then ASSERT().
-
- @param Address Address that encodes the PCI Bus, Device, Function and
- Register.
-
- @return The value read from the PCI configuration register.
-
-**/
-UINT16
-EFIAPI
-PciRead16 (
- IN UINTN Address
- )
-{
- ASSERT_INVALID_PCI_ADDRESS (Address, 1);
-
- return (UINT16) DxePciLibEsalReadWorker (Address, 2);
-}
-
-/**
- Writes a 16-bit PCI configuration register.
-
- Writes the 16-bit PCI configuration register specified by Address with the
- value specified by Value. Value is returned. This function must guarantee
- that all PCI read and write operations are serialized.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If Address is not aligned on a 16-bit boundary, then ASSERT().
-
- @param Address Address that encodes the PCI Bus, Device, Function and
- Register.
- @param Data The value to write.
-
- @return The value written to the PCI configuration register.
-
-**/
-UINT16
-EFIAPI
-PciWrite16 (
- IN UINTN Address,
- IN UINT16 Data
- )
-{
- ASSERT_INVALID_PCI_ADDRESS (Address, 1);
-
- return (UINT16) DxePciLibEsalWriteWorker (Address, 2, Data);
-}
-
-/**
- Performs a bitwise OR of a 16-bit PCI configuration register with
- a 16-bit value.
-
- Reads the 16-bit PCI configuration register specified by Address, performs a
- bitwise OR between the read result and the value specified by
- OrData, and writes the result to the 16-bit PCI configuration register
- specified by Address. The value written to the PCI configuration register is
- returned. This function must guarantee that all PCI read and write operations
- are serialized.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If Address is not aligned on a 16-bit boundary, then ASSERT().
-
- @param Address Address that encodes the PCI Bus, Device, Function and
- Register.
- @param OrData The value to OR with the PCI configuration register.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT16
-EFIAPI
-PciOr16 (
- IN UINTN Address,
- IN UINT16 OrData
- )
-{
- return PciWrite16 (Address, (UINT16)(PciRead16 (Address) | OrData));
-}
-
-/**
- Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
- value.
-
- Reads the 16-bit PCI configuration register specified by Address, performs a
- bitwise AND between the read result and the value specified by AndData, and
- writes the result to the 16-bit PCI configuration register specified by
- Address. The value written to the PCI configuration register is returned.
- This function must guarantee that all PCI read and write operations are
- serialized.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If Address is not aligned on a 16-bit boundary, then ASSERT().
-
- @param Address Address that encodes the PCI Bus, Device, Function and
- Register.
- @param AndData The value to AND with the PCI configuration register.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT16
-EFIAPI
-PciAnd16 (
- IN UINTN Address,
- IN UINT16 AndData
- )
-{
- return PciWrite16 (Address, (UINT16)(PciRead16 (Address) & AndData));
-}
-
-/**
- Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
- value, followed a bitwise OR with another 16-bit value.
-
- Reads the 16-bit PCI configuration register specified by Address, performs a
- bitwise AND between the read result and the value specified by AndData,
- performs a bitwise OR between the result of the AND operation and
- the value specified by OrData, and writes the result to the 16-bit PCI
- configuration register specified by Address. The value written to the PCI
- configuration register is returned. This function must guarantee that all PCI
- read and write operations are serialized.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If Address is not aligned on a 16-bit boundary, then ASSERT().
-
- @param Address Address that encodes the PCI Bus, Device, Function and
- Register.
- @param AndData The value to AND with the PCI configuration register.
- @param OrData The value to OR with the result of the AND operation.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT16
-EFIAPI
-PciAndThenOr16 (
- IN UINTN Address,
- IN UINT16 AndData,
- IN UINT16 OrData
- )
-{
- return PciWrite16 (Address, (UINT16)((PciRead16 (Address) & AndData) | OrData));
-}
-
-/**
- Reads a bit field of a PCI configuration register.
-
- Reads the bit field in a 16-bit PCI configuration register. The bit field is
- specified by the StartBit and the EndBit. The value of the bit field is
- returned.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If Address is not aligned on a 16-bit boundary, then ASSERT().
- If StartBit is greater than 15, then ASSERT().
- If EndBit is greater than 15, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
-
- @param Address PCI configuration register to read.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..15.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..15.
-
- @return The value of the bit field read from the PCI configuration register.
-
-**/
-UINT16
-EFIAPI
-PciBitFieldRead16 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit
- )
-{
- return BitFieldRead16 (PciRead16 (Address), StartBit, EndBit);
-}
-
-/**
- Writes a bit field to a PCI configuration register.
-
- Writes Value to the bit field of the PCI configuration register. The bit
- field is specified by the StartBit and the EndBit. All other bits in the
- destination PCI configuration register are preserved. The new value of the
- 16-bit register is returned.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If Address is not aligned on a 16-bit boundary, then ASSERT().
- If StartBit is greater than 15, then ASSERT().
- If EndBit is greater than 15, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Address PCI configuration register to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..15.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..15.
- @param Value New value of the bit field.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT16
-EFIAPI
-PciBitFieldWrite16 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 Value
- )
-{
- return PciWrite16 (
- Address,
- BitFieldWrite16 (PciRead16 (Address), StartBit, EndBit, Value)
- );
-}
-
-/**
- Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
- writes the result back to the bit field in the 16-bit port.
-
- Reads the 16-bit PCI configuration register specified by Address, performs a
- bitwise OR between the read result and the value specified by
- OrData, and writes the result to the 16-bit PCI configuration register
- specified by Address. The value written to the PCI configuration register is
- returned. This function must guarantee that all PCI read and write operations
- are serialized. Extra left bits in OrData are stripped.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If Address is not aligned on a 16-bit boundary, then ASSERT().
- If StartBit is greater than 15, then ASSERT().
- If EndBit is greater than 15, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Address PCI configuration register to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..15.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..15.
- @param OrData The value to OR with the PCI configuration register.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT16
-EFIAPI
-PciBitFieldOr16 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 OrData
- )
-{
- return PciWrite16 (
- Address,
- BitFieldOr16 (PciRead16 (Address), StartBit, EndBit, OrData)
- );
-}
-
-/**
- Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
- AND, and writes the result back to the bit field in the 16-bit register.
-
- Reads the 16-bit PCI configuration register specified by Address, performs a
- bitwise AND between the read result and the value specified by AndData, and
- writes the result to the 16-bit PCI configuration register specified by
- Address. The value written to the PCI configuration register is returned.
- This function must guarantee that all PCI read and write operations are
- serialized. Extra left bits in AndData are stripped.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If Address is not aligned on a 16-bit boundary, then ASSERT().
- If StartBit is greater than 15, then ASSERT().
- If EndBit is greater than 15, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Address PCI configuration register to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..15.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..15.
- @param AndData The value to AND with the PCI configuration register.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT16
-EFIAPI
-PciBitFieldAnd16 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 AndData
- )
-{
- return PciWrite16 (
- Address,
- BitFieldAnd16 (PciRead16 (Address), StartBit, EndBit, AndData)
- );
-}
-
-/**
- Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
- bitwise OR, and writes the result back to the bit field in the
- 16-bit port.
-
- Reads the 16-bit PCI configuration register specified by Address, performs a
- bitwise AND followed by a bitwise OR between the read result and
- the value specified by AndData, and writes the result to the 16-bit PCI
- configuration register specified by Address. The value written to the PCI
- configuration register is returned. This function must guarantee that all PCI
- read and write operations are serialized. Extra left bits in both AndData and
- OrData are stripped.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If Address is not aligned on a 16-bit boundary, then ASSERT().
- If StartBit is greater than 15, then ASSERT().
- If EndBit is greater than 15, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Address PCI configuration register to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..15.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..15.
- @param AndData The value to AND with the PCI configuration register.
- @param OrData The value to OR with the result of the AND operation.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT16
-EFIAPI
-PciBitFieldAndThenOr16 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 AndData,
- IN UINT16 OrData
- )
-{
- return PciWrite16 (
- Address,
- BitFieldAndThenOr16 (PciRead16 (Address), StartBit, EndBit, AndData, OrData)
- );
-}
-
-/**
- Reads a 32-bit PCI configuration register.
-
- Reads and returns the 32-bit PCI configuration register specified by Address.
- This function must guarantee that all PCI read and write operations are
- serialized.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If Address is not aligned on a 32-bit boundary, then ASSERT().
-
- @param Address Address that encodes the PCI Bus, Device, Function and
- Register.
-
- @return The value read from the PCI configuration register.
-
-**/
-UINT32
-EFIAPI
-PciRead32 (
- IN UINTN Address
- )
-{
- ASSERT_INVALID_PCI_ADDRESS (Address, 3);
-
- return DxePciLibEsalReadWorker (Address, 4);
-}
-
-/**
- Writes a 32-bit PCI configuration register.
-
- Writes the 32-bit PCI configuration register specified by Address with the
- value specified by Value. Value is returned. This function must guarantee
- that all PCI read and write operations are serialized.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If Address is not aligned on a 32-bit boundary, then ASSERT().
-
- @param Address Address that encodes the PCI Bus, Device, Function and
- Register.
- @param Data The value to write.
-
- @return The value written to the PCI configuration register.
-
-**/
-UINT32
-EFIAPI
-PciWrite32 (
- IN UINTN Address,
- IN UINT32 Data
- )
-{
- ASSERT_INVALID_PCI_ADDRESS (Address, 3);
-
- return DxePciLibEsalWriteWorker (Address, 4, Data);
-}
-
-/**
- Performs a bitwise OR of a 32-bit PCI configuration register with
- a 32-bit value.
-
- Reads the 32-bit PCI configuration register specified by Address, performs a
- bitwise OR between the read result and the value specified by
- OrData, and writes the result to the 32-bit PCI configuration register
- specified by Address. The value written to the PCI configuration register is
- returned. This function must guarantee that all PCI read and write operations
- are serialized.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If Address is not aligned on a 32-bit boundary, then ASSERT().
-
- @param Address Address that encodes the PCI Bus, Device, Function and
- Register.
- @param OrData The value to OR with the PCI configuration register.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT32
-EFIAPI
-PciOr32 (
- IN UINTN Address,
- IN UINT32 OrData
- )
-{
- return PciWrite32 (Address, PciRead32 (Address) | OrData);
-}
-
-/**
- Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
- value.
-
- Reads the 32-bit PCI configuration register specified by Address, performs a
- bitwise AND between the read result and the value specified by AndData, and
- writes the result to the 32-bit PCI configuration register specified by
- Address. The value written to the PCI configuration register is returned.
- This function must guarantee that all PCI read and write operations are
- serialized.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If Address is not aligned on a 32-bit boundary, then ASSERT().
-
- @param Address Address that encodes the PCI Bus, Device, Function and
- Register.
- @param AndData The value to AND with the PCI configuration register.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT32
-EFIAPI
-PciAnd32 (
- IN UINTN Address,
- IN UINT32 AndData
- )
-{
- return PciWrite32 (Address, PciRead32 (Address) & AndData);
-}
-
-/**
- Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
- value, followed a bitwise OR with another 32-bit value.
-
- Reads the 32-bit PCI configuration register specified by Address, performs a
- bitwise AND between the read result and the value specified by AndData,
- performs a bitwise OR between the result of the AND operation and
- the value specified by OrData, and writes the result to the 32-bit PCI
- configuration register specified by Address. The value written to the PCI
- configuration register is returned. This function must guarantee that all PCI
- read and write operations are serialized.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If Address is not aligned on a 32-bit boundary, then ASSERT().
-
- @param Address Address that encodes the PCI Bus, Device, Function and
- Register.
- @param AndData The value to AND with the PCI configuration register.
- @param OrData The value to OR with the result of the AND operation.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT32
-EFIAPI
-PciAndThenOr32 (
- IN UINTN Address,
- IN UINT32 AndData,
- IN UINT32 OrData
- )
-{
- return PciWrite32 (Address, (PciRead32 (Address) & AndData) | OrData);
-}
-
-/**
- Reads a bit field of a PCI configuration register.
-
- Reads the bit field in a 32-bit PCI configuration register. The bit field is
- specified by the StartBit and the EndBit. The value of the bit field is
- returned.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If Address is not aligned on a 32-bit boundary, then ASSERT().
- If StartBit is greater than 31, then ASSERT().
- If EndBit is greater than 31, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
-
- @param Address PCI configuration register to read.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..31.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..31.
-
- @return The value of the bit field read from the PCI configuration register.
-
-**/
-UINT32
-EFIAPI
-PciBitFieldRead32 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit
- )
-{
- return BitFieldRead32 (PciRead32 (Address), StartBit, EndBit);
-}
-
-/**
- Writes a bit field to a PCI configuration register.
-
- Writes Value to the bit field of the PCI configuration register. The bit
- field is specified by the StartBit and the EndBit. All other bits in the
- destination PCI configuration register are preserved. The new value of the
- 32-bit register is returned.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If Address is not aligned on a 32-bit boundary, then ASSERT().
- If StartBit is greater than 31, then ASSERT().
- If EndBit is greater than 31, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Address PCI configuration register to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..31.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..31.
- @param Value New value of the bit field.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT32
-EFIAPI
-PciBitFieldWrite32 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 Value
- )
-{
- return PciWrite32 (
- Address,
- BitFieldWrite32 (PciRead32 (Address), StartBit, EndBit, Value)
- );
-}
-
-/**
- Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
- writes the result back to the bit field in the 32-bit port.
-
- Reads the 32-bit PCI configuration register specified by Address, performs a
- bitwise OR between the read result and the value specified by
- OrData, and writes the result to the 32-bit PCI configuration register
- specified by Address. The value written to the PCI configuration register is
- returned. This function must guarantee that all PCI read and write operations
- are serialized. Extra left bits in OrData are stripped.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If Address is not aligned on a 32-bit boundary, then ASSERT().
- If StartBit is greater than 31, then ASSERT().
- If EndBit is greater than 31, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Address PCI configuration register to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..31.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..31.
- @param OrData The value to OR with the PCI configuration register.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT32
-EFIAPI
-PciBitFieldOr32 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 OrData
- )
-{
- return PciWrite32 (
- Address,
- BitFieldOr32 (PciRead32 (Address), StartBit, EndBit, OrData)
- );
-}
-
-/**
- Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
- AND, and writes the result back to the bit field in the 32-bit register.
-
- Reads the 32-bit PCI configuration register specified by Address, performs a
- bitwise AND between the read result and the value specified by AndData, and
- writes the result to the 32-bit PCI configuration register specified by
- Address. The value written to the PCI configuration register is returned.
- This function must guarantee that all PCI read and write operations are
- serialized. Extra left bits in AndData are stripped.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If Address is not aligned on a 32-bit boundary, then ASSERT().
- If StartBit is greater than 31, then ASSERT().
- If EndBit is greater than 31, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Address PCI configuration register to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..31.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..31.
- @param AndData The value to AND with the PCI configuration register.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT32
-EFIAPI
-PciBitFieldAnd32 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 AndData
- )
-{
- return PciWrite32 (
- Address,
- BitFieldAnd32 (PciRead32 (Address), StartBit, EndBit, AndData)
- );
-}
-
-/**
- Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
- bitwise OR, and writes the result back to the bit field in the
- 32-bit port.
-
- Reads the 32-bit PCI configuration register specified by Address, performs a
- bitwise AND followed by a bitwise OR between the read result and
- the value specified by AndData, and writes the result to the 32-bit PCI
- configuration register specified by Address. The value written to the PCI
- configuration register is returned. This function must guarantee that all PCI
- read and write operations are serialized. Extra left bits in both AndData and
- OrData are stripped.
-
- If Address > 0x0FFFFFFF, then ASSERT().
- If Address is not aligned on a 32-bit boundary, then ASSERT().
- If StartBit is greater than 31, then ASSERT().
- If EndBit is greater than 31, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Address PCI configuration register to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..31.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..31.
- @param AndData The value to AND with the PCI configuration register.
- @param OrData The value to OR with the result of the AND operation.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT32
-EFIAPI
-PciBitFieldAndThenOr32 (
- IN UINTN Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 AndData,
- IN UINT32 OrData
- )
-{
- return PciWrite32 (
- Address,
- BitFieldAndThenOr32 (PciRead32 (Address), StartBit, EndBit, AndData, OrData)
- );
-}
-
-/**
- Reads a range of PCI configuration registers into a caller supplied buffer.
-
- Reads the range of PCI configuration registers specified by StartAddress and
- Size into the buffer specified by Buffer. This function only allows the PCI
- configuration registers from a single PCI function to be read. Size is
- returned. When possible 32-bit PCI configuration read cycles are used to read
- from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
- and 16-bit PCI configuration read cycles may be used at the beginning and the
- end of the range.
-
- If StartAddress > 0x0FFFFFFF, then ASSERT().
- If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
- If Size > 0 and Buffer is NULL, then ASSERT().
-
- @param StartAddress Starting address that encodes the PCI Bus, Device,
- Function and Register.
- @param Size Size in bytes of the transfer.
- @param Buffer Pointer to a buffer receiving the data read.
-
- @return Size
-
-**/
-UINTN
-EFIAPI
-PciReadBuffer (
- IN UINTN StartAddress,
- IN UINTN Size,
- OUT VOID *Buffer
- )
-{
- UINTN ReturnValue;
-
- ASSERT_INVALID_PCI_ADDRESS (StartAddress, 0);
- ASSERT (((StartAddress & 0xFFF) + Size) <= 0x100);
-
- if (Size == 0) {
- return Size;
- }
-
- ASSERT (Buffer != NULL);
-
- //
- // Save Size for return
- //
- ReturnValue = Size;
-
- if ((StartAddress & 1) != 0) {
- //
- // Read a byte if StartAddress is byte aligned
- //
- *(volatile UINT8 *)Buffer = PciRead8 (StartAddress);
- StartAddress += sizeof (UINT8);
- Size -= sizeof (UINT8);
- Buffer = (UINT8*)Buffer + 1;
- }
-
- if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {
- //
- // Read a word if StartAddress is word aligned
- //
- *(volatile UINT16 *)Buffer = PciRead16 (StartAddress);
- StartAddress += sizeof (UINT16);
- Size -= sizeof (UINT16);
- Buffer = (UINT16*)Buffer + 1;
- }
-
- while (Size >= sizeof (UINT32)) {
- //
- // Read as many double words as possible
- //
- *(volatile UINT32 *)Buffer = PciRead32 (StartAddress);
- StartAddress += sizeof (UINT32);
- Size -= sizeof (UINT32);
- Buffer = (UINT32*)Buffer + 1;
- }
-
- if (Size >= sizeof (UINT16)) {
- //
- // Read the last remaining word if exist
- //
- *(volatile UINT16 *)Buffer = PciRead16 (StartAddress);
- StartAddress += sizeof (UINT16);
- Size -= sizeof (UINT16);
- Buffer = (UINT16*)Buffer + 1;
- }
-
- if (Size >= sizeof (UINT8)) {
- //
- // Read the last remaining byte if exist
- //
- *(volatile UINT8 *)Buffer = PciRead8 (StartAddress);
- }
-
- return ReturnValue;
-}
-
-/**
- Copies the data in a caller supplied buffer to a specified range of PCI
- configuration space.
-
- Writes the range of PCI configuration registers specified by StartAddress and
- Size from the buffer specified by Buffer. This function only allows the PCI
- configuration registers from a single PCI function to be written. Size is
- returned. When possible 32-bit PCI configuration write cycles are used to
- write from StartAdress to StartAddress + Size. Due to alignment restrictions,
- 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
- and the end of the range.
-
- If StartAddress > 0x0FFFFFFF, then ASSERT().
- If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
- If Size > 0 and Buffer is NULL, then ASSERT().
-
- @param StartAddress Starting address that encodes the PCI Bus, Device,
- Function and Register.
- @param Size Size in bytes of the transfer.
- @param Buffer Pointer to a buffer containing the data to write.
-
- @return Size
-
-**/
-UINTN
-EFIAPI
-PciWriteBuffer (
- IN UINTN StartAddress,
- IN UINTN Size,
- IN VOID *Buffer
- )
-{
- UINTN ReturnValue;
-
- ASSERT_INVALID_PCI_ADDRESS (StartAddress, 0);
- ASSERT (((StartAddress & 0xFFF) + Size) <= 0x100);
-
- if (Size == 0) {
- return 0;
- }
-
- ASSERT (Buffer != NULL);
-
- //
- // Save Size for return
- //
- ReturnValue = Size;
-
- if ((StartAddress & 1) != 0) {
- //
- // Write a byte if StartAddress is byte aligned
- //
- PciWrite8 (StartAddress, *(UINT8*)Buffer);
- StartAddress += sizeof (UINT8);
- Size -= sizeof (UINT8);
- Buffer = (UINT8*)Buffer + 1;
- }
-
- if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {
- //
- // Write a word if StartAddress is word aligned
- //
- PciWrite16 (StartAddress, *(UINT16*)Buffer);
- StartAddress += sizeof (UINT16);
- Size -= sizeof (UINT16);
- Buffer = (UINT16*)Buffer + 1;
- }
-
- while (Size >= sizeof (UINT32)) {
- //
- // Write as many double words as possible
- //
- PciWrite32 (StartAddress, *(UINT32*)Buffer);
- StartAddress += sizeof (UINT32);
- Size -= sizeof (UINT32);
- Buffer = (UINT32*)Buffer + 1;
- }
-
- if (Size >= sizeof (UINT16)) {
- //
- // Write the last remaining word if exist
- //
- PciWrite16 (StartAddress, *(UINT16*)Buffer);
- StartAddress += sizeof (UINT16);
- Size -= sizeof (UINT16);
- Buffer = (UINT16*)Buffer + 1;
- }
-
- if (Size >= sizeof (UINT8)) {
- //
- // Write the last remaining byte if exist
- //
- PciWrite8 (StartAddress, *(UINT8*)Buffer);
- }
-
- return ReturnValue;
-}
diff --git a/MdePkg/Library/DxePciSegmentLibEsal/DxePciSegmentLibEsal.inf b/MdePkg/Library/DxePciSegmentLibEsal/DxePciSegmentLibEsal.inf
deleted file mode 100644
index dad1cecf78..0000000000
--- a/MdePkg/Library/DxePciSegmentLibEsal/DxePciSegmentLibEsal.inf
+++ /dev/null
@@ -1,40 +0,0 @@
-## @file
-# PCI Segment Library that uses ESAL services to perform PCI Configuration cycles.
-#
-# Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php.
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-##
-
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = DxePciSegementLibEsal
- MODULE_UNI_FILE = DxePciSegementLibEsal.uni
- FILE_GUID = 6D497A7A-D7DA-467c-B485-B7FB3493C41F
- MODULE_TYPE = DXE_DRIVER
- VERSION_STRING = 1.0
- LIBRARY_CLASS = PciSegmentLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
-
-#
-# The following information is for reference only and not required by the build tools.
-#
-# VALID_ARCHITECTURES = IPF
-#
-
-[Sources]
- PciLib.c
-
-[Packages]
- MdePkg/MdePkg.dec
-
-[LibraryClasses]
- ExtendedSalLib
- DebugLib
- BaseLib
-
diff --git a/MdePkg/Library/DxePciSegmentLibEsal/PciLib.c b/MdePkg/Library/DxePciSegmentLibEsal/PciLib.c
deleted file mode 100644
index fe0fb8b624..0000000000
--- a/MdePkg/Library/DxePciSegmentLibEsal/PciLib.c
+++ /dev/null
@@ -1,1416 +0,0 @@
-/** @file
- DXE PCI Segment Library instance layered on top of ESAL services.
-
- Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php.
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include <PiDxe.h>
-
-#include <Protocol/ExtendedSalServiceClasses.h>
-
-#include <Library/PciSegmentLib.h>
-#include <Library/BaseLib.h>
-#include <Library/DebugLib.h>
-#include <Library/ExtendedSalLib.h>
-
-/**
- Assert the validity of a PCI Segment address.
- A valid PCI Segment address should not contain 1's in bits 31:28
-
- @param A The address to validate.
- @param M Additional bits to assert to be zero.
-
-**/
-#define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A,M) \
- ASSERT (((A) & (0xf0000000 | (M))) == 0)
-
-/**
- Converts a PCI Library Address to a ESAL PCI Service Address.
- Based on SAL Spec 3.2, there are two SAL PCI Address:
-
- If address type = 0
- Bits 0..7 - Register address
- Bits 8..10 - Function number
- Bits 11..15 - Device number
- Bits 16..23 - Bus number
- Bits 24..31 - PCI segment group
- Bits 32..63 - Reserved (0)
-
- If address type = 1
- Bits 0..7 - Register address
- Bits 8..11 - Extended Register address
- Bits 12..14 - Function number
- Bits 15..19 - Device number
- Bits 20..27 - Bus number
- Bits 28..43 - PCI segment group
- Bits 44..63 - Reserved (0)
-
- @param A The PCI Library Address to convert.
-
-**/
-#define CONVERT_PCI_SEGMENT_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS0(Address) (((Address >> 8) & 0xff000000) | (((Address) >> 4) & 0x00ffff00) | ((Address) & 0xff))
-#define CONVERT_PCI_SEGMENT_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS1(Address) (((Address >> 4) & 0xffff0000000) | ((Address) & 0xfffffff))
-
-/**
- Check a PCI Library Address is a PCI Compatible Address or not.
-**/
-#define IS_PCI_COMPATIBLE_ADDRESS(Address) (((Address) & 0xf00) == 0)
-
-/**
- Internal worker function to read a PCI configuration register.
-
- This function wraps EsalPciConfigRead function of Extended SAL PCI
- Services Class.
- It reads and returns the PCI configuration register specified by Address,
- the width of data is specified by Width.
-
- @param Address Address that encodes the PCI Bus, Device, Function and
- Register.
- @param Width Width of data to read
-
- @return The value read from the PCI configuration register.
-
-**/
-UINT32
-DxePciSegmentLibEsalReadWorker (
- IN UINT64 Address,
- IN UINTN Width
- )
-{
- SAL_RETURN_REGS Return;
-
- if (IS_PCI_COMPATIBLE_ADDRESS(Address)) {
- Return = EsalCall (
- EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_HI,
- SalPciConfigReadFunctionId,
- CONVERT_PCI_SEGMENT_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS0 (Address),
- Width,
- EFI_SAL_PCI_COMPATIBLE_ADDRESS,
- 0,
- 0,
- 0,
- 0
- );
- } else {
- Return = EsalCall (
- EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_HI,
- SalPciConfigReadFunctionId,
- CONVERT_PCI_SEGMENT_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS1 (Address),
- Width,
- EFI_SAL_PCI_EXTENDED_REGISTER_ADDRESS,
- 0,
- 0,
- 0,
- 0
- );
- }
-
- return (UINT32) Return.r9;
-}
-
-/**
- Internal worker function to writes a PCI configuration register.
-
- This function wraps EsalPciConfigWrite function of Extended SAL PCI
- Services Class.
- It writes the PCI configuration register specified by Address with the
- value specified by Data. The width of data is specified by Width.
- Data is returned.
-
- @param Address Address that encodes the PCI Bus, Device, Function and
- Register.
- @param Width Width of data to write
- @param Data The value to write.
-
- @return The value written to the PCI configuration register.
-
-**/
-UINT32
-DxePciSegmentLibEsalWriteWorker (
- IN UINT64 Address,
- IN UINTN Width,
- IN UINT32 Data
- )
-{
- if (IS_PCI_COMPATIBLE_ADDRESS(Address)) {
- EsalCall (
- EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_HI,
- SalPciConfigWriteFunctionId,
- CONVERT_PCI_SEGMENT_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS0 (Address),
- Width,
- Data,
- EFI_SAL_PCI_COMPATIBLE_ADDRESS,
- 0,
- 0,
- 0
- );
- } else {
- EsalCall (
- EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_HI,
- SalPciConfigWriteFunctionId,
- CONVERT_PCI_SEGMENT_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS1 (Address),
- Width,
- Data,
- EFI_SAL_PCI_EXTENDED_REGISTER_ADDRESS,
- 0,
- 0,
- 0
- );
- }
-
- return Data;
-}
-
-/**
- Reads an 8-bit PCI configuration register.
-
- Reads and returns the 8-bit PCI configuration register specified by Address.
- This function must guarantee that all PCI read and write operations are
- serialized.
-
- If any reserved bits in Address are set, then ASSERT().
-
- @param Address Address that encodes the PCI Segment, Bus, Device, Function and
- Register.
-
- @return The value read from the PCI configuration register.
-
-**/
-UINT8
-EFIAPI
-PciSegmentRead8 (
- IN UINT64 Address
- )
-{
- ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
-
- return (UINT8) DxePciSegmentLibEsalReadWorker (Address, 1);
-}
-
-/**
- Writes an 8-bit PCI configuration register.
-
- Writes the 8-bit PCI configuration register specified by Address with the
- value specified by Value. Value is returned. This function must guarantee
- that all PCI read and write operations are serialized.
-
- If any reserved bits in Address are set, then ASSERT().
-
- @param Address Address that encodes the PCI Segment, Bus, Device, Function and
- Register.
- @param Data The value to write.
-
- @return The value written to the PCI configuration register.
-
-**/
-UINT8
-EFIAPI
-PciSegmentWrite8 (
- IN UINT64 Address,
- IN UINT8 Data
- )
-{
- ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
-
- return (UINT8) DxePciSegmentLibEsalWriteWorker (Address, 1, Data);
-}
-
-/**
- Performs a bitwise OR of an 8-bit PCI configuration register with
- an 8-bit value.
-
- Reads the 8-bit PCI configuration register specified by Address, performs a
- bitwise OR between the read result and the value specified by
- OrData, and writes the result to the 8-bit PCI configuration register
- specified by Address. The value written to the PCI configuration register is
- returned. This function must guarantee that all PCI read and write operations
- are serialized.
-
- If any reserved bits in Address are set, then ASSERT().
-
- @param Address Address that encodes the PCI Segment, Bus, Device, Function and
- Register.
- @param OrData The value to OR with the PCI configuration register.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT8
-EFIAPI
-PciSegmentOr8 (
- IN UINT64 Address,
- IN UINT8 OrData
- )
-{
- return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) | OrData));
-}
-
-/**
- Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
- value.
-
- Reads the 8-bit PCI configuration register specified by Address, performs a
- bitwise AND between the read result and the value specified by AndData, and
- writes the result to the 8-bit PCI configuration register specified by
- Address. The value written to the PCI configuration register is returned.
- This function must guarantee that all PCI read and write operations are
- serialized.
-
- If any reserved bits in Address are set, then ASSERT().
-
- @param Address Address that encodes the PCI Segment, Bus, Device, Function and
- Register.
- @param AndData The value to AND with the PCI configuration register.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT8
-EFIAPI
-PciSegmentAnd8 (
- IN UINT64 Address,
- IN UINT8 AndData
- )
-{
- return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) & AndData));
-}
-
-/**
- Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
- value, followed a bitwise OR with another 8-bit value.
-
- Reads the 8-bit PCI configuration register specified by Address, performs a
- bitwise AND between the read result and the value specified by AndData,
- performs a bitwise OR between the result of the AND operation and
- the value specified by OrData, and writes the result to the 8-bit PCI
- configuration register specified by Address. The value written to the PCI
- configuration register is returned. This function must guarantee that all PCI
- read and write operations are serialized.
-
- If any reserved bits in Address are set, then ASSERT().
-
- @param Address Address that encodes the PCI Segment, Bus, Device, Function and
- Register.
- @param AndData The value to AND with the PCI configuration register.
- @param OrData The value to OR with the result of the AND operation.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT8
-EFIAPI
-PciSegmentAndThenOr8 (
- IN UINT64 Address,
- IN UINT8 AndData,
- IN UINT8 OrData
- )
-{
- return PciSegmentWrite8 (Address, (UINT8) ((PciSegmentRead8 (Address) & AndData) | OrData));
-}
-
-/**
- Reads a bit field of a PCI configuration register.
-
- Reads the bit field in an 8-bit PCI configuration register. The bit field is
- specified by the StartBit and the EndBit. The value of the bit field is
- returned.
-
- If any reserved bits in Address are set, then ASSERT().
- If StartBit is greater than 7, then ASSERT().
- If EndBit is greater than 7, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
-
- @param Address PCI configuration register to read.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..7.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..7.
-
- @return The value of the bit field read from the PCI configuration register.
-
-**/
-UINT8
-EFIAPI
-PciSegmentBitFieldRead8 (
- IN UINT64 Address,
- IN UINTN StartBit,
- IN UINTN EndBit
- )
-{
- return BitFieldRead8 (PciSegmentRead8 (Address), StartBit, EndBit);
-}
-
-/**
- Writes a bit field to a PCI configuration register.
-
- Writes Value to the bit field of the PCI configuration register. The bit
- field is specified by the StartBit and the EndBit. All other bits in the
- destination PCI configuration register are preserved. The new value of the
- 8-bit register is returned.
-
- If any reserved bits in Address are set, then ASSERT().
- If StartBit is greater than 7, then ASSERT().
- If EndBit is greater than 7, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Address PCI configuration register to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..7.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..7.
- @param Value New value of the bit field.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT8
-EFIAPI
-PciSegmentBitFieldWrite8 (
- IN UINT64 Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 Value
- )
-{
- return PciSegmentWrite8 (
- Address,
- BitFieldWrite8 (PciSegmentRead8 (Address), StartBit, EndBit, Value)
- );
-}
-
-/**
- Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
- writes the result back to the bit field in the 8-bit port.
-
- Reads the 8-bit PCI configuration register specified by Address, performs a
- bitwise OR between the read result and the value specified by
- OrData, and writes the result to the 8-bit PCI configuration register
- specified by Address. The value written to the PCI configuration register is
- returned. This function must guarantee that all PCI read and write operations
- are serialized. Extra left bits in OrData are stripped.
-
- If any reserved bits in Address are set, then ASSERT().
- If StartBit is greater than 7, then ASSERT().
- If EndBit is greater than 7, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Address PCI configuration register to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..7.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..7.
- @param OrData The value to OR with the PCI configuration register.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT8
-EFIAPI
-PciSegmentBitFieldOr8 (
- IN UINT64 Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 OrData
- )
-{
- return PciSegmentWrite8 (
- Address,
- BitFieldOr8 (PciSegmentRead8 (Address), StartBit, EndBit, OrData)
- );
-}
-
-/**
- Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
- AND, and writes the result back to the bit field in the 8-bit register.
-
- Reads the 8-bit PCI configuration register specified by Address, performs a
- bitwise AND between the read result and the value specified by AndData, and
- writes the result to the 8-bit PCI configuration register specified by
- Address. The value written to the PCI configuration register is returned.
- This function must guarantee that all PCI read and write operations are
- serialized. Extra left bits in AndData are stripped.
-
- If any reserved bits in Address are set, then ASSERT().
- If StartBit is greater than 7, then ASSERT().
- If EndBit is greater than 7, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Address PCI configuration register to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..7.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..7.
- @param AndData The value to AND with the PCI configuration register.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT8
-EFIAPI
-PciSegmentBitFieldAnd8 (
- IN UINT64 Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 AndData
- )
-{
- return PciSegmentWrite8 (
- Address,
- BitFieldAnd8 (PciSegmentRead8 (Address), StartBit, EndBit, AndData)
- );
-}
-
-/**
- Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
- bitwise OR, and writes the result back to the bit field in the
- 8-bit port.
-
- Reads the 8-bit PCI configuration register specified by Address, performs a
- bitwise AND followed by a bitwise OR between the read result and
- the value specified by AndData, and writes the result to the 8-bit PCI
- configuration register specified by Address. The value written to the PCI
- configuration register is returned. This function must guarantee that all PCI
- read and write operations are serialized. Extra left bits in both AndData and
- OrData are stripped.
-
- If any reserved bits in Address are set, then ASSERT().
- If StartBit is greater than 7, then ASSERT().
- If EndBit is greater than 7, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Address PCI configuration register to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..7.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..7.
- @param AndData The value to AND with the PCI configuration register.
- @param OrData The value to OR with the result of the AND operation.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT8
-EFIAPI
-PciSegmentBitFieldAndThenOr8 (
- IN UINT64 Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT8 AndData,
- IN UINT8 OrData
- )
-{
- return PciSegmentWrite8 (
- Address,
- BitFieldAndThenOr8 (PciSegmentRead8 (Address), StartBit, EndBit, AndData, OrData)
- );
-}
-
-/**
- Reads a 16-bit PCI configuration register.
-
- Reads and returns the 16-bit PCI configuration register specified by Address.
- This function must guarantee that all PCI read and write operations are
- serialized.
-
- If any reserved bits in Address are set, then ASSERT().
-
- @param Address Address that encodes the PCI Segment, Bus, Device, Function and
- Register.
-
- @return The value read from the PCI configuration register.
-
-**/
-UINT16
-EFIAPI
-PciSegmentRead16 (
- IN UINT64 Address
- )
-{
- ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);
-
- return (UINT16) DxePciSegmentLibEsalReadWorker (Address, 2);
-}
-
-/**
- Writes a 16-bit PCI configuration register.
-
- Writes the 16-bit PCI configuration register specified by Address with the
- value specified by Value. Value is returned. This function must guarantee
- that all PCI read and write operations are serialized.
-
- If any reserved bits in Address are set, then ASSERT().
-
- @param Address Address that encodes the PCI Segment, Bus, Device, Function and
- Register.
- @param Data The value to write.
-
- @return The value written to the PCI configuration register.
-
-**/
-UINT16
-EFIAPI
-PciSegmentWrite16 (
- IN UINT64 Address,
- IN UINT16 Data
- )
-{
- ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);
-
- return (UINT16) DxePciSegmentLibEsalWriteWorker (Address, 2, Data);
-}
-
-/**
- Performs a bitwise OR of a 16-bit PCI configuration register with
- a 16-bit value.
-
- Reads the 16-bit PCI configuration register specified by Address, performs a
- bitwise OR between the read result and the value specified by
- OrData, and writes the result to the 16-bit PCI configuration register
- specified by Address. The value written to the PCI configuration register is
- returned. This function must guarantee that all PCI read and write operations
- are serialized.
-
- If any reserved bits in Address are set, then ASSERT().
-
- @param Address Address that encodes the PCI Segment, Bus, Device, Function and
- Register.
- @param OrData The value to OR with the PCI configuration register.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT16
-EFIAPI
-PciSegmentOr16 (
- IN UINT64 Address,
- IN UINT16 OrData
- )
-{
- return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) | OrData));
-}
-
-/**
- Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
- value.
-
- Reads the 16-bit PCI configuration register specified by Address, performs a
- bitwise AND between the read result and the value specified by AndData, and
- writes the result to the 16-bit PCI configuration register specified by
- Address. The value written to the PCI configuration register is returned.
- This function must guarantee that all PCI read and write operations are
- serialized.
-
- If any reserved bits in Address are set, then ASSERT().
-
- @param Address Address that encodes the PCI Segment, Bus, Device, Function and
- Register.
- @param AndData The value to AND with the PCI configuration register.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT16
-EFIAPI
-PciSegmentAnd16 (
- IN UINT64 Address,
- IN UINT16 AndData
- )
-{
- return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) & AndData));
-}
-
-/**
- Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
- value, followed a bitwise OR with another 16-bit value.
-
- Reads the 16-bit PCI configuration register specified by Address, performs a
- bitwise AND between the read result and the value specified by AndData,
- performs a bitwise OR between the result of the AND operation and
- the value specified by OrData, and writes the result to the 16-bit PCI
- configuration register specified by Address. The value written to the PCI
- configuration register is returned. This function must guarantee that all PCI
- read and write operations are serialized.
-
- If any reserved bits in Address are set, then ASSERT().
-
- @param Address Address that encodes the PCI Segment, Bus, Device, Function and
- Register.
- @param AndData The value to AND with the PCI configuration register.
- @param OrData The value to OR with the result of the AND operation.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT16
-EFIAPI
-PciSegmentAndThenOr16 (
- IN UINT64 Address,
- IN UINT16 AndData,
- IN UINT16 OrData
- )
-{
- return PciSegmentWrite16 (Address, (UINT16) ((PciSegmentRead16 (Address) & AndData) | OrData));
-}
-
-/**
- Reads a bit field of a PCI configuration register.
-
- Reads the bit field in a 16-bit PCI configuration register. The bit field is
- specified by the StartBit and the EndBit. The value of the bit field is
- returned.
-
- If any reserved bits in Address are set, then ASSERT().
- If StartBit is greater than 15, then ASSERT().
- If EndBit is greater than 15, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
-
- @param Address PCI configuration register to read.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..15.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..15.
-
- @return The value of the bit field read from the PCI configuration register.
-
-**/
-UINT16
-EFIAPI
-PciSegmentBitFieldRead16 (
- IN UINT64 Address,
- IN UINTN StartBit,
- IN UINTN EndBit
- )
-{
- return BitFieldRead16 (PciSegmentRead16 (Address), StartBit, EndBit);
-}
-
-/**
- Writes a bit field to a PCI configuration register.
-
- Writes Value to the bit field of the PCI configuration register. The bit
- field is specified by the StartBit and the EndBit. All other bits in the
- destination PCI configuration register are preserved. The new value of the
- 16-bit register is returned.
-
- If any reserved bits in Address are set, then ASSERT().
- If StartBit is greater than 15, then ASSERT().
- If EndBit is greater than 15, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Address PCI configuration register to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..15.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..15.
- @param Value New value of the bit field.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT16
-EFIAPI
-PciSegmentBitFieldWrite16 (
- IN UINT64 Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 Value
- )
-{
- return PciSegmentWrite16 (
- Address,
- BitFieldWrite16 (PciSegmentRead16 (Address), StartBit, EndBit, Value)
- );
-}
-
-/**
- Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
- writes the result back to the bit field in the 16-bit port.
-
- Reads the 16-bit PCI configuration register specified by Address, performs a
- bitwise OR between the read result and the value specified by
- OrData, and writes the result to the 16-bit PCI configuration register
- specified by Address. The value written to the PCI configuration register is
- returned. This function must guarantee that all PCI read and write operations
- are serialized. Extra left bits in OrData are stripped.
-
- If any reserved bits in Address are set, then ASSERT().
- If StartBit is greater than 15, then ASSERT().
- If EndBit is greater than 15, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Address PCI configuration register to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..15.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..15.
- @param OrData The value to OR with the PCI configuration register.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT16
-EFIAPI
-PciSegmentBitFieldOr16 (
- IN UINT64 Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 OrData
- )
-{
- return PciSegmentWrite16 (
- Address,
- BitFieldOr16 (PciSegmentRead16 (Address), StartBit, EndBit, OrData)
- );
-}
-
-/**
- Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
- AND, and writes the result back to the bit field in the 16-bit register.
-
- Reads the 16-bit PCI configuration register specified by Address, performs a
- bitwise AND between the read result and the value specified by AndData, and
- writes the result to the 16-bit PCI configuration register specified by
- Address. The value written to the PCI configuration register is returned.
- This function must guarantee that all PCI read and write operations are
- serialized. Extra left bits in AndData are stripped.
-
- If any reserved bits in Address are set, then ASSERT().
- If StartBit is greater than 15, then ASSERT().
- If EndBit is greater than 15, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Address PCI configuration register to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..15.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..15.
- @param AndData The value to AND with the PCI configuration register.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT16
-EFIAPI
-PciSegmentBitFieldAnd16 (
- IN UINT64 Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 AndData
- )
-{
- return PciSegmentWrite16 (
- Address,
- BitFieldAnd16 (PciSegmentRead16 (Address), StartBit, EndBit, AndData)
- );
-}
-
-/**
- Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
- bitwise OR, and writes the result back to the bit field in the
- 16-bit port.
-
- Reads the 16-bit PCI configuration register specified by Address, performs a
- bitwise AND followed by a bitwise OR between the read result and
- the value specified by AndData, and writes the result to the 16-bit PCI
- configuration register specified by Address. The value written to the PCI
- configuration register is returned. This function must guarantee that all PCI
- read and write operations are serialized. Extra left bits in both AndData and
- OrData are stripped.
-
- If any reserved bits in Address are set, then ASSERT().
- If StartBit is greater than 15, then ASSERT().
- If EndBit is greater than 15, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Address PCI configuration register to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..15.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..15.
- @param AndData The value to AND with the PCI configuration register.
- @param OrData The value to OR with the result of the AND operation.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT16
-EFIAPI
-PciSegmentBitFieldAndThenOr16 (
- IN UINT64 Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT16 AndData,
- IN UINT16 OrData
- )
-{
- return PciSegmentWrite16 (
- Address,
- BitFieldAndThenOr16 (PciSegmentRead16 (Address), StartBit, EndBit, AndData, OrData)
- );
-}
-
-/**
- Reads a 32-bit PCI configuration register.
-
- Reads and returns the 32-bit PCI configuration register specified by Address.
- This function must guarantee that all PCI read and write operations are
- serialized.
-
- If any reserved bits in Address are set, then ASSERT().
-
- @param Address Address that encodes the PCI Segment, Bus, Device, Function and
- Register.
-
- @return The value read from the PCI configuration register.
-
-**/
-UINT32
-EFIAPI
-PciSegmentRead32 (
- IN UINT64 Address
- )
-{
- ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);
-
- return DxePciSegmentLibEsalReadWorker (Address, 4);
-}
-
-/**
- Writes a 32-bit PCI configuration register.
-
- Writes the 32-bit PCI configuration register specified by Address with the
- value specified by Value. Value is returned. This function must guarantee
- that all PCI read and write operations are serialized.
-
- If any reserved bits in Address are set, then ASSERT().
-
- @param Address Address that encodes the PCI Segment, Bus, Device, Function and
- Register.
- @param Data The value to write.
-
- @return The value written to the PCI configuration register.
-
-**/
-UINT32
-EFIAPI
-PciSegmentWrite32 (
- IN UINT64 Address,
- IN UINT32 Data
- )
-{
- ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);
-
- return DxePciSegmentLibEsalWriteWorker (Address, 4, Data);
-}
-
-/**
- Performs a bitwise OR of a 32-bit PCI configuration register with
- a 32-bit value.
-
- Reads the 32-bit PCI configuration register specified by Address, performs a
- bitwise OR between the read result and the value specified by
- OrData, and writes the result to the 32-bit PCI configuration register
- specified by Address. The value written to the PCI configuration register is
- returned. This function must guarantee that all PCI read and write operations
- are serialized.
-
- If any reserved bits in Address are set, then ASSERT().
-
- @param Address Address that encodes the PCI Segment, Bus, Device, Function and
- Register.
- @param OrData The value to OR with the PCI configuration register.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT32
-EFIAPI
-PciSegmentOr32 (
- IN UINT64 Address,
- IN UINT32 OrData
- )
-{
- return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) | OrData);
-}
-
-/**
- Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
- value.
-
- Reads the 32-bit PCI configuration register specified by Address, performs a
- bitwise AND between the read result and the value specified by AndData, and
- writes the result to the 32-bit PCI configuration register specified by
- Address. The value written to the PCI configuration register is returned.
- This function must guarantee that all PCI read and write operations are
- serialized.
-
- If any reserved bits in Address are set, then ASSERT().
-
- @param Address Address that encodes the PCI Segment, Bus, Device, Function and
- Register.
- @param AndData The value to AND with the PCI configuration register.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT32
-EFIAPI
-PciSegmentAnd32 (
- IN UINT64 Address,
- IN UINT32 AndData
- )
-{
- return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) & AndData);
-}
-
-/**
- Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
- value, followed a bitwise OR with another 32-bit value.
-
- Reads the 32-bit PCI configuration register specified by Address, performs a
- bitwise AND between the read result and the value specified by AndData,
- performs a bitwise OR between the result of the AND operation and
- the value specified by OrData, and writes the result to the 32-bit PCI
- configuration register specified by Address. The value written to the PCI
- configuration register is returned. This function must guarantee that all PCI
- read and write operations are serialized.
-
- If any reserved bits in Address are set, then ASSERT().
-
- @param Address Address that encodes the PCI Segment, Bus, Device, Function and
- Register.
- @param AndData The value to AND with the PCI configuration register.
- @param OrData The value to OR with the result of the AND operation.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT32
-EFIAPI
-PciSegmentAndThenOr32 (
- IN UINT64 Address,
- IN UINT32 AndData,
- IN UINT32 OrData
- )
-{
- return PciSegmentWrite32 (Address, (PciSegmentRead32 (Address) & AndData) | OrData);
-}
-
-/**
- Reads a bit field of a PCI configuration register.
-
- Reads the bit field in a 32-bit PCI configuration register. The bit field is
- specified by the StartBit and the EndBit. The value of the bit field is
- returned.
-
- If any reserved bits in Address are set, then ASSERT().
- If StartBit is greater than 31, then ASSERT().
- If EndBit is greater than 31, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
-
- @param Address PCI configuration register to read.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..31.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..31.
-
- @return The value of the bit field read from the PCI configuration register.
-
-**/
-UINT32
-EFIAPI
-PciSegmentBitFieldRead32 (
- IN UINT64 Address,
- IN UINTN StartBit,
- IN UINTN EndBit
- )
-{
- return BitFieldRead32 (PciSegmentRead32 (Address), StartBit, EndBit);
-}
-
-/**
- Writes a bit field to a PCI configuration register.
-
- Writes Value to the bit field of the PCI configuration register. The bit
- field is specified by the StartBit and the EndBit. All other bits in the
- destination PCI configuration register are preserved. The new value of the
- 32-bit register is returned.
-
- If any reserved bits in Address are set, then ASSERT().
- If StartBit is greater than 31, then ASSERT().
- If EndBit is greater than 31, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Address PCI configuration register to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..31.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..31.
- @param Value New value of the bit field.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT32
-EFIAPI
-PciSegmentBitFieldWrite32 (
- IN UINT64 Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 Value
- )
-{
- return PciSegmentWrite32 (
- Address,
- BitFieldWrite32 (PciSegmentRead32 (Address), StartBit, EndBit, Value)
- );
-}
-
-/**
- Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
- writes the result back to the bit field in the 32-bit port.
-
- Reads the 32-bit PCI configuration register specified by Address, performs a
- bitwise OR between the read result and the value specified by
- OrData, and writes the result to the 32-bit PCI configuration register
- specified by Address. The value written to the PCI configuration register is
- returned. This function must guarantee that all PCI read and write operations
- are serialized. Extra left bits in OrData are stripped.
-
- If any reserved bits in Address are set, then ASSERT().
- If StartBit is greater than 31, then ASSERT().
- If EndBit is greater than 31, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Address PCI configuration register to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..31.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..31.
- @param OrData The value to OR with the PCI configuration register.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT32
-EFIAPI
-PciSegmentBitFieldOr32 (
- IN UINT64 Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 OrData
- )
-{
- return PciSegmentWrite32 (
- Address,
- BitFieldOr32 (PciSegmentRead32 (Address), StartBit, EndBit, OrData)
- );
-}
-
-/**
- Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
- AND, and writes the result back to the bit field in the 32-bit register.
-
- Reads the 32-bit PCI configuration register specified by Address, performs a
- bitwise AND between the read result and the value specified by AndData, and
- writes the result to the 32-bit PCI configuration register specified by
- Address. The value written to the PCI configuration register is returned.
- This function must guarantee that all PCI read and write operations are
- serialized. Extra left bits in AndData are stripped.
-
- If any reserved bits in Address are set, then ASSERT().
- If StartBit is greater than 31, then ASSERT().
- If EndBit is greater than 31, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Address PCI configuration register to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..31.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..31.
- @param AndData The value to AND with the PCI configuration register.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT32
-EFIAPI
-PciSegmentBitFieldAnd32 (
- IN UINT64 Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 AndData
- )
-{
- return PciSegmentWrite32 (
- Address,
- BitFieldAnd32 (PciSegmentRead32 (Address), StartBit, EndBit, AndData)
- );
-}
-
-/**
- Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
- bitwise OR, and writes the result back to the bit field in the
- 32-bit port.
-
- Reads the 32-bit PCI configuration register specified by Address, performs a
- bitwise AND followed by a bitwise OR between the read result and
- the value specified by AndData, and writes the result to the 32-bit PCI
- configuration register specified by Address. The value written to the PCI
- configuration register is returned. This function must guarantee that all PCI
- read and write operations are serialized. Extra left bits in both AndData and
- OrData are stripped.
-
- If any reserved bits in Address are set, then ASSERT().
- If StartBit is greater than 31, then ASSERT().
- If EndBit is greater than 31, then ASSERT().
- If EndBit is less than StartBit, then ASSERT().
- If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
- If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
-
- @param Address PCI configuration register to write.
- @param StartBit The ordinal of the least significant bit in the bit field.
- Range 0..31.
- @param EndBit The ordinal of the most significant bit in the bit field.
- Range 0..31.
- @param AndData The value to AND with the PCI configuration register.
- @param OrData The value to OR with the result of the AND operation.
-
- @return The value written back to the PCI configuration register.
-
-**/
-UINT32
-EFIAPI
-PciSegmentBitFieldAndThenOr32 (
- IN UINT64 Address,
- IN UINTN StartBit,
- IN UINTN EndBit,
- IN UINT32 AndData,
- IN UINT32 OrData
- )
-{
- return PciSegmentWrite32 (
- Address,
- BitFieldAndThenOr32 (PciSegmentRead32 (Address), StartBit, EndBit, AndData, OrData)
- );
-}
-
-/**
- Reads a range of PCI configuration registers into a caller supplied buffer.
-
- Reads the range of PCI configuration registers specified by StartAddress and
- Size into the buffer specified by Buffer. This function only allows the PCI
- configuration registers from a single PCI function to be read. Size is
- returned. When possible 32-bit PCI configuration read cycles are used to read
- from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
- and 16-bit PCI configuration read cycles may be used at the beginning and the
- end of the range.
-
- If StartAddress > 0x0FFFFFFF, then ASSERT().
- If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
- If Size > 0 and Buffer is NULL, then ASSERT().
-
- @param StartAddress Starting Address that encodes the PCI Segment, Bus, Device,
- Function and Register.
- @param Size Size in bytes of the transfer.
- @param Buffer Pointer to a buffer receiving the data read.
-
- @return Size
-
-**/
-UINTN
-EFIAPI
-PciSegmentReadBuffer (
- IN UINT64 StartAddress,
- IN UINTN Size,
- OUT VOID *Buffer
- )
-{
- UINTN ReturnValue;
-
- ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);
- ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
-
- if (Size == 0) {
- return Size;
- }
-
- ASSERT (Buffer != NULL);
-
- //
- // Save Size for return
- //
- ReturnValue = Size;
-
- if ((StartAddress & 1) != 0) {
- //
- // Read a byte if StartAddress is byte aligned
- //
- *(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress);
- StartAddress += sizeof (UINT8);
- Size -= sizeof (UINT8);
- Buffer = (UINT8*)Buffer + 1;
- }
-
- if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {
- //
- // Read a word if StartAddress is word aligned
- //
- *(volatile UINT16 *)Buffer = PciSegmentRead16 (StartAddress);
- StartAddress += sizeof (UINT16);
- Size -= sizeof (UINT16);
- Buffer = (UINT16*)Buffer + 1;
- }
-
- while (Size >= sizeof (UINT32)) {
- //
- // Read as many double words as possible
- //
- *(volatile UINT32 *)Buffer = PciSegmentRead32 (StartAddress);
- StartAddress += sizeof (UINT32);
- Size -= sizeof (UINT32);
- Buffer = (UINT32*)Buffer + 1;
- }
-
- if (Size >= sizeof (UINT16)) {
- //
- // Read the last remaining word if exist
- //
- *(volatile UINT16 *)Buffer = PciSegmentRead16 (StartAddress);
- StartAddress += sizeof (UINT16);
- Size -= sizeof (UINT16);
- Buffer = (UINT16*)Buffer + 1;
- }
-
- if (Size >= sizeof (UINT8)) {
- //
- // Read the last remaining byte if exist
- //
- *(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress);
- }
-
- return ReturnValue;
-}
-
-/**
- Copies the data in a caller supplied buffer to a specified range of PCI
- configuration space.
-
- Writes the range of PCI configuration registers specified by StartAddress and
- Size from the buffer specified by Buffer. This function only allows the PCI
- configuration registers from a single PCI function to be written. Size is
- returned. When possible 32-bit PCI configuration write cycles are used to
- write from StartAdress to StartAddress + Size. Due to alignment restrictions,
- 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
- and the end of the range.
-
- If StartAddress > 0x0FFFFFFF, then ASSERT().
- If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
- If Size > 0 and Buffer is NULL, then ASSERT().
-
- @param StartAddress Starting Address that encodes the PCI Segment, Bus, Device,
- Function and Register.
- @param Size Size in bytes of the transfer.
- @param Buffer Pointer to a buffer containing the data to write.
-
- @return Size
-
-**/
-UINTN
-EFIAPI
-PciSegmentWriteBuffer (
- IN UINT64 StartAddress,
- IN UINTN Size,
- IN VOID *Buffer
- )
-{
- UINTN ReturnValue;
-
- ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);
- ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
-
- if (Size == 0) {
- return 0;
- }
-
- ASSERT (Buffer != NULL);
-
- //
- // Save Size for return
- //
- ReturnValue = Size;
-
- if ((StartAddress & 1) != 0) {
- //
- // Write a byte if StartAddress is byte aligned
- //
- PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer);
- StartAddress += sizeof (UINT8);
- Size -= sizeof (UINT8);
- Buffer = (UINT8*)Buffer + 1;
- }
-
- if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {
- //
- // Write a word if StartAddress is word aligned
- //
- PciSegmentWrite16 (StartAddress, *(UINT16*)Buffer);
- StartAddress += sizeof (UINT16);
- Size -= sizeof (UINT16);
- Buffer = (UINT16*)Buffer + 1;
- }
-
- while (Size >= sizeof (UINT32)) {
- //
- // Write as many double words as possible
- //
- PciSegmentWrite32 (StartAddress, *(UINT32*)Buffer);
- StartAddress += sizeof (UINT32);
- Size -= sizeof (UINT32);
- Buffer = (UINT32*)Buffer + 1;
- }
-
- if (Size >= sizeof (UINT16)) {
- //
- // Write the last remaining word if exist
- //
- PciSegmentWrite16 (StartAddress, *(UINT16*)Buffer);
- StartAddress += sizeof (UINT16);
- Size -= sizeof (UINT16);
- Buffer = (UINT16*)Buffer + 1;
- }
-
- if (Size >= sizeof (UINT8)) {
- //
- // Write the last remaining byte if exist
- //
- PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer);
- }
-
- return ReturnValue;
-}
diff --git a/MdePkg/Library/DxeRuntimeDebugLibSerialPort/DxeRuntimeDebugLibSerialPort.inf b/MdePkg/Library/DxeRuntimeDebugLibSerialPort/DxeRuntimeDebugLibSerialPort.inf
index 8133580969..5050a8aaca 100644
--- a/MdePkg/Library/DxeRuntimeDebugLibSerialPort/DxeRuntimeDebugLibSerialPort.inf
+++ b/MdePkg/Library/DxeRuntimeDebugLibSerialPort/DxeRuntimeDebugLibSerialPort.inf
@@ -29,7 +29,7 @@
DESTRUCTOR = DxeRuntimeDebugLibSerialPortDestructor
#
-# VALID_ARCHITECTURES = AARCH64 ARM IA32 X64 IPF EBC
+# VALID_ARCHITECTURES = AARCH64 ARM IA32 X64 EBC
#
[Sources]
diff --git a/MdePkg/Library/DxeRuntimeExtendedSalLib/DxeRuntimeExtendedSalLib.inf b/MdePkg/Library/DxeRuntimeExtendedSalLib/DxeRuntimeExtendedSalLib.inf
deleted file mode 100644
index 4bc09f9308..0000000000
--- a/MdePkg/Library/DxeRuntimeExtendedSalLib/DxeRuntimeExtendedSalLib.inf
+++ /dev/null
@@ -1,52 +0,0 @@
-## @file
-# This library implements the Extended SAL Library Class for use in boot services and runtime.
-#
-# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php.
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-##
-
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = DxeRuntimeExtendedSalLib
- MODULE_UNI_FILE = DxeRuntimeExtendedSalLib.uni
- FILE_GUID = AE66715B-75F5-4423-8FAD-A4AFB3C53ACF
- MODULE_TYPE = DXE_RUNTIME_DRIVER
- VERSION_STRING = 1.0
- LIBRARY_CLASS = ExtendedSalLib|DXE_RUNTIME_DRIVER DXE_SAL_DRIVER
- CONSTRUCTOR = DxeRuntimeExtendedSalLibConstruct
- DESTRUCTOR = DxeRuntimeExtendedSalLibDeconstruct
-
-#
-# The following information is for reference only and not required by the build tools.
-#
-# VALID_ARCHITECTURES = IPF
-#
-
-[Sources.IPF]
- ExtendedSalLib.c
- Ipf/AsmExtendedSalLib.s
-
-[Packages]
- MdePkg/MdePkg.dec
-
-[LibraryClasses]
- UefiBootServicesTableLib
- UefiRuntimeServicesTableLib
- DebugLib
-
-[Protocols]
- gEfiExtendedSalBootServiceProtocolGuid ## CONSUMES
-
-[Guids]
- gEfiEventVirtualAddressChangeGuid ## CONSUMES ## Event
-
-[Depex]
- gEfiExtendedSalBootServiceProtocolGuid
-
diff --git a/MdePkg/Library/DxeRuntimeExtendedSalLib/ExtendedSalLib.c b/MdePkg/Library/DxeRuntimeExtendedSalLib/ExtendedSalLib.c
deleted file mode 100644
index f9e974b373..0000000000
--- a/MdePkg/Library/DxeRuntimeExtendedSalLib/ExtendedSalLib.c
+++ /dev/null
@@ -1,1124 +0,0 @@
-/** @file
- This library implements the Extended SAL Library Class for use in boot services and runtime.
-
- Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php.
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include <PiDxe.h>
-
-#include <Protocol/ExtendedSalBootService.h>
-#include <Protocol/ExtendedSalServiceClasses.h>
-#include <Guid/EventGroup.h>
-
-#include <Library/ExtendedSalLib.h>
-#include <Library/UefiBootServicesTableLib.h>
-#include <Library/UefiRuntimeServicesTableLib.h>
-#include <Library/UefiRuntimeLib.h>
-#include <Library/DebugLib.h>
-
-/**
- Stores the virtual plabel of ESAL entrypoint.
-
- This assembly function stores the virtual plabel of ESAL entrypoint
- where GetEsalEntryPoint() can easily retrieve.
-
- @param EntryPoint Virtual address of ESAL entrypoint
- @param Gp Virtual GP of ESAL entrypoint
-
- @return r8 = EFI_SAL_SUCCESS
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-SetEsalVirtualEntryPoint (
- IN UINT64 EntryPoint,
- IN UINT64 Gp
- );
-
-/**
- Stores the physical plabel of ESAL entrypoint.
-
- This assembly function stores the physical plabel of ESAL entrypoint
- where GetEsalEntryPoint() can easily retrieve.
-
- @param EntryPoint Physical address of ESAL entrypoint
- @param Gp Physical GP of ESAL entrypoint
-
- @return r8 = EFI_SAL_SUCCESS
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-SetEsalPhysicalEntryPoint (
- IN UINT64 EntryPoint,
- IN UINT64 Gp
- );
-
-/**
- Retrieves plabel of ESAL entrypoint.
-
- This function retrives plabel of ESAL entrypoint stored by
- SetEsalPhysicalEntryPoint().
-
- @return r8 = EFI_SAL_SUCCESS
- r9 = Physical Plabel
- r10 = Virtual Plabel
- r11 = PSR
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-GetEsalEntryPoint (
- VOID
- );
-
-EXTENDED_SAL_BOOT_SERVICE_PROTOCOL *mEsalBootService = NULL;
-EFI_PLABEL mPlabel;
-EFI_EVENT mEfiVirtualNotifyEvent;
-
-/**
- Notification function of EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE to set virtual plabel of
- ESAL entrypoint.
-
- This is a notification function registered on EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE event.
- It converts physical plabel of ESAL entrypoint to virtual plabel and stores it where
- GetEsalEntryPoint() can easily retrieve.
-
- @param Event Event whose notification function is being invoked.
- @param Context Pointer to the notification function's context
-
-**/
-VOID
-EFIAPI
-ExtendedSalVirtualNotifyEvent (
- IN EFI_EVENT Event,
- IN VOID *Context
- )
-{
- UINT64 PhysicalEntryPoint;
-
- PhysicalEntryPoint = mPlabel.EntryPoint;
-
- gRT->ConvertPointer (0x0, (VOID **) &mPlabel.EntryPoint);
-
- mPlabel.GP += mPlabel.EntryPoint - PhysicalEntryPoint;
-
- SetEsalVirtualEntryPoint (mPlabel.EntryPoint, mPlabel.GP);
-}
-
-/**
- Gets Extended SAL Boot Service Protocol, and initializes physical plabel of
- ESAL entrypoint.
-
- This function first locates Extended SAL Boot Service Protocol and caches it in global variable.
- Then it initializes the physical plable of ESAL entrypoint, and stores
- it where GetEsalEntryPoint() can easily retrieve.
-
- @retval EFI_SUCCESS Plable of ESAL entrypoint successfully stored.
-
-**/
-EFI_STATUS
-DxeSalLibInitialize (
- VOID
- )
-{
- EFI_PLABEL *Plabel;
- EFI_STATUS Status;
-
- //
- // The protocol contains a function pointer, which is an indirect procedure call.
- // An indirect procedure call goes through a plabel, and pointer to a function is
- // a pointer to a plabel. To implement indirect procedure calls that can work in
- // both physical and virtual mode, two plabels are required (one physical and one
- // virtual). So lets grap the physical PLABEL for the EsalEntryPoint and store it
- // away. We cache it in a module global, so we can register the vitrual version.
- //
- Status = gBS->LocateProtocol (&gEfiExtendedSalBootServiceProtocolGuid, NULL, (VOID **) &mEsalBootService);
- ASSERT_EFI_ERROR (Status);
-
- Plabel = (EFI_PLABEL *) (UINTN) mEsalBootService->ExtendedSalProc;
- mPlabel.EntryPoint = Plabel->EntryPoint;
- mPlabel.GP = Plabel->GP;
- //
- // Stores the physical plabel of ESAL entrypoint where GetEsalEntryPoint() can easily retrieve.
- //
- SetEsalPhysicalEntryPoint (mPlabel.EntryPoint, mPlabel.GP);
-
- return EFI_SUCCESS;
-}
-
-/**
- Constructor function to initializes physical plabel of ESAL entrypoint and register an event
- for initialization of virtual plabel of ESAL entrypoint.
-
- This is the library constructor function to call a function to initialize physical plabel of ESAL entrypoint
- and to register notification function for
- EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE, which sets virtual plabel of ESAL entrypoint.
-
- @param ImageHandle The firmware allocated handle for the EFI image.
- @param SystemTable A pointer to the EFI System Table.
-
- @retval EFI_SUCCESS Notification function successfully registered.
-
-**/
-EFI_STATUS
-EFIAPI
-DxeRuntimeExtendedSalLibConstruct (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
- )
-{
- EFI_STATUS Status;
-
- //
- // Register notify function for EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE
- //
- ASSERT (gBS != NULL);
-
- DxeSalLibInitialize ();
-
- Status = gBS->CreateEventEx (
- EVT_NOTIFY_SIGNAL,
- TPL_NOTIFY,
- ExtendedSalVirtualNotifyEvent,
- NULL,
- &gEfiEventVirtualAddressChangeGuid,
- &mEfiVirtualNotifyEvent
- );
-
- ASSERT_EFI_ERROR (Status);
-
- return EFI_SUCCESS;
-}
-
-/**
- Destructor function to close the event created by the library constructor
-
- This is the library destructor function to close the event with type of
- EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE, which is created by the library constructor.
-
- @param ImageHandle The firmware allocated handle for the EFI image.
- @param SystemTable A pointer to the EFI System Table.
-
- @retval EFI_SUCCESS Event successfully closed.
-
-**/
-EFI_STATUS
-EFIAPI
-DxeRuntimeExtendedSalLibDeconstruct (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
- )
-{
- EFI_STATUS Status;
-
- //
- // Close SetVirtualAddressMap () notify function
- //
- ASSERT (gBS != NULL);
- Status = gBS->CloseEvent (mEfiVirtualNotifyEvent);
- ASSERT_EFI_ERROR (Status);
-
- return EFI_SUCCESS;
-}
-
-/**
- Registers function of ESAL class and it's associated global.
-
- This function registers function of ESAL class, together with its associated global.
- It is worker function for RegisterEsalClass().
- It is only for boot time.
-
- @param FunctionId ID of function to register
- @param ClassGuidLo GUID of ESAL class, lower 64-bits
- @param ClassGuidHi GUID of ESAL class, upper 64-bits
- @param Function Function to register with ClassGuid/FunctionId pair
- @param ModuleGlobal Module global for the function.
-
- @return Status returned by RegisterExtendedSalProc() of Extended SAL Boot Service Protocol
-
-**/
-EFI_STATUS
-RegisterEsalFunction (
- IN UINT64 FunctionId,
- IN UINT64 ClassGuidLo,
- IN UINT64 ClassGuidHi,
- IN SAL_INTERNAL_EXTENDED_SAL_PROC Function,
- IN VOID *ModuleGlobal
- )
-{
- return mEsalBootService->RegisterExtendedSalProc (
- mEsalBootService,
- ClassGuidLo,
- ClassGuidHi,
- FunctionId,
- Function,
- ModuleGlobal
- );
-}
-
-/**
- Registers ESAL Class and it's associated global.
-
- This function registers one or more Extended SAL services in a given
- class along with the associated global context.
- This function is only available prior to ExitBootServices().
-
- @param ClassGuidLo GUID of function class, lower 64-bits
- @param ClassGuidHi GUID of function class, upper 64-bits
- @param ModuleGlobal Module global for the class.
- @param ... List of Function/FunctionId pairs, ended by NULL
-
- @retval EFI_SUCCESS The Extended SAL services were registered.
- @retval EFI_UNSUPPORTED This function was called after ExitBootServices().
- @retval EFI_OUT_OF_RESOURCES There are not enough resources available to register one or more of the specified services.
- @retval Other ClassGuid could not be installed onto a new handle.
-
-**/
-EFI_STATUS
-EFIAPI
-RegisterEsalClass (
- IN CONST UINT64 ClassGuidLo,
- IN CONST UINT64 ClassGuidHi,
- IN VOID *ModuleGlobal, OPTIONAL
- ...
- )
-{
- VA_LIST Args;
- EFI_STATUS Status;
- SAL_INTERNAL_EXTENDED_SAL_PROC Function;
- UINT64 FunctionId;
- EFI_HANDLE NewHandle;
- EFI_GUID ClassGuid;
-
- VA_START (Args, ModuleGlobal);
-
- //
- // Register all functions of the class to register.
- //
- Status = EFI_SUCCESS;
- while (!EFI_ERROR (Status)) {
- Function = (SAL_INTERNAL_EXTENDED_SAL_PROC) VA_ARG (Args, SAL_INTERNAL_EXTENDED_SAL_PROC);
- //
- // NULL serves as the end mark of function list
- //
- if (Function == NULL) {
- break;
- }
-
- FunctionId = VA_ARG (Args, UINT64);
-
- Status = RegisterEsalFunction (FunctionId, ClassGuidLo, ClassGuidHi, Function, ModuleGlobal);
- }
-
- VA_END (Args);
-
- if (EFI_ERROR (Status)) {
- return Status;
- }
-
- NewHandle = NULL;
- *((UINT64 *)(&ClassGuid) + 0) = ClassGuidLo;
- *((UINT64 *)(&ClassGuid) + 1) = ClassGuidHi;
- return gBS->InstallProtocolInterface (
- &NewHandle,
- &ClassGuid,
- EFI_NATIVE_INTERFACE,
- NULL
- );
-}
-
-/**
- Calls an Extended SAL Class service that was previously registered with RegisterEsalClass().
-
- This function gets the entrypoint of Extended SAL, and calls an Extended SAL Class service
- that was previously registered with RegisterEsalClass() through this entrypoint.
-
- @param ClassGuidLo GUID of function, lower 64-bits
- @param ClassGuidHi GUID of function, upper 64-bits
- @param FunctionId Function in ClassGuid to call
- @param Arg2 Argument 2 ClassGuid/FunctionId defined
- @param Arg3 Argument 3 ClassGuid/FunctionId defined
- @param Arg4 Argument 4 ClassGuid/FunctionId defined
- @param Arg5 Argument 5 ClassGuid/FunctionId defined
- @param Arg6 Argument 6 ClassGuid/FunctionId defined
- @param Arg7 Argument 7 ClassGuid/FunctionId defined
- @param Arg8 Argument 8 ClassGuid/FunctionId defined
-
- @retval EFI_SAL_SUCCESS ESAL procedure successfully called.
- @retval EFI_SAL_ERROR The address of ExtendedSalProc() can not be correctly
- initialized.
- @retval Other Status returned from ExtendedSalProc() service of
- EXTENDED_SAL_BOOT_SERVICE_PROTOCOL.
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-EsalCall (
- IN UINT64 ClassGuidLo,
- IN UINT64 ClassGuidHi,
- IN UINT64 FunctionId,
- IN UINT64 Arg2,
- IN UINT64 Arg3,
- IN UINT64 Arg4,
- IN UINT64 Arg5,
- IN UINT64 Arg6,
- IN UINT64 Arg7,
- IN UINT64 Arg8
- )
-{
- SAL_RETURN_REGS ReturnReg;
- EXTENDED_SAL_PROC EsalProc;
-
- //
- // Get the entrypoint of Extended SAL
- //
- ReturnReg = GetEsalEntryPoint ();
- if (*(UINT64 *)ReturnReg.r9 == 0 && *(UINT64 *)(ReturnReg.r9 + 8) == 0) {
- //
- // The ESAL Entry Point could not be initialized
- //
- ReturnReg.Status = EFI_SAL_ERROR;
- return ReturnReg;
- }
-
- //
- // Test PSR.it which is BIT36
- //
- if ((ReturnReg.r11 & BIT36) != 0) {
- //
- // Virtual mode plabel to entry point
- //
- EsalProc = (EXTENDED_SAL_PROC) ReturnReg.r10;
- } else {
- //
- // Physical mode plabel to entry point
- //
- EsalProc = (EXTENDED_SAL_PROC) ReturnReg.r9;
- }
-
- return EsalProc (
- ClassGuidLo,
- ClassGuidHi,
- FunctionId,
- Arg2,
- Arg3,
- Arg4,
- Arg5,
- Arg6,
- Arg7,
- Arg8
- );
-}
-
-/**
- Wrapper for the EsalStallFunctionId service of Extended SAL Stall Services Class.
-
- This function is a wrapper for the EsalStallFunctionId service of Extended SAL
- Stall Services Class. See EsalStallFunctionId of Extended SAL Specification.
-
- @param Microseconds The number of microseconds to delay.
-
- @retval EFI_SAL_SUCCESS Call completed without error.
- @retval EFI_SAL_INVALID_ARGUMENT Invalid argument.
- @retval EFI_SAL_VIRTUAL_ADDRESS_ERROR Virtual address not registered
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-EsalStall (
- IN UINTN Microseconds
- )
-{
- return EsalCall (
- EFI_EXTENDED_SAL_STALL_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_STALL_SERVICES_PROTOCOL_GUID_HI,
- StallFunctionId,
- Microseconds,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0
- );
-}
-
-/**
- Wrapper for the EsalSetNewPalEntryFunctionId service of Extended SAL PAL Services Services Class.
-
- This function is a wrapper for the EsalSetNewPalEntryFunctionId service of Extended SAL
- PAL Services Services Class. See EsalSetNewPalEntryFunctionId of Extended SAL Specification.
-
- @param PhysicalAddress If TRUE, then PalEntryPoint is a physical address.
- If FALSE, then PalEntryPoint is a virtual address.
- @param PalEntryPoint The PAL Entry Point being set.
-
- @retval EFI_SAL_SUCCESS The PAL Entry Point was set.
- @retval EFI_SAL_VIRTUAL_ADDRESS_ERROR This function was called in virtual mode before
- virtual mappings for the specified Extended SAL
- Procedure are available.
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-EsalSetNewPalEntry (
- IN BOOLEAN PhysicalAddress,
- IN UINT64 PalEntryPoint
- )
-{
- return EsalCall (
- EFI_EXTENDED_SAL_PAL_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_PAL_SERVICES_PROTOCOL_GUID_HI,
- SetNewPalEntryFunctionId,
- PhysicalAddress,
- PalEntryPoint,
- 0,
- 0,
- 0,
- 0,
- 0
- );
-}
-
-/**
- Wrapper for the EsalGetNewPalEntryFunctionId service of Extended SAL PAL Services Services Class.
-
- This function is a wrapper for the EsalGetNewPalEntryFunctionId service of Extended SAL
- PAL Services Services Class. See EsalGetNewPalEntryFunctionId of Extended SAL Specification.
-
- @param PhysicalAddress If TRUE, then PalEntryPoint is a physical address.
- If FALSE, then PalEntryPoint is a virtual address.
-
- @retval EFI_SAL_SUCCESS The PAL Entry Point was retrieved and returned in
- SAL_RETURN_REGS.r9.
- @retval EFI_SAL_VIRTUAL_ADDRESS_ERROR This function was called in virtual mode before
- virtual mappings for the specified Extended SAL
- Procedure are available.
- @return r9 PAL entry point retrieved.
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-EsalGetNewPalEntry (
- IN BOOLEAN PhysicalAddress
- )
-{
- return EsalCall (
- EFI_EXTENDED_SAL_PAL_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_PAL_SERVICES_PROTOCOL_GUID_HI,
- GetNewPalEntryFunctionId,
- PhysicalAddress,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0
- );
-}
-
-/**
- Wrapper for the EsalGetStateBufferFunctionId service of Extended SAL MCA Log Services Class.
-
- This function is a wrapper for the EsalGetStateBufferFunctionId service of Extended SAL
- MCA Log Services Class. See EsalGetStateBufferFunctionId of Extended SAL Specification.
-
- @param McaType See type parameter of SAL Procedure SAL_GET_STATE_INFO.
- @param McaBuffer A pointer to the base address of the returned buffer.
- Copied from SAL_RETURN_REGS.r9.
- @param BufferSize A pointer to the size, in bytes, of the returned buffer.
- Copied from SAL_RETURN_REGS.r10.
-
- @retval EFI_SAL_SUCCESS The memory buffer to store error records was returned in r9 and r10.
- @retval EFI_OUT_OF_RESOURCES A memory buffer for string error records in not available
- @return r9 Base address of the returned buffer
- @return r10 Size of the returned buffer in bytes
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-EsalGetStateBuffer (
- IN UINT64 McaType,
- OUT UINT8 **McaBuffer,
- OUT UINTN *BufferSize
- )
-{
- SAL_RETURN_REGS Regs;
-
- Regs = EsalCall (
- EFI_EXTENDED_SAL_MCA_LOG_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_MCA_LOG_SERVICES_PROTOCOL_GUID_HI,
- EsalGetStateBufferFunctionId,
- McaType,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0
- );
-
- *McaBuffer = (UINT8 *) Regs.r9;
- *BufferSize = Regs.r10;
-
- return Regs;
-}
-
-/**
- Wrapper for the EsalSaveStateBufferFunctionId service of Extended SAL MCA Log Services Class.
-
- This function is a wrapper for the EsalSaveStateBufferFunctionId service of Extended SAL
- MCA Log Services Class. See EsalSaveStateBufferFunctionId of Extended SAL Specification.
-
- @param McaType See type parameter of SAL Procedure SAL_GET_STATE_INFO.
-
- @retval EFI_SUCCESS The memory buffer containing the error record was written to nonvolatile storage.
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-EsalSaveStateBuffer (
- IN UINT64 McaType
- )
-{
- return EsalCall (
- EFI_EXTENDED_SAL_MCA_LOG_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_MCA_LOG_SERVICES_PROTOCOL_GUID_HI,
- EsalSaveStateBufferFunctionId,
- McaType,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0
- );
-}
-
-/**
- Wrapper for the EsalGetVectorsFunctionId service of Extended SAL Base Services Class.
-
- This function is a wrapper for the EsalGetVectorsFunctionId service of Extended SAL
- Base Services Class. See EsalGetVectorsFunctionId of Extended SAL Specification.
-
- @param VectorType The vector type to retrieve.
- 0 - MCA, 1 - BSP INIT, 2 - BOOT_RENDEZ, 3 - AP INIT.
-
- @retval EFI_SAL_SUCCESS Call completed without error.
- @retval EFI_SAL_INVALID_ARGUMENT Invalid argument.
- @retval EFI_SAL_NO_INFORMATION The requested vector has not been registered
- with the SAL Procedure SAL_SET_VECTORS.
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-EsalGetVectors (
- IN UINT64 VectorType
- )
-{
- return EsalCall (
- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_HI,
- EsalGetVectorsFunctionId,
- VectorType,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0
- );
-}
-
-/**
- Wrapper for the EsalMcGetParamsFunctionId service of Extended SAL Base Services Class.
-
- This function is a wrapper for the EsalMcGetParamsFunctionId service of Extended SAL
- Base Services Class. See EsalMcGetParamsFunctionId of Extended SAL Specification.
-
- @param ParamInfoType The parameter type to retrieve.
- 1 - rendezvous interrupt
- 2 - wake up
- 3 - Corrected Platform Error Vector.
-
- @retval EFI_SAL_SUCCESS Call completed without error.
- @retval EFI_SAL_INVALID_ARGUMENT Invalid argument.
- @retval EFI_SAL_NO_INFORMATION The requested vector has not been registered
- with the SAL Procedure SAL_MC_SET_PARAMS.
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-EsalMcGetParams (
- IN UINT64 ParamInfoType
- )
-{
- return EsalCall (
- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_HI,
- EsalMcGetParamsFunctionId,
- ParamInfoType,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0
- );
-}
-
-/**
- Wrapper for the EsalMcGetParamsFunctionId service of Extended SAL Base Services Class.
-
- This function is a wrapper for the EsalMcGetParamsFunctionId service of Extended SAL
- Base Services Class. See EsalMcGetParamsFunctionId of Extended SAL Specification.
-
- @retval EFI_SAL_SUCCESS Call completed without error.
- @retval EFI_SAL_NO_INFORMATION The requested vector has not been registered
- with the SAL Procedure SAL_MC_SET_PARAMS.
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-EsalMcGetMcParams (
- VOID
- )
-{
- return EsalCall (
- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_HI,
- EsalMcGetMcParamsFunctionId,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0
- );
-}
-
-/**
- Wrapper for the EsalGetMcCheckinFlagsFunctionId service of Extended SAL Base Services Class.
-
- This function is a wrapper for the EsalGetMcCheckinFlagsFunctionId service of Extended SAL
- Base Services Class. See EsalGetMcCheckinFlagsFunctionId of Extended SAL Specification.
-
- @param CpuIndex The index of the CPU of set of enabled CPUs to check.
-
- @retval EFI_SAL_SUCCESS The checkin status of the requested CPU was returned.
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-EsalGetMcCheckinFlags (
- IN UINT64 CpuIndex
- )
-{
- return EsalCall (
- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_HI,
- EsalGetMcCheckinFlagsFunctionId,
- CpuIndex,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0
- );
-}
-
-/**
- Wrapper for the EsalAddCpuDataFunctionId service of Extended SAL MP Services Class.
-
- This function is a wrapper for the EsalAddCpuDataFunctionId service of Extended SAL
- MP Services Class. See EsalAddCpuDataFunctionId of Extended SAL Specification.
-
- @param CpuGlobalId The Global ID for the CPU being added.
- @param Enabled The enable flag for the CPU being added.
- TRUE means the CPU is enabled.
- FALSE means the CPU is disabled.
- @param PalCompatibility The PAL Compatibility value for the CPU being added.
-
- @retval EFI_SAL_SUCCESS The CPU was added to the database.
- @retval EFI_SAL_NOT_ENOUGH_SCRATCH There are not enough resource available to add the CPU.
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-EsalAddCpuData (
- IN UINT64 CpuGlobalId,
- IN BOOLEAN Enabled,
- IN UINT64 PalCompatibility
- )
-{
- return EsalCall (
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_HI,
- AddCpuDataFunctionId,
- CpuGlobalId,
- Enabled,
- PalCompatibility,
- 0,
- 0,
- 0,
- 0
- );
-}
-
-/**
- Wrapper for the EsalRemoveCpuDataFunctionId service of Extended SAL MP Services Class.
-
- This function is a wrapper for the EsalRemoveCpuDataFunctionId service of Extended SAL
- MP Services Class. See EsalRemoveCpuDataFunctionId of Extended SAL Specification.
-
- @param CpuGlobalId The Global ID for the CPU being removed.
-
- @retval EFI_SAL_SUCCESS The CPU was removed from the database.
- @retval EFI_SAL_NO_INFORMATION The specified CPU is not in the database.
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-EsalRemoveCpuData (
- IN UINT64 CpuGlobalId
- )
-{
- return EsalCall (
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_HI,
- RemoveCpuDataFunctionId,
- CpuGlobalId,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0
- );
-}
-
-/**
- Wrapper for the EsalModifyCpuDataFunctionId service of Extended SAL MP Services Class.
-
- This function is a wrapper for the EsalModifyCpuDataFunctionId service of Extended SAL
- MP Services Class. See EsalModifyCpuDataFunctionId of Extended SAL Specification.
-
- @param CpuGlobalId The Global ID for the CPU being modified.
- @param Enabled The enable flag for the CPU being modified.
- TRUE means the CPU is enabled.
- FALSE means the CPU is disabled.
- @param PalCompatibility The PAL Compatibility value for the CPU being modified.
-
- @retval EFI_SAL_SUCCESS The CPU database was updated.
- @retval EFI_SAL_NO_INFORMATION The specified CPU is not in the database.
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-EsalModifyCpuData (
- IN UINT64 CpuGlobalId,
- IN BOOLEAN Enabled,
- IN UINT64 PalCompatibility
- )
-{
- return EsalCall (
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_HI,
- ModifyCpuDataFunctionId,
- CpuGlobalId,
- Enabled,
- PalCompatibility,
- 0,
- 0,
- 0,
- 0
- );
-}
-
-/**
- Wrapper for the EsalGetCpuDataByIdFunctionId service of Extended SAL MP Services Class.
-
- This function is a wrapper for the EsalGetCpuDataByIdFunctionId service of Extended SAL
- MP Services Class. See EsalGetCpuDataByIdFunctionId of Extended SAL Specification.
-
- @param CpuGlobalId The Global ID for the CPU being looked up.
- @param IndexByEnabledCpu If TRUE, then the index of set of enabled CPUs of database is returned.
- If FALSE, then the index of set of all CPUs of database is returned.
-
- @retval EFI_SAL_SUCCESS The information on the specified CPU was returned.
- @retval EFI_SAL_NO_INFORMATION The specified CPU is not in the database.
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-EsalGetCpuDataById (
- IN UINT64 CpuGlobalId,
- IN BOOLEAN IndexByEnabledCpu
- )
-{
- return EsalCall (
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_HI,
- GetCpuDataByIDFunctionId,
- CpuGlobalId,
- IndexByEnabledCpu,
- 0,
- 0,
- 0,
- 0,
- 0
- );
-}
-
-/**
- Wrapper for the EsalGetCpuDataByIndexFunctionId service of Extended SAL MP Services Class.
-
- This function is a wrapper for the EsalGetCpuDataByIndexFunctionId service of Extended SAL
- MP Services Class. See EsalGetCpuDataByIndexFunctionId of Extended SAL Specification.
-
- @param Index The Global ID for the CPU being modified.
- @param IndexByEnabledCpu If TRUE, then the index of set of enabled CPUs of database is returned.
- If FALSE, then the index of set of all CPUs of database is returned.
-
- @retval EFI_SAL_SUCCESS The information on the specified CPU was returned.
- @retval EFI_SAL_NO_INFORMATION The specified CPU is not in the database.
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-EsalGetCpuDataByIndex (
- IN UINT64 Index,
- IN BOOLEAN IndexByEnabledCpu
- )
-{
- return EsalCall (
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_HI,
- GetCpuDataByIndexFunctionId,
- Index,
- IndexByEnabledCpu,
- 0,
- 0,
- 0,
- 0,
- 0
- );
-}
-
-/**
- Wrapper for the EsalWhoAmIFunctionId service of Extended SAL MP Services Class.
-
- This function is a wrapper for the EsalWhoAmIFunctionId service of Extended SAL
- MP Services Class. See EsalWhoAmIFunctionId of Extended SAL Specification.
-
- @param IndexByEnabledCpu If TRUE, then the index of set of enabled CPUs of database is returned.
- If FALSE, then the index of set of all CPUs of database is returned.
-
- @retval EFI_SAL_SUCCESS The Global ID for the calling CPU was returned.
- @retval EFI_SAL_NO_INFORMATION The calling CPU is not in the database.
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-EsalWhoAmI (
- IN BOOLEAN IndexByEnabledCpu
- )
-{
- return EsalCall (
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_HI,
- CurrentProcInfoFunctionId,
- IndexByEnabledCpu,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0
- );
-}
-
-/**
- Wrapper for the EsalNumProcessors service of Extended SAL MP Services Class.
-
- This function is a wrapper for the EsalNumProcessors service of Extended SAL
- MP Services Class. See EsalNumProcessors of Extended SAL Specification.
-
- @retval EFI_SAL_SUCCESS The information on the number of CPUs in the platform
- was returned.
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-EsalNumProcessors (
- VOID
- )
-{
- return EsalCall (
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_HI,
- NumProcessorsFunctionId,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0
- );
-}
-
-/**
- Wrapper for the EsalSetMinStateFnctionId service of Extended SAL MP Services Class.
-
- This function is a wrapper for the EsalSetMinStateFnctionId service of Extended SAL
- MP Services Class. See EsalSetMinStateFnctionId of Extended SAL Specification.
-
- @param CpuGlobalId The Global ID for the CPU whose MINSTATE pointer is being set.
- @param MinStatePointer The physical address of the MINSTATE buffer for the CPU
- specified by CpuGlobalId.
-
- @retval EFI_SAL_SUCCESS The MINSTATE pointer was set for the specified CPU.
- @retval EFI_SAL_NO_INFORMATION The specified CPU is not in the database.
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-EsalSetMinState (
- IN UINT64 CpuGlobalId,
- IN EFI_PHYSICAL_ADDRESS MinStatePointer
- )
-{
- return EsalCall (
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_HI,
- SetMinStateFunctionId,
- CpuGlobalId,
- MinStatePointer,
- 0,
- 0,
- 0,
- 0,
- 0
- );
-}
-
-/**
- Wrapper for the EsalGetMinStateFunctionId service of Extended SAL MP Services Class.
-
- This function is a wrapper for the EsalGetMinStateFunctionId service of Extended SAL
- MP Services Class. See EsalGetMinStateFunctionId of Extended SAL Specification.
-
- @param CpuGlobalId The Global ID for the CPU whose MINSTATE pointer is being retrieved.
-
- @retval EFI_SAL_SUCCESS The MINSTATE pointer for the specified CPU was retrieved.
- @retval EFI_SAL_NO_INFORMATION The specified CPU is not in the database.
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-EsalGetMinState (
- IN UINT64 CpuGlobalId
- )
-{
- return EsalCall (
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_HI,
- GetMinStateFunctionId,
- CpuGlobalId,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0
- );
-}
-
-/**
- Wrapper for the EsalMcsGetStateInfoFunctionId service of Extended SAL MCA Services Class.
-
- This function is a wrapper for the EsalMcsGetStateInfoFunctionId service of Extended SAL
- MCA Services Class. See EsalMcsGetStateInfoFunctionId of Extended SAL Specification.
-
- @param CpuGlobalId The Global ID for the CPU whose MCA state buffer is being retrieved.
- @param StateBufferPointer A pointer to the returned MCA state buffer.
- @param RequiredStateBufferSize A pointer to the size, in bytes, of the returned MCA state buffer.
-
- @retval EFI_SUCCESS MINSTATE successfully got and size calculated.
- @retval EFI_SAL_NO_INFORMATION Fail to get MINSTATE.
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-EsalMcaGetStateInfo (
- IN UINT64 CpuGlobalId,
- OUT EFI_PHYSICAL_ADDRESS *StateBufferPointer,
- OUT UINT64 *RequiredStateBufferSize
- )
-{
- SAL_RETURN_REGS Regs;
-
- Regs = EsalCall (
- EFI_EXTENDED_SAL_MCA_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_MCA_SERVICES_PROTOCOL_GUID_HI,
- McaGetStateInfoFunctionId,
- CpuGlobalId,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0
- );
-
- *StateBufferPointer = (EFI_PHYSICAL_ADDRESS) Regs.r9;
- *RequiredStateBufferSize = (UINT64) Regs.r10;
-
- return Regs;
-}
-
-/**
- Wrapper for the EsalMcaRegisterCpuFunctionId service of Extended SAL MCA Services Class.
-
- This function is a wrapper for the EsalMcaRegisterCpuFunctionId service of Extended SAL
- MCA Services Class. See EsalMcaRegisterCpuFunctionId of Extended SAL Specification.
-
- @param CpuGlobalId The Global ID for the CPU whose MCA state buffer is being set.
- @param StateBufferPointer A pointer to the MCA state buffer.
-
- @retval EFI_SAL_NO_INFORMATION Cannot get the processor info with the CpuId
- @retval EFI_SUCCESS Save the processor's state info successfully
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-EsalMcaRegisterCpu (
- IN UINT64 CpuGlobalId,
- IN EFI_PHYSICAL_ADDRESS StateBufferPointer
- )
-{
- return EsalCall (
- EFI_EXTENDED_SAL_MCA_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_MCA_SERVICES_PROTOCOL_GUID_HI,
- McaRegisterCpuFunctionId,
- CpuGlobalId,
- StateBufferPointer,
- 0,
- 0,
- 0,
- 0,
- 0
- );
-}
diff --git a/MdePkg/Library/DxeRuntimeExtendedSalLib/Ipf/AsmExtendedSalLib.s b/MdePkg/Library/DxeRuntimeExtendedSalLib/Ipf/AsmExtendedSalLib.s
deleted file mode 100644
index ddabc76e0d..0000000000
--- a/MdePkg/Library/DxeRuntimeExtendedSalLib/Ipf/AsmExtendedSalLib.s
+++ /dev/null
@@ -1,131 +0,0 @@
-/// @file
-/// Assembly procedures to get and set ESAL entry point.
-///
-/// Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
-/// This program and the accompanying materials
-/// are licensed and made available under the terms and conditions of the BSD License
-/// which accompanies this distribution. The full text of the license may be found at
-/// http://opensource.org/licenses/bsd-license.php.
-///
-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-///
-
-.auto
-.text
-
-#include "IpfMacro.i"
-
-//
-// Exports
-//
-ASM_GLOBAL GetEsalEntryPoint
-
-//-----------------------------------------------------------------------------
-//++
-// GetEsalEntryPoint
-//
-// Return Esal global and PSR register.
-//
-// On Entry :
-//
-//
-// Return Value:
-// r8 = EFI_SAL_SUCCESS
-// r9 = Physical Plabel
-// r10 = Virtual Plabel
-// r11 = psr
-//
-// As per static calling conventions.
-//
-//--
-//---------------------------------------------------------------------------
-PROCEDURE_ENTRY (GetEsalEntryPoint)
-
- NESTED_SETUP (0,8,0,0)
-
-EsalCalcStart:
- mov r8 = ip;;
- add r8 = (EsalEntryPoint - EsalCalcStart), r8;;
- mov r9 = r8;;
- add r10 = 0x10, r8;;
- mov r11 = psr;;
- mov r8 = r0;;
-
- NESTED_RETURN
-
-PROCEDURE_EXIT (GetEsalEntryPoint)
-
-//-----------------------------------------------------------------------------
-//++
-// SetEsalPhysicalEntryPoint
-//
-// Set the dispatcher entry point
-//
-// On Entry:
-// in0 = Physical address of Esal Dispatcher
-// in1 = Physical GP
-//
-// Return Value:
-// r8 = EFI_SAL_SUCCESS
-//
-// As per static calling conventions.
-//
-//--
-//---------------------------------------------------------------------------
-PROCEDURE_ENTRY (SetEsalPhysicalEntryPoint)
-
- NESTED_SETUP (2,8,0,0)
-
-EsalCalcStart1:
- mov r8 = ip;;
- add r8 = (EsalEntryPoint - EsalCalcStart1), r8;;
- st8 [r8] = in0;;
- add r8 = 0x08, r8;;
- st8 [r8] = in1;;
- mov r8 = r0;;
-
- NESTED_RETURN
-
-PROCEDURE_EXIT (SetEsalPhysicalEntryPoint)
-
-//-----------------------------------------------------------------------------
-//++
-// SetEsalVirtualEntryPoint
-//
-// Register physical address of Esal globals.
-//
-// On Entry :
-// in0 = Virtual address of Esal Dispatcher
-// in1 = Virtual GP
-//
-// Return Value:
-// r8 = EFI_SAL_ERROR
-//
-// As per static calling conventions.
-//
-//--
-//---------------------------------------------------------------------------
-PROCEDURE_ENTRY (SetEsalVirtualEntryPoint)
-
- NESTED_SETUP (2,8,0,0)
-
-EsalCalcStart2:
- mov r8 = ip;;
- add r8 = (EsalEntryPoint - EsalCalcStart2), r8;;
- add r8 = 0x10, r8;;
- st8 [r8] = in0;;
- add r8 = 0x08, r8;;
- st8 [r8] = in1;;
- mov r8 = r0;;
-
- NESTED_RETURN
-
-PROCEDURE_EXIT (SetEsalVirtualEntryPoint)
-
-.align 32
-EsalEntryPoint:
- data8 0 // Physical Entry
- data8 0 // GP
- data8 0 // Virtual Entry
- data8 0 // GP
diff --git a/MdePkg/Library/DxeRuntimePciExpressLib/DxeRuntimePciExpressLib.inf b/MdePkg/Library/DxeRuntimePciExpressLib/DxeRuntimePciExpressLib.inf
index 5d7357035b..48848496cb 100644
--- a/MdePkg/Library/DxeRuntimePciExpressLib/DxeRuntimePciExpressLib.inf
+++ b/MdePkg/Library/DxeRuntimePciExpressLib/DxeRuntimePciExpressLib.inf
@@ -31,7 +31,7 @@
DESTRUCTOR = DxeRuntimePciExpressLibDestructor
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]
diff --git a/MdePkg/Library/DxeSalLibEsal/DxeSalLibEsal.c b/MdePkg/Library/DxeSalLibEsal/DxeSalLibEsal.c
deleted file mode 100644
index 8d1dd9ae15..0000000000
--- a/MdePkg/Library/DxeSalLibEsal/DxeSalLibEsal.c
+++ /dev/null
@@ -1,286 +0,0 @@
-/** @file
- This library implements the SAL Library Class using Extended SAL functions
-
- Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php.
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include <PiDxe.h>
-
-#include <Protocol/ExtendedSalServiceClasses.h>
-
-#include <Library/SalLib.h>
-#include <Library/ExtendedSalLib.h>
-
-/**
- Makes a SAL procedure call.
-
- This is a wrapper function to make a SAL procedure call.
- No parameter checking is performed on the 8 input parameters,
- but there are some common rules that the caller should follow
- when making a SAL call. Any address passed to SAL as buffers
- for return parameters must be 8-byte aligned. Unaligned
- addresses may cause undefined results. For those parameters
- defined as reserved or some fields defined as reserved must be
- zero filled or the invalid argument return value may be returned
- or undefined result may occur during the execution of the procedure.
- This function is only available on IPF.
-
- @param Index The SAL procedure Index number
- @param Arg2 The 2nd parameter for SAL procedure calls
- @param Arg3 The 3rd parameter for SAL procedure calls
- @param Arg4 The 4th parameter for SAL procedure calls
- @param Arg5 The 5th parameter for SAL procedure calls
- @param Arg6 The 6th parameter for SAL procedure calls
- @param Arg7 The 7th parameter for SAL procedure calls
- @param Arg8 The 8th parameter for SAL procedure calls
-
- @return SAL returned registers.
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-SalCall (
- IN UINT64 Index,
- IN UINT64 Arg2,
- IN UINT64 Arg3,
- IN UINT64 Arg4,
- IN UINT64 Arg5,
- IN UINT64 Arg6,
- IN UINT64 Arg7,
- IN UINT64 Arg8
- )
-{
- SAL_RETURN_REGS Regs;
-
- //
- // Initial all members in this structure.
- //
- Regs.r9 = 0;
- Regs.r10 = 0;
- Regs.r11 = 0;
- Regs.Status = EFI_SAL_INVALID_ARGUMENT;
-
- switch (Index) {
- case EFI_SAL_SET_VECTORS:
- return EsalCall (
- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_HI,
- SalSetVectorsFunctionId,
- Arg2,
- Arg3,
- Arg4,
- Arg5,
- Arg6,
- Arg7,
- Arg8
- );
- break;
-
- case EFI_SAL_GET_STATE_INFO:
- return EsalCall (
- EFI_EXTENDED_SAL_MCA_LOG_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_MCA_LOG_SERVICES_PROTOCOL_GUID_HI,
- SalGetStateInfoFunctionId,
- Arg2,
- Arg3,
- Arg4,
- Arg5,
- Arg6,
- Arg7,
- Arg8
- );
- break;
-
- case EFI_SAL_GET_STATE_INFO_SIZE:
- return EsalCall (
- EFI_EXTENDED_SAL_MCA_LOG_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_MCA_LOG_SERVICES_PROTOCOL_GUID_HI,
- SalGetStateInfoSizeFunctionId,
- Arg2,
- Arg3,
- Arg4,
- Arg5,
- Arg6,
- Arg7,
- Arg8
- );
- break;
-
- case EFI_SAL_CLEAR_STATE_INFO:
- return EsalCall (
- EFI_EXTENDED_SAL_MCA_LOG_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_MCA_LOG_SERVICES_PROTOCOL_GUID_HI,
- SalClearStateInfoFunctionId,
- Arg2,
- Arg3,
- Arg4,
- Arg5,
- Arg6,
- Arg7,
- Arg8
- );
- break;
-
- case EFI_SAL_MC_RENDEZ:
- return EsalCall (
- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_HI,
- SalMcRendezFunctionId,
- Arg2,
- Arg3,
- Arg4,
- Arg5,
- Arg6,
- Arg7,
- Arg8
- );
- break;
-
- case EFI_SAL_MC_SET_PARAMS:
- return EsalCall (
- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_HI,
- SalMcSetParamsFunctionId,
- Arg2,
- Arg3,
- Arg4,
- Arg5,
- Arg6,
- Arg7,
- Arg8
- );
- break;
-
- case EFI_SAL_REGISTER_PHYSICAL_ADDR:
- return EsalCall (
- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_HI,
- EsalRegisterPhysicalAddrFunctionId,
- Arg2,
- Arg3,
- Arg4,
- Arg5,
- Arg6,
- Arg7,
- Arg8
- );
- break;
-
- case EFI_SAL_CACHE_FLUSH:
- return EsalCall (
- EFI_EXTENDED_SAL_CACHE_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_CACHE_SERVICES_PROTOCOL_GUID_HI,
- SalCacheFlushFunctionId,
- Arg2,
- Arg3,
- Arg4,
- Arg5,
- Arg6,
- Arg7,
- Arg8
- );
- break;
-
- case EFI_SAL_CACHE_INIT:
- return EsalCall (
- EFI_EXTENDED_SAL_CACHE_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_CACHE_SERVICES_PROTOCOL_GUID_HI,
- SalCacheInitFunctionId,
- Arg2,
- Arg3,
- Arg4,
- Arg5,
- Arg6,
- Arg7,
- Arg8
- );
- break;
-
- case EFI_SAL_PCI_CONFIG_READ:
- return EsalCall (
- EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_HI,
- SalPciConfigReadFunctionId,
- Arg2,
- Arg3,
- Arg4,
- Arg5,
- Arg6,
- Arg7,
- Arg8
- );
- break;
-
- case EFI_SAL_PCI_CONFIG_WRITE:
- return EsalCall (
- EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_HI,
- SalPciConfigWriteFunctionId,
- Arg2,
- Arg3,
- Arg4,
- Arg5,
- Arg6,
- Arg7,
- Arg8
- );
- break;
-
- case EFI_SAL_FREQ_BASE:
- return EsalCall (
- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_HI,
- EsalGetPlatformBaseFreqFunctionId,
- Arg2,
- Arg3,
- Arg4,
- Arg5,
- Arg6,
- Arg7,
- Arg8
- );
- break;
-
- case EFI_SAL_PHYSICAL_ID_INFO:
- return EsalCall (
- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_HI,
- EsalPhysicalIdInfoFunctionId,
- Arg2,
- Arg3,
- Arg4,
- Arg5,
- Arg6,
- Arg7,
- Arg8
- );
- break;
-
- case EFI_SAL_UPDATE_PAL:
- return EsalCall (
- EFI_EXTENDED_SAL_PAL_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_PAL_SERVICES_PROTOCOL_GUID_HI,
- EsalUpdatePalFunctionId,
- Arg2,
- Arg3,
- Arg4,
- Arg5,
- Arg6,
- Arg7,
- Arg8
- );
- break;
-
- default:
- return Regs;
- break;
- }
-}
diff --git a/MdePkg/Library/DxeSalLibEsal/DxeSalLibEsal.inf b/MdePkg/Library/DxeSalLibEsal/DxeSalLibEsal.inf
deleted file mode 100644
index 656d949574..0000000000
--- a/MdePkg/Library/DxeSalLibEsal/DxeSalLibEsal.inf
+++ /dev/null
@@ -1,38 +0,0 @@
-## @file
-# This library implements the SAL Library Class using Extended SAL functions
-#
-# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php.
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-##
-
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = DxeSalLibEsal
- MODULE_UNI_FILE = DxeSalLibEsal.uni
- FILE_GUID = 2B73B074-2E67-498b-82AC-CE38FB770FFC
- MODULE_TYPE = DXE_DRIVER
- VERSION_STRING = 1.0
- LIBRARY_CLASS = SalLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
-
-#
-# The following information is for reference only and not required by the build tools.
-#
-# VALID_ARCHITECTURES = IPF
-#
-
-[Sources.IPF]
- DxeSalLibEsal.c
-
-[Packages]
- MdePkg/MdePkg.dec
-
-[LibraryClasses]
- ExtendedSalLib
-
diff --git a/MdePkg/Library/DxeServicesLib/DxeServicesLib.inf b/MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
index 50ae24f8ee..ab53ffbd3c 100644
--- a/MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+++ b/MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
@@ -24,16 +24,16 @@
FILE_GUID = EE680C58-FFC0-4a5d-858F-66FF9C84BC9F
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
- LIBRARY_CLASS = DxeServicesLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER SMM_CORE UEFI_APPLICATION UEFI_DRIVER
+ LIBRARY_CLASS = DxeServicesLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER SMM_CORE UEFI_APPLICATION UEFI_DRIVER
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC ARM AARCH64
+# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64
#
[Sources]
DxeServicesLib.c
-[Sources.IA32, Sources.IPF, Sources.EBC, Sources.ARM, Sources.AARCH64]
+[Sources.IA32, Sources.EBC, Sources.ARM, Sources.AARCH64]
Allocate.c
[Sources.X64]
diff --git a/MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf b/MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
index 8ad198c2f3..7a34716e4a 100644
--- a/MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
+++ b/MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
@@ -23,12 +23,12 @@
FILE_GUID = baa1baa3-0a8d-402c-8042-985115fae953
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
- LIBRARY_CLASS = DxeServicesTableLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER SMM_CORE
+ LIBRARY_CLASS = DxeServicesTableLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER SMM_CORE
CONSTRUCTOR = DxeServicesTableLibConstructor
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]
diff --git a/MdePkg/Library/DxeSmbusLib/DxeSmbusLib.inf b/MdePkg/Library/DxeSmbusLib/DxeSmbusLib.inf
index d4f082ec4c..c8eca3d73d 100644
--- a/MdePkg/Library/DxeSmbusLib/DxeSmbusLib.inf
+++ b/MdePkg/Library/DxeSmbusLib/DxeSmbusLib.inf
@@ -20,12 +20,12 @@
FILE_GUID = 4F369FB1-31A7-423c-960E-B3EFD337894F
MODULE_TYPE = DXE_DRIVER
VERSION_STRING = 1.0
- LIBRARY_CLASS = SmbusLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER
+ LIBRARY_CLASS = SmbusLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER
CONSTRUCTOR = SmbusLibConstructor
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]
diff --git a/MdePkg/Library/DxeTimerLibEsal/DxeTimerLibEsal.c b/MdePkg/Library/DxeTimerLibEsal/DxeTimerLibEsal.c
deleted file mode 100644
index 8ca3ec6f8b..0000000000
--- a/MdePkg/Library/DxeTimerLibEsal/DxeTimerLibEsal.c
+++ /dev/null
@@ -1,223 +0,0 @@
-/** @file
- This library implements the Timer Library using the Extended SAL Stall Services Class.
-
- Copyright (c) 2007 - 2011, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php.
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include <PiDxe.h>
-
-#include <Protocol/ExtendedSalServiceClasses.h>
-
-#include <Library/TimerLib.h>
-#include <Library/BaseLib.h>
-#include <Library/ExtendedSalLib.h>
-#include <Library/DebugLib.h>
-#include <Library/PalLib.h>
-
-/**
- Stalls the CPU for at least the given number of microseconds.
-
- This function wraps EsalStall function of Extended SAL Stall Services Class.
- It stalls the CPU for the number of microseconds specified by MicroSeconds.
-
- @param MicroSeconds The minimum number of microseconds to delay.
-
- @return MicroSeconds
-
-**/
-UINTN
-EFIAPI
-MicroSecondDelay (
- IN UINTN MicroSeconds
- )
-{
- EsalCall (
- EFI_EXTENDED_SAL_STALL_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_STALL_SERVICES_PROTOCOL_GUID_HI,
- StallFunctionId,
- MicroSeconds,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0
- );
- return MicroSeconds;
-}
-
-/**
- Stalls the CPU for at least the given number of nanoseconds.
-
- This function wraps EsalStall function of Extended SAL Stall Services Class.
- It stalls the CPU for the number of nanoseconds specified by NanoSeconds.
-
- @param NanoSeconds The minimum number of nanoseconds to delay.
-
- @return NanoSeconds
-
-**/
-UINTN
-EFIAPI
-NanoSecondDelay (
- IN UINTN NanoSeconds
- )
-{
- UINT64 MicroSeconds;
-
- //
- // The unit of ESAL Stall service is microsecond, so we turn the time interval
- // from nanosecond to microsecond, using the ceiling value to ensure stalling
- // at least the given number of nanoseconds.
- //
- MicroSeconds = DivU64x32 (NanoSeconds + 999, 1000);
- EsalCall (
- EFI_EXTENDED_SAL_STALL_SERVICES_PROTOCOL_GUID_LO,
- EFI_EXTENDED_SAL_STALL_SERVICES_PROTOCOL_GUID_HI,
- StallFunctionId,
- MicroSeconds,
- 0,
- 0,
- 0,
- 0,
- 0,
- 0
- );
- return NanoSeconds;
-}
-
-/**
- Retrieves the current value of a 64-bit free running performance counter.
-
- Retrieves the current value of a 64-bit free running performance counter. The
- counter can either count up by 1 or count down by 1. If the physical
- performance counter counts by a larger increment, then the counter values
- must be translated. The properties of the counter can be retrieved from
- GetPerformanceCounterProperties().
-
- @return The current value of the free running performance counter.
-
-**/
-UINT64
-EFIAPI
-GetPerformanceCounter (
- VOID
- )
-{
- return AsmReadItc ();
-}
-
-/**
- Retrieves the 64-bit frequency in Hz and the range of performance counter
- values.
-
- If StartValue is not NULL, then the value that the performance counter starts
- with immediately after is it rolls over is returned in StartValue. If
- EndValue is not NULL, then the value that the performance counter end with
- immediately before it rolls over is returned in EndValue. The 64-bit
- frequency of the performance counter in Hz is always returned. If StartValue
- is less than EndValue, then the performance counter counts up. If StartValue
- is greater than EndValue, then the performance counter counts down. For
- example, a 64-bit free running counter that counts up would have a StartValue
- of 0 and an EndValue of 0xFFFFFFFFFFFFFFFF. A 24-bit free running counter
- that counts down would have a StartValue of 0xFFFFFF and an EndValue of 0.
-
- @param StartValue The value the performance counter starts with when it
- rolls over.
- @param EndValue The value that the performance counter ends with before
- it rolls over.
-
- @return The frequency in Hz.
-
-**/
-UINT64
-EFIAPI
-GetPerformanceCounterProperties (
- OUT UINT64 *StartValue, OPTIONAL
- OUT UINT64 *EndValue OPTIONAL
- )
-{
- PAL_CALL_RETURN PalRet;
- UINT64 BaseFrequence;
-
- //
- // Get processor base frequency
- //
- PalRet = PalCall (PAL_FREQ_BASE, 0, 0, 0);
- ASSERT (PalRet.Status == 0);
- BaseFrequence = PalRet.r9;
-
- //
- // Get processor frequency ratio
- //
- PalRet = PalCall (PAL_FREQ_RATIOS, 0, 0, 0);
- ASSERT (PalRet.Status == 0);
-
- //
- // Start value of counter is 0
- //
- if (StartValue != NULL) {
- *StartValue = 0;
- }
-
- //
- // End value of counter is 0xFFFFFFFFFFFFFFFF
- //
- if (EndValue != NULL) {
- *EndValue = (UINT64)(-1);
- }
-
- return BaseFrequence * (PalRet.r11 >> 32) / (UINT32)PalRet.r11;
-}
-
-/**
- Converts elapsed ticks of performance counter to time in nanoseconds.
-
- This function converts the elapsed ticks of running performance counter to
- time value in unit of nanoseconds.
-
- @param Ticks The number of elapsed ticks of running performance counter.
-
- @return The elapsed time in nanoseconds.
-
-**/
-UINT64
-EFIAPI
-GetTimeInNanoSecond (
- IN UINT64 Ticks
- )
-{
- UINT64 Frequency;
- UINT64 NanoSeconds;
- UINT64 Remainder;
- INTN Shift;
-
- Frequency = GetPerformanceCounterProperties (NULL, NULL);
-
- //
- // Ticks
- // Time = --------- x 1,000,000,000
- // Frequency
- //
- NanoSeconds = MultU64x32 (DivU64x64Remainder (Ticks, Frequency, &Remainder), 1000000000u);
-
- //
- // Ensure (Remainder * 1,000,000,000) will not overflow 64-bit.
- // Since 2^29 < 1,000,000,000 = 0x3B9ACA00 < 2^30, Remainder should < 2^(64-30) = 2^34,
- // i.e. highest bit set in Remainder should <= 33.
- //
- Shift = MAX (0, HighBitSet64 (Remainder) - 33);
- Remainder = RShiftU64 (Remainder, (UINTN) Shift);
- Frequency = RShiftU64 (Frequency, (UINTN) Shift);
- NanoSeconds += DivU64x64Remainder (MultU64x32 (Remainder, 1000000000u), Frequency, NULL);
-
- return NanoSeconds;
-}
diff --git a/MdePkg/Library/DxeTimerLibEsal/DxeTimerLibEsal.inf b/MdePkg/Library/DxeTimerLibEsal/DxeTimerLibEsal.inf
deleted file mode 100644
index 0f24989ab9..0000000000
--- a/MdePkg/Library/DxeTimerLibEsal/DxeTimerLibEsal.inf
+++ /dev/null
@@ -1,41 +0,0 @@
-## @file
-# This library implements the Timer Library using the Extended SAL Stall Services Class.
-#
-# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php.
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-##
-
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = DxeTimerLibEsal
- MODULE_UNI_FILE = DxeTimerLibEsal.uni
- FILE_GUID = F672AE85-3769-4fb8-A5A0-70B38FB0A7C4
- MODULE_TYPE = DXE_DRIVER
- VERSION_STRING = 1.0
- LIBRARY_CLASS = TimerLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
-
-#
-# The following information is for reference only and not required by the build tools.
-#
-# VALID_ARCHITECTURES = IPF
-#
-
-[Sources]
- DxeTimerLibEsal.c
-
-[Packages]
- MdePkg/MdePkg.dec
-
-[LibraryClasses]
- DebugLib
- ExtendedSalLib
- BaseLib
- PalLib
-
diff --git a/MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLibSegmentInfo.inf b/MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLibSegmentInfo.inf
index 9cd60764dc..d18cc97e54 100644
--- a/MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLibSegmentInfo.inf
+++ b/MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLibSegmentInfo.inf
@@ -28,7 +28,7 @@
#
# The following information is for reference only and not required by the build tools.
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]
diff --git a/MdePkg/Library/PciSegmentLibSegmentInfo/DxeRuntimePciSegmentLibSegmentInfo.inf b/MdePkg/Library/PciSegmentLibSegmentInfo/DxeRuntimePciSegmentLibSegmentInfo.inf
index e484af5b06..21bc412f8c 100644
--- a/MdePkg/Library/PciSegmentLibSegmentInfo/DxeRuntimePciSegmentLibSegmentInfo.inf
+++ b/MdePkg/Library/PciSegmentLibSegmentInfo/DxeRuntimePciSegmentLibSegmentInfo.inf
@@ -30,7 +30,7 @@
#
# The following information is for reference only and not required by the build tools.
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]
diff --git a/MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf b/MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
index d920306713..f04f388e96 100644
--- a/MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
+++ b/MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
@@ -23,7 +23,7 @@
LIBRARY_CLASS = PeiCoreEntryPoint|PEI_CORE
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC (EBC is for build only)
+# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only)
#
[Sources]
diff --git a/MdePkg/Library/PeiDxePostCodeLibReportStatusCode/PeiDxePostCodeLibReportStatusCode.inf b/MdePkg/Library/PeiDxePostCodeLibReportStatusCode/PeiDxePostCodeLibReportStatusCode.inf
index dc162c2ddb..97013361df 100644
--- a/MdePkg/Library/PeiDxePostCodeLibReportStatusCode/PeiDxePostCodeLibReportStatusCode.inf
+++ b/MdePkg/Library/PeiDxePostCodeLibReportStatusCode/PeiDxePostCodeLibReportStatusCode.inf
@@ -22,11 +22,11 @@
FILE_GUID = e062c52d-78dc-4cc5-b246-b13497a8123c
MODULE_TYPE = PEIM
VERSION_STRING = 1.0
- LIBRARY_CLASS = PostCodeLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER PEIM PEI_CORE UEFI_APPLICATION UEFI_DRIVER
+ LIBRARY_CLASS = PostCodeLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER PEIM PEI_CORE UEFI_APPLICATION UEFI_DRIVER
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]
diff --git a/MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf b/MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
index 1b6e6a8680..9d47a8e5c1 100644
--- a/MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
+++ b/MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
@@ -27,7 +27,7 @@
#
# The following information is for reference only and not required by the build tools.
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC (EBC is for build only)
+# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only)
#
[Sources]
diff --git a/MdePkg/Library/PeiHobLib/PeiHobLib.inf b/MdePkg/Library/PeiHobLib/PeiHobLib.inf
index 027ba6f856..2817c113f6 100644
--- a/MdePkg/Library/PeiHobLib/PeiHobLib.inf
+++ b/MdePkg/Library/PeiHobLib/PeiHobLib.inf
@@ -26,7 +26,7 @@
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC (EBC is for build only)
+# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only)
#
[Sources]
diff --git a/MdePkg/Library/PeiIoLibCpuIo/PeiIoLibCpuIo.inf b/MdePkg/Library/PeiIoLibCpuIo/PeiIoLibCpuIo.inf
index d12418127e..c34b3760a7 100644
--- a/MdePkg/Library/PeiIoLibCpuIo/PeiIoLibCpuIo.inf
+++ b/MdePkg/Library/PeiIoLibCpuIo/PeiIoLibCpuIo.inf
@@ -27,7 +27,7 @@
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC (EBC is for build only)
+# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only)
#
[Sources]
diff --git a/MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf b/MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
index db158135b8..ceac7a9ee1 100644
--- a/MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+++ b/MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
@@ -27,7 +27,7 @@
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC (EBC is for build only)
+# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only)
#
[Sources]
diff --git a/MdePkg/Library/PeiMemoryLib/PeiMemoryLib.inf b/MdePkg/Library/PeiMemoryLib/PeiMemoryLib.inf
index 56d584dad6..68b8919001 100644
--- a/MdePkg/Library/PeiMemoryLib/PeiMemoryLib.inf
+++ b/MdePkg/Library/PeiMemoryLib/PeiMemoryLib.inf
@@ -27,7 +27,7 @@
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC (EBC is for build only)
+# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only)
#
[Sources]
diff --git a/MdePkg/Library/PeiPalLib/PeiPalLib.c b/MdePkg/Library/PeiPalLib/PeiPalLib.c
deleted file mode 100644
index 8209e1d478..0000000000
--- a/MdePkg/Library/PeiPalLib/PeiPalLib.c
+++ /dev/null
@@ -1,99 +0,0 @@
-/** @file
- PAL Call Services Function.
-
- Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php.
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-
-#include <PiPei.h>
-
-#include <Ppi/SecPlatformInformation.h>
-
-#include <Library/PalLib.h>
-#include <Library/PeiServicesTablePointerLib.h>
-#include <Library/PeiServicesLib.h>
-#include <Library/BaseLib.h>
-#include <Library/DebugLib.h>
-
-/**
- Makes a PAL procedure call.
-
- This is a wrapper function to make a PAL procedure call. Based on the Index value,
- this API will make static or stacked PAL call. Architected procedures may be designated
- as required or optional. If a PAL procedure is specified as optional, a unique return
- code of 0xFFFFFFFFFFFFFFFF is returned in the Status field of the PAL_CALL_RETURN structure.
- This indicates that the procedure is not present in this PAL implementation. It is the
- caller's responsibility to check for this return code after calling any optional PAL
- procedure. No parameter checking is performed on the 4 input parameters, but there are
- some common rules that the caller should follow when making a PAL call. Any address
- passed to PAL as buffers for return parameters must be 8-byte aligned. Unaligned addresses
- may cause undefined results. For those parameters defined as reserved or some fields
- defined as reserved must be zero filled or the invalid argument return value may be
- returned or undefined result may occur during the execution of the procedure.
- This function is only available on IPF.
-
- @param Index The PAL procedure Index number.
- @param Arg2 The 2nd parameter for PAL procedure calls.
- @param Arg3 The 3rd parameter for PAL procedure calls.
- @param Arg4 The 4th parameter for PAL procedure calls.
-
- @return Structure returned from the PAL Call procedure, including the status and return value.
-
-**/
-PAL_CALL_RETURN
-EFIAPI
-PalCall (
- IN UINT64 Index,
- IN UINT64 Arg2,
- IN UINT64 Arg3,
- IN UINT64 Arg4
- )
-{
- UINT64 PalCallAddress;
- PAL_CALL_RETURN ReturnVal;
- CONST EFI_PEI_SERVICES **PeiServices;
- EFI_STATUS Status;
- EFI_SEC_PLATFORM_INFORMATION_PPI *SecPlatformPpi;
- EFI_SEC_PLATFORM_INFORMATION_RECORD SecPlatformInfoRecord;
- UINT64 RecordSize;
-
- //
- // Get PEI Service Table Pointer
- //
- PeiServices = GetPeiServicesTablePointer ();
-
- //
- // Locate SEC Platform Information PPI
- //
- Status = PeiServicesLocatePpi (
- &gEfiSecPlatformInformationPpiGuid,
- 0,
- NULL,
- (VOID **)&SecPlatformPpi
- );
- ASSERT_EFI_ERROR (Status);
-
- //
- // Retrieve PAL call address from platform information reported by the PPI
- //
- RecordSize = sizeof (SecPlatformInfoRecord);
- SecPlatformPpi->PlatformInformation (
- PeiServices,
- &RecordSize,
- &SecPlatformInfoRecord
- );
- PalCallAddress = SecPlatformInfoRecord.ItaniumHealthFlags.PalCallAddress;
-
- ReturnVal = AsmPalCall (PalCallAddress, Index, Arg2, Arg3, Arg4);
-
- return ReturnVal;
-}
-
diff --git a/MdePkg/Library/PeiPalLib/PeiPalLib.inf b/MdePkg/Library/PeiPalLib/PeiPalLib.inf
deleted file mode 100644
index 6b49f6e502..0000000000
--- a/MdePkg/Library/PeiPalLib/PeiPalLib.inf
+++ /dev/null
@@ -1,51 +0,0 @@
-## @file
-# Instance of PAL Library using a PPI for PAL entrypoint.
-#
-# Instance of PAL Library that uses a PPI to retrieve the PAL
-# Entry Point and layers on top of AsmPalCall() in the Base Library
-#
-# Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php.
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#
-##
-
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = PeiPalLib
- MODULE_UNI_FILE = PeiPalLib.uni
- FILE_GUID = B53DC524-6B98-4584-940B-8F1363DEF09E
- MODULE_TYPE = PEIM
- VERSION_STRING = 1.0
- LIBRARY_CLASS = PalLib|PEIM SEC PEI_CORE
-
-
-#
-# The following information is for reference only and not required by the build tools.
-#
-# VALID_ARCHITECTURES = IPF
-#
-
-[Sources]
- PeiPalLib.c
-
-
-[Packages]
- MdePkg/MdePkg.dec
-
-
-[LibraryClasses]
- BaseLib
- PeiServicesLib
- PeiServicesTablePointerLib
-
-
-[Ppis]
- gEfiSecPlatformInformationPpiGuid ## CONSUMES
-
diff --git a/MdePkg/Library/PeiPcdLib/PeiPcdLib.inf b/MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
index 75786c1d4f..f2f1f593aa 100644
--- a/MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
+++ b/MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
@@ -38,7 +38,7 @@
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC (EBC is for build only)
+# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only)
#
[Sources]
diff --git a/MdePkg/Library/PeiPciLibPciCfg2/PeiPciLibPciCfg2.inf b/MdePkg/Library/PeiPciLibPciCfg2/PeiPciLibPciCfg2.inf
index 2a6168522f..12ef7fa7ae 100644
--- a/MdePkg/Library/PeiPciLibPciCfg2/PeiPciLibPciCfg2.inf
+++ b/MdePkg/Library/PeiPciLibPciCfg2/PeiPciLibPciCfg2.inf
@@ -31,7 +31,7 @@
#
# The following information is for reference only and not required by the build tools.
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC (EBC is for build only)
+# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only)
#
[Sources]
diff --git a/MdePkg/Library/PeiPciSegmentLibPciCfg2/PeiPciSegmentLibPciCfg2.inf b/MdePkg/Library/PeiPciSegmentLibPciCfg2/PeiPciSegmentLibPciCfg2.inf
index 3458bc6227..bce771a7c5 100644
--- a/MdePkg/Library/PeiPciSegmentLibPciCfg2/PeiPciSegmentLibPciCfg2.inf
+++ b/MdePkg/Library/PeiPciSegmentLibPciCfg2/PeiPciSegmentLibPciCfg2.inf
@@ -30,7 +30,7 @@
#
# The following information is for reference only and not required by the build tools.
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC (EBC is for build only)
+# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only)
#
[Sources]
diff --git a/MdePkg/Library/PeiResourcePublicationLib/PeiResourcePublicationLib.inf b/MdePkg/Library/PeiResourcePublicationLib/PeiResourcePublicationLib.inf
index b09f48b86a..435e96f9d9 100644
--- a/MdePkg/Library/PeiResourcePublicationLib/PeiResourcePublicationLib.inf
+++ b/MdePkg/Library/PeiResourcePublicationLib/PeiResourcePublicationLib.inf
@@ -26,7 +26,7 @@
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC (EBC is for build only)
+# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only)
#
[Sources]
diff --git a/MdePkg/Library/PeiServicesLib/PeiServicesLib.inf b/MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
index ed992661d6..9990972e44 100644
--- a/MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
+++ b/MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
@@ -24,7 +24,7 @@
PI_SPECIFICATION_VERSION = 0x0001000A
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC (EBC is for build only)
+# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only)
#
[Sources]
diff --git a/MdePkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf b/MdePkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
index 5925f13937..6fb1770e04 100644
--- a/MdePkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
+++ b/MdePkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
@@ -29,7 +29,7 @@
CONSTRUCTOR = PeiServicesTablePointerLibConstructor
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC (EBC is for build only)
+# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only)
#
[Sources]
diff --git a/MdePkg/Library/PeiServicesTablePointerLibKr7/PeiServicesTablePointer.c b/MdePkg/Library/PeiServicesTablePointerLibKr7/PeiServicesTablePointer.c
deleted file mode 100644
index 66cf7bc471..0000000000
--- a/MdePkg/Library/PeiServicesTablePointerLibKr7/PeiServicesTablePointer.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/** @file
- PEI Services Table Pointer Library implementation for IPF that uses Kernel
- Register 7 to store the pointer.
-
- Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php.
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include <PiPei.h>
-#include <Library/BaseLib.h>
-#include <Library/DebugLib.h>
-
-/**
- Retrieves the cached value of the PEI Services Table pointer.
-
- Returns the cached value of the PEI Services Table pointer in a CPU specific manner
- as specified in the CPU binding section of the Platform Initialization Pre-EFI
- Initialization Core Interface Specification.
-
- If the cached PEI Services Table pointer is NULL, then ASSERT().
-
- @return The pointer to PeiServices.
-
-**/
-CONST EFI_PEI_SERVICES **
-EFIAPI
-GetPeiServicesTablePointer (
- VOID
- )
-{
- CONST EFI_PEI_SERVICES **PeiServices;
-
- PeiServices = (CONST EFI_PEI_SERVICES **)(UINTN)AsmReadKr7 ();
- ASSERT (PeiServices != NULL);
- return PeiServices;
-}
-
-
-/**
- Caches a pointer PEI Services Table.
-
- Caches the pointer to the PEI Services Table specified by PeiServicesTablePointer
- in a CPU specific manner as specified in the CPU binding section of the Platform Initialization
- Pre-EFI Initialization Core Interface Specification.
- The function set the pointer of PEI services in KR7 register
- according to PI specification.
-
- If PeiServicesTablePointer is NULL, then ASSERT().
-
- @param PeiServicesTablePointer The address of PeiServices pointer.
-**/
-VOID
-EFIAPI
-SetPeiServicesTablePointer (
- IN CONST EFI_PEI_SERVICES ** PeiServicesTablePointer
- )
-{
- ASSERT (PeiServicesTablePointer != NULL);
- AsmWriteKr7 ((UINT64)(UINTN)PeiServicesTablePointer);
-}
-
-/**
- Perform CPU specific actions required to migrate the PEI Services Table
- pointer from temporary RAM to permanent RAM.
-
- For IA32 CPUs, the PEI Services Table pointer is stored in the 4 bytes
- immediately preceding the Interrupt Descriptor Table (IDT) in memory.
- For X64 CPUs, the PEI Services Table pointer is stored in the 8 bytes
- immediately preceding the Interrupt Descriptor Table (IDT) in memory.
- For Itanium and ARM CPUs, a the PEI Services Table Pointer is stored in
- a dedicated CPU register. This means that there is no memory storage
- associated with storing the PEI Services Table pointer, so no additional
- migration actions are required for Itanium or ARM CPUs.
-
-**/
-VOID
-EFIAPI
-MigratePeiServicesTablePointer (
- VOID
- )
-{
- return;
-}
-
diff --git a/MdePkg/Library/PeiServicesTablePointerLibKr7/PeiServicesTablePointerLibKr7.inf b/MdePkg/Library/PeiServicesTablePointerLibKr7/PeiServicesTablePointerLibKr7.inf
deleted file mode 100644
index ae38fc0046..0000000000
--- a/MdePkg/Library/PeiServicesTablePointerLibKr7/PeiServicesTablePointerLibKr7.inf
+++ /dev/null
@@ -1,42 +0,0 @@
-## @file
-# Instance of PEI Services Table Pointer Library using KR7 for the table pointer.
-#
-# PEI Services Table Pointer Library implementation that retrieves a pointer to the PEI
-# Services Table from KR7 on IPF.
-#
-# Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php.
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#
-##
-
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = PeiServicesTablePointerLibKr7
- MODULE_UNI_FILE = PeiServicesTablePointerLibKr7.uni
- FILE_GUID = E0E7D776-E7EB-4e5f-9AA8-54CF3AA64A43
- MODULE_TYPE = PEIM
- VERSION_STRING = 1.0
- LIBRARY_CLASS = PeiServicesTablePointerLib|SEC PEIM PEI_CORE
-
-
-#
-# VALID_ARCHITECTURES = IPF
-#
-
-[Sources.Ipf]
- PeiServicesTablePointer.c
-
-[Packages]
- MdePkg/MdePkg.dec
-
-[LibraryClasses]
- DebugLib
- BaseLib
-
diff --git a/MdePkg/Library/PeiSmbusLibSmbus2Ppi/PeiSmbusLibSmbus2Ppi.inf b/MdePkg/Library/PeiSmbusLibSmbus2Ppi/PeiSmbusLibSmbus2Ppi.inf
index cef8e03ad8..b50335a0fc 100644
--- a/MdePkg/Library/PeiSmbusLibSmbus2Ppi/PeiSmbusLibSmbus2Ppi.inf
+++ b/MdePkg/Library/PeiSmbusLibSmbus2Ppi/PeiSmbusLibSmbus2Ppi.inf
@@ -24,7 +24,7 @@
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC (EBC is for build only)
+# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only)
#
[Sources]
diff --git a/MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf b/MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
index a2db9e058b..b36a5f2ba5 100644
--- a/MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
+++ b/MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
@@ -23,7 +23,7 @@
LIBRARY_CLASS = PeimEntryPoint|PEIM
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC (EBC is for build only)
+# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only)
#
[Sources]
diff --git a/MdePkg/Library/SecPeiDxeTimerLibCpu/IpfTimerLib.c b/MdePkg/Library/SecPeiDxeTimerLibCpu/IpfTimerLib.c
deleted file mode 100644
index 714b99eec4..0000000000
--- a/MdePkg/Library/SecPeiDxeTimerLibCpu/IpfTimerLib.c
+++ /dev/null
@@ -1,216 +0,0 @@
-/** @file
- Timer Library functions built upon ITC on IPF.
-
- Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials
- are licensed and made available under the terms and conditions of the BSD License
- which accompanies this distribution. The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php.
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include <Base.h>
-#include <Library/TimerLib.h>
-#include <Library/BaseLib.h>
-#include <Library/PalLib.h>
-
-
-/**
- Performs a delay measured as number of ticks.
-
- An internal function to perform a delay measured as number of ticks. It's
- invoked by MicroSecondDelay() and NanoSecondDelay().
-
- @param Delay The number of ticks to delay.
-
-**/
-VOID
-EFIAPI
-InternalIpfDelay (
- IN INT64 Delay
- )
-{
- INT64 Ticks;
-
- //
- // The target timer count is calculated here
- //
- Ticks = (INT64)AsmReadItc () + Delay;
-
- //
- // Wait until time out
- // Delay > 2^63 could not be handled by this function
- // Timer wrap-arounds are handled correctly by this function
- //
- while (Ticks - (INT64)AsmReadItc() >= 0);
-}
-
-/**
- Stalls the CPU for at least the given number of microseconds.
-
- Stalls the CPU for the number of microseconds specified by MicroSeconds.
-
- @param MicroSeconds The minimum number of microseconds to delay.
-
- @return The value of MicroSeconds inputted.
-
-**/
-UINTN
-EFIAPI
-MicroSecondDelay (
- IN UINTN MicroSeconds
- )
-{
- InternalIpfDelay (
- GetPerformanceCounterProperties (NULL, NULL) *
- MicroSeconds /
- 1000000
- );
- return MicroSeconds;
-}
-
-/**
- Stalls the CPU for at least the given number of nanoseconds.
-
- Stalls the CPU for the number of nanoseconds specified by NanoSeconds.
-
- @param NanoSeconds The minimum number of nanoseconds to delay.
-
- @return The value of NanoSeconds inputted.
-
-**/
-UINTN
-EFIAPI
-NanoSecondDelay (
- IN UINTN NanoSeconds
- )
-{
- InternalIpfDelay (
- GetPerformanceCounterProperties (NULL, NULL) *
- NanoSeconds /
- 1000000000
- );
- return NanoSeconds;
-}
-
-/**
- Retrieves the current value of a 64-bit free running performance counter.
-
- The counter can either count up by 1 or count down by 1. If the physical
- performance counter counts by a larger increment, then the counter values
- must be translated. The properties of the counter can be retrieved from
- GetPerformanceCounterProperties().
-
- @return The current value of the free running performance counter.
-
-**/
-UINT64
-EFIAPI
-GetPerformanceCounter (
- VOID
- )
-{
- return AsmReadItc ();
-}
-
-/**
- Retrieves the 64-bit frequency in Hz and the range of performance counter
- values.
-
- If StartValue is not NULL, then the value that the performance counter starts
- with immediately after is it rolls over is returned in StartValue. If
- EndValue is not NULL, then the value that the performance counter end with
- immediately before it rolls over is returned in EndValue. The 64-bit
- frequency of the performance counter in Hz is always returned. If StartValue
- is less than EndValue, then the performance counter counts up. If StartValue
- is greater than EndValue, then the performance counter counts down. For
- example, a 64-bit free running counter that counts up would have a StartValue
- of 0 and an EndValue of 0xFFFFFFFFFFFFFFFF. A 24-bit free running counter
- that counts down would have a StartValue of 0xFFFFFF and an EndValue of 0.
-
- @param StartValue The value the performance counter starts with when it
- rolls over.
- @param EndValue The value that the performance counter ends with before
- it rolls over.
-
- @return The frequency in Hz.
-
-**/
-UINT64
-EFIAPI
-GetPerformanceCounterProperties (
- OUT UINT64 *StartValue, OPTIONAL
- OUT UINT64 *EndValue OPTIONAL
- )
-{
- PAL_CALL_RETURN PalRet;
- UINT64 BaseFrequence;
-
- if (StartValue != NULL) {
- *StartValue = 0;
- }
-
- if (EndValue != NULL) {
- *EndValue = (UINT64)(-1);
- }
-
- PalRet = PalCall (PAL_FREQ_BASE, 0, 0, 0);
- if (PalRet.Status != 0) {
- return 1000000;
- }
- BaseFrequence = PalRet.r9;
-
- PalRet = PalCall (PAL_FREQ_RATIOS, 0, 0, 0);
- if (PalRet.Status != 0) {
- return 1000000;
- }
-
- return BaseFrequence * (PalRet.r11 >> 32) / (UINT32)PalRet.r11;
-}
-
-/**
- Converts elapsed ticks of performance counter to time in nanoseconds.
-
- This function converts the elapsed ticks of running performance counter to
- time value in unit of nanoseconds.
-
- @param Ticks The number of elapsed ticks of running performance counter.
-
- @return The elapsed time in nanoseconds.
-
-**/
-UINT64
-EFIAPI
-GetTimeInNanoSecond (
- IN UINT64 Ticks
- )
-{
- UINT64 Frequency;
- UINT64 NanoSeconds;
- UINT64 Remainder;
- INTN Shift;
-
- Frequency = GetPerformanceCounterProperties (NULL, NULL);
-
- //
- // Ticks
- // Time = --------- x 1,000,000,000
- // Frequency
- //
- NanoSeconds = MultU64x32 (DivU64x64Remainder (Ticks, Frequency, &Remainder), 1000000000u);
-
- //
- // Ensure (Remainder * 1,000,000,000) will not overflow 64-bit.
- // Since 2^29 < 1,000,000,000 = 0x3B9ACA00 < 2^30, Remainder should < 2^(64-30) = 2^34,
- // i.e. highest bit set in Remainder should <= 33.
- //
- Shift = MAX (0, HighBitSet64 (Remainder) - 33);
- Remainder = RShiftU64 (Remainder, (UINTN) Shift);
- Frequency = RShiftU64 (Frequency, (UINTN) Shift);
- NanoSeconds += DivU64x64Remainder (MultU64x32 (Remainder, 1000000000u), Frequency, NULL);
-
- return NanoSeconds;
-}
diff --git a/MdePkg/Library/SecPeiDxeTimerLibCpu/SecPeiDxeTimerLibCpu.inf b/MdePkg/Library/SecPeiDxeTimerLibCpu/SecPeiDxeTimerLibCpu.inf
index a00ebb0eeb..780ef9d9b7 100644
--- a/MdePkg/Library/SecPeiDxeTimerLibCpu/SecPeiDxeTimerLibCpu.inf
+++ b/MdePkg/Library/SecPeiDxeTimerLibCpu/SecPeiDxeTimerLibCpu.inf
@@ -36,16 +36,12 @@
#
-# VALID_ARCHITECTURES = IA32 X64 IPF
+# VALID_ARCHITECTURES = IA32 X64
#
[Sources.Ia32, Sources.X64]
X86TimerLib.c
-[Sources.IPF]
- IpfTimerLib.c
-
-
[Packages]
MdePkg/MdePkg.dec
@@ -58,10 +54,6 @@
IoLib
DebugLib
-[LibraryClasses.IPF]
- PalLib
-
-
[Pcd.IA32, Pcd.X64]
gEfiMdePkgTokenSpaceGuid.PcdFSBClock ## CONSUMES
diff --git a/MdePkg/Library/SmiHandlerProfileLibNull/SmiHandlerProfileLibNull.inf b/MdePkg/Library/SmiHandlerProfileLibNull/SmiHandlerProfileLibNull.inf
index 82208345ee..f5dfd307e6 100644
--- a/MdePkg/Library/SmiHandlerProfileLibNull/SmiHandlerProfileLibNull.inf
+++ b/MdePkg/Library/SmiHandlerProfileLibNull/SmiHandlerProfileLibNull.inf
@@ -25,7 +25,7 @@
#
# The following information is for reference only and not required by the build tools.
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]
diff --git a/MdePkg/Library/SmmLibNull/SmmLibNull.inf b/MdePkg/Library/SmmLibNull/SmmLibNull.inf
index 597b884df2..cd905d5e38 100644
--- a/MdePkg/Library/SmmLibNull/SmmLibNull.inf
+++ b/MdePkg/Library/SmmLibNull/SmmLibNull.inf
@@ -25,7 +25,7 @@
#
# The following information is for reference only and not required by the build tools.
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]
diff --git a/MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf b/MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
index be92b3dc07..087607606f 100644
--- a/MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
+++ b/MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
@@ -23,7 +23,7 @@
LIBRARY_CLASS = UefiApplicationEntryPoint|UEFI_APPLICATION
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]
diff --git a/MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf b/MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
index 22a2d634fe..7c2e24fe58 100644
--- a/MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
+++ b/MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
@@ -20,12 +20,12 @@
FILE_GUID = ff5c7a2c-ab7a-4366-8616-11c6e53247b6
MODULE_TYPE = UEFI_DRIVER
VERSION_STRING = 1.0
- LIBRARY_CLASS = UefiBootServicesTableLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER SMM_CORE
+ LIBRARY_CLASS = UefiBootServicesTableLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER SMM_CORE
CONSTRUCTOR = UefiBootServicesTableLibConstructor
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]
diff --git a/MdePkg/Library/UefiDebugLibConOut/UefiDebugLibConOut.inf b/MdePkg/Library/UefiDebugLibConOut/UefiDebugLibConOut.inf
index 583872f54e..fc5635b6c9 100644
--- a/MdePkg/Library/UefiDebugLibConOut/UefiDebugLibConOut.inf
+++ b/MdePkg/Library/UefiDebugLibConOut/UefiDebugLibConOut.inf
@@ -22,11 +22,11 @@
FILE_GUID = 5cddfaf3-e9a7-4d16-bdce-1e002df475bb
MODULE_TYPE = UEFI_DRIVER
VERSION_STRING = 1.0
- LIBRARY_CLASS = DebugLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER
+ LIBRARY_CLASS = DebugLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+# VALID_ARCHITECTURES = IA32 X64 EBC
#
diff --git a/MdePkg/Library/UefiDebugLibDebugPortProtocol/UefiDebugLibDebugPortProtocol.inf b/MdePkg/Library/UefiDebugLibDebugPortProtocol/UefiDebugLibDebugPortProtocol.inf
index 0f18c27a11..9d9f9f372f 100644
--- a/MdePkg/Library/UefiDebugLibDebugPortProtocol/UefiDebugLibDebugPortProtocol.inf
+++ b/MdePkg/Library/UefiDebugLibDebugPortProtocol/UefiDebugLibDebugPortProtocol.inf
@@ -22,11 +22,11 @@
FILE_GUID = 102287b4-6b12-4D41-91e1-ebee1f3aa614
MODULE_TYPE = UEFI_DRIVER
VERSION_STRING = 1.0
- LIBRARY_CLASS = DebugLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER
+ LIBRARY_CLASS = DebugLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+# VALID_ARCHITECTURES = IA32 X64 EBC
#
diff --git a/MdePkg/Library/UefiDebugLibStdErr/UefiDebugLibStdErr.inf b/MdePkg/Library/UefiDebugLibStdErr/UefiDebugLibStdErr.inf
index 196487cf8c..7d8efea98e 100644
--- a/MdePkg/Library/UefiDebugLibStdErr/UefiDebugLibStdErr.inf
+++ b/MdePkg/Library/UefiDebugLibStdErr/UefiDebugLibStdErr.inf
@@ -22,11 +22,11 @@
FILE_GUID = b57a1df6-ffdb-4247-a3df-3a562176751a
MODULE_TYPE = UEFI_DRIVER
VERSION_STRING = 1.0
- LIBRARY_CLASS = DebugLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER
+ LIBRARY_CLASS = DebugLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]
diff --git a/MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf b/MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
index c76275b9d7..ea1af21d0b 100644
--- a/MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
+++ b/MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
@@ -22,11 +22,11 @@
FILE_GUID = 91c1677a-e57f-4191-8b8e-eb7711a716e0
MODULE_TYPE = UEFI_DRIVER
VERSION_STRING = 1.0
- LIBRARY_CLASS = DevicePathLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER SMM_CORE
+ LIBRARY_CLASS = DevicePathLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER SMM_CORE
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]
diff --git a/MdePkg/Library/UefiDevicePathLib/UefiDevicePathLibOptionalDevicePathProtocol.inf b/MdePkg/Library/UefiDevicePathLib/UefiDevicePathLibOptionalDevicePathProtocol.inf
index 9e3029cd1c..50006f0095 100644
--- a/MdePkg/Library/UefiDevicePathLib/UefiDevicePathLibOptionalDevicePathProtocol.inf
+++ b/MdePkg/Library/UefiDevicePathLib/UefiDevicePathLibOptionalDevicePathProtocol.inf
@@ -24,12 +24,12 @@
FILE_GUID = 3E1C696D-FCF0-45a7-85A7-E86C2A1C1080
MODULE_TYPE = UEFI_DRIVER
VERSION_STRING = 1.0
- LIBRARY_CLASS = DevicePathLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER SMM_CORE
+ LIBRARY_CLASS = DevicePathLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER SMM_CORE
CONSTRUCTOR = UefiDevicePathLibOptionalDevicePathProtocolConstructor
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]
@@ -86,4 +86,4 @@
[Depex.common.DXE_DRIVER, Depex.common.DXE_RUNTIME_DRIVER, Depex.common.DXE_SAL_DRIVER, Depex.common.DXE_SMM_DRIVER]
gEfiDevicePathUtilitiesProtocolGuid
-
\ No newline at end of file
+
diff --git a/MdePkg/Library/UefiDevicePathLibDevicePathProtocol/UefiDevicePathLibDevicePathProtocol.inf b/MdePkg/Library/UefiDevicePathLibDevicePathProtocol/UefiDevicePathLibDevicePathProtocol.inf
index 5cab72ebfe..a365a527a1 100644
--- a/MdePkg/Library/UefiDevicePathLibDevicePathProtocol/UefiDevicePathLibDevicePathProtocol.inf
+++ b/MdePkg/Library/UefiDevicePathLibDevicePathProtocol/UefiDevicePathLibDevicePathProtocol.inf
@@ -23,12 +23,12 @@
FILE_GUID = 050EB8C6-C12E-4b86-892B-40985E8B3137
MODULE_TYPE = UEFI_DRIVER
VERSION_STRING = 1.0
- LIBRARY_CLASS = DevicePathLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER SMM_CORE
+ LIBRARY_CLASS = DevicePathLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER SMM_CORE
CONSTRUCTOR = DevicePathLibConstructor
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]
diff --git a/MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf b/MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
index 7a9dcbcd4d..0be4a2721f 100644
--- a/MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
+++ b/MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
@@ -20,12 +20,12 @@
FILE_GUID = 331deb15-454b-48d8-9b74-70d01f3f3556
MODULE_TYPE = UEFI_DRIVER
VERSION_STRING = 1.0
- LIBRARY_CLASS = UefiDriverEntryPoint|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER UEFI_DRIVER SMM_CORE DXE_SMM_DRIVER
+ LIBRARY_CLASS = UefiDriverEntryPoint|DXE_DRIVER DXE_RUNTIME_DRIVER UEFI_DRIVER SMM_CORE DXE_SMM_DRIVER
#
# The following information is for reference only and not required by the build tools.
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]
diff --git a/MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf b/MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
index 811d769ae9..5b6b488db6 100644
--- a/MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
+++ b/MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
@@ -21,7 +21,7 @@
LIBRARY_CLASS = FileHandleLib|DXE_DRIVER UEFI_APPLICATION UEFI_DRIVER DXE_RUNTIME_DRIVER
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources.common]
diff --git a/MdePkg/Library/UefiLib/UefiLib.inf b/MdePkg/Library/UefiLib/UefiLib.inf
index 8284dc58af..74f4b31e6e 100644
--- a/MdePkg/Library/UefiLib/UefiLib.inf
+++ b/MdePkg/Library/UefiLib/UefiLib.inf
@@ -26,12 +26,12 @@
FILE_GUID = 3a004ba5-efe0-4a61-9f1a-267a46ae5ba9
MODULE_TYPE = UEFI_DRIVER
VERSION_STRING = 1.0
- LIBRARY_CLASS = UefiLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER SMM_CORE
+ LIBRARY_CLASS = UefiLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER SMM_CORE
CONSTRUCTOR = UefiLibConstructor
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]
diff --git a/MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf b/MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
index e5936ed40a..ea287ab63d 100644
--- a/MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+++ b/MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
@@ -23,10 +23,10 @@
FILE_GUID = 4674739d-3195-4fb2-8094-ac1d22d00194
MODULE_TYPE = UEFI_DRIVER
VERSION_STRING = 1.0
- LIBRARY_CLASS = MemoryAllocationLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER
+ LIBRARY_CLASS = MemoryAllocationLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]
diff --git a/MdePkg/Library/UefiMemoryLib/UefiMemoryLib.inf b/MdePkg/Library/UefiMemoryLib/UefiMemoryLib.inf
index 7382204f63..abac73fa15 100644
--- a/MdePkg/Library/UefiMemoryLib/UefiMemoryLib.inf
+++ b/MdePkg/Library/UefiMemoryLib/UefiMemoryLib.inf
@@ -23,11 +23,11 @@
FILE_GUID = f1bbe03d-2f28-4dee-bec7-d98d7a30c36a
MODULE_TYPE = UEFI_DRIVER
VERSION_STRING = 1.0
- LIBRARY_CLASS = BaseMemoryLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER
+ LIBRARY_CLASS = BaseMemoryLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]
diff --git a/MdePkg/Library/UefiPalLib/UefiPalLib.c b/MdePkg/Library/UefiPalLib/UefiPalLib.c
deleted file mode 100644
index df52a9125f..0000000000
--- a/MdePkg/Library/UefiPalLib/UefiPalLib.c
+++ /dev/null
@@ -1,127 +0,0 @@
-/** @file
- PAL Library implementation retrieving the PAL Entry Point from the SAL System Table
- register in the EFI System Confguration Table.
-
- Copyright (c) 2007 - 2008, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials are
- licensed and made available under the terms and conditions of
- the BSD License which accompanies this distribution. The full
- text of the license may be found at
- http://opensource.org/licenses/bsd-license.php.
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include <PiDxe.h>
-
-#include <IndustryStandard/Sal.h>
-#include <Library/UefiLib.h>
-#include <Library/BaseLib.h>
-#include <Library/DebugLib.h>
-
-#include <Guid/SalSystemTable.h>
-
-UINT64 mPalProcEntry;
-
-/**
- Makes a PAL procedure call.
-
- This is a wrapper function to make a PAL procedure call. Based on the Index value,
- this API will make static or stacked PAL call. Architected procedures may be designated
- as required or optional. If a PAL procedure is specified as optional, a unique return
- code of 0xFFFFFFFFFFFFFFFF is returned in the Status field of the PAL_CALL_RETURN structure.
- This indicates that the procedure is not present in this PAL implementation. It is the
- caller's responsibility to check for this return code after calling any optional PAL
- procedure. No parameter checking is performed on the 4 input parameters, but there are
- some common rules that the caller should follow when making a PAL call. Any address
- passed to PAL as buffers for return parameters must be 8-byte aligned. Unaligned addresses
- may cause undefined results. For those parameters defined as reserved or some fields
- defined as reserved must be zero filled or the invalid argument return value may be
- returned or undefined result may occur during the execution of the procedure.
- This function is only available on IPF.
-
- @param Index The PAL procedure Index number.
- @param Arg2 The 2nd parameter for PAL procedure calls.
- @param Arg3 The 3rd parameter for PAL procedure calls.
- @param Arg4 The 4th parameter for PAL procedure calls.
-
- @return Structure returned from the PAL Call procedure, including the status and return value.
-
-**/
-PAL_CALL_RETURN
-EFIAPI
-PalCall (
- IN UINT64 Index,
- IN UINT64 Arg2,
- IN UINT64 Arg3,
- IN UINT64 Arg4
- )
-{
- //
- // mPalProcEntry is initialized in library constructor as PAL entry.
- //
- return AsmPalCall (
- mPalProcEntry,
- Index,
- Arg2,
- Arg3,
- Arg4
- );
-
-}
-
-/**
- The constructor function of UEFI Pal Lib.
-
- The constructor function looks up the SAL System Table in the EFI System Configuration
- Table. Once the SAL System Table is found, the PAL Entry Point in the SAL System Table
- will be derived and stored into a global variable for library usage.
- It will ASSERT() if the SAL System Table cannot be found or the data in the SAL System
- Table is not the valid data.
-
- @param ImageHandle The firmware allocated handle for the EFI image.
- @param SystemTable A pointer to the EFI System Table.
-
- @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.
-
-**/
-EFI_STATUS
-EFIAPI
-UefiPalLibConstructor (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
- )
-{
- EFI_STATUS Status;
- SAL_ST_ENTRY_POINT_DESCRIPTOR *SalStEntryDes;
- SAL_SYSTEM_TABLE_HEADER *SalSystemTable;
-
- Status = EfiGetSystemConfigurationTable (
- &gEfiSalSystemTableGuid,
- (VOID **) &SalSystemTable
- );
- ASSERT_EFI_ERROR (Status);
- ASSERT (SalSystemTable != NULL);
-
- //
- // Check the first entry of SAL System Table,
- // because the SAL entry is in ascending order with the entry type,
- // the type 0 entry should be the first if exist.
- //
- SalStEntryDes = (SAL_ST_ENTRY_POINT_DESCRIPTOR *)(SalSystemTable + 1);
-
- //
- // Assure the SAL ENTRY Type is 0
- //
- ASSERT (SalStEntryDes->Type == EFI_SAL_ST_ENTRY_POINT);
-
- mPalProcEntry = SalStEntryDes->PalProcEntry;
- //
- // Make sure the PalCallAddress has the valid value
- //
- ASSERT (mPalProcEntry != 0);
-
- return EFI_SUCCESS;
-}
diff --git a/MdePkg/Library/UefiPalLib/UefiPalLib.inf b/MdePkg/Library/UefiPalLib/UefiPalLib.inf
deleted file mode 100644
index 914c75128d..0000000000
--- a/MdePkg/Library/UefiPalLib/UefiPalLib.inf
+++ /dev/null
@@ -1,49 +0,0 @@
-## @file
-# UEFI Instance of PAL Library Class.
-#
-# This instance of PAL library retrieves the PAL Entry Point from the SAL System Table
-# register in the EFI System Confguration Table.
-#
-# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php.
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#
-##
-
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = UefiPalLib
- MODULE_UNI_FILE = UefiPalLib.uni
- FILE_GUID = B7F30170-9E5F-482a-B553-A145A5787003
- MODULE_TYPE = UEFI_DRIVER
- VERSION_STRING = 1.0
- LIBRARY_CLASS = PalLib|UEFI_DRIVER UEFI_APPLICATION
-
- CONSTRUCTOR = UefiPalLibConstructor
-
-#
-# The following information is for reference only and not required by the build tools.
-#
-# VALID_ARCHITECTURES = IPF
-#
-
-[Sources]
- UefiPalLib.c
-
-[Packages]
- MdePkg/MdePkg.dec
-
-[LibraryClasses]
- UefiLib
- BaseLib
- DebugLib
-
-[Guids]
- gEfiSalSystemTableGuid ## CONSUMES ## SystemTable
-
diff --git a/MdePkg/Library/UefiPciLibPciRootBridgeIo/UefiPciLibPciRootBridgeIo.inf b/MdePkg/Library/UefiPciLibPciRootBridgeIo/UefiPciLibPciRootBridgeIo.inf
index b741d1b317..be917356a2 100644
--- a/MdePkg/Library/UefiPciLibPciRootBridgeIo/UefiPciLibPciRootBridgeIo.inf
+++ b/MdePkg/Library/UefiPciLibPciRootBridgeIo/UefiPciLibPciRootBridgeIo.inf
@@ -26,14 +26,14 @@
FILE_GUID = 90EC42CB-B780-4eb8-8E99-C8E3E5F37530
MODULE_TYPE = UEFI_DRIVER
VERSION_STRING = 1.0
- LIBRARY_CLASS = PciLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
+ LIBRARY_CLASS = PciLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER UEFI_DRIVER UEFI_APPLICATION
CONSTRUCTOR = PciLibConstructor
#
# The following information is for reference only and not required by the build tools.
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]
diff --git a/MdePkg/Library/UefiPciSegmentLibPciRootBridgeIo/UefiPciSegmentLibPciRootBridgeIo.inf b/MdePkg/Library/UefiPciSegmentLibPciRootBridgeIo/UefiPciSegmentLibPciRootBridgeIo.inf
index 12f465ba9e..9a90476f07 100644
--- a/MdePkg/Library/UefiPciSegmentLibPciRootBridgeIo/UefiPciSegmentLibPciRootBridgeIo.inf
+++ b/MdePkg/Library/UefiPciSegmentLibPciRootBridgeIo/UefiPciSegmentLibPciRootBridgeIo.inf
@@ -26,7 +26,7 @@
FILE_GUID = C6068612-B6E0-48a3-BB92-60E4A4F89EDF
MODULE_TYPE = UEFI_DRIVER
VERSION_STRING = 1.0
- LIBRARY_CLASS = PciSegmentLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
+ LIBRARY_CLASS = PciSegmentLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER UEFI_DRIVER UEFI_APPLICATION
CONSTRUCTOR = PciSegmentLibConstructor
DESTRUCTOR = PciSegmentLibDestructor
@@ -34,7 +34,7 @@
#
# The following information is for reference only and not required by the build tools.
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]
diff --git a/MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf b/MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
index 8f46495fc5..d9b51dad92 100644
--- a/MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
+++ b/MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
@@ -24,13 +24,13 @@
FILE_GUID = b1ee6c28-54aa-4d17-b705-3e28ccb27b2e
MODULE_TYPE = DXE_RUNTIME_DRIVER
VERSION_STRING = 1.0
- LIBRARY_CLASS = UefiRuntimeLib|DXE_RUNTIME_DRIVER DXE_SAL_DRIVER
+ LIBRARY_CLASS = UefiRuntimeLib|DXE_RUNTIME_DRIVER
CONSTRUCTOR = RuntimeDriverLibConstruct
DESTRUCTOR = RuntimeDriverLibDeconstruct
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+# VALID_ARCHITECTURES = IA32 X64 EBC
#
diff --git a/MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf b/MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
index a843436244..798a9e869c 100644
--- a/MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
+++ b/MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
@@ -20,12 +20,12 @@
FILE_GUID = 19cbbb97-ff61-45ff-8c3f-dfa66dd118c8
MODULE_TYPE = UEFI_DRIVER
VERSION_STRING = 1.0
- LIBRARY_CLASS = UefiRuntimeServicesTableLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER SMM_CORE
+ LIBRARY_CLASS = UefiRuntimeServicesTableLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER SMM_CORE
CONSTRUCTOR = UefiRuntimeServicesTableLibConstructor
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]
diff --git a/MdePkg/Library/UefiSalLib/UefiSalLib.c b/MdePkg/Library/UefiSalLib/UefiSalLib.c
deleted file mode 100644
index e79c7ce8a9..0000000000
--- a/MdePkg/Library/UefiSalLib/UefiSalLib.c
+++ /dev/null
@@ -1,139 +0,0 @@
-/** @file
- SAL Library implementation retrieving the SAL Entry Point from the SAL System Table
- register in the EFI System Configuration Table.
-
- Copyright (c) 2007 - 2010, Intel Corporation. All rights reserved.<BR>
- This program and the accompanying materials are
- licensed and made available under the terms and conditions of
- the BSD License which accompanies this distribution. The full
- text of the license may be found at
- http://opensource.org/licenses/bsd-license.php.
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#include <PiDxe.h>
-#include <IndustryStandard/Sal.h>
-
-#include <Library/SalLib.h>
-#include <Library/UefiLib.h>
-#include <Library/DebugLib.h>
-
-#include <Guid/SalSystemTable.h>
-
-EFI_PLABEL mPlabel;
-SAL_PROC mSalProcEntry;
-
-/**
- Makes a SAL procedure call.
-
- This is a wrapper function to make a SAL procedure call.
- No parameter checking is performed on the 8 input parameters,
- but there are some common rules that the caller should follow
- when making a SAL call. Any address passed to SAL as buffers
- for return parameters must be 8-byte aligned. Unaligned
- addresses may cause undefined results. For those parameters
- defined as reserved or some fields defined as reserved must be
- zero filled or the invalid argument return value may be returned
- or undefined result may occur during the execution of the procedure.
- This function is only available on IPF.
-
- @param Index The SAL procedure Index number.
- @param Arg2 The 2nd parameter for SAL procedure calls.
- @param Arg3 The 3rd parameter for SAL procedure calls.
- @param Arg4 The 4th parameter for SAL procedure calls.
- @param Arg5 The 5th parameter for SAL procedure calls.
- @param Arg6 The 6th parameter for SAL procedure calls.
- @param Arg7 The 7th parameter for SAL procedure calls.
- @param Arg8 The 8th parameter for SAL procedure calls.
-
- @return SAL returned registers.
-
-**/
-SAL_RETURN_REGS
-EFIAPI
-SalCall (
- IN UINT64 Index,
- IN UINT64 Arg2,
- IN UINT64 Arg3,
- IN UINT64 Arg4,
- IN UINT64 Arg5,
- IN UINT64 Arg6,
- IN UINT64 Arg7,
- IN UINT64 Arg8
- )
-{
- //
- // mSalProcEntry is initialized in library constructor as SAL entry.
- //
- return mSalProcEntry(
- Index,
- Arg2,
- Arg3,
- Arg4,
- Arg5,
- Arg6,
- Arg7,
- Arg8
- );
-
-}
-
-/**
- The constructor function of UEFI SAL Lib.
-
- The constructor function looks up the SAL System Table in the EFI System Configuration
- Table. Once the SAL System Table is found, the SAL Entry Point in the SAL System Table
- will be derived and stored into a global variable for library usage.
- It will ASSERT() if the SAL System Table cannot be found or the data in the SAL System
- Table is not the valid data.
-
- @param ImageHandle The firmware allocated handle for the EFI image.
- @param SystemTable A pointer to the EFI System Table.
-
- @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.
-
-**/
-EFI_STATUS
-EFIAPI
-UefiSalLibConstructor (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
- )
-{
- EFI_STATUS Status;
- SAL_ST_ENTRY_POINT_DESCRIPTOR *SalStEntryDes;
- SAL_SYSTEM_TABLE_HEADER *SalSystemTable;
-
- Status = EfiGetSystemConfigurationTable (
- &gEfiSalSystemTableGuid,
- (VOID **) &SalSystemTable
- );
- ASSERT_EFI_ERROR (Status);
- ASSERT (SalSystemTable != NULL);
-
- //
- // Check the first entry of SAL System Table,
- // because the SAL entry is in ascending order with the entry type,
- // the type 0 entry should be the first if exist.
- //
- SalStEntryDes = (SAL_ST_ENTRY_POINT_DESCRIPTOR *)(SalSystemTable + 1);
-
- //
- // Assure the SAL ENTRY Type is 0
- //
- ASSERT (SalStEntryDes->Type == EFI_SAL_ST_ENTRY_POINT);
-
- mPlabel.EntryPoint = SalStEntryDes->SalProcEntry;
- mPlabel.GP = SalStEntryDes->SalGlobalDataPointer;
- //
- // Make sure the EntryPoint has the valid value
- //
- ASSERT ((mPlabel.EntryPoint != 0) && (mPlabel.GP != 0));
-
- mSalProcEntry = (SAL_PROC)((UINT64)&(mPlabel.EntryPoint));
-
- return EFI_SUCCESS;
-}
diff --git a/MdePkg/Library/UefiSalLib/UefiSalLib.inf b/MdePkg/Library/UefiSalLib/UefiSalLib.inf
deleted file mode 100644
index bc25c53b83..0000000000
--- a/MdePkg/Library/UefiSalLib/UefiSalLib.inf
+++ /dev/null
@@ -1,47 +0,0 @@
-## @file
-# UEFI Instance of SAL Library Class.
-#
-# This instance of SAL library retrieves the SAL Entry Point from the SAL System Table
-# register in the EFI System Confguration Table.
-#
-# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
-#
-# This program and the accompanying materials
-# are licensed and made available under the terms and conditions of the BSD License
-# which accompanies this distribution. The full text of the license may be found at
-# http://opensource.org/licenses/bsd-license.php.
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#
-##
-
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = UefiSalLib
- MODULE_UNI_FILE = UefiSalLib.uni
- FILE_GUID = 4ABCFD77-4A33-4089-B003-5F09BCA940A2
- MODULE_TYPE = UEFI_DRIVER
- VERSION_STRING = 1.0
- LIBRARY_CLASS = SalLib|UEFI_DRIVER UEFI_APPLICATION
-
- CONSTRUCTOR = UefiSalLibConstructor
-#
-# The following information is for reference only and not required by the build tools.
-#
-# VALID_ARCHITECTURES = IPF
-#
-
-[Sources]
- UefiSalLib.c
-
-[Packages]
- MdePkg/MdePkg.dec
-
-[LibraryClasses]
- UefiLib
- DebugLib
-
-[Guids]
- gEfiSalSystemTableGuid ## CONSUMES ## SystemTable
-
diff --git a/MdePkg/Library/UefiScsiLib/UefiScsiLib.inf b/MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
index cd0c5c1ec8..0e00ab909e 100644
--- a/MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
+++ b/MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
@@ -23,11 +23,11 @@
FILE_GUID = 280E42C3-826E-4573-9772-B74EF1086D95
MODULE_TYPE = UEFI_DRIVER
VERSION_STRING = 1.0
- LIBRARY_CLASS = UefiScsiLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER
+ LIBRARY_CLASS = UefiScsiLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]
diff --git a/MdePkg/Library/UefiUsbLib/UefiUsbLib.inf b/MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
index 33062fd692..746daa79f8 100644
--- a/MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
+++ b/MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
@@ -23,11 +23,11 @@
FILE_GUID = 87eb5df9-722a-4241-ad7f-370d0b3a56d7
MODULE_TYPE = UEFI_DRIVER
VERSION_STRING = 1.0
- LIBRARY_CLASS = UefiUsbLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER
+ LIBRARY_CLASS = UefiUsbLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER
#
-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+# VALID_ARCHITECTURES = IA32 X64 EBC
#
[Sources]
diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec
index 0e64f22f4a..73923a04d2 100644
--- a/MdePkg/MdePkg.dec
+++ b/MdePkg/MdePkg.dec
@@ -36,9 +36,6 @@
[Includes.X64]
Include/X64
-[Includes.IPF]
- Include/Ipf
-
[Includes.EBC]
Include/Ebc
@@ -274,16 +271,6 @@
## @libraryclass Provides services to log the SMI handler registration.
SmiHandlerProfileLib|Include/Library/SmiHandlerProfileLib.h
-[LibraryClasses.IPF]
- ## @libraryclass The SAL Library provides a service to make a SAL CALL.
- SalLib|Include/Library/SalLib.h
-
- ## @libraryclass Provides library services to make PAL Calls.
- PalLib|Include/Library/PalLib.h
-
- ## @libraryclass Provides library services to make Extended SAL Calls.
- ExtendedSalLib|Include/Library/ExtendedSalLib.h
-
[Guids]
#
# GUID defined in UEFI2.1/UEFI2.0/EFI1.1
@@ -2212,11 +2199,6 @@
# @Prompt Memory Address of GuidedExtractHandler Table.
gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress|0x1000000|UINT64|0x30001015
-[PcdsFixedAtBuild.IPF, PcdsPatchableInModule.IPF]
- ## The base address of IO port space for IA64 arch.
- # @Prompt IA64 IO Port Space Base Address.
- gEfiMdePkgTokenSpaceGuid.PcdIoBlockBaseAddressForIpf|0x0ffffc000000|UINT64|0x0000000f
-
[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
## This value is used to set the base address of PCI express hierarchy.
# @Prompt PCI Express Base Address.
diff --git a/MdePkg/MdePkg.dsc b/MdePkg/MdePkg.dsc
index cf20bc3a1f..9ee84b2b50 100644
--- a/MdePkg/MdePkg.dsc
+++ b/MdePkg/MdePkg.dsc
@@ -20,7 +20,7 @@
PLATFORM_VERSION = 1.08
DSC_SPECIFICATION = 0x00010005
OUTPUT_DIRECTORY = Build/Mde
- SUPPORTED_ARCHITECTURES = IA32|IPF|X64|EBC|ARM|AARCH64
+ SUPPORTED_ARCHITECTURES = IA32|X64|EBC|ARM|AARCH64
BUILD_TARGETS = DEBUG|RELEASE|NOOPT
SKUID_IDENTIFIER = DEFAULT
@@ -32,28 +32,6 @@
gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000000
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000
-[PcdsFixedAtBuild.IPF]
- gEfiMdePkgTokenSpaceGuid.PcdIoBlockBaseAddressForIpf|0x0ffffc000000
-
-###################################################################################################
-#
-# Components Section - list of the modules and components that will be processed by compilation
-# tools and the EDK II tools to generate PE32/PE32+/Coff image files.
-#
-# Note: The EDK II DSC file is not used to specify how compiled binary images get placed
-# into firmware volume images. This section is just a list of modules to compile from
-# source into UEFI-compliant binaries.
-# It is the FDF file that contains information on combining binary files into firmware
-# volume images, whose concept is beyond UEFI and is described in PI specification.
-# Binary modules do not need to be listed in this section, as they should be
-# specified in the FDF file. For example: Shell binary (Shell_Full.efi), FAT binary (Fat.efi),
-# Logo (Logo.bmp), and etc.
-# There may also be modules listed in this section that are not required in the FDF file,
-# When a module listed here is excluded from FDF file, then UEFI-compliant binary will be
-# generated for it, but the binary will not be put into any firmware volume.
-#
-###################################################################################################
-
[Components]
MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
@@ -164,23 +142,6 @@
MdePkg/Library/SmmPciExpressLib/SmmPciExpressLib.inf
MdePkg/Library/SmiHandlerProfileLibNull/SmiHandlerProfileLibNull.inf
-[Components.IPF]
- MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
- MdePkg/Library/BasePalLibNull/BasePalLibNull.inf
- MdePkg/Library/PeiPalLib/PeiPalLib.inf
- MdePkg/Library/PeiServicesTablePointerLibKr7/PeiServicesTablePointerLibKr7.inf
- MdePkg/Library/SecPeiDxeTimerLibCpu/SecPeiDxeTimerLibCpu.inf
- MdePkg/Library/UefiPalLib/UefiPalLib.inf
- MdePkg/Library/UefiSalLib/UefiSalLib.inf
- MdePkg/Library/DxeExtendedSalLib/DxeExtendedSalLib.inf
- MdePkg/Library/DxeIoLibEsal/DxeIoLibEsal.inf
- MdePkg/Library/DxePalLibEsal/DxePalLibEsal.inf
- MdePkg/Library/DxePciLibEsal/DxePciLibEsal.inf
- MdePkg/Library/DxePciSegmentLibEsal/DxePciSegmentLibEsal.inf
- MdePkg/Library/DxeRuntimeExtendedSalLib/DxeRuntimeExtendedSalLib.inf
- MdePkg/Library/DxeSalLibEsal/DxeSalLibEsal.inf
- MdePkg/Library/DxeTimerLibEsal/DxeTimerLibEsal.inf
-
[Components.EBC]
MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
--
2.16.2.windows.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH 21/37] MdePkg: Removing ipf which is no longer supported from edk2.
2018-06-13 3:44 [PATCH 21/37] MdePkg: Removing ipf which is no longer supported from edk2 chenc2
@ 2018-06-13 5:48 ` Gao, Liming
0 siblings, 0 replies; 2+ messages in thread
From: Gao, Liming @ 2018-06-13 5:48 UTC (permalink / raw)
To: Chen, Chen A, edk2-devel@lists.01.org; +Cc: Kinney, Michael D
Chen:
PcdIoBlockBaseAddressForIpf has been removed from DEC file. Please also remove it from MdePkg.uni.
Other changes are good.
Thanks
Liming
>-----Original Message-----
>From: Chen, Chen A
>Sent: Wednesday, June 13, 2018 11:45 AM
>To: edk2-devel@lists.01.org
>Cc: Chen, Chen A <chen.a.chen@intel.com>; Gao, Liming
><liming.gao@intel.com>; Kinney, Michael D <michael.d.kinney@intel.com>
>Subject: [PATCH 21/37] MdePkg: Removing ipf which is no longer supported
>from edk2.
>
>Removing rules for Ipf sources file:
>* Remove the source file which path with "ipf" and also listed in
> [Sources.IPF] section of INF file.
>* Remove the source file which listed in [Components.IPF] section
> of DSC file and not listed in any other [Components] section.
>* Remove the embedded Ipf code for MDE_CPU_IPF.
>
>Removing rules for Inf file:
>* Remove IPF from VALID_ARCHITECTURES comments.
>* Remove DXE_SAL_DRIVER from LIBRARY_CLASS in [Defines] section.
>* Remove the INF which only listed in [Components.IPF] section in DSC.
>* Remove statements from [BuildOptions] that provide IPF specific flags.
>* Remove any IPF sepcific sections.
>
>Removing rules for Dec file:
>* Remove [Includes.IPF] section from Dec.
>
>Removing rules for Dsc file:
>* Remove IPF from SUPPORTED_ARCHITECTURES in [Defines] section of DSC.
>* Remove any IPF specific sections.
>* Remove statements from [BuildOptions] that provide IPF specific flags.
>
>Cc: Liming Gao <liming.gao@intel.com>
>Cc: Michael D Kinney <michael.d.kinney@intel.com>
>Signed-off-by: chenc2 <chen.a.chen@intel.com>
>Contributed-under: TianoCore Contribution Agreement 1.1
>---
> MdePkg/Include/Ipf/IpfMacro.i | 58 -
> MdePkg/Include/Ipf/ProcessorBind.h | 324 ---
> MdePkg/Include/Library/BaseLib.h | 1442 ------------
> MdePkg/Include/Protocol/PxeBaseCode.h | 2 -
> MdePkg/Include/Uefi/UefiBaseType.h | 7 -
> MdePkg/Include/Uefi/UefiSpec.h | 2 -
> .../BaseCacheMaintenanceLib.inf | 8 +-
> MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c | 242 --
> MdePkg/Library/BaseCpuLib/BaseCpuLib.inf | 10 +-
> MdePkg/Library/BaseCpuLib/Ipf/CpuFlushTlb.s | 58 -
> MdePkg/Library/BaseCpuLib/Ipf/CpuSleep.c | 66 -
> .../Library/BaseDebugLibNull/BaseDebugLibNull.inf | 2 +-
> .../BaseDebugLibSerialPort.inf | 2 +-
> .../BaseDebugPrintErrorLevelLib.inf | 2 +-
> .../BaseExtractGuidedSectionLib.inf | 2 +-
> .../BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf | 11 +-
> MdePkg/Library/BaseIoLibIntrinsic/IoLibIpf.c | 736 -------
> MdePkg/Library/BaseLib/BaseLib.inf | 35 +-
> MdePkg/Library/BaseLib/BaseLibInternals.h | 920 --------
> MdePkg/Library/BaseLib/Ipf/AccessDbr.s | 118 -
> MdePkg/Library/BaseLib/Ipf/AccessEicr.s | 512 -----
> MdePkg/Library/BaseLib/Ipf/AccessGcr.s | 274 ---
> MdePkg/Library/BaseLib/Ipf/AccessGp.s | 86 -
> MdePkg/Library/BaseLib/Ipf/AccessKr.s | 360 ---
> MdePkg/Library/BaseLib/Ipf/AccessKr7.s | 63 -
> MdePkg/Library/BaseLib/Ipf/AccessMsr.s | 79 -
> MdePkg/Library/BaseLib/Ipf/AccessMsrDb.s | 121 -
> MdePkg/Library/BaseLib/Ipf/AccessPmr.s | 124 --
> MdePkg/Library/BaseLib/Ipf/AccessPsr.s | 111 -
> MdePkg/Library/BaseLib/Ipf/Asm.h | 27 -
> MdePkg/Library/BaseLib/Ipf/AsmCpuMisc.s | 79 -
> MdePkg/Library/BaseLib/Ipf/AsmPalCall.s | 158 --
> MdePkg/Library/BaseLib/Ipf/CpuBreakpoint.c | 96 -
> MdePkg/Library/BaseLib/Ipf/CpuBreakpointMsc.c | 102 -
> MdePkg/Library/BaseLib/Ipf/CpuPause.s | 25 -
> MdePkg/Library/BaseLib/Ipf/ExecFc.s | 66 -
> MdePkg/Library/BaseLib/Ipf/FlushCacheRange.c | 51 -
> MdePkg/Library/BaseLib/Ipf/GetInterruptState.s | 27 -
> MdePkg/Library/BaseLib/Ipf/Ia64gen.h | 205 --
> .../Library/BaseLib/Ipf/InternalFlushCacheRange.s | 94 -
> MdePkg/Library/BaseLib/Ipf/InternalSwitchStack.c | 64 -
> MdePkg/Library/BaseLib/Ipf/LongJmp.s | 121 -
> MdePkg/Library/BaseLib/Ipf/ReadAr.s | 109 -
> MdePkg/Library/BaseLib/Ipf/ReadCpuid.s | 40 -
> MdePkg/Library/BaseLib/Ipf/ReadCr.s | 102 -
> MdePkg/Library/BaseLib/Ipf/SetJmp.s | 108 -
> MdePkg/Library/BaseLib/Ipf/SwitchStack.s | 52 -
> MdePkg/Library/BaseLib/Ipf/Unaligned.c | 243 ---
> MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf | 2 +-
> .../BaseOrderedCollectionRedBlackTreeLib.inf | 2 +-
> MdePkg/Library/BasePalLibNull/BasePalLibNull.inf | 40 -
> MdePkg/Library/BasePalLibNull/PalCall.c | 59 -
> MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf | 2 +-
> MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf | 2 +-
> .../BasePciExpressLib/BasePciExpressLib.inf | 2 +-
> MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf | 2 +-
> .../BasePciLibPciExpress/BasePciLibPciExpress.inf | 2 +-
> .../BasePciSegmentInfoLibNull.inf | 2 +-
> .../BasePciSegmentLibPci/BasePciSegmentLibPci.inf | 2 +-
> .../BasePeCoffExtraActionLibNull.inf | 2 +-
> .../BasePeCoffGetEntryPointLib.inf | 2 +-
> MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf | 5 +-
> MdePkg/Library/BasePeCoffLib/Ipf/PeCoffLoaderEx.c | 422 ----
> .../BasePerformanceLibNull.inf | 2 +-
> .../BasePostCodeLibDebug/BasePostCodeLibDebug.inf | 2 +-
> .../BasePostCodeLibPort80.inf | 2 +-
> MdePkg/Library/BasePrintLib/BasePrintLib.inf | 2 +-
> .../BaseReportStatusCodeLibNull.inf | 2 +-
> .../BaseS3BootScriptLibNull.inf | 2 +-
> MdePkg/Library/BaseS3IoLib/BaseS3IoLib.inf | 2 +-
> MdePkg/Library/BaseS3PciLib/BaseS3PciLib.inf | 2 +-
> .../BaseS3PciSegmentLib/BaseS3PciSegmentLib.inf | 2 +-
> MdePkg/Library/BaseS3SmbusLib/BaseS3SmbusLib.inf | 2 +-
> MdePkg/Library/BaseS3StallLib/BaseS3StallLib.inf | 2 +-
> MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf | 2 +-
> .../BaseSerialPortLibNull.inf | 2 +-
> .../Library/BaseSmbusLibNull/BaseSmbusLibNull.inf | 2 +-
> .../BaseSynchronizationLib.inf | 15 +-
> .../Ipf/InterlockedCompareExchange16.s | 30 -
> .../Ipf/InterlockedCompareExchange32.s | 29 -
> .../Ipf/InterlockedCompareExchange64.s | 28 -
> .../Ipf/InternalGetSpinLockProperties.c | 29 -
> .../BaseSynchronizationLib/Ipf/Synchronization.c | 77 -
> .../BaseTimerLibNullTemplate.inf | 2 +-
> .../BaseUefiDecompressLib.inf | 2 +-
> .../DxeCoreEntryPoint/DxeCoreEntryPoint.inf | 2 +-
> MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf | 2 +-
> .../DxeExtendedSalLib/DxeExtendedSalLib.inf | 46 -
> MdePkg/Library/DxeExtendedSalLib/ExtendedSalLib.c | 1001 ---------
> .../DxeExtendedSalLib/Ipf/AsmExtendedSalLib.s | 97 -
> .../DxeExtractGuidedSectionLib.inf | 4 +-
> MdePkg/Library/DxeHobLib/DxeHobLib.inf | 4 +-
> MdePkg/Library/DxeHstiLib/DxeHstiLib.inf | 2 +-
> MdePkg/Library/DxeIoLibCpuIo2/DxeIoLibCpuIo2.inf | 4 +-
> MdePkg/Library/DxeIoLibEsal/DxeIoLibEsal.inf | 49 -
> MdePkg/Library/DxeIoLibEsal/DxeIoLibEsalInternal.h | 28 -
> MdePkg/Library/DxeIoLibEsal/IoHighLevel.c | 2303 --------------------
> MdePkg/Library/DxeIoLibEsal/IoLib.c | 879 --------
> MdePkg/Library/DxeIoLibEsal/IoLibMmioBuffer.c | 411 ----
> MdePkg/Library/DxePalLibEsal/DxePalLibEsal.c | 73 -
> MdePkg/Library/DxePalLibEsal/DxePalLibEsal.inf | 41 -
> MdePkg/Library/DxePcdLib/DxePcdLib.inf | 4 +-
> MdePkg/Library/DxePciLibEsal/DxePciLibEsal.inf | 40 -
> MdePkg/Library/DxePciLibEsal/PciLib.c | 1464 -------------
> .../DxePciSegmentLibEsal/DxePciSegmentLibEsal.inf | 40 -
> MdePkg/Library/DxePciSegmentLibEsal/PciLib.c | 1416 ------------
> .../DxeRuntimeDebugLibSerialPort.inf | 2 +-
> .../DxeRuntimeExtendedSalLib.inf | 52 -
> .../DxeRuntimeExtendedSalLib/ExtendedSalLib.c | 1124 ----------
> .../Ipf/AsmExtendedSalLib.s | 131 --
> .../DxeRuntimePciExpressLib.inf | 2 +-
> MdePkg/Library/DxeSalLibEsal/DxeSalLibEsal.c | 286 ---
> MdePkg/Library/DxeSalLibEsal/DxeSalLibEsal.inf | 38 -
> MdePkg/Library/DxeServicesLib/DxeServicesLib.inf | 6 +-
> .../DxeServicesTableLib/DxeServicesTableLib.inf | 4 +-
> MdePkg/Library/DxeSmbusLib/DxeSmbusLib.inf | 4 +-
> MdePkg/Library/DxeTimerLibEsal/DxeTimerLibEsal.c | 223 --
> MdePkg/Library/DxeTimerLibEsal/DxeTimerLibEsal.inf | 41 -
> .../BasePciSegmentLibSegmentInfo.inf | 2 +-
> .../DxeRuntimePciSegmentLibSegmentInfo.inf | 2 +-
> .../PeiCoreEntryPoint/PeiCoreEntryPoint.inf | 2 +-
> .../PeiDxePostCodeLibReportStatusCode.inf | 4 +-
> .../PeiExtractGuidedSectionLib.inf | 2 +-
> MdePkg/Library/PeiHobLib/PeiHobLib.inf | 2 +-
> MdePkg/Library/PeiIoLibCpuIo/PeiIoLibCpuIo.inf | 2 +-
> .../PeiMemoryAllocationLib.inf | 2 +-
> MdePkg/Library/PeiMemoryLib/PeiMemoryLib.inf | 2 +-
> MdePkg/Library/PeiPalLib/PeiPalLib.c | 99 -
> MdePkg/Library/PeiPalLib/PeiPalLib.inf | 51 -
> MdePkg/Library/PeiPcdLib/PeiPcdLib.inf | 2 +-
> .../Library/PeiPciLibPciCfg2/PeiPciLibPciCfg2.inf | 2 +-
> .../PeiPciSegmentLibPciCfg2.inf | 2 +-
> .../PeiResourcePublicationLib.inf | 2 +-
> MdePkg/Library/PeiServicesLib/PeiServicesLib.inf | 2 +-
> .../PeiServicesTablePointerLib.inf | 2 +-
> .../PeiServicesTablePointer.c | 91 -
> .../PeiServicesTablePointerLibKr7.inf | 42 -
> .../PeiSmbusLibSmbus2Ppi/PeiSmbusLibSmbus2Ppi.inf | 2 +-
> MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf | 2 +-
> MdePkg/Library/SecPeiDxeTimerLibCpu/IpfTimerLib.c | 216 --
> .../SecPeiDxeTimerLibCpu/SecPeiDxeTimerLibCpu.inf | 10 +-
> .../SmiHandlerProfileLibNull.inf | 2 +-
> MdePkg/Library/SmmLibNull/SmmLibNull.inf | 2 +-
> .../UefiApplicationEntryPoint.inf | 2 +-
> .../UefiBootServicesTableLib.inf | 4 +-
> .../UefiDebugLibConOut/UefiDebugLibConOut.inf | 4 +-
> .../UefiDebugLibDebugPortProtocol.inf | 4 +-
> .../UefiDebugLibStdErr/UefiDebugLibStdErr.inf | 4 +-
> .../UefiDevicePathLib/UefiDevicePathLib.inf | 4 +-
> ...UefiDevicePathLibOptionalDevicePathProtocol.inf | 6 +-
> .../UefiDevicePathLibDevicePathProtocol.inf | 4 +-
> .../UefiDriverEntryPoint/UefiDriverEntryPoint.inf | 4 +-
> .../UefiFileHandleLib/UefiFileHandleLib.inf | 2 +-
> MdePkg/Library/UefiLib/UefiLib.inf | 4 +-
> .../UefiMemoryAllocationLib.inf | 4 +-
> MdePkg/Library/UefiMemoryLib/UefiMemoryLib.inf | 4 +-
> MdePkg/Library/UefiPalLib/UefiPalLib.c | 127 --
> MdePkg/Library/UefiPalLib/UefiPalLib.inf | 49 -
> .../UefiPciLibPciRootBridgeIo.inf | 4 +-
> .../UefiPciSegmentLibPciRootBridgeIo.inf | 4 +-
> MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf | 4 +-
> .../UefiRuntimeServicesTableLib.inf | 4 +-
> MdePkg/Library/UefiSalLib/UefiSalLib.c | 139 --
> MdePkg/Library/UefiSalLib/UefiSalLib.inf | 47 -
> MdePkg/Library/UefiScsiLib/UefiScsiLib.inf | 4 +-
> MdePkg/Library/UefiUsbLib/UefiUsbLib.inf | 4 +-
> MdePkg/MdePkg.dec | 18 -
> MdePkg/MdePkg.dsc | 41 +-
> 168 files changed, 116 insertions(+), 19085 deletions(-)
> delete mode 100644 MdePkg/Include/Ipf/IpfMacro.i
> delete mode 100644 MdePkg/Include/Ipf/ProcessorBind.h
> delete mode 100644 MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c
> delete mode 100644 MdePkg/Library/BaseCpuLib/Ipf/CpuFlushTlb.s
> delete mode 100644 MdePkg/Library/BaseCpuLib/Ipf/CpuSleep.c
> delete mode 100644 MdePkg/Library/BaseIoLibIntrinsic/IoLibIpf.c
> delete mode 100644 MdePkg/Library/BaseLib/Ipf/AccessDbr.s
> delete mode 100644 MdePkg/Library/BaseLib/Ipf/AccessEicr.s
> delete mode 100644 MdePkg/Library/BaseLib/Ipf/AccessGcr.s
> delete mode 100644 MdePkg/Library/BaseLib/Ipf/AccessGp.s
> delete mode 100644 MdePkg/Library/BaseLib/Ipf/AccessKr.s
> delete mode 100644 MdePkg/Library/BaseLib/Ipf/AccessKr7.s
> delete mode 100644 MdePkg/Library/BaseLib/Ipf/AccessMsr.s
> delete mode 100644 MdePkg/Library/BaseLib/Ipf/AccessMsrDb.s
> delete mode 100644 MdePkg/Library/BaseLib/Ipf/AccessPmr.s
> delete mode 100644 MdePkg/Library/BaseLib/Ipf/AccessPsr.s
> delete mode 100644 MdePkg/Library/BaseLib/Ipf/Asm.h
> delete mode 100644 MdePkg/Library/BaseLib/Ipf/AsmCpuMisc.s
> delete mode 100644 MdePkg/Library/BaseLib/Ipf/AsmPalCall.s
> delete mode 100644 MdePkg/Library/BaseLib/Ipf/CpuBreakpoint.c
> delete mode 100644 MdePkg/Library/BaseLib/Ipf/CpuBreakpointMsc.c
> delete mode 100644 MdePkg/Library/BaseLib/Ipf/CpuPause.s
> delete mode 100644 MdePkg/Library/BaseLib/Ipf/ExecFc.s
> delete mode 100644 MdePkg/Library/BaseLib/Ipf/FlushCacheRange.c
> delete mode 100644 MdePkg/Library/BaseLib/Ipf/GetInterruptState.s
> delete mode 100644 MdePkg/Library/BaseLib/Ipf/Ia64gen.h
> delete mode 100644 MdePkg/Library/BaseLib/Ipf/InternalFlushCacheRange.s
> delete mode 100644 MdePkg/Library/BaseLib/Ipf/InternalSwitchStack.c
> delete mode 100644 MdePkg/Library/BaseLib/Ipf/LongJmp.s
> delete mode 100644 MdePkg/Library/BaseLib/Ipf/ReadAr.s
> delete mode 100644 MdePkg/Library/BaseLib/Ipf/ReadCpuid.s
> delete mode 100644 MdePkg/Library/BaseLib/Ipf/ReadCr.s
> delete mode 100644 MdePkg/Library/BaseLib/Ipf/SetJmp.s
> delete mode 100644 MdePkg/Library/BaseLib/Ipf/SwitchStack.s
> delete mode 100644 MdePkg/Library/BaseLib/Ipf/Unaligned.c
> delete mode 100644 MdePkg/Library/BasePalLibNull/BasePalLibNull.inf
> delete mode 100644 MdePkg/Library/BasePalLibNull/PalCall.c
> delete mode 100644 MdePkg/Library/BasePeCoffLib/Ipf/PeCoffLoaderEx.c
> delete mode 100644
>MdePkg/Library/BaseSynchronizationLib/Ipf/InterlockedCompareExchange16
>.s
> delete mode 100644
>MdePkg/Library/BaseSynchronizationLib/Ipf/InterlockedCompareExchange32
>.s
> delete mode 100644
>MdePkg/Library/BaseSynchronizationLib/Ipf/InterlockedCompareExchange64
>.s
> delete mode 100644
>MdePkg/Library/BaseSynchronizationLib/Ipf/InternalGetSpinLockProperties.c
> delete mode 100644
>MdePkg/Library/BaseSynchronizationLib/Ipf/Synchronization.c
> delete mode 100644
>MdePkg/Library/DxeExtendedSalLib/DxeExtendedSalLib.inf
> delete mode 100644 MdePkg/Library/DxeExtendedSalLib/ExtendedSalLib.c
> delete mode 100644
>MdePkg/Library/DxeExtendedSalLib/Ipf/AsmExtendedSalLib.s
> delete mode 100644 MdePkg/Library/DxeIoLibEsal/DxeIoLibEsal.inf
> delete mode 100644 MdePkg/Library/DxeIoLibEsal/DxeIoLibEsalInternal.h
> delete mode 100644 MdePkg/Library/DxeIoLibEsal/IoHighLevel.c
> delete mode 100644 MdePkg/Library/DxeIoLibEsal/IoLib.c
> delete mode 100644 MdePkg/Library/DxeIoLibEsal/IoLibMmioBuffer.c
> delete mode 100644 MdePkg/Library/DxePalLibEsal/DxePalLibEsal.c
> delete mode 100644 MdePkg/Library/DxePalLibEsal/DxePalLibEsal.inf
> delete mode 100644 MdePkg/Library/DxePciLibEsal/DxePciLibEsal.inf
> delete mode 100644 MdePkg/Library/DxePciLibEsal/PciLib.c
> delete mode 100644
>MdePkg/Library/DxePciSegmentLibEsal/DxePciSegmentLibEsal.inf
> delete mode 100644 MdePkg/Library/DxePciSegmentLibEsal/PciLib.c
> delete mode 100644
>MdePkg/Library/DxeRuntimeExtendedSalLib/DxeRuntimeExtendedSalLib.inf
> delete mode 100644
>MdePkg/Library/DxeRuntimeExtendedSalLib/ExtendedSalLib.c
> delete mode 100644
>MdePkg/Library/DxeRuntimeExtendedSalLib/Ipf/AsmExtendedSalLib.s
> delete mode 100644 MdePkg/Library/DxeSalLibEsal/DxeSalLibEsal.c
> delete mode 100644 MdePkg/Library/DxeSalLibEsal/DxeSalLibEsal.inf
> delete mode 100644 MdePkg/Library/DxeTimerLibEsal/DxeTimerLibEsal.c
> delete mode 100644 MdePkg/Library/DxeTimerLibEsal/DxeTimerLibEsal.inf
> delete mode 100644 MdePkg/Library/PeiPalLib/PeiPalLib.c
> delete mode 100644 MdePkg/Library/PeiPalLib/PeiPalLib.inf
> delete mode 100644
>MdePkg/Library/PeiServicesTablePointerLibKr7/PeiServicesTablePointer.c
> delete mode 100644
>MdePkg/Library/PeiServicesTablePointerLibKr7/PeiServicesTablePointerLibKr
>7.inf
> delete mode 100644 MdePkg/Library/SecPeiDxeTimerLibCpu/IpfTimerLib.c
> delete mode 100644 MdePkg/Library/UefiPalLib/UefiPalLib.c
> delete mode 100644 MdePkg/Library/UefiPalLib/UefiPalLib.inf
> delete mode 100644 MdePkg/Library/UefiSalLib/UefiSalLib.c
> delete mode 100644 MdePkg/Library/UefiSalLib/UefiSalLib.inf
>
>diff --git a/MdePkg/Include/Ipf/IpfMacro.i b/MdePkg/Include/Ipf/IpfMacro.i
>deleted file mode 100644
>index e66a63b83c..0000000000
>--- a/MdePkg/Include/Ipf/IpfMacro.i
>+++ /dev/null
>@@ -1,58 +0,0 @@
>-// @file
>-// Contains the macros required by calling procedures in Itanium-based
>assembly code.
>-//
>-// Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
>-// This program and the accompanying materials
>-// are licensed and made available under the terms and conditions of the BSD
>License
>-// which accompanies this distribution. The full text of the license may be
>found at
>-// http://opensource.org/licenses/bsd-license.php
>-//
>-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-//
>-
>-#ifndef __IA64PROC_I__
>-#define __IA64PROC_I__
>-
>-//
>-// Delcare the begin of assembly function entry.
>-//
>-// @param name Name of function in assembly code.
>-//
>-#define PROCEDURE_ENTRY(name) .##text; \
>- .##type name, @function; \
>- .##proc name; \
>-name::
>-
>-//
>-// End of assembly function.
>-//
>-// @param name Name of function in assembly code.
>-//
>-#define PROCEDURE_EXIT(name) .##endp name
>-
>-//
>-// NESTED_SETUP Requires number of locals (l) >= 3
>-//
>-#define NESTED_SETUP(i,l,o,r) \
>- alloc loc1=ar##.##pfs,i,l,o,r ;\
>- mov loc0=b0
>-
>-//
>-// End of Nested
>-//
>-#define NESTED_RETURN \
>- mov b0=loc0 ;\
>- mov ar##.##pfs=loc1 ;;\
>- br##.##ret##.##dpnt b0;;
>-
>-//
>-// Export assembly function as the global function.
>-//
>-// @param Function Name of function in assembly code.
>-//
>-#define GLOBAL_FUNCTION(Function) \
>- .##type Function, @function; \
>- .##globl Function
>-
>-#endif
>diff --git a/MdePkg/Include/Ipf/ProcessorBind.h
>b/MdePkg/Include/Ipf/ProcessorBind.h
>deleted file mode 100644
>index bfbae01abb..0000000000
>--- a/MdePkg/Include/Ipf/ProcessorBind.h
>+++ /dev/null
>@@ -1,324 +0,0 @@
>-/** @file
>- Processor or Compiler specific defines and types for Intel Itanium(TM)
>processors.
>-
>-Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
>-This program and the accompanying materials are licensed and made
>available
>-under the terms and conditions of the BSD License which accompanies this
>-distribution. The full text of the license may be found at
>-http://opensource.org/licenses/bsd-license.php.
>-
>-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
>-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-
>-**/
>-
>-#ifndef __PROCESSOR_BIND_H__
>-#define __PROCESSOR_BIND_H__
>-
>-
>-///
>-/// Define the processor type so other code can make processor-based
>choices.
>-///
>-#define MDE_CPU_IPF
>-
>-
>-//
>-// Make sure we are using the correct packing rules per EFI specification
>-//
>-#pragma pack()
>-
>-
>-#if defined(__INTEL_COMPILER)
>-//
>-// Disable ICC's remark #869: "Parameter" was never referenced warning.
>-// This is legal ANSI C code so we disable the remark that is turned on with -
>Wall
>-//
>-#pragma warning ( disable : 869 )
>-
>-//
>-// Disable ICC's remark #1418: external function definition with no prior
>declaration.
>-// This is legal ANSI C code so we disable the remark that is turned on with
>/W4
>-//
>-#pragma warning ( disable : 1418 )
>-
>-//
>-// Disable ICC's remark #1419: external declaration in primary source file
>-// This is legal ANSI C code so we disable the remark that is turned on with
>/W4
>-//
>-#pragma warning ( disable : 1419 )
>-
>-//
>-// Disable ICC's remark #593: "Variable" was set but never used.
>-// This is legal ANSI C code so we disable the remark that is turned on with
>/W4
>-//
>-#pragma warning ( disable : 593 )
>-
>-#endif
>-
>-
>-#if defined(_MSC_EXTENSIONS)
>-//
>-// Disable warning that make it impossible to compile at /W4
>-// This only works for Microsoft* tools
>-//
>-
>-//
>-// Disabling bitfield type checking warnings.
>-//
>-#pragma warning ( disable : 4214 )
>-
>-//
>-// Disabling the unreferenced formal parameter warnings.
>-//
>-#pragma warning ( disable : 4100 )
>-
>-//
>-// Disable slightly different base types warning as CHAR8 * can not be set
>-// to a constant string.
>-//
>-#pragma warning ( disable : 4057 )
>-
>-//
>-// Disable warning on conversion from function pointer to a data pointer
>-//
>-#pragma warning ( disable : 4054 )
>-
>-//
>-// ASSERT(FALSE) or while (TRUE) are legal constructs so suppress this
>warning
>-//
>-#pragma warning ( disable : 4127 )
>-
>-//
>-// Can not cast a function pointer to a data pointer. We need to do this on
>-// Itanium processors to get access to the PLABEL.
>-//
>-#pragma warning ( disable : 4514 )
>-
>-//
>-// This warning is caused by functions defined but not used. For precompiled
>header only.
>-//
>-#pragma warning ( disable : 4505 )
>-
>-//
>-// This warning is caused by empty (after preprocessing) source file. For
>precompiled header only.
>-//
>-#pragma warning ( disable : 4206 )
>-
>-#endif
>-
>-#if defined(_MSC_EXTENSIONS)
>- //
>- // use Microsoft C compiler dependent integer width types
>- //
>-
>- ///
>- /// 8-byte unsigned value.
>- ///
>- typedef unsigned __int64 UINT64;
>- ///
>- /// 8-byte signed value.
>- ///
>- typedef __int64 INT64;
>- ///
>- /// 4-byte unsigned value.
>- ///
>- typedef unsigned __int32 UINT32;
>- ///
>- /// 4-byte signed value.
>- ///
>- typedef __int32 INT32;
>- ///
>- /// 2-byte unsigned value.
>- ///
>- typedef unsigned short UINT16;
>- ///
>- /// 2-byte Character. Unless otherwise specified all strings are stored in the
>- /// UTF-16 encoding format as defined by Unicode 2.1 and ISO/IEC 10646
>standards.
>- ///
>- typedef unsigned short CHAR16;
>- ///
>- /// 2-byte signed value.
>- ///
>- typedef short INT16;
>- ///
>- /// Logical Boolean. 1-byte value containing 0 for FALSE or a 1 for TRUE.
>Other
>- /// values are undefined.
>- ///
>- typedef unsigned char BOOLEAN;
>- ///
>- /// 1-byte unsigned value.
>- ///
>- typedef unsigned char UINT8;
>- ///
>- /// 1-byte Character.
>- ///
>- typedef char CHAR8;
>- ///
>- /// 1-byte signed value.
>- ///
>- typedef signed char INT8;
>-#else
>- ///
>- /// 8-byte unsigned value.
>- ///
>- typedef unsigned long long UINT64;
>- ///
>- /// 8-byte signed value.
>- ///
>- typedef long long INT64;
>- ///
>- /// 4-byte unsigned value.
>- ///
>- typedef unsigned int UINT32;
>- ///
>- /// 4-byte signed value.
>- ///
>- typedef int INT32;
>- ///
>- /// 2-byte unsigned value.
>- ///
>- typedef unsigned short UINT16;
>- ///
>- /// 2-byte Character. Unless otherwise specified all strings are stored in the
>- /// UTF-16 encoding format as defined by Unicode 2.1 and ISO/IEC 10646
>standards.
>- ///
>- typedef unsigned short CHAR16;
>- ///
>- /// 2-byte signed value.
>- ///
>- typedef short INT16;
>- ///
>- /// Logical Boolean. 1-byte value containing 0 for FALSE or a 1 for TRUE.
>Other
>- /// values are undefined.
>- ///
>- typedef unsigned char BOOLEAN;
>- ///
>- /// 1-byte unsigned value.
>- ///
>- typedef unsigned char UINT8;
>- ///
>- /// 1-byte Character.
>- ///
>- typedef char CHAR8;
>- ///
>- /// 1-byte signed value.
>- ///
>- typedef signed char INT8;
>-#endif
>-
>-///
>-/// Unsigned value of native width. (4 bytes on supported 32-bit processor
>instructions;
>-/// 8 bytes on supported 64-bit processor instructions.)
>-///
>-typedef UINT64 UINTN;
>-///
>-/// Signed value of native width. (4 bytes on supported 32-bit processor
>instructions;
>-/// 8 bytes on supported 64-bit processor instructions.)
>-///
>-typedef INT64 INTN;
>-
>-
>-//
>-// Processor specific defines
>-//
>-
>-///
>-/// A value of native width with the highest bit set.
>-///
>-#define MAX_BIT 0x8000000000000000ULL
>-///
>-/// A value of native width with the two highest bits set.
>-///
>-#define MAX_2_BITS 0xC000000000000000ULL
>-
>-///
>-/// The maximum legal Itanium-based address
>-///
>-#define MAX_ADDRESS 0xFFFFFFFFFFFFFFFFULL
>-
>-///
>-/// Maximum legal Itanium-based INTN and UINTN values.
>-///
>-#define MAX_INTN ((INTN)0x7FFFFFFFFFFFFFFFULL)
>-#define MAX_UINTN ((UINTN)0xFFFFFFFFFFFFFFFFULL)
>-
>-///
>-/// Minimum legal Itanium-based INTN value.
>-///
>-#define MIN_INTN (((INTN)-9223372036854775807LL) - 1)
>-
>-///
>-/// Per the Itanium Software Conventions and Runtime Architecture Guide,
>-/// section 3.3.4, IPF stack must always be 16-byte aligned.
>-///
>-#define CPU_STACK_ALIGNMENT 16
>-
>-///
>-/// Page allocation granularity for Itanium
>-///
>-#define DEFAULT_PAGE_ALLOCATION_GRANULARITY (0x1000)
>-#define RUNTIME_PAGE_ALLOCATION_GRANULARITY (0x2000)
>-
>-//
>-// Modifier to ensure that all protocol member functions and EFI intrinsics
>-// use the correct C calling convention. All protocol member functions and
>-// EFI intrinsics are required to modify their member functions with EFIAPI.
>-//
>-#ifdef EFIAPI
>- ///
>- /// If EFIAPI is already defined, then we use that definition.
>- ///
>-#elif defined(_MSC_EXTENSIONS)
>- ///
>- /// Microsoft* compiler-specific method for EFIAPI calling convention.
>- ///
>- #define EFIAPI __cdecl
>-#else
>- #define EFIAPI
>-#endif
>-
>-///
>-/// For GNU assembly code, .global or .globl can declare global symbols.
>-/// Define this macro to unify the usage.
>-///
>-#define ASM_GLOBAL .globl
>-
>-///
>-/// A pointer to a function in IPF points to a plabel.
>-///
>-typedef struct {
>- UINT64 EntryPoint;
>- UINT64 GP;
>-} EFI_PLABEL;
>-
>-///
>-/// PAL Call return structure.
>-///
>-typedef struct {
>- UINT64 Status;
>- UINT64 r9;
>- UINT64 r10;
>- UINT64 r11;
>-} PAL_CALL_RETURN;
>-
>-/**
>- Return the pointer to the first instruction of a function given a function
>pointer.
>- For Itanium processors, all function calls are made through a PLABEL, so a
>pointer to a function
>- is actually a pointer to a PLABEL. The pointer to the first instruction of the
>function
>- is contained within the PLABEL. This macro may be used to retrieve a
>pointer to the first
>- instruction of a function independent of the CPU architecture being used.
>This is very
>- useful when printing function addresses through DEBUG() macros.
>-
>- @param FunctionPointer A pointer to a function.
>-
>- @return The pointer to the first instruction of a function given a function
>pointer.
>-
>-**/
>-#define FUNCTION_ENTRY_POINT(FunctionPointer) (VOID
>*)(UINTN)(((EFI_PLABEL *)(FunctionPointer))->EntryPoint)
>-
>-#ifndef __USER_LABEL_PREFIX__
>-#define __USER_LABEL_PREFIX__
>-#endif
>-
>-#endif
>-
>diff --git a/MdePkg/Include/Library/BaseLib.h
>b/MdePkg/Include/Library/BaseLib.h
>index eb2899f852..99b74e8650 100644
>--- a/MdePkg/Include/Library/BaseLib.h
>+++ b/MdePkg/Include/Library/BaseLib.h
>@@ -37,56 +37,6 @@ typedef struct {
>
> #endif // defined (MDE_CPU_IA32)
>
>-#if defined (MDE_CPU_IPF)
>-
>-///
>-/// The Itanium architecture context buffer used by SetJump() and
>LongJump().
>-///
>-typedef struct {
>- UINT64 F2[2];
>- UINT64 F3[2];
>- UINT64 F4[2];
>- UINT64 F5[2];
>- UINT64 F16[2];
>- UINT64 F17[2];
>- UINT64 F18[2];
>- UINT64 F19[2];
>- UINT64 F20[2];
>- UINT64 F21[2];
>- UINT64 F22[2];
>- UINT64 F23[2];
>- UINT64 F24[2];
>- UINT64 F25[2];
>- UINT64 F26[2];
>- UINT64 F27[2];
>- UINT64 F28[2];
>- UINT64 F29[2];
>- UINT64 F30[2];
>- UINT64 F31[2];
>- UINT64 R4;
>- UINT64 R5;
>- UINT64 R6;
>- UINT64 R7;
>- UINT64 SP;
>- UINT64 BR0;
>- UINT64 BR1;
>- UINT64 BR2;
>- UINT64 BR3;
>- UINT64 BR4;
>- UINT64 BR5;
>- UINT64 InitialUNAT;
>- UINT64 AfterSpillUNAT;
>- UINT64 PFS;
>- UINT64 BSP;
>- UINT64 Predicates;
>- UINT64 LoopCount;
>- UINT64 FPSR;
>-} BASE_LIBRARY_JUMP_BUFFER;
>-
>-#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 0x10
>-
>-#endif // defined (MDE_CPU_IPF)
>-
> #if defined (MDE_CPU_X64)
> ///
> /// The x64 architecture context buffer used by SetJump() and LongJump().
>@@ -5104,1398 +5054,6 @@ EFIAPI
> CpuDeadLoop (
> VOID
> );
>-
>-#if defined (MDE_CPU_IPF)
>-
>-/**
>- Flush a range of cache lines in the cache coherency domain of the calling
>- CPU.
>-
>- Flushes the cache lines specified by Address and Length. If Address is not
>aligned
>- on a cache line boundary, then entire cache line containing Address is
>flushed.
>- If Address + Length is not aligned on a cache line boundary, then the entire
>cache
>- line containing Address + Length - 1 is flushed. This function may choose to
>flush
>- the entire cache if that is more efficient than flushing the specified range. If
>- Length is 0, the no cache lines are flushed. Address is returned.
>- This function is only available on Itanium processors.
>-
>- If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
>-
>- @param Address The base address of the instruction lines to invalidate. If
>- the CPU is in a physical addressing mode, then Address is a
>- physical address. If the CPU is in a virtual addressing mode,
>- then Address is a virtual address.
>-
>- @param Length The number of bytes to invalidate from the instruction
>cache.
>-
>- @return Address.
>-
>-**/
>-VOID *
>-EFIAPI
>-AsmFlushCacheRange (
>- IN VOID *Address,
>- IN UINTN Length
>- );
>-
>-
>-/**
>- Executes an FC instruction.
>- Executes an FC instruction on the cache line specified by Address.
>- The cache line size affected is at least 32-bytes (aligned on a 32-byte
>boundary).
>- An implementation may flush a larger region. This function is only available
>on Itanium processors.
>-
>- @param Address The Address of cache line to be flushed.
>-
>- @return The address of FC instruction executed.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmFc (
>- IN UINT64 Address
>- );
>-
>-
>-/**
>- Executes an FC.I instruction.
>- Executes an FC.I instruction on the cache line specified by Address.
>- The cache line size affected is at least 32-bytes (aligned on a 32-byte
>boundary).
>- An implementation may flush a larger region. This function is only available
>on Itanium processors.
>-
>- @param Address The Address of cache line to be flushed.
>-
>- @return The address of the FC.I instruction executed.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmFci (
>- IN UINT64 Address
>- );
>-
>-
>-/**
>- Reads the current value of a Processor Identifier Register (CPUID).
>-
>- Reads and returns the current value of Processor Identifier Register
>specified by Index.
>- The Index of largest implemented CPUID (One less than the number of
>implemented CPUID
>- registers) is determined by CPUID [3] bits {7:0}.
>- No parameter checking is performed on Index. If the Index value is beyond
>the
>- implemented CPUID register range, a Reserved Register/Field fault may
>occur. The caller
>- must either guarantee that Index is valid, or the caller must set up fault
>handlers to
>- catch the faults. This function is only available on Itanium processors.
>-
>- @param Index The 8-bit Processor Identifier Register index to read.
>-
>- @return The current value of Processor Identifier Register specified by
>Index.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadCpuid (
>- IN UINT8 Index
>- );
>-
>-
>-/**
>- Reads the current value of 64-bit Processor Status Register (PSR).
>- This function is only available on Itanium processors.
>-
>- @return The current value of PSR.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadPsr (
>- VOID
>- );
>-
>-
>-/**
>- Writes the current value of 64-bit Processor Status Register (PSR).
>-
>- No parameter checking is performed on Value. All bits of Value
>corresponding to
>- reserved fields of PSR must be 0 or a Reserved Register/Field fault may
>occur.
>- The caller must either guarantee that Value is valid, or the caller must set up
>- fault handlers to catch the faults. This function is only available on Itanium
>processors.
>-
>- @param Value The 64-bit value to write to PSR.
>-
>- @return The 64-bit value written to the PSR.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmWritePsr (
>- IN UINT64 Value
>- );
>-
>-
>-/**
>- Reads the current value of 64-bit Kernel Register #0 (KR0).
>-
>- Reads and returns the current value of KR0.
>- This function is only available on Itanium processors.
>-
>- @return The current value of KR0.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadKr0 (
>- VOID
>- );
>-
>-
>-/**
>- Reads the current value of 64-bit Kernel Register #1 (KR1).
>-
>- Reads and returns the current value of KR1.
>- This function is only available on Itanium processors.
>-
>- @return The current value of KR1.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadKr1 (
>- VOID
>- );
>-
>-
>-/**
>- Reads the current value of 64-bit Kernel Register #2 (KR2).
>-
>- Reads and returns the current value of KR2.
>- This function is only available on Itanium processors.
>-
>- @return The current value of KR2.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadKr2 (
>- VOID
>- );
>-
>-
>-/**
>- Reads the current value of 64-bit Kernel Register #3 (KR3).
>-
>- Reads and returns the current value of KR3.
>- This function is only available on Itanium processors.
>-
>- @return The current value of KR3.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadKr3 (
>- VOID
>- );
>-
>-
>-/**
>- Reads the current value of 64-bit Kernel Register #4 (KR4).
>-
>- Reads and returns the current value of KR4.
>- This function is only available on Itanium processors.
>-
>- @return The current value of KR4.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadKr4 (
>- VOID
>- );
>-
>-
>-/**
>- Reads the current value of 64-bit Kernel Register #5 (KR5).
>-
>- Reads and returns the current value of KR5.
>- This function is only available on Itanium processors.
>-
>- @return The current value of KR5.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadKr5 (
>- VOID
>- );
>-
>-
>-/**
>- Reads the current value of 64-bit Kernel Register #6 (KR6).
>-
>- Reads and returns the current value of KR6.
>- This function is only available on Itanium processors.
>-
>- @return The current value of KR6.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadKr6 (
>- VOID
>- );
>-
>-
>-/**
>- Reads the current value of 64-bit Kernel Register #7 (KR7).
>-
>- Reads and returns the current value of KR7.
>- This function is only available on Itanium processors.
>-
>- @return The current value of KR7.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadKr7 (
>- VOID
>- );
>-
>-
>-/**
>- Write the current value of 64-bit Kernel Register #0 (KR0).
>-
>- Writes the current value of KR0. The 64-bit value written to
>- the KR0 is returned. This function is only available on Itanium processors.
>-
>- @param Value The 64-bit value to write to KR0.
>-
>- @return The 64-bit value written to the KR0.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmWriteKr0 (
>- IN UINT64 Value
>- );
>-
>-
>-/**
>- Write the current value of 64-bit Kernel Register #1 (KR1).
>-
>- Writes the current value of KR1. The 64-bit value written to
>- the KR1 is returned. This function is only available on Itanium processors.
>-
>- @param Value The 64-bit value to write to KR1.
>-
>- @return The 64-bit value written to the KR1.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmWriteKr1 (
>- IN UINT64 Value
>- );
>-
>-
>-/**
>- Write the current value of 64-bit Kernel Register #2 (KR2).
>-
>- Writes the current value of KR2. The 64-bit value written to
>- the KR2 is returned. This function is only available on Itanium processors.
>-
>- @param Value The 64-bit value to write to KR2.
>-
>- @return The 64-bit value written to the KR2.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmWriteKr2 (
>- IN UINT64 Value
>- );
>-
>-
>-/**
>- Write the current value of 64-bit Kernel Register #3 (KR3).
>-
>- Writes the current value of KR3. The 64-bit value written to
>- the KR3 is returned. This function is only available on Itanium processors.
>-
>- @param Value The 64-bit value to write to KR3.
>-
>- @return The 64-bit value written to the KR3.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmWriteKr3 (
>- IN UINT64 Value
>- );
>-
>-
>-/**
>- Write the current value of 64-bit Kernel Register #4 (KR4).
>-
>- Writes the current value of KR4. The 64-bit value written to
>- the KR4 is returned. This function is only available on Itanium processors.
>-
>- @param Value The 64-bit value to write to KR4.
>-
>- @return The 64-bit value written to the KR4.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmWriteKr4 (
>- IN UINT64 Value
>- );
>-
>-
>-/**
>- Write the current value of 64-bit Kernel Register #5 (KR5).
>-
>- Writes the current value of KR5. The 64-bit value written to
>- the KR5 is returned. This function is only available on Itanium processors.
>-
>- @param Value The 64-bit value to write to KR5.
>-
>- @return The 64-bit value written to the KR5.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmWriteKr5 (
>- IN UINT64 Value
>- );
>-
>-
>-/**
>- Write the current value of 64-bit Kernel Register #6 (KR6).
>-
>- Writes the current value of KR6. The 64-bit value written to
>- the KR6 is returned. This function is only available on Itanium processors.
>-
>- @param Value The 64-bit value to write to KR6.
>-
>- @return The 64-bit value written to the KR6.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmWriteKr6 (
>- IN UINT64 Value
>- );
>-
>-
>-/**
>- Write the current value of 64-bit Kernel Register #7 (KR7).
>-
>- Writes the current value of KR7. The 64-bit value written to
>- the KR7 is returned. This function is only available on Itanium processors.
>-
>- @param Value The 64-bit value to write to KR7.
>-
>- @return The 64-bit value written to the KR7.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmWriteKr7 (
>- IN UINT64 Value
>- );
>-
>-
>-/**
>- Reads the current value of Interval Timer Counter Register (ITC).
>-
>- Reads and returns the current value of ITC.
>- This function is only available on Itanium processors.
>-
>- @return The current value of ITC.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadItc (
>- VOID
>- );
>-
>-
>-/**
>- Reads the current value of Interval Timer Vector Register (ITV).
>-
>- Reads and returns the current value of ITV.
>- This function is only available on Itanium processors.
>-
>- @return The current value of ITV.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadItv (
>- VOID
>- );
>-
>-
>-/**
>- Reads the current value of Interval Timer Match Register (ITM).
>-
>- Reads and returns the current value of ITM.
>- This function is only available on Itanium processors.
>-
>- @return The current value of ITM.
>-**/
>-UINT64
>-EFIAPI
>-AsmReadItm (
>- VOID
>- );
>-
>-
>-/**
>- Writes the current value of 64-bit Interval Timer Counter Register (ITC).
>-
>- Writes the current value of ITC. The 64-bit value written to the ITC is
>returned.
>- This function is only available on Itanium processors.
>-
>- @param Value The 64-bit value to write to ITC.
>-
>- @return The 64-bit value written to the ITC.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmWriteItc (
>- IN UINT64 Value
>- );
>-
>-
>-/**
>- Writes the current value of 64-bit Interval Timer Match Register (ITM).
>-
>- Writes the current value of ITM. The 64-bit value written to the ITM is
>returned.
>- This function is only available on Itanium processors.
>-
>- @param Value The 64-bit value to write to ITM.
>-
>- @return The 64-bit value written to the ITM.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmWriteItm (
>- IN UINT64 Value
>- );
>-
>-
>-/**
>- Writes the current value of 64-bit Interval Timer Vector Register (ITV).
>-
>- Writes the current value of ITV. The 64-bit value written to the ITV is
>returned.
>- No parameter checking is performed on Value. All bits of Value
>corresponding to
>- reserved fields of ITV must be 0 or a Reserved Register/Field fault may occur.
>- The caller must either guarantee that Value is valid, or the caller must set up
>- fault handlers to catch the faults.
>- This function is only available on Itanium processors.
>-
>- @param Value The 64-bit value to write to ITV.
>-
>- @return The 64-bit value written to the ITV.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmWriteItv (
>- IN UINT64 Value
>- );
>-
>-
>-/**
>- Reads the current value of Default Control Register (DCR).
>-
>- Reads and returns the current value of DCR. This function is only available
>on Itanium processors.
>-
>- @return The current value of DCR.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadDcr (
>- VOID
>- );
>-
>-
>-/**
>- Reads the current value of Interruption Vector Address Register (IVA).
>-
>- Reads and returns the current value of IVA. This function is only available on
>Itanium processors.
>-
>- @return The current value of IVA.
>-**/
>-UINT64
>-EFIAPI
>-AsmReadIva (
>- VOID
>- );
>-
>-
>-/**
>- Reads the current value of Page Table Address Register (PTA).
>-
>- Reads and returns the current value of PTA. This function is only available
>on Itanium processors.
>-
>- @return The current value of PTA.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadPta (
>- VOID
>- );
>-
>-
>-/**
>- Writes the current value of 64-bit Default Control Register (DCR).
>-
>- Writes the current value of DCR. The 64-bit value written to the DCR is
>returned.
>- No parameter checking is performed on Value. All bits of Value
>corresponding to
>- reserved fields of DCR must be 0 or a Reserved Register/Field fault may
>occur.
>- The caller must either guarantee that Value is valid, or the caller must set up
>- fault handlers to catch the faults.
>- This function is only available on Itanium processors.
>-
>- @param Value The 64-bit value to write to DCR.
>-
>- @return The 64-bit value written to the DCR.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmWriteDcr (
>- IN UINT64 Value
>- );
>-
>-
>-/**
>- Writes the current value of 64-bit Interruption Vector Address Register (IVA).
>-
>- Writes the current value of IVA. The 64-bit value written to the IVA is
>returned.
>- The size of vector table is 32 K bytes and is 32 K bytes aligned
>- the low 15 bits of Value is ignored when written.
>- This function is only available on Itanium processors.
>-
>- @param Value The 64-bit value to write to IVA.
>-
>- @return The 64-bit value written to the IVA.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmWriteIva (
>- IN UINT64 Value
>- );
>-
>-
>-/**
>- Writes the current value of 64-bit Page Table Address Register (PTA).
>-
>- Writes the current value of PTA. The 64-bit value written to the PTA is
>returned.
>- No parameter checking is performed on Value. All bits of Value
>corresponding to
>- reserved fields of DCR must be 0 or a Reserved Register/Field fault may
>occur.
>- The caller must either guarantee that Value is valid, or the caller must set up
>- fault handlers to catch the faults.
>- This function is only available on Itanium processors.
>-
>- @param Value The 64-bit value to write to PTA.
>-
>- @return The 64-bit value written to the PTA.
>-**/
>-UINT64
>-EFIAPI
>-AsmWritePta (
>- IN UINT64 Value
>- );
>-
>-
>-/**
>- Reads the current value of Local Interrupt ID Register (LID).
>-
>- Reads and returns the current value of LID. This function is only available on
>Itanium processors.
>-
>- @return The current value of LID.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadLid (
>- VOID
>- );
>-
>-
>-/**
>- Reads the current value of External Interrupt Vector Register (IVR).
>-
>- Reads and returns the current value of IVR. This function is only available on
>Itanium processors.
>-
>- @return The current value of IVR.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadIvr (
>- VOID
>- );
>-
>-
>-/**
>- Reads the current value of Task Priority Register (TPR).
>-
>- Reads and returns the current value of TPR. This function is only available on
>Itanium processors.
>-
>- @return The current value of TPR.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadTpr (
>- VOID
>- );
>-
>-
>-/**
>- Reads the current value of External Interrupt Request Register #0 (IRR0).
>-
>- Reads and returns the current value of IRR0. This function is only available
>on Itanium processors.
>-
>- @return The current value of IRR0.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadIrr0 (
>- VOID
>- );
>-
>-
>-/**
>- Reads the current value of External Interrupt Request Register #1 (IRR1).
>-
>- Reads and returns the current value of IRR1. This function is only available
>on Itanium processors.
>-
>- @return The current value of IRR1.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadIrr1 (
>- VOID
>- );
>-
>-
>-/**
>- Reads the current value of External Interrupt Request Register #2 (IRR2).
>-
>- Reads and returns the current value of IRR2. This function is only available
>on Itanium processors.
>-
>- @return The current value of IRR2.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadIrr2 (
>- VOID
>- );
>-
>-
>-/**
>- Reads the current value of External Interrupt Request Register #3 (IRR3).
>-
>- Reads and returns the current value of IRR3. This function is only available
>on Itanium processors.
>-
>- @return The current value of IRR3.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadIrr3 (
>- VOID
>- );
>-
>-
>-/**
>- Reads the current value of Performance Monitor Vector Register (PMV).
>-
>- Reads and returns the current value of PMV. This function is only available
>on Itanium processors.
>-
>- @return The current value of PMV.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadPmv (
>- VOID
>- );
>-
>-
>-/**
>- Reads the current value of Corrected Machine Check Vector Register
>(CMCV).
>-
>- Reads and returns the current value of CMCV. This function is only available
>on Itanium processors.
>-
>- @return The current value of CMCV.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadCmcv (
>- VOID
>- );
>-
>-
>-/**
>- Reads the current value of Local Redirection Register #0 (LRR0).
>-
>- Reads and returns the current value of LRR0. This function is only available
>on Itanium processors.
>-
>- @return The current value of LRR0.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadLrr0 (
>- VOID
>- );
>-
>-
>-/**
>- Reads the current value of Local Redirection Register #1 (LRR1).
>-
>- Reads and returns the current value of LRR1. This function is only available
>on Itanium processors.
>-
>- @return The current value of LRR1.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadLrr1 (
>- VOID
>- );
>-
>-
>-/**
>- Writes the current value of 64-bit Page Local Interrupt ID Register (LID).
>-
>- Writes the current value of LID. The 64-bit value written to the LID is
>returned.
>- No parameter checking is performed on Value. All bits of Value
>corresponding to
>- reserved fields of LID must be 0 or a Reserved Register/Field fault may occur.
>- The caller must either guarantee that Value is valid, or the caller must set up
>- fault handlers to catch the faults.
>- This function is only available on Itanium processors.
>-
>- @param Value The 64-bit value to write to LID.
>-
>- @return The 64-bit value written to the LID.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmWriteLid (
>- IN UINT64 Value
>- );
>-
>-
>-/**
>- Writes the current value of 64-bit Task Priority Register (TPR).
>-
>- Writes the current value of TPR. The 64-bit value written to the TPR is
>returned.
>- No parameter checking is performed on Value. All bits of Value
>corresponding to
>- reserved fields of TPR must be 0 or a Reserved Register/Field fault may
>occur.
>- The caller must either guarantee that Value is valid, or the caller must set up
>- fault handlers to catch the faults.
>- This function is only available on Itanium processors.
>-
>- @param Value The 64-bit value to write to TPR.
>-
>- @return The 64-bit value written to the TPR.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmWriteTpr (
>- IN UINT64 Value
>- );
>-
>-
>-/**
>- Performs a write operation on End OF External Interrupt Register (EOI).
>-
>- Writes a value of 0 to the EOI Register. This function is only available on
>Itanium processors.
>-
>-**/
>-VOID
>-EFIAPI
>-AsmWriteEoi (
>- VOID
>- );
>-
>-
>-/**
>- Writes the current value of 64-bit Performance Monitor Vector Register
>(PMV).
>-
>- Writes the current value of PMV. The 64-bit value written to the PMV is
>returned.
>- No parameter checking is performed on Value. All bits of Value
>corresponding
>- to reserved fields of PMV must be 0 or a Reserved Register/Field fault may
>occur.
>- The caller must either guarantee that Value is valid, or the caller must set up
>- fault handlers to catch the faults.
>- This function is only available on Itanium processors.
>-
>- @param Value The 64-bit value to write to PMV.
>-
>- @return The 64-bit value written to the PMV.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmWritePmv (
>- IN UINT64 Value
>- );
>-
>-
>-/**
>- Writes the current value of 64-bit Corrected Machine Check Vector Register
>(CMCV).
>-
>- Writes the current value of CMCV. The 64-bit value written to the CMCV is
>returned.
>- No parameter checking is performed on Value. All bits of Value
>corresponding
>- to reserved fields of CMCV must be 0 or a Reserved Register/Field fault may
>occur.
>- The caller must either guarantee that Value is valid, or the caller must set up
>- fault handlers to catch the faults.
>- This function is only available on Itanium processors.
>-
>- @param Value The 64-bit value to write to CMCV.
>-
>- @return The 64-bit value written to the CMCV.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmWriteCmcv (
>- IN UINT64 Value
>- );
>-
>-
>-/**
>- Writes the current value of 64-bit Local Redirection Register #0 (LRR0).
>-
>- Writes the current value of LRR0. The 64-bit value written to the LRR0 is
>returned.
>- No parameter checking is performed on Value. All bits of Value
>corresponding
>- to reserved fields of LRR0 must be 0 or a Reserved Register/Field fault may
>occur.
>- The caller must either guarantee that Value is valid, or the caller must set up
>- fault handlers to catch the faults.
>- This function is only available on Itanium processors.
>-
>- @param Value The 64-bit value to write to LRR0.
>-
>- @return The 64-bit value written to the LRR0.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmWriteLrr0 (
>- IN UINT64 Value
>- );
>-
>-
>-/**
>- Writes the current value of 64-bit Local Redirection Register #1 (LRR1).
>-
>- Writes the current value of LRR1. The 64-bit value written to the LRR1 is
>returned.
>- No parameter checking is performed on Value. All bits of Value
>corresponding
>- to reserved fields of LRR1 must be 0 or a Reserved Register/Field fault may
>occur.
>- The caller must either guarantee that Value is valid, or the caller must
>- set up fault handlers to catch the faults.
>- This function is only available on Itanium processors.
>-
>- @param Value The 64-bit value to write to LRR1.
>-
>- @return The 64-bit value written to the LRR1.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmWriteLrr1 (
>- IN UINT64 Value
>- );
>-
>-
>-/**
>- Reads the current value of Instruction Breakpoint Register (IBR).
>-
>- The Instruction Breakpoint Registers are used in pairs. The even numbered
>- registers contain breakpoint addresses, and the odd numbered registers
>contain
>- breakpoint mask conditions. At least four instruction registers pairs are
>implemented
>- on all processor models. Implemented registers are contiguous starting
>with
>- register 0. No parameter checking is performed on Index, and if the Index
>value
>- is beyond the implemented IBR register range, a Reserved Register/Field
>fault may
>- occur. The caller must either guarantee that Index is valid, or the caller must
>- set up fault handlers to catch the faults.
>- This function is only available on Itanium processors.
>-
>- @param Index The 8-bit Instruction Breakpoint Register index to read.
>-
>- @return The current value of Instruction Breakpoint Register specified by
>Index.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadIbr (
>- IN UINT8 Index
>- );
>-
>-
>-/**
>- Reads the current value of Data Breakpoint Register (DBR).
>-
>- The Data Breakpoint Registers are used in pairs. The even numbered
>registers
>- contain breakpoint addresses, and odd numbered registers contain
>breakpoint
>- mask conditions. At least four data registers pairs are implemented on all
>processor
>- models. Implemented registers are contiguous starting with register 0.
>- No parameter checking is performed on Index. If the Index value is beyond
>- the implemented DBR register range, a Reserved Register/Field fault may
>occur.
>- The caller must either guarantee that Index is valid, or the caller must set up
>- fault handlers to catch the faults.
>- This function is only available on Itanium processors.
>-
>- @param Index The 8-bit Data Breakpoint Register index to read.
>-
>- @return The current value of Data Breakpoint Register specified by Index.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadDbr (
>- IN UINT8 Index
>- );
>-
>-
>-/**
>- Reads the current value of Performance Monitor Configuration Register
>(PMC).
>-
>- All processor implementations provide at least four performance counters
>- (PMC/PMD [4]...PMC/PMD [7] pairs), and four performance monitor
>counter overflow
>- status registers (PMC [0]... PMC [3]). Processor implementations may
>provide
>- additional implementation-dependent PMC and PMD to increase the
>number of
>- 'generic' performance counters (PMC/PMD pairs). The remainder of PMC
>and PMD
>- register set is implementation dependent. No parameter checking is
>performed
>- on Index. If the Index value is beyond the implemented PMC register range,
>- zero value will be returned.
>- This function is only available on Itanium processors.
>-
>- @param Index The 8-bit Performance Monitor Configuration Register
>index to read.
>-
>- @return The current value of Performance Monitor Configuration Register
>- specified by Index.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadPmc (
>- IN UINT8 Index
>- );
>-
>-
>-/**
>- Reads the current value of Performance Monitor Data Register (PMD).
>-
>- All processor implementations provide at least 4 performance counters
>- (PMC/PMD [4]...PMC/PMD [7] pairs), and 4 performance monitor counter
>- overflow status registers (PMC [0]... PMC [3]). Processor implementations
>may
>- provide additional implementation-dependent PMC and PMD to increase
>the number
>- of 'generic' performance counters (PMC/PMD pairs). The remainder of PMC
>and PMD
>- register set is implementation dependent. No parameter checking is
>performed
>- on Index. If the Index value is beyond the implemented PMD register range,
>- zero value will be returned.
>- This function is only available on Itanium processors.
>-
>- @param Index The 8-bit Performance Monitor Data Register index to read.
>-
>- @return The current value of Performance Monitor Data Register specified
>by Index.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadPmd (
>- IN UINT8 Index
>- );
>-
>-
>-/**
>- Writes the current value of 64-bit Instruction Breakpoint Register (IBR).
>-
>- Writes current value of Instruction Breakpoint Register specified by Index.
>- The Instruction Breakpoint Registers are used in pairs. The even numbered
>- registers contain breakpoint addresses, and odd numbered registers contain
>- breakpoint mask conditions. At least four instruction registers pairs are
>implemented
>- on all processor models. Implemented registers are contiguous starting with
>- register 0. No parameter checking is performed on Index. If the Index value
>- is beyond the implemented IBR register range, a Reserved Register/Field
>fault may
>- occur. The caller must either guarantee that Index is valid, or the caller must
>- set up fault handlers to catch the faults.
>- This function is only available on Itanium processors.
>-
>- @param Index The 8-bit Instruction Breakpoint Register index to write.
>- @param Value The 64-bit value to write to IBR.
>-
>- @return The 64-bit value written to the IBR.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmWriteIbr (
>- IN UINT8 Index,
>- IN UINT64 Value
>- );
>-
>-
>-/**
>- Writes the current value of 64-bit Data Breakpoint Register (DBR).
>-
>- Writes current value of Data Breakpoint Register specified by Index.
>- The Data Breakpoint Registers are used in pairs. The even numbered
>registers
>- contain breakpoint addresses, and odd numbered registers contain
>breakpoint
>- mask conditions. At least four data registers pairs are implemented on all
>processor
>- models. Implemented registers are contiguous starting with register 0. No
>parameter
>- checking is performed on Index. If the Index value is beyond the
>implemented
>- DBR register range, a Reserved Register/Field fault may occur. The caller
>must
>- either guarantee that Index is valid, or the caller must set up fault handlers
>to
>- catch the faults.
>- This function is only available on Itanium processors.
>-
>- @param Index The 8-bit Data Breakpoint Register index to write.
>- @param Value The 64-bit value to write to DBR.
>-
>- @return The 64-bit value written to the DBR.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmWriteDbr (
>- IN UINT8 Index,
>- IN UINT64 Value
>- );
>-
>-
>-/**
>- Writes the current value of 64-bit Performance Monitor Configuration
>Register (PMC).
>-
>- Writes current value of Performance Monitor Configuration Register
>specified by Index.
>- All processor implementations provide at least four performance counters
>- (PMC/PMD [4]...PMC/PMD [7] pairs), and four performance monitor
>counter overflow status
>- registers (PMC [0]... PMC [3]). Processor implementations may provide
>additional
>- implementation-dependent PMC and PMD to increase the number of
>'generic' performance
>- counters (PMC/PMD pairs). The remainder of PMC and PMD register set is
>implementation
>- dependent. No parameter checking is performed on Index. If the Index
>value is
>- beyond the implemented PMC register range, the write is ignored.
>- This function is only available on Itanium processors.
>-
>- @param Index The 8-bit Performance Monitor Configuration Register
>index to write.
>- @param Value The 64-bit value to write to PMC.
>-
>- @return The 64-bit value written to the PMC.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmWritePmc (
>- IN UINT8 Index,
>- IN UINT64 Value
>- );
>-
>-
>-/**
>- Writes the current value of 64-bit Performance Monitor Data Register (PMD).
>-
>- Writes current value of Performance Monitor Data Register specified by
>Index.
>- All processor implementations provide at least four performance counters
>- (PMC/PMD [4]...PMC/PMD [7] pairs), and four performance monitor
>counter overflow
>- status registers (PMC [0]... PMC [3]). Processor implementations may
>provide
>- additional implementation-dependent PMC and PMD to increase the
>number of 'generic'
>- performance counters (PMC/PMD pairs). The remainder of PMC and PMD
>register set
>- is implementation dependent. No parameter checking is performed on
>Index. If the
>- Index value is beyond the implemented PMD register range, the write is
>ignored.
>- This function is only available on Itanium processors.
>-
>- @param Index The 8-bit Performance Monitor Data Register index to write.
>- @param Value The 64-bit value to write to PMD.
>-
>- @return The 64-bit value written to the PMD.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmWritePmd (
>- IN UINT8 Index,
>- IN UINT64 Value
>- );
>-
>-
>-/**
>- Reads the current value of 64-bit Global Pointer (GP).
>-
>- Reads and returns the current value of GP.
>- This function is only available on Itanium processors.
>-
>- @return The current value of GP.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadGp (
>- VOID
>- );
>-
>-
>-/**
>- Write the current value of 64-bit Global Pointer (GP).
>-
>- Writes the current value of GP. The 64-bit value written to the GP is
>returned.
>- No parameter checking is performed on Value.
>- This function is only available on Itanium processors.
>-
>- @param Value The 64-bit value to write to GP.
>-
>- @return The 64-bit value written to the GP.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmWriteGp (
>- IN UINT64 Value
>- );
>-
>-
>-/**
>- Reads the current value of 64-bit Stack Pointer (SP).
>-
>- Reads and returns the current value of SP.
>- This function is only available on Itanium processors.
>-
>- @return The current value of SP.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadSp (
>- VOID
>- );
>-
>-
>-///
>-/// Valid Index value for AsmReadControlRegister().
>-///
>-#define IPF_CONTROL_REGISTER_DCR 0
>-#define IPF_CONTROL_REGISTER_ITM 1
>-#define IPF_CONTROL_REGISTER_IVA 2
>-#define IPF_CONTROL_REGISTER_PTA 8
>-#define IPF_CONTROL_REGISTER_IPSR 16
>-#define IPF_CONTROL_REGISTER_ISR 17
>-#define IPF_CONTROL_REGISTER_IIP 19
>-#define IPF_CONTROL_REGISTER_IFA 20
>-#define IPF_CONTROL_REGISTER_ITIR 21
>-#define IPF_CONTROL_REGISTER_IIPA 22
>-#define IPF_CONTROL_REGISTER_IFS 23
>-#define IPF_CONTROL_REGISTER_IIM 24
>-#define IPF_CONTROL_REGISTER_IHA 25
>-#define IPF_CONTROL_REGISTER_LID 64
>-#define IPF_CONTROL_REGISTER_IVR 65
>-#define IPF_CONTROL_REGISTER_TPR 66
>-#define IPF_CONTROL_REGISTER_EOI 67
>-#define IPF_CONTROL_REGISTER_IRR0 68
>-#define IPF_CONTROL_REGISTER_IRR1 69
>-#define IPF_CONTROL_REGISTER_IRR2 70
>-#define IPF_CONTROL_REGISTER_IRR3 71
>-#define IPF_CONTROL_REGISTER_ITV 72
>-#define IPF_CONTROL_REGISTER_PMV 73
>-#define IPF_CONTROL_REGISTER_CMCV 74
>-#define IPF_CONTROL_REGISTER_LRR0 80
>-#define IPF_CONTROL_REGISTER_LRR1 81
>-
>-/**
>- Reads a 64-bit control register.
>-
>- Reads and returns the control register specified by Index. The valid Index
>valued
>- are defined above in "Related Definitions".
>- If Index is invalid then 0xFFFFFFFFFFFFFFFF is returned. This function is only
>- available on Itanium processors.
>-
>- @param Index The index of the control register to read.
>-
>- @return The control register specified by Index.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadControlRegister (
>- IN UINT64 Index
>- );
>-
>-
>-///
>-/// Valid Index value for AsmReadApplicationRegister().
>-///
>-#define IPF_APPLICATION_REGISTER_K0 0
>-#define IPF_APPLICATION_REGISTER_K1 1
>-#define IPF_APPLICATION_REGISTER_K2 2
>-#define IPF_APPLICATION_REGISTER_K3 3
>-#define IPF_APPLICATION_REGISTER_K4 4
>-#define IPF_APPLICATION_REGISTER_K5 5
>-#define IPF_APPLICATION_REGISTER_K6 6
>-#define IPF_APPLICATION_REGISTER_K7 7
>-#define IPF_APPLICATION_REGISTER_RSC 16
>-#define IPF_APPLICATION_REGISTER_BSP 17
>-#define IPF_APPLICATION_REGISTER_BSPSTORE 18
>-#define IPF_APPLICATION_REGISTER_RNAT 19
>-#define IPF_APPLICATION_REGISTER_FCR 21
>-#define IPF_APPLICATION_REGISTER_EFLAG 24
>-#define IPF_APPLICATION_REGISTER_CSD 25
>-#define IPF_APPLICATION_REGISTER_SSD 26
>-#define IPF_APPLICATION_REGISTER_CFLG 27
>-#define IPF_APPLICATION_REGISTER_FSR 28
>-#define IPF_APPLICATION_REGISTER_FIR 29
>-#define IPF_APPLICATION_REGISTER_FDR 30
>-#define IPF_APPLICATION_REGISTER_CCV 32
>-#define IPF_APPLICATION_REGISTER_UNAT 36
>-#define IPF_APPLICATION_REGISTER_FPSR 40
>-#define IPF_APPLICATION_REGISTER_ITC 44
>-#define IPF_APPLICATION_REGISTER_PFS 64
>-#define IPF_APPLICATION_REGISTER_LC 65
>-#define IPF_APPLICATION_REGISTER_EC 66
>-
>-/**
>- Reads a 64-bit application register.
>-
>- Reads and returns the application register specified by Index. The valid
>Index
>- valued are defined above in "Related Definitions".
>- If Index is invalid then 0xFFFFFFFFFFFFFFFF is returned. This function is only
>- available on Itanium processors.
>-
>- @param Index The index of the application register to read.
>-
>- @return The application register specified by Index.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadApplicationRegister (
>- IN UINT64 Index
>- );
>-
>-
>-/**
>- Reads the current value of a Machine Specific Register (MSR).
>-
>- Reads and returns the current value of the Machine Specific Register
>specified by Index. No
>- parameter checking is performed on Index, and if the Index value is beyond
>the implemented MSR
>- register range, a Reserved Register/Field fault may occur. The caller must
>either guarantee that
>- Index is valid, or the caller must set up fault handlers to catch the faults. This
>function is
>- only available on Itanium processors.
>-
>- @param Index The 8-bit Machine Specific Register index to read.
>-
>- @return The current value of the Machine Specific Register specified by
>Index.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadMsr (
>- IN UINT8 Index
>- );
>-
>-
>-/**
>- Writes the current value of a Machine Specific Register (MSR).
>-
>- Writes Value to the Machine Specific Register specified by Index. Value is
>returned. No
>- parameter checking is performed on Index, and if the Index value is beyond
>the implemented MSR
>- register range, a Reserved Register/Field fault may occur. The caller must
>either guarantee that
>- Index is valid, or the caller must set up fault handlers to catch the faults. This
>function is
>- only available on Itanium processors.
>-
>- @param Index The 8-bit Machine Specific Register index to write.
>- @param Value The 64-bit value to write to the Machine Specific
>Register.
>-
>- @return The 64-bit value to write to the Machine Specific Register.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmWriteMsr (
>- IN UINT8 Index,
>- IN UINT64 Value
>- );
>-
>-
>-/**
>- Determines if the CPU is currently executing in virtual, physical, or mixed
>mode.
>-
>- Determines the current execution mode of the CPU.
>- If the CPU is in virtual mode(PSR.RT=1, PSR.DT=1, PSR.IT=1), then 1 is
>returned.
>- If the CPU is in physical mode(PSR.RT=0, PSR.DT=0, PSR.IT=0), then 0 is
>returned.
>- If the CPU is not in physical mode or virtual mode, then it is in mixed mode,
>- and -1 is returned.
>- This function is only available on Itanium processors.
>-
>- @retval 1 The CPU is in virtual mode.
>- @retval 0 The CPU is in physical mode.
>- @retval -1 The CPU is in mixed mode.
>-
>-**/
>-INT64
>-EFIAPI
>-AsmCpuVirtual (
>- VOID
>- );
>-
>-
>-/**
>- Makes a PAL procedure call.
>-
>- This is a wrapper function to make a PAL procedure call. Based on the Index
>- value this API will make static or stacked PAL call. The following table
>- describes the usage of PAL Procedure Index Assignment. Architected
>procedures
>- may be designated as required or optional. If a PAL procedure is specified
>- as optional, a unique return code of 0xFFFFFFFFFFFFFFFF is returned in the
>- Status field of the PAL_CALL_RETURN structure.
>- This indicates that the procedure is not present in this PAL implementation.
>- It is the caller's responsibility to check for this return code after calling
>- any optional PAL procedure.
>- No parameter checking is performed on the 5 input parameters, but there
>are
>- some common rules that the caller should follow when making a PAL call.
>Any
>- address passed to PAL as buffers for return parameters must be 8-byte
>aligned.
>- Unaligned addresses may cause undefined results. For those parameters
>defined
>- as reserved or some fields defined as reserved must be zero filled or the
>invalid
>- argument return value may be returned or undefined result may occur
>during the
>- execution of the procedure. If the PalEntryPoint does not point to a valid
>- PAL entry point then the system behavior is undefined. This function is only
>- available on Itanium processors.
>-
>- @param PalEntryPoint The PAL procedure calls entry point.
>- @param Index The PAL procedure Index number.
>- @param Arg2 The 2nd parameter for PAL procedure calls.
>- @param Arg3 The 3rd parameter for PAL procedure calls.
>- @param Arg4 The 4th parameter for PAL procedure calls.
>-
>- @return structure returned from the PAL Call procedure, including the
>status and return value.
>-
>-**/
>-PAL_CALL_RETURN
>-EFIAPI
>-AsmPalCall (
>- IN UINT64 PalEntryPoint,
>- IN UINT64 Index,
>- IN UINT64 Arg2,
>- IN UINT64 Arg3,
>- IN UINT64 Arg4
>- );
>-#endif // defined (MDE_CPU_IPF)
>
> #if defined (MDE_CPU_IA32) || defined (MDE_CPU_X64)
> ///
>diff --git a/MdePkg/Include/Protocol/PxeBaseCode.h
>b/MdePkg/Include/Protocol/PxeBaseCode.h
>index 7cef457374..bf9af68ab1 100644
>--- a/MdePkg/Include/Protocol/PxeBaseCode.h
>+++ b/MdePkg/Include/Protocol/PxeBaseCode.h
>@@ -153,8 +153,6 @@ typedef UINT16 EFI_PXE_BASE_CODE_UDP_PORT;
> //
> #if defined (MDE_CPU_IA32)
> #define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x0006
>-#elif defined (MDE_CPU_IPF)
>-#define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x0002
> #elif defined (MDE_CPU_X64)
> #define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x0007
> #elif defined (MDE_CPU_ARM)
>diff --git a/MdePkg/Include/Uefi/UefiBaseType.h
>b/MdePkg/Include/Uefi/UefiBaseType.h
>index d9556cd2ec..fa5b36b565 100644
>--- a/MdePkg/Include/Uefi/UefiBaseType.h
>+++ b/MdePkg/Include/Uefi/UefiBaseType.h
>@@ -254,13 +254,6 @@ typedef union {
>
> #define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine)
>((Machine) == EFI_IMAGE_MACHINE_X64)
>
>-#elif defined (MDE_CPU_IPF)
>-
>-#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \
>- (((Machine) == EFI_IMAGE_MACHINE_IA64) || ((Machine) ==
>EFI_IMAGE_MACHINE_EBC))
>-
>-#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE)
>-
> #elif defined (MDE_CPU_X64)
>
> #define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \
>diff --git a/MdePkg/Include/Uefi/UefiSpec.h
>b/MdePkg/Include/Uefi/UefiSpec.h
>index ee016b48de..17b89416e5 100644
>--- a/MdePkg/Include/Uefi/UefiSpec.h
>+++ b/MdePkg/Include/Uefi/UefiSpec.h
>@@ -2190,8 +2190,6 @@ typedef struct {
>
> #if defined (MDE_CPU_IA32)
> #define EFI_REMOVABLE_MEDIA_FILE_NAME
>EFI_REMOVABLE_MEDIA_FILE_NAME_IA32
>-#elif defined (MDE_CPU_IPF)
>- #define EFI_REMOVABLE_MEDIA_FILE_NAME
>EFI_REMOVABLE_MEDIA_FILE_NAME_IA64
> #elif defined (MDE_CPU_X64)
> #define EFI_REMOVABLE_MEDIA_FILE_NAME
>EFI_REMOVABLE_MEDIA_FILE_NAME_X64
> #elif defined (MDE_CPU_EBC)
>diff --git
>a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
>b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
>index d659161f33..df082eb413 100644
>---
>a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
>+++
>b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
>@@ -28,7 +28,7 @@
>
>
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC ARM AARCH64
>+# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64
> #
>
> [Sources.IA32]
>@@ -37,9 +37,6 @@
> [Sources.X64]
> X86Cache.c
>
>-[Sources.IPF]
>- IpfCache.c
>-
> [Sources.EBC]
> EbcCache.c
>
>@@ -56,6 +53,3 @@
> BaseLib
> DebugLib
>
>-[LibraryClasses.Ipf]
>- PalLib
>-
>diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c
>b/MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c
>deleted file mode 100644
>index 24e985174e..0000000000
>--- a/MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c
>+++ /dev/null
>@@ -1,242 +0,0 @@
>-/** @file
>- Cache Maintenance Functions.
>-
>- Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
>- This program and the accompanying materials
>- are licensed and made available under the terms and conditions of the BSD
>License
>- which accompanies this distribution. The full text of the license may be
>found at
>- http://opensource.org/licenses/bsd-license.php.
>-
>- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-
>-**/
>-
>-#include <Base.h>
>-#include <Library/CacheMaintenanceLib.h>
>-#include <Library/BaseLib.h>
>-#include <Library/DebugLib.h>
>-#include <Library/PalLib.h>
>-
>-/**
>- Invalidates the entire instruction cache in cache coherency domain of the
>- calling CPU.
>-
>-**/
>-VOID
>-EFIAPI
>-InvalidateInstructionCache (
>- VOID
>- )
>-{
>- PalCall (PAL_CACHE_FLUSH, PAL_CACHE_FLUSH_INSTRUCTION_ALL,
>PAL_CACHE_FLUSH_INVALIDATE_LINES |
>PAL_CACHE_FLUSH_NO_INTERRUPT, 0);
>-}
>-
>-/**
>- Invalidates a range of instruction cache lines in the cache coherency domain
>- of the calling CPU.
>-
>- Invalidates the instruction cache lines specified by Address and Length. If
>- Address is not aligned on a cache line boundary, then entire instruction
>- cache line containing Address is invalidated. If Address + Length is not
>- aligned on a cache line boundary, then the entire instruction cache line
>- containing Address + Length -1 is invalidated. This function may choose to
>- invalidate the entire instruction cache if that is more efficient than
>- invalidating the specified range. If Length is 0, then no instruction cache
>- lines are invalidated. Address is returned.
>-
>- If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
>-
>- @param Address The base address of the instruction cache lines to
>- invalidate. If the CPU is in a physical addressing mode, then
>- Address is a physical address. If the CPU is in a virtual
>- addressing mode, then Address is a virtual address.
>-
>- @param Length The number of bytes to invalidate from the instruction
>cache.
>-
>- @return Address.
>-
>-**/
>-VOID *
>-EFIAPI
>-InvalidateInstructionCacheRange (
>- IN VOID *Address,
>- IN UINTN Length
>- )
>-{
>- return AsmFlushCacheRange (Address, Length);
>-}
>-
>-/**
>- Writes back and invalidates the entire data cache in cache coherency domain
>- of the calling CPU.
>-
>- Writes back and invalidates the entire data cache in cache coherency domain
>- of the calling CPU. This function guarantees that all dirty cache lines are
>- written back to system memory, and also invalidates all the data cache lines
>- in the cache coherency domain of the calling CPU.
>-
>-**/
>-VOID
>-EFIAPI
>-WriteBackInvalidateDataCache (
>- VOID
>- )
>-{
>- PalCall (PAL_CACHE_FLUSH, PAL_CACHE_FLUSH_DATA_ALL,
>PAL_CACHE_FLUSH_INVALIDATE_LINES |
>PAL_CACHE_FLUSH_NO_INTERRUPT, 0);
>-}
>-
>-/**
>- Writes back and invalidates a range of data cache lines in the cache
>- coherency domain of the calling CPU.
>-
>- Writes back and invalidates the data cache lines specified by Address and
>- Length. If Address is not aligned on a cache line boundary, then entire data
>- cache line containing Address is written back and invalidated. If Address +
>- Length is not aligned on a cache line boundary, then the entire data cache
>- line containing Address + Length -1 is written back and invalidated. This
>- function may choose to write back and invalidate the entire data cache if
>- that is more efficient than writing back and invalidating the specified
>- range. If Length is 0, then no data cache lines are written back and
>- invalidated. Address is returned.
>-
>- If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
>-
>- @param Address The base address of the data cache lines to write back and
>- invalidate. If the CPU is in a physical addressing mode, then
>- Address is a physical address. If the CPU is in a virtual
>- addressing mode, then Address is a virtual address.
>- @param Length The number of bytes to write back and invalidate from the
>- data cache.
>-
>- @return Address of cache invalidation.
>-
>-**/
>-VOID *
>-EFIAPI
>-WriteBackInvalidateDataCacheRange (
>- IN VOID *Address,
>- IN UINTN Length
>- )
>-{
>- return AsmFlushCacheRange (Address, Length);
>-}
>-
>-/**
>- Writes Back the entire data cache in cache coherency domain of the calling
>- CPU.
>-
>- Writes Back the entire data cache in cache coherency domain of the calling
>- CPU. This function guarantees that all dirty cache lines are written back to
>- system memory. This function may also invalidate all the data cache lines in
>- the cache coherency domain of the calling CPU.
>-
>-**/
>-VOID
>-EFIAPI
>-WriteBackDataCache (
>- VOID
>- )
>-{
>- PalCall (PAL_CACHE_FLUSH, PAL_CACHE_FLUSH_DATA_ALL,
>PAL_CACHE_FLUSH_NO_INVALIDATE_LINES |
>PAL_CACHE_FLUSH_NO_INTERRUPT, 0);
>-}
>-
>-/**
>- Writes Back a range of data cache lines in the cache coherency domain of
>the
>- calling CPU.
>-
>- Writes Back the data cache lines specified by Address and Length. If Address
>- is not aligned on a cache line boundary, then entire data cache line
>- containing Address is written back. If Address + Length is not aligned on a
>- cache line boundary, then the entire data cache line containing Address +
>- Length -1 is written back. This function may choose to write back the entire
>- data cache if that is more efficient than writing back the specified range.
>- If Length is 0, then no data cache lines are written back. This function may
>- also invalidate all the data cache lines in the specified range of the cache
>- coherency domain of the calling CPU. Address is returned.
>-
>- If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
>-
>- @param Address The base address of the data cache lines to write back. If
>- the CPU is in a physical addressing mode, then Address is a
>- physical address. If the CPU is in a virtual addressing
>- mode, then Address is a virtual address.
>- @param Length The number of bytes to write back from the data cache.
>-
>- @return Address of cache written in main memory.
>-
>-**/
>-VOID *
>-EFIAPI
>-WriteBackDataCacheRange (
>- IN VOID *Address,
>- IN UINTN Length
>- )
>-{
>- return AsmFlushCacheRange (Address, Length);
>-}
>-
>-/**
>- Invalidates the entire data cache in cache coherency domain of the calling
>- CPU.
>-
>- Invalidates the entire data cache in cache coherency domain of the calling
>- CPU. This function must be used with care because dirty cache lines are not
>- written back to system memory. It is typically used for cache diagnostics. If
>- the CPU does not support invalidation of the entire data cache, then a write
>- back and invalidate operation should be performed on the entire data cache.
>-
>-**/
>-VOID
>-EFIAPI
>-InvalidateDataCache (
>- VOID
>- )
>-{
>- //
>- // Invalidation of the entire data cache without writing back is not supported
>- // on IPF architecture, so a write back and invalidate operation is performed.
>- //
>- WriteBackInvalidateDataCache ();
>-}
>-
>-/**
>- Invalidates a range of data cache lines in the cache coherency domain of the
>- calling CPU.
>-
>- Invalidates the data cache lines specified by Address and Length. If Address
>- is not aligned on a cache line boundary, then entire data cache line
>- containing Address is invalidated. If Address + Length is not aligned on a
>- cache line boundary, then the entire data cache line containing Address +
>- Length -1 is invalidated. This function must never invalidate any cache lines
>- outside the specified range. If Length is 0, then no data cache lines are
>- invalidated. Address is returned. This function must be used with care
>- because dirty cache lines are not written back to system memory. It is
>- typically used for cache diagnostics. If the CPU does not support
>- invalidation of a data cache range, then a write back and invalidate
>- operation should be performed on the data cache range.
>-
>- If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
>-
>- @param Address The base address of the data cache lines to invalidate. If
>- the CPU is in a physical addressing mode, then Address is a
>- physical address. If the CPU is in a virtual addressing mode,
>- then Address is a virtual address.
>- @param Length The number of bytes to invalidate from the data cache.
>-
>- @return Address.
>-
>-**/
>-VOID *
>-EFIAPI
>-InvalidateDataCacheRange (
>- IN VOID *Address,
>- IN UINTN Length
>- )
>-{
>- //
>- // Invalidation of a data cache range without writing back is not supported
>on
>- // IPF architecture, so write back and invalidate operation is performed.
>- //
>- return AsmFlushCacheRange (Address, Length);
>-}
>diff --git a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
>b/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
>index 84564e00d7..2622fbeb9f 100644
>--- a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
>+++ b/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
>@@ -29,7 +29,7 @@
>
>
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC ARM AARCH64
>+# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64
> #
>
> [Sources.IA32]
>@@ -51,10 +51,6 @@
> X64/CpuFlushTlb.nasm| GCC
> X64/CpuFlushTlb.S | GCC
>
>-[Sources.IPF]
>- Ipf/CpuFlushTlb.s
>- Ipf/CpuSleep.c
>-
> [Sources.EBC]
> Ebc/CpuSleepFlushTlb.c
>
>@@ -76,7 +72,3 @@
> MdePkg/MdePkg.dec
>
>
>-[LibraryClasses.IPF]
>- PalLib
>- BaseLib
>-
>diff --git a/MdePkg/Library/BaseCpuLib/Ipf/CpuFlushTlb.s
>b/MdePkg/Library/BaseCpuLib/Ipf/CpuFlushTlb.s
>deleted file mode 100644
>index 911f7809a0..0000000000
>--- a/MdePkg/Library/BaseCpuLib/Ipf/CpuFlushTlb.s
>+++ /dev/null
>@@ -1,58 +0,0 @@
>-/// @file
>-/// CpuFlushTlb() function for Itanium-based architecture.
>-///
>-/// Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
>-/// This program and the accompanying materials
>-/// are licensed and made available under the terms and conditions of the
>BSD License
>-/// which accompanies this distribution. The full text of the license may be
>found at
>-/// http://opensource.org/licenses/bsd-license.php.
>-///
>-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-///
>-/// Module Name: CpuFlushTlb.s
>-///
>-///
>-
>-.auto
>-.text
>-
>-ASM_GLOBAL PalCall
>-.type PalCall, @function
>-
>-.proc CpuFlushTlb
>-.type CpuFlushTlb, @function
>-CpuFlushTlb::
>- alloc loc0 = ar.pfs, 0, 3, 5, 0
>- mov out0 = 0
>- mov out1 = 6
>- mov out2 = 0
>- mov out3 = 0
>- mov loc1 = b0
>- mov out4 = 0
>- brl.call.sptk b0 = PalCall
>- mov loc2 = psr // save PSR
>- mov ar.pfs = loc0
>- extr.u r14 = r10, 32, 32 // r14 <- count1
>- rsm 1 << 14 // Disable interrupts
>- extr.u r15 = r11, 32, 32 // r15 <- stride1
>- extr.u r10 = r10, 0, 32 // r10 <- count2
>- add r10 = -1, r10
>- extr.u r11 = r11, 0, 32 // r11 <- stride2
>- br.cond.sptk LoopPredicate
>-LoopOuter:
>- mov ar.lc = r10 // LC <- count2
>- mov ar.ec = r0 // EC <- 0
>-Loop:
>- ptc.e r9
>- add r9 = r11, r9 // r9 += stride2
>- br.ctop.sptk Loop
>- add r9 = r15, r9 // r9 += stride1
>-LoopPredicate:
>- cmp.ne p6 = r0, r14 // count1 == 0?
>- add r14 = -1, r14
>-(p6) br.cond.sptk LoopOuter
>- mov psr.l = loc2
>- mov b0 = loc1
>- br.ret.sptk.many b0
>-.endp
>diff --git a/MdePkg/Library/BaseCpuLib/Ipf/CpuSleep.c
>b/MdePkg/Library/BaseCpuLib/Ipf/CpuSleep.c
>deleted file mode 100644
>index 59c07cac72..0000000000
>--- a/MdePkg/Library/BaseCpuLib/Ipf/CpuSleep.c
>+++ /dev/null
>@@ -1,66 +0,0 @@
>-/** @file
>- Base Library CPU functions for Itanium
>-
>- Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
>- This program and the accompanying materials
>- are licensed and made available under the terms and conditions of the BSD
>License
>- which accompanies this distribution. The full text of the license may be
>found at
>- http://opensource.org/licenses/bsd-license.php.
>-
>- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-
>-**/
>-
>-#include <Library/PalLib.h>
>-#include <Library/BaseLib.h>
>-
>-/**
>- Places the CPU in a sleep state until an interrupt is received.
>-
>- Places the CPU in a sleep state until an interrupt is received. If interrupts
>- are disabled prior to calling this function, then the CPU will be placed in a
>- sleep state indefinitely.
>-
>-**/
>-VOID
>-EFIAPI
>-CpuSleep (
>- VOID
>- )
>-{
>- UINT64 Tpr;
>-
>- //
>- // It is the TPR register that controls if external interrupt would bring
>processor in LIGHT HALT low-power state
>- // back to normal state. PAL_HALT_LIGHT does not depend on PSR setting.
>- // So here if interrupts are disabled (via PSR.i), TRP.mmi needs to be set to
>prevent processor being interrupted by external interrupts.
>- // If interrupts are enabled, then just use current TRP setting.
>- //
>- if (GetInterruptState ()) {
>- //
>- // If interrupts are enabled, then call PAL_HALT_LIGHT with the current TPR
>setting.
>- //
>- PalCall (PAL_HALT_LIGHT, 0, 0, 0);
>- } else {
>- //
>- // If interrupts are disabled on entry, then mask all interrupts in TPR before
>calling PAL_HALT_LIGHT.
>- //
>-
>- //
>- // Save TPR
>- //
>- Tpr = AsmReadTpr();
>- //
>- // Set TPR.mmi to mask all external interrupts
>- //
>- AsmWriteTpr (BIT16 | Tpr);
>-
>- PalCall (PAL_HALT_LIGHT, 0, 0, 0);
>-
>- //
>- // Restore TPR
>- //
>- AsmWriteTpr (Tpr);
>- }
>-}
>diff --git a/MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
>b/MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
>index a203e187cf..bea5fc8a73 100644
>--- a/MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
>+++ b/MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
>@@ -24,7 +24,7 @@
>
>
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
>+# VALID_ARCHITECTURES = IA32 X64 EBC
> #
>
> [Sources]
>diff --git
>a/MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
>b/MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
>index 823511b22f..761c35a8b1 100644
>--- a/MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
>+++ b/MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
>@@ -25,7 +25,7 @@
> CONSTRUCTOR = BaseDebugLibSerialPortConstructor
>
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
>+# VALID_ARCHITECTURES = IA32 X64 EBC
> #
>
> [Sources]
>diff --git
>a/MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLi
>b.inf
>b/MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLi
>b.inf
>index 7f611b0b9b..93020e7101 100644
>---
>a/MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLi
>b.inf
>+++
>b/MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLi
>b.inf
>@@ -23,7 +23,7 @@
> LIBRARY_CLASS = DebugPrintErrorLevelLib
>
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
>+# VALID_ARCHITECTURES = IA32 X64 EBC
> #
>
> [Sources]
>diff --git
>a/MdePkg/Library/BaseExtractGuidedSectionLib/BaseExtractGuidedSectionLi
>b.inf
>b/MdePkg/Library/BaseExtractGuidedSectionLib/BaseExtractGuidedSectionLi
>b.inf
>index f211b77a95..959785e3cd 100644
>---
>a/MdePkg/Library/BaseExtractGuidedSectionLib/BaseExtractGuidedSectionLi
>b.inf
>+++
>b/MdePkg/Library/BaseExtractGuidedSectionLib/BaseExtractGuidedSectionLi
>b.inf
>@@ -34,7 +34,7 @@
> #
> # The following information is for reference only and not required by the
>build tools.
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC (EBC is for build only)
>+# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only)
> #
>
> [Sources]
>diff --git a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
>b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
>index 6c4d7ccfb7..64844e4c7c 100644
>--- a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
>+++ b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
>@@ -30,7 +30,7 @@
>
>
> #
>-# VALID_ARCHITECTURES = IA32 X64 EBC IPF ARM AARCH64
>+# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64
> #
>
> [Sources]
>@@ -56,9 +56,6 @@
> IoLibEbc.c
> IoLib.c
>
>-[Sources.IPF]
>- IoLibIpf.c
>-
> [Sources.ARM]
> IoLibArm.c
>
>@@ -72,9 +69,3 @@
> DebugLib
> BaseLib
>
>-[LibraryClasses.IPF]
>- PcdLib
>-
>-[Pcd.IPF]
>- gEfiMdePkgTokenSpaceGuid.PcdIoBlockBaseAddressForIpf ##
>SOMETIMES_CONSUMES
>-
>diff --git a/MdePkg/Library/BaseIoLibIntrinsic/IoLibIpf.c
>b/MdePkg/Library/BaseIoLibIntrinsic/IoLibIpf.c
>deleted file mode 100644
>index b84134b757..0000000000
>--- a/MdePkg/Library/BaseIoLibIntrinsic/IoLibIpf.c
>+++ /dev/null
>@@ -1,736 +0,0 @@
>-/** @file
>- Common I/O Library routines.
>-
>- Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
>- Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
>-
>- This program and the accompanying materials
>- are licensed and made available under the terms and conditions of the BSD
>License
>- which accompanies this distribution. The full text of the license may be
>found at
>- http://opensource.org/licenses/bsd-license.php.
>-
>- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-
>-**/
>-
>-
>-#include "BaseIoLibIntrinsicInternal.h"
>-#include <Library/PcdLib.h>
>-
>-#define MAP_PORT_BASE_TO_MEM(_Port) \
>- ((((_Port) & 0xfffc) << 10) | ((_Port) & 0x0fff))
>-
>-/**
>- Translates I/O port address to memory address.
>-
>- This function translates I/O port address to memory address by adding the
>64MB
>- aligned I/O Port space to the I/O address.
>- If I/O Port space base is not 64MB aligned, then ASSERT ().
>-
>- @param Port The I/O port to read.
>-
>- @return The memory address.
>-
>-**/
>-UINTN
>-InternalGetMemoryMapAddress (
>- IN UINTN Port
>- )
>-{
>- UINTN Address;
>- UINTN IoBlockBaseAddress;
>-
>- Address = MAP_PORT_BASE_TO_MEM (Port);
>- IoBlockBaseAddress = PcdGet64(PcdIoBlockBaseAddressForIpf);
>-
>- //
>- // Make sure that the I/O Port space base is 64MB aligned.
>- //
>- ASSERT ((IoBlockBaseAddress & 0x3ffffff) == 0);
>- Address += IoBlockBaseAddress;
>-
>- return Address;
>-}
>-
>-/**
>- Reads an 8-bit I/O port.
>-
>- Reads the 8-bit I/O port specified by Port. The 8-bit read value is returned.
>- This function must guarantee that all I/O read and write operations are
>- serialized.
>-
>- If 8-bit I/O port operations are not supported, then ASSERT().
>-
>- @param Port The I/O port to read.
>-
>- @return The value read.
>-
>-**/
>-UINT8
>-EFIAPI
>-IoRead8 (
>- IN UINTN Port
>- )
>-{
>- return MmioRead8 (InternalGetMemoryMapAddress (Port));
>-}
>-
>-/**
>- Reads a 16-bit I/O port.
>-
>- Reads the 16-bit I/O port specified by Port. The 16-bit read value is returned.
>- This function must guarantee that all I/O read and write operations are
>- serialized.
>-
>- If 16-bit I/O port operations are not supported, then ASSERT().
>- If Port is not aligned on a 16-bit boundary, then ASSERT().
>-
>- @param Port The I/O port to read.
>-
>- @return The value read.
>-
>-**/
>-UINT16
>-EFIAPI
>-IoRead16 (
>- IN UINTN Port
>- )
>-{
>- return MmioRead16 (InternalGetMemoryMapAddress (Port));
>-}
>-
>-/**
>- Reads a 32-bit I/O port.
>-
>- Reads the 32-bit I/O port specified by Port. The 32-bit read value is returned.
>- This function must guarantee that all I/O read and write operations are
>- serialized.
>-
>- If 32-bit I/O port operations are not supported, then ASSERT().
>- If Port is not aligned on a 32-bit boundary, then ASSERT().
>-
>- @param Port The I/O port to read.
>-
>- @return The value read.
>-
>-**/
>-UINT32
>-EFIAPI
>-IoRead32 (
>- IN UINTN Port
>- )
>-{
>- return MmioRead32 (InternalGetMemoryMapAddress (Port));
>-}
>-
>-/**
>- Reads a 64-bit I/O port.
>-
>- Reads the 64-bit I/O port specified by Port. The 64-bit read value is returned.
>- This function must guarantee that all I/O read and write operations are
>- serialized.
>-
>- If 64-bit I/O port operations are not supported, then ASSERT().
>- If Port is not aligned on a 64-bit boundary, then ASSERT().
>-
>- @param Port The I/O port to read.
>-
>- @return The value read.
>-
>-**/
>-UINT64
>-EFIAPI
>-IoRead64 (
>- IN UINTN Port
>- )
>-{
>- ASSERT (FALSE);
>- return 0;
>-}
>-
>-
>-/**
>- Writes an 8-bit I/O port.
>-
>- Writes the 8-bit I/O port specified by Port with the value specified by Value
>- and returns Value. This function must guarantee that all I/O read and write
>- operations are serialized.
>-
>- If 8-bit I/O port operations are not supported, then ASSERT().
>-
>- @param Port The I/O port to write.
>- @param Value The value to write to the I/O port.
>-
>- @return The value written the I/O port.
>-
>-**/
>-UINT8
>-EFIAPI
>-IoWrite8 (
>- IN UINTN Port,
>- IN UINT8 Value
>- )
>-{
>- return MmioWrite8 (InternalGetMemoryMapAddress (Port), Value);
>-}
>-
>-/**
>- Writes a 16-bit I/O port.
>-
>- Writes the 16-bit I/O port specified by Port with the value specified by Value
>- and returns Value. This function must guarantee that all I/O read and write
>- operations are serialized.
>-
>- If 16-bit I/O port operations are not supported, then ASSERT().
>- If Port is not aligned on a 16-bit boundary, then ASSERT().
>-
>- @param Port The I/O port to write.
>- @param Value The value to write to the I/O port.
>-
>- @return The value written the I/O port.
>-
>-**/
>-UINT16
>-EFIAPI
>-IoWrite16 (
>- IN UINTN Port,
>- IN UINT16 Value
>- )
>-{
>- return MmioWrite16 (InternalGetMemoryMapAddress (Port), Value);
>-}
>-
>-/**
>- Writes a 32-bit I/O port.
>-
>- Writes the 32-bit I/O port specified by Port with the value specified by Value
>- and returns Value. This function must guarantee that all I/O read and write
>- operations are serialized.
>-
>- If 32-bit I/O port operations are not supported, then ASSERT().
>- If Port is not aligned on a 32-bit boundary, then ASSERT().
>-
>- @param Port The I/O port to write.
>- @param Value The value to write to the I/O port.
>-
>- @return The value written the I/O port.
>-
>-**/
>-UINT32
>-EFIAPI
>-IoWrite32 (
>- IN UINTN Port,
>- IN UINT32 Value
>- )
>-{
>- return MmioWrite32 (InternalGetMemoryMapAddress (Port), Value);
>-}
>-
>-/**
>- Writes a 64-bit I/O port.
>-
>- Writes the 64-bit I/O port specified by Port with the value specified by Value
>- and returns Value. This function must guarantee that all I/O read and write
>- operations are serialized.
>-
>- If 64-bit I/O port operations are not supported, then ASSERT().
>- If Port is not aligned on a 64-bit boundary, then ASSERT().
>-
>- @param Port The I/O port to write.
>- @param Value The value to write to the I/O port.
>-
>- @return The value written the I/O port.
>-
>-**/
>-UINT64
>-EFIAPI
>-IoWrite64 (
>- IN UINTN Port,
>- IN UINT64 Value
>- )
>-{
>- ASSERT (FALSE);
>- return 0;
>-}
>-
>-/**
>- Reads an 8-bit I/O port fifo into a block of memory.
>-
>- Reads the 8-bit I/O fifo port specified by Port.
>- The port is read Count times, and the read data is
>- stored in the provided Buffer.
>-
>- This function must guarantee that all I/O read and write operations are
>- serialized.
>-
>- If 8-bit I/O port operations are not supported, then ASSERT().
>-
>- @param Port The I/O port to read.
>- @param Count The number of times to read I/O port.
>- @param Buffer The buffer to store the read data into.
>-
>-**/
>-VOID
>-EFIAPI
>-IoReadFifo8 (
>- IN UINTN Port,
>- IN UINTN Count,
>- OUT VOID *Buffer
>- )
>-{
>- UINT8 *Buffer8;
>-
>- Buffer8 = (UINT8 *)Buffer;
>- while (Count-- > 0) {
>- *Buffer8++ = IoRead8 (Port);
>- }
>-}
>-
>-/**
>- Reads a 16-bit I/O port fifo into a block of memory.
>-
>- Reads the 16-bit I/O fifo port specified by Port.
>- The port is read Count times, and the read data is
>- stored in the provided Buffer.
>-
>- This function must guarantee that all I/O read and write operations are
>- serialized.
>-
>- If 16-bit I/O port operations are not supported, then ASSERT().
>-
>- @param Port The I/O port to read.
>- @param Count The number of times to read I/O port.
>- @param Buffer The buffer to store the read data into.
>-
>-**/
>-VOID
>-EFIAPI
>-IoReadFifo16 (
>- IN UINTN Port,
>- IN UINTN Count,
>- OUT VOID *Buffer
>- )
>-{
>- UINT16 *Buffer16;
>-
>- Buffer16 = (UINT16 *)Buffer;
>- while (Count-- > 0) {
>- *Buffer16++ = IoRead16 (Port);
>- }
>-}
>-
>-/**
>- Reads a 32-bit I/O port fifo into a block of memory.
>-
>- Reads the 32-bit I/O fifo port specified by Port.
>- The port is read Count times, and the read data is
>- stored in the provided Buffer.
>-
>- This function must guarantee that all I/O read and write operations are
>- serialized.
>-
>- If 32-bit I/O port operations are not supported, then ASSERT().
>-
>- @param Port The I/O port to read.
>- @param Count The number of times to read I/O port.
>- @param Buffer The buffer to store the read data into.
>-
>-**/
>-VOID
>-EFIAPI
>-IoReadFifo32 (
>- IN UINTN Port,
>- IN UINTN Count,
>- OUT VOID *Buffer
>- )
>-{
>- UINT32 *Buffer32;
>-
>- Buffer32 = (UINT32 *)Buffer;
>- while (Count-- > 0) {
>- *Buffer32++ = IoRead32 (Port);
>- }
>-}
>-
>-/**
>- Writes a block of memory into an 8-bit I/O port fifo.
>-
>- Writes the 8-bit I/O fifo port specified by Port.
>- The port is written Count times, and the write data is
>- retrieved from the provided Buffer.
>-
>- This function must guarantee that all I/O write and write operations are
>- serialized.
>-
>- If 8-bit I/O port operations are not supported, then ASSERT().
>-
>- @param Port The I/O port to write.
>- @param Count The number of times to write I/O port.
>- @param Buffer The buffer to retrieve the write data from.
>-
>-**/
>-VOID
>-EFIAPI
>-IoWriteFifo8 (
>- IN UINTN Port,
>- IN UINTN Count,
>- IN VOID *Buffer
>- )
>-{
>- UINT8 *Buffer8;
>-
>- Buffer8 = (UINT8 *)Buffer;
>- while (Count-- > 0) {
>- IoWrite8 (Port, *Buffer8++);
>- }
>-}
>-
>-/**
>- Writes a block of memory into a 16-bit I/O port fifo.
>-
>- Writes the 16-bit I/O fifo port specified by Port.
>- The port is written Count times, and the write data is
>- retrieved from the provided Buffer.
>-
>- This function must guarantee that all I/O write and write operations are
>- serialized.
>-
>- If 16-bit I/O port operations are not supported, then ASSERT().
>-
>- @param Port The I/O port to write.
>- @param Count The number of times to write I/O port.
>- @param Buffer The buffer to retrieve the write data from.
>-
>-**/
>-VOID
>-EFIAPI
>-IoWriteFifo16 (
>- IN UINTN Port,
>- IN UINTN Count,
>- IN VOID *Buffer
>- )
>-{
>- UINT16 *Buffer16;
>-
>- Buffer16 = (UINT16 *)Buffer;
>- while (Count-- > 0) {
>- IoWrite16 (Port, *Buffer16++);
>- }
>-}
>-
>-/**
>- Writes a block of memory into a 32-bit I/O port fifo.
>-
>- Writes the 32-bit I/O fifo port specified by Port.
>- The port is written Count times, and the write data is
>- retrieved from the provided Buffer.
>-
>- This function must guarantee that all I/O write and write operations are
>- serialized.
>-
>- If 32-bit I/O port operations are not supported, then ASSERT().
>-
>- @param Port The I/O port to write.
>- @param Count The number of times to write I/O port.
>- @param Buffer The buffer to retrieve the write data from.
>-
>-**/
>-VOID
>-EFIAPI
>-IoWriteFifo32 (
>- IN UINTN Port,
>- IN UINTN Count,
>- IN VOID *Buffer
>- )
>-{
>- UINT32 *Buffer32;
>-
>- Buffer32 = (UINT32 *)Buffer;
>- while (Count-- > 0) {
>- IoWrite32 (Port, *Buffer32++);
>- }
>-}
>-
>-/**
>- Reads an 8-bit MMIO register.
>-
>- Reads the 8-bit MMIO register specified by Address. The 8-bit read value is
>- returned. This function must guarantee that all MMIO read and write
>- operations are serialized.
>-
>- If 8-bit MMIO register operations are not supported, then ASSERT().
>-
>- @param Address The MMIO register to read.
>-
>- @return The value read.
>-
>-**/
>-UINT8
>-EFIAPI
>-MmioRead8 (
>- IN UINTN Address
>- )
>-{
>- UINT8 Data;
>-
>- Address |= BIT63;
>-
>- MemoryFence ();
>- Data = *((volatile UINT8 *) Address);
>- MemoryFence ();
>-
>- return Data;
>-}
>-
>-/**
>- Reads a 16-bit MMIO register.
>-
>- Reads the 16-bit MMIO register specified by Address. The 16-bit read value
>is
>- returned. This function must guarantee that all MMIO read and write
>- operations are serialized.
>-
>- If 16-bit MMIO register operations are not supported, then ASSERT().
>- If Address is not aligned on a 16-bit boundary, then ASSERT().
>-
>- @param Address The MMIO register to read.
>-
>- @return The value read.
>-
>-**/
>-UINT16
>-EFIAPI
>-MmioRead16 (
>- IN UINTN Address
>- )
>-{
>- UINT16 Data;
>-
>- //
>- // Make sure that Address is 16-bit aligned.
>- //
>- ASSERT ((Address & 1) == 0);
>-
>- Address |= BIT63;
>-
>- MemoryFence ();
>- Data = *((volatile UINT16 *) Address);
>- MemoryFence ();
>-
>- return Data;
>-}
>-
>-/**
>- Reads a 32-bit MMIO register.
>-
>- Reads the 32-bit MMIO register specified by Address. The 32-bit read value
>is
>- returned. This function must guarantee that all MMIO read and write
>- operations are serialized.
>-
>- If 32-bit MMIO register operations are not supported, then ASSERT().
>- If Address is not aligned on a 32-bit boundary, then ASSERT().
>-
>- @param Address The MMIO register to read.
>-
>- @return The value read.
>-
>-**/
>-UINT32
>-EFIAPI
>-MmioRead32 (
>- IN UINTN Address
>- )
>-{
>- UINT32 Data;
>-
>- //
>- // Make sure that Address is 32-bit aligned.
>- //
>- ASSERT ((Address & 3) == 0);
>-
>- Address |= BIT63;
>-
>- MemoryFence ();
>- Data = *((volatile UINT32 *) Address);
>- MemoryFence ();
>-
>- return Data;
>-}
>-
>-/**
>- Reads a 64-bit MMIO register.
>-
>- Reads the 64-bit MMIO register specified by Address. The 64-bit read value
>is
>- returned. This function must guarantee that all MMIO read and write
>- operations are serialized.
>-
>- If 64-bit MMIO register operations are not supported, then ASSERT().
>- If Address is not aligned on a 64-bit boundary, then ASSERT().
>-
>- @param Address The MMIO register to read.
>-
>- @return The value read.
>-
>-**/
>-UINT64
>-EFIAPI
>-MmioRead64 (
>- IN UINTN Address
>- )
>-{
>- UINT64 Data;
>-
>- //
>- // Make sure that Address is 64-bit aligned.
>- //
>- ASSERT ((Address & 7) == 0);
>-
>- Address |= BIT63;
>-
>- MemoryFence ();
>- Data = *((volatile UINT64 *) Address);
>- MemoryFence ();
>-
>- return Data;
>-
>-}
>-
>-/**
>- Writes an 8-bit MMIO register.
>-
>- Writes the 8-bit MMIO register specified by Address with the value specified
>- by Value and returns Value. This function must guarantee that all MMIO
>read
>- and write operations are serialized.
>-
>- If 8-bit MMIO register operations are not supported, then ASSERT().
>-
>- @param Address The MMIO register to write.
>- @param Value The value to write to the MMIO register.
>-
>- @return Value.
>-
>-**/
>-UINT8
>-EFIAPI
>-MmioWrite8 (
>- IN UINTN Address,
>- IN UINT8 Value
>- )
>-{
>- Address |= BIT63;
>-
>- MemoryFence ();
>- *((volatile UINT8 *) Address) = Value;
>- MemoryFence ();
>-
>- return Value;
>-}
>-
>-/**
>- Writes a 16-bit MMIO register.
>-
>- Writes the 16-bit MMIO register specified by Address with the value
>specified
>- by Value and returns Value. This function must guarantee that all MMIO
>read
>- and write operations are serialized.
>-
>- If 16-bit MMIO register operations are not supported, then ASSERT().
>- If Address is not aligned on a 16-bit boundary, then ASSERT().
>-
>- @param Address The MMIO register to write.
>- @param Value The value to write to the MMIO register.
>-
>- @return Value.
>-
>-**/
>-UINT16
>-EFIAPI
>-MmioWrite16 (
>- IN UINTN Address,
>- IN UINT16 Value
>- )
>-{
>- //
>- // Make sure that Address is 16-bit aligned.
>- //
>- ASSERT ((Address & 1) == 0);
>-
>- Address |= BIT63;
>-
>- MemoryFence ();
>- *((volatile UINT16 *) Address) = Value;
>- MemoryFence ();
>-
>- return Value;
>-}
>-
>-/**
>- Writes a 32-bit MMIO register.
>-
>- Writes the 32-bit MMIO register specified by Address with the value
>specified
>- by Value and returns Value. This function must guarantee that all MMIO
>read
>- and write operations are serialized.
>-
>- If 32-bit MMIO register operations are not supported, then ASSERT().
>- If Address is not aligned on a 32-bit boundary, then ASSERT().
>-
>- @param Address The MMIO register to write.
>- @param Value The value to write to the MMIO register.
>-
>- @return Value.
>-
>-**/
>-UINT32
>-EFIAPI
>-MmioWrite32 (
>- IN UINTN Address,
>- IN UINT32 Value
>- )
>-{
>- //
>- // Make sure that Address is 32-bit aligned.
>- //
>- ASSERT ((Address & 3) == 0);
>-
>- Address |= BIT63;
>-
>- MemoryFence ();
>- *((volatile UINT32 *) Address) = Value;
>- MemoryFence ();
>-
>- return Value;
>-}
>-
>-/**
>- Writes a 64-bit MMIO register.
>-
>- Writes the 64-bit MMIO register specified by Address with the value
>specified
>- by Value and returns Value. This function must guarantee that all MMIO
>read
>- and write operations are serialized.
>-
>- If 64-bit MMIO register operations are not supported, then ASSERT().
>- If Address is not aligned on a 64-bit boundary, then ASSERT().
>-
>- @param Address The MMIO register to write.
>- @param Value The value to write to the MMIO register.
>-
>-**/
>-UINT64
>-EFIAPI
>-MmioWrite64 (
>- IN UINTN Address,
>- IN UINT64 Value
>- )
>-{
>- //
>- // Make sure that Address is 64-bit aligned.
>- //
>- ASSERT ((Address & 7) == 0);
>-
>- Address |= BIT63;
>-
>- MemoryFence ();
>- *((volatile UINT64 *) Address) = Value;
>- MemoryFence ();
>-
>- return Value;
>-}
>diff --git a/MdePkg/Library/BaseLib/BaseLib.inf
>b/MdePkg/Library/BaseLib/BaseLib.inf
>index 12e883cbb8..e84470e10f 100644
>--- a/MdePkg/Library/BaseLib/BaseLib.inf
>+++ b/MdePkg/Library/BaseLib/BaseLib.inf
>@@ -25,7 +25,7 @@
> LIBRARY_CLASS = BaseLib
>
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC ARM AARCH64
>+# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64
> #
>
> [Sources]
>@@ -537,39 +537,6 @@
> X64/RdRand.S | GCC
> ChkStkGcc.c | GCC
>
>-[Sources.IPF]
>- Ipf/AccessGp.s
>- Ipf/ReadCpuid.s
>- Ipf/ExecFc.s
>- Ipf/AsmPalCall.s
>- Ipf/AccessPsr.s
>- Ipf/AccessPmr.s
>- Ipf/AccessKr.s
>- Ipf/AccessKr7.s
>- Ipf/AccessGcr.s
>- Ipf/AccessEicr.s
>- Ipf/AccessDbr.s
>- Ipf/AccessMsr.s | INTEL
>- Ipf/AccessMsr.s | GCC
>- Ipf/AccessMsrDb.s | MSFT
>- Ipf/InternalFlushCacheRange.s
>- Ipf/FlushCacheRange.c
>- Ipf/InternalSwitchStack.c
>- Ipf/GetInterruptState.s
>- Ipf/CpuPause.s
>- Ipf/CpuBreakpoint.c | INTEL
>- Ipf/CpuBreakpointMsc.c | MSFT
>- Ipf/AsmCpuMisc.s | GCC
>- Ipf/Unaligned.c
>- Ipf/SwitchStack.s
>- Ipf/LongJmp.s
>- Ipf/SetJmp.s
>- Ipf/ReadCr.s
>- Ipf/ReadAr.s
>- Ipf/Ia64gen.h
>- Ipf/Asm.h
>- Math64.c
>-
> [Sources.EBC]
> Ebc/CpuBreakpoint.c
> Ebc/SetJumpLongJump.c
>diff --git a/MdePkg/Library/BaseLib/BaseLibInternals.h
>b/MdePkg/Library/BaseLib/BaseLibInternals.h
>index 9dca97a0dc..e8ebd03834 100644
>--- a/MdePkg/Library/BaseLib/BaseLibInternals.h
>+++ b/MdePkg/Library/BaseLib/BaseLibInternals.h
>@@ -910,926 +910,6 @@ InternalX86RdRand64 (
> OUT UINT64 *Rand
> );
>
>-
>-#elif defined (MDE_CPU_IPF)
>-//
>-//
>-// IPF specific functions
>-//
>-
>-/**
>- Reads control register DCR.
>-
>- This is a worker function for AsmReadControlRegister()
>- when its parameter Index is IPF_CONTROL_REGISTER_DCR.
>-
>- @return The 64-bit control register DCR.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadControlRegisterDcr (
>- VOID
>- );
>-
>-
>-/**
>- Reads control register ITM.
>-
>- This is a worker function for AsmReadControlRegister()
>- when its parameter Index is IPF_CONTROL_REGISTER_ITM.
>-
>- @return The 64-bit control register ITM.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadControlRegisterItm (
>- VOID
>- );
>-
>-
>-/**
>- Reads control register IVA.
>-
>- This is a worker function for AsmReadControlRegister()
>- when its parameter Index is IPF_CONTROL_REGISTER_IVA.
>-
>- @return The 64-bit control register IVA.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadControlRegisterIva (
>- VOID
>- );
>-
>-
>-/**
>- Reads control register PTA.
>-
>- This is a worker function for AsmReadControlRegister()
>- when its parameter Index is IPF_CONTROL_REGISTER_PTA.
>-
>- @return The 64-bit control register PTA.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadControlRegisterPta (
>- VOID
>- );
>-
>-
>-/**
>- Reads control register IPSR.
>-
>- This is a worker function for AsmReadControlRegister()
>- when its parameter Index is IPF_CONTROL_REGISTER_IPSR.
>-
>- @return The 64-bit control register IPSR.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadControlRegisterIpsr (
>- VOID
>- );
>-
>-
>-/**
>- Reads control register ISR.
>-
>- This is a worker function for AsmReadControlRegister()
>- when its parameter Index is IPF_CONTROL_REGISTER_ISR.
>-
>- @return The 64-bit control register ISR.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadControlRegisterIsr (
>- VOID
>- );
>-
>-
>-/**
>- Reads control register IIP.
>-
>- This is a worker function for AsmReadControlRegister()
>- when its parameter Index is IPF_CONTROL_REGISTER_IIP.
>-
>- @return The 64-bit control register IIP.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadControlRegisterIip (
>- VOID
>- );
>-
>-
>-/**
>- Reads control register IFA.
>-
>- This is a worker function for AsmReadControlRegister()
>- when its parameter Index is IPF_CONTROL_REGISTER_IFA.
>-
>- @return The 64-bit control register IFA.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadControlRegisterIfa (
>- VOID
>- );
>-
>-
>-/**
>- Reads control register ITIR.
>-
>- This is a worker function for AsmReadControlRegister()
>- when its parameter Index is IPF_CONTROL_REGISTER_ITIR.
>-
>- @return The 64-bit control register ITIR.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadControlRegisterItir (
>- VOID
>- );
>-
>-
>-/**
>- Reads control register IIPA.
>-
>- This is a worker function for AsmReadControlRegister()
>- when its parameter Index is IPF_CONTROL_REGISTER_IIPA.
>-
>- @return The 64-bit control register IIPA.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadControlRegisterIipa (
>- VOID
>- );
>-
>-
>-/**
>- Reads control register IFS.
>-
>- This is a worker function for AsmReadControlRegister()
>- when its parameter Index is IPF_CONTROL_REGISTER_IFS.
>-
>- @return The 64-bit control register IFS.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadControlRegisterIfs (
>- VOID
>- );
>-
>-
>-/**
>- Reads control register IIM.
>-
>- This is a worker function for AsmReadControlRegister()
>- when its parameter Index is IPF_CONTROL_REGISTER_IIM.
>-
>- @return The 64-bit control register IIM.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadControlRegisterIim (
>- VOID
>- );
>-
>-
>-/**
>- Reads control register IHA.
>-
>- This is a worker function for AsmReadControlRegister()
>- when its parameter Index is IPF_CONTROL_REGISTER_IHA.
>-
>- @return The 64-bit control register IHA.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadControlRegisterIha (
>- VOID
>- );
>-
>-
>-/**
>- Reads control register LID.
>-
>- This is a worker function for AsmReadControlRegister()
>- when its parameter Index is IPF_CONTROL_REGISTER_LID.
>-
>- @return The 64-bit control register LID.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadControlRegisterLid (
>- VOID
>- );
>-
>-
>-/**
>- Reads control register IVR.
>-
>- This is a worker function for AsmReadControlRegister()
>- when its parameter Index is IPF_CONTROL_REGISTER_IVR.
>-
>- @return The 64-bit control register IVR.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadControlRegisterIvr (
>- VOID
>- );
>-
>-
>-/**
>- Reads control register TPR.
>-
>- This is a worker function for AsmReadControlRegister()
>- when its parameter Index is IPF_CONTROL_REGISTER_TPR.
>-
>- @return The 64-bit control register TPR.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadControlRegisterTpr (
>- VOID
>- );
>-
>-
>-/**
>- Reads control register EOI.
>-
>- This is a worker function for AsmReadControlRegister()
>- when its parameter Index is IPF_CONTROL_REGISTER_EOI.
>-
>- @return The 64-bit control register EOI.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadControlRegisterEoi (
>- VOID
>- );
>-
>-
>-/**
>- Reads control register IRR0.
>-
>- This is a worker function for AsmReadControlRegister()
>- when its parameter Index is IPF_CONTROL_REGISTER_IRR0.
>-
>- @return The 64-bit control register IRR0.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadControlRegisterIrr0 (
>- VOID
>- );
>-
>-
>-/**
>- Reads control register IRR1.
>-
>- This is a worker function for AsmReadControlRegister()
>- when its parameter Index is IPF_CONTROL_REGISTER_IRR1.
>-
>- @return The 64-bit control register IRR1.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadControlRegisterIrr1 (
>- VOID
>- );
>-
>-
>-/**
>- Reads control register IRR2.
>-
>- This is a worker function for AsmReadControlRegister()
>- when its parameter Index is IPF_CONTROL_REGISTER_IRR2.
>-
>- @return The 64-bit control register IRR2.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadControlRegisterIrr2 (
>- VOID
>- );
>-
>-
>-/**
>- Reads control register IRR3.
>-
>- This is a worker function for AsmReadControlRegister()
>- when its parameter Index is IPF_CONTROL_REGISTER_IRR3.
>-
>- @return The 64-bit control register IRR3.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadControlRegisterIrr3 (
>- VOID
>- );
>-
>-
>-/**
>- Reads control register ITV.
>-
>- This is a worker function for AsmReadControlRegister()
>- when its parameter Index is IPF_CONTROL_REGISTER_ITV.
>-
>- @return The 64-bit control register ITV.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadControlRegisterItv (
>- VOID
>- );
>-
>-
>-/**
>- Reads control register PMV.
>-
>- This is a worker function for AsmReadControlRegister()
>- when its parameter Index is IPF_CONTROL_REGISTER_PMV.
>-
>- @return The 64-bit control register PMV.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadControlRegisterPmv (
>- VOID
>- );
>-
>-
>-/**
>- Reads control register CMCV.
>-
>- This is a worker function for AsmReadControlRegister()
>- when its parameter Index is IPF_CONTROL_REGISTER_CMCV.
>-
>- @return The 64-bit control register CMCV.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadControlRegisterCmcv (
>- VOID
>- );
>-
>-
>-/**
>- Reads control register LRR0.
>-
>- This is a worker function for AsmReadControlRegister()
>- when its parameter Index is IPF_CONTROL_REGISTER_LRR0.
>-
>- @return The 64-bit control register LRR0.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadControlRegisterLrr0 (
>- VOID
>- );
>-
>-
>-/**
>- Reads control register LRR1.
>-
>- This is a worker function for AsmReadControlRegister()
>- when its parameter Index is IPF_CONTROL_REGISTER_LRR1.
>-
>- @return The 64-bit control register LRR1.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadControlRegisterLrr1 (
>- VOID
>- );
>-
>-
>-/**
>- Reads application register K0.
>-
>- This is a worker function for AsmReadApplicationRegister()
>- when its parameter Index is IPF_APPLICATION_REGISTER_K0.
>-
>- @return The 64-bit application register K0.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadApplicationRegisterK0 (
>- VOID
>- );
>-
>-
>-
>-/**
>- Reads application register K1.
>-
>- This is a worker function for AsmReadApplicationRegister()
>- when its parameter Index is IPF_APPLICATION_REGISTER_K1.
>-
>- @return The 64-bit application register K1.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadApplicationRegisterK1 (
>- VOID
>- );
>-
>-
>-/**
>- Reads application register K2.
>-
>- This is a worker function for AsmReadApplicationRegister()
>- when its parameter Index is IPF_APPLICATION_REGISTER_K2.
>-
>- @return The 64-bit application register K2.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadApplicationRegisterK2 (
>- VOID
>- );
>-
>-
>-/**
>- Reads application register K3.
>-
>- This is a worker function for AsmReadApplicationRegister()
>- when its parameter Index is IPF_APPLICATION_REGISTER_K3.
>-
>- @return The 64-bit application register K3.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadApplicationRegisterK3 (
>- VOID
>- );
>-
>-
>-/**
>- Reads application register K4.
>-
>- This is a worker function for AsmReadApplicationRegister()
>- when its parameter Index is IPF_APPLICATION_REGISTER_K4.
>-
>- @return The 64-bit application register K4.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadApplicationRegisterK4 (
>- VOID
>- );
>-
>-
>-/**
>- Reads application register K5.
>-
>- This is a worker function for AsmReadApplicationRegister()
>- when its parameter Index is IPF_APPLICATION_REGISTER_K5.
>-
>- @return The 64-bit application register K5.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadApplicationRegisterK5 (
>- VOID
>- );
>-
>-
>-/**
>- Reads application register K6.
>-
>- This is a worker function for AsmReadApplicationRegister()
>- when its parameter Index is IPF_APPLICATION_REGISTER_K6.
>-
>- @return The 64-bit application register K6.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadApplicationRegisterK6 (
>- VOID
>- );
>-
>-
>-/**
>- Reads application register K7.
>-
>- This is a worker function for AsmReadApplicationRegister()
>- when its parameter Index is IPF_APPLICATION_REGISTER_K7.
>-
>- @return The 64-bit application register K7.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadApplicationRegisterK7 (
>- VOID
>- );
>-
>-
>-/**
>- Reads application register RSC.
>-
>- This is a worker function for AsmReadApplicationRegister()
>- when its parameter Index is IPF_APPLICATION_REGISTER_RSC.
>-
>- @return The 64-bit application register RSC.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadApplicationRegisterRsc (
>- VOID
>- );
>-
>-
>-/**
>- Reads application register BSP.
>-
>- This is a worker function for AsmReadApplicationRegister()
>- when its parameter Index is IPF_APPLICATION_REGISTER_BSP.
>-
>- @return The 64-bit application register BSP.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadApplicationRegisterBsp (
>- VOID
>- );
>-
>-
>-/**
>- Reads application register BSPSTORE.
>-
>- This is a worker function for AsmReadApplicationRegister()
>- when its parameter Index is IPF_APPLICATION_REGISTER_BSPSTORE.
>-
>- @return The 64-bit application register BSPSTORE.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadApplicationRegisterBspstore (
>- VOID
>- );
>-
>-
>-/**
>- Reads application register RNAT.
>-
>- This is a worker function for AsmReadApplicationRegister()
>- when its parameter Index is IPF_APPLICATION_REGISTER_RNAT.
>-
>- @return The 64-bit application register RNAT.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadApplicationRegisterRnat (
>- VOID
>- );
>-
>-
>-/**
>- Reads application register FCR.
>-
>- This is a worker function for AsmReadApplicationRegister()
>- when its parameter Index is IPF_APPLICATION_REGISTER_FCR.
>-
>- @return The 64-bit application register FCR.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadApplicationRegisterFcr (
>- VOID
>- );
>-
>-
>-/**
>- Reads application register EFLAG.
>-
>- This is a worker function for AsmReadApplicationRegister()
>- when its parameter Index is IPF_APPLICATION_REGISTER_EFLAG.
>-
>- @return The 64-bit application register EFLAG.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadApplicationRegisterEflag (
>- VOID
>- );
>-
>-
>-/**
>- Reads application register CSD.
>-
>- This is a worker function for AsmReadApplicationRegister()
>- when its parameter Index is IPF_APPLICATION_REGISTER_CSD.
>-
>- @return The 64-bit application register CSD.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadApplicationRegisterCsd (
>- VOID
>- );
>-
>-
>-/**
>- Reads application register SSD.
>-
>- This is a worker function for AsmReadApplicationRegister()
>- when its parameter Index is IPF_APPLICATION_REGISTER_SSD.
>-
>- @return The 64-bit application register SSD.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadApplicationRegisterSsd (
>- VOID
>- );
>-
>-
>-/**
>- Reads application register CFLG.
>-
>- This is a worker function for AsmReadApplicationRegister()
>- when its parameter Index is IPF_APPLICATION_REGISTER_CFLG.
>-
>- @return The 64-bit application register CFLG.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadApplicationRegisterCflg (
>- VOID
>- );
>-
>-
>-/**
>- Reads application register FSR.
>-
>- This is a worker function for AsmReadApplicationRegister()
>- when its parameter Index is IPF_APPLICATION_REGISTER_FSR.
>-
>- @return The 64-bit application register FSR.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadApplicationRegisterFsr (
>- VOID
>- );
>-
>-
>-/**
>- Reads application register FIR.
>-
>- This is a worker function for AsmReadApplicationRegister()
>- when its parameter Index is IPF_APPLICATION_REGISTER_FIR.
>-
>- @return The 64-bit application register FIR.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadApplicationRegisterFir (
>- VOID
>- );
>-
>-
>-/**
>- Reads application register FDR.
>-
>- This is a worker function for AsmReadApplicationRegister()
>- when its parameter Index is IPF_APPLICATION_REGISTER_FDR.
>-
>- @return The 64-bit application register FDR.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadApplicationRegisterFdr (
>- VOID
>- );
>-
>-
>-/**
>- Reads application register CCV.
>-
>- This is a worker function for AsmReadApplicationRegister()
>- when its parameter Index is IPF_APPLICATION_REGISTER_CCV.
>-
>- @return The 64-bit application register CCV.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadApplicationRegisterCcv (
>- VOID
>- );
>-
>-
>-/**
>- Reads application register UNAT.
>-
>- This is a worker function for AsmReadApplicationRegister()
>- when its parameter Index is IPF_APPLICATION_REGISTER_UNAT.
>-
>- @return The 64-bit application register UNAT.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadApplicationRegisterUnat (
>- VOID
>- );
>-
>-
>-/**
>- Reads application register FPSR.
>-
>- This is a worker function for AsmReadApplicationRegister()
>- when its parameter Index is IPF_APPLICATION_REGISTER_FPSR.
>-
>- @return The 64-bit application register FPSR.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadApplicationRegisterFpsr (
>- VOID
>- );
>-
>-
>-/**
>- Reads application register ITC.
>-
>- This is a worker function for AsmReadApplicationRegister()
>- when its parameter Index is IPF_APPLICATION_REGISTER_ITC.
>-
>- @return The 64-bit application register ITC.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadApplicationRegisterItc (
>- VOID
>- );
>-
>-
>-/**
>- Reads application register PFS.
>-
>- This is a worker function for AsmReadApplicationRegister()
>- when its parameter Index is IPF_APPLICATION_REGISTER_PFS.
>-
>- @return The 64-bit application register PFS.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadApplicationRegisterPfs (
>- VOID
>- );
>-
>-
>-/**
>- Reads application register LC.
>-
>- This is a worker function for AsmReadApplicationRegister()
>- when its parameter Index is IPF_APPLICATION_REGISTER_LC.
>-
>- @return The 64-bit application register LC.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadApplicationRegisterLc (
>- VOID
>- );
>-
>-
>-/**
>- Reads application register EC.
>-
>- This is a worker function for AsmReadApplicationRegister()
>- when its parameter Index is IPF_APPLICATION_REGISTER_EC.
>-
>- @return The 64-bit application register EC.
>-
>-**/
>-UINT64
>-EFIAPI
>-AsmReadApplicationRegisterEc (
>- VOID
>- );
>-
>-
>-
>-/**
>- Transfers control to a function starting with a new stack.
>-
>- Transfers control to the function specified by EntryPoint using the new stack
>- specified by NewStack and passing in the parameters specified by Context1
>and
>- Context2. Context1 and Context2 are optional and may be NULL. The
>function
>- EntryPoint must never return.
>-
>- If EntryPoint is NULL, then ASSERT().
>- If NewStack is NULL, then ASSERT().
>-
>- @param EntryPoint A pointer to function to call with the new stack.
>- @param Context1 A pointer to the context to pass into the EntryPoint
>- function.
>- @param Context2 A pointer to the context to pass into the EntryPoint
>- function.
>- @param NewStack A pointer to the new stack to use for the EntryPoint
>- function.
>- @param NewBsp A pointer to the new memory location for RSE backing
>- store.
>-
>-**/
>-VOID
>-EFIAPI
>-AsmSwitchStackAndBackingStore (
>- IN SWITCH_STACK_ENTRY_POINT EntryPoint,
>- IN VOID *Context1, OPTIONAL
>- IN VOID *Context2, OPTIONAL
>- IN VOID *NewStack,
>- IN VOID *NewBsp
>- );
>-
>-/**
>- Internal worker function to invalidate a range of instruction cache lines
>- in the cache coherency domain of the calling CPU.
>-
>- Internal worker function to invalidate the instruction cache lines specified
>- by Address and Length. If Address is not aligned on a cache line boundary,
>- then entire instruction cache line containing Address is invalidated. If
>- Address + Length is not aligned on a cache line boundary, then the entire
>- instruction cache line containing Address + Length -1 is invalidated. This
>- function may choose to invalidate the entire instruction cache if that is more
>- efficient than invalidating the specified range. If Length is 0, the no
>instruction
>- cache lines are invalidated. Address is returned.
>- This function is only available on IPF.
>-
>- @param Address The base address of the instruction cache lines to
>- invalidate. If the CPU is in a physical addressing mode, then
>- Address is a physical address. If the CPU is in a virtual
>- addressing mode, then Address is a virtual address.
>-
>- @param Length The number of bytes to invalidate from the instruction
>cache.
>-
>- @return Address
>-
>-**/
>-VOID *
>-EFIAPI
>-InternalFlushCacheRange (
>- IN VOID *Address,
>- IN UINTN Length
>- );
>-
> #else
>
> #endif
>diff --git a/MdePkg/Library/BaseLib/Ipf/AccessDbr.s
>b/MdePkg/Library/BaseLib/Ipf/AccessDbr.s
>deleted file mode 100644
>index c74737bbf1..0000000000
>--- a/MdePkg/Library/BaseLib/Ipf/AccessDbr.s
>+++ /dev/null
>@@ -1,118 +0,0 @@
>-/// @file
>-/// IPF specific Debug Breakpoint Registers accessing functions
>-///
>-/// Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
>-/// This program and the accompanying materials
>-/// are licensed and made available under the terms and conditions of the
>BSD License
>-/// which accompanies this distribution. The full text of the license may be
>found at
>-/// http://opensource.org/licenses/bsd-license.php.
>-///
>-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-///
>-/// Module Name: AccessDbr.s
>-///
>-///
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmReadDbr
>-//
>-// This routine is used to Reads the current value of Data Breakpoint Register
>(DBR).
>-//
>-// Arguments :
>-//
>-// On Entry : The 8-bit DBR index to read.
>-//
>-// Return Value: The current value of DBR by Index.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmReadDbr, @function
>-.proc AsmReadDbr
>-.regstk 1, 0, 0, 0
>-
>-AsmReadDbr::
>- mov r8 = dbr[in0];;
>- br.ret.dpnt b0;;
>-.endp AsmReadDbr
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmWriteDbr
>-//
>-// This routine is used to write the current value to Data Breakpoint Register
>(DBR).
>-//
>-// Arguments :
>-//
>-// On Entry : The 8-bit DBR index to read.
>-// The value should be written to DBR
>-//
>-// Return Value: The value written to DBR.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmWriteDbr, @function
>-.proc AsmWriteDbr
>-.regstk 2, 0, 0, 0
>-
>-AsmWriteDbr::
>- mov dbr[in0] = in1
>- mov r8 = in1;;
>- srlz.d;;
>- br.ret.dpnt b0;;
>-.endp AsmWriteDbr
>-
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmReadIbr
>-//
>-// This routine is used to Reads the current value of Instruction Breakpoint
>Register (IBR).
>-//
>-// Arguments :
>-//
>-// On Entry : The 8-bit IBR index.
>-//
>-// Return Value: The current value of IBR by Index.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmReadIbr, @function
>-.proc AsmReadIbr
>-.regstk 1, 0, 0, 0
>-
>-AsmReadIbr::
>- mov r8 = ibr[in0];;
>- br.ret.dpnt b0;;
>-.endp AsmReadIbr
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmWriteIbr
>-//
>-// This routine is used to write the current value to Instruction Breakpoint
>Register (IBR).
>-//
>-// Arguments :
>-//
>-// On Entry : The 8-bit IBR index.
>-// The value should be written to IBR
>-//
>-// Return Value: The value written to IBR.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmWriteIbr, @function
>-.proc AsmWriteIbr
>-.regstk 2, 0, 0, 0
>-
>-AsmWriteIbr::
>- mov ibr[in0] = in1
>- mov r8 = in1;;
>- srlz.i;;
>- br.ret.dpnt b0;;
>-.endp AsmWriteIbr
>diff --git a/MdePkg/Library/BaseLib/Ipf/AccessEicr.s
>b/MdePkg/Library/BaseLib/Ipf/AccessEicr.s
>deleted file mode 100644
>index c2f977e3a8..0000000000
>--- a/MdePkg/Library/BaseLib/Ipf/AccessEicr.s
>+++ /dev/null
>@@ -1,512 +0,0 @@
>-/// @file
>-/// IPF specific External Interrupt Control Registers accessing functions
>-///
>-/// Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
>-/// This program and the accompanying materials
>-/// are licensed and made available under the terms and conditions of the
>BSD License
>-/// which accompanies this distribution. The full text of the license may be
>found at
>-/// http://opensource.org/licenses/bsd-license.php.
>-///
>-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-///
>-/// Module Name: AccessEicr.s
>-///
>-///
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmReadLid
>-//
>-// This routine is used to read the value of Local Interrupt ID Register (LID).
>-//
>-// Arguments :
>-//
>-// On Entry :
>-//
>-// Return Value: The current value of LID.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmReadLid, @function
>-.proc AsmReadLid
>-
>-AsmReadLid::
>- mov r8 = cr.lid;;
>- srlz.d;;
>- br.ret.dpnt b0;;
>-.endp AsmReadLid
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmWriteLid
>-//
>-// This routine is used to write the value to Local Interrupt ID Register (LID).
>-//
>-// Arguments :
>-//
>-// On Entry : The value need to be written to LID.
>-//
>-// Return Value: The value written to LID.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmWriteLid, @function
>-.proc AsmWriteLid
>-.regstk 1, 0, 0, 0
>-
>-AsmWriteLid::
>- mov cr.lid = in0
>- mov r8 = in0;;
>- srlz.d;;
>- br.ret.dpnt b0;;
>-.endp AsmWriteLid
>-
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmReadIvr
>-//
>-// This routine is used to read the value of External Interrupt Vector Register
>(IVR).
>-//
>-// Arguments :
>-//
>-// On Entry :
>-//
>-// Return Value: The current value of IVR.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmReadIvr, @function
>-.proc AsmReadIvr
>-
>-AsmReadIvr::
>- mov r8 = cr.ivr;;
>- srlz.d;;
>- br.ret.dpnt b0;;
>-.endp AsmReadIvr
>-
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmReadTpr
>-//
>-// This routine is used to read the value of Task Priority Register (TPR).
>-//
>-// Arguments :
>-//
>-// On Entry :
>-//
>-// Return Value: The current value of TPR.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmReadTpr, @function
>-.proc AsmReadTpr
>-
>-AsmReadTpr::
>- mov r8 = cr.tpr;;
>- br.ret.dpnt b0;;
>-.endp AsmReadTpr
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmWriteTpr
>-//
>-// This routine is used to write the value to Task Priority Register (TPR).
>-//
>-// Arguments :
>-//
>-// On Entry : The value need to be written to TPR.
>-//
>-// Return Value: The value written to TPR.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmWriteTpr, @function
>-.proc AsmWriteTpr
>-.regstk 1, 0, 0, 0
>-
>-AsmWriteTpr::
>- mov cr.tpr = in0
>- mov r8 = in0;;
>- srlz.d;;
>- br.ret.dpnt b0;;
>-.endp AsmWriteTpr
>-
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmWriteEoi
>-//
>-// This routine is used to write the value to End of External Interrupt Register
>(EOI).
>-//
>-// Arguments :
>-//
>-// On Entry : The value need to be written to EOI.
>-//
>-// Return Value: The value written to EOI.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmWriteEoi, @function
>-.proc AsmWriteEoi
>-
>-AsmWriteEoi::
>- mov cr.eoi = r0;;
>- srlz.d;;
>- br.ret.dpnt b0;;
>-.endp AsmWriteEoi
>-
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmReadIrr0
>-//
>-// This routine is used to Read the value of External Interrupt Request
>Register 0 (IRR0).
>-//
>-// Arguments :
>-//
>-// On Entry :
>-//
>-// Return Value: The current value of IRR0.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmReadIrr0, @function
>-.proc AsmReadIrr0
>-
>-AsmReadIrr0::
>- mov r8 = cr.irr0;;
>- br.ret.dpnt b0;;
>-.endp AsmReadIrr0
>-
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmReadIrr1
>-//
>-// This routine is used to Read the value of External Interrupt Request
>Register 1 (IRR1).
>-//
>-// Arguments :
>-//
>-// On Entry :
>-//
>-// Return Value: The current value of IRR1.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmReadIrr1, @function
>-.proc AsmReadIrr1
>-
>-AsmReadIrr1::
>- mov r8 = cr.irr1;;
>- br.ret.dpnt b0;;
>-.endp AsmReadIrr1
>-
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmReadIrr2
>-//
>-// This routine is used to Read the value of External Interrupt Request
>Register 2 (IRR2).
>-//
>-// Arguments :
>-//
>-// On Entry :
>-//
>-// Return Value: The current value of IRR2.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmReadIrr2, @function
>-.proc AsmReadIrr2
>-
>-AsmReadIrr2::
>- mov r8 = cr.irr2;;
>- br.ret.dpnt b0;;
>-.endp AsmReadIrr2
>-
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmReadIrr3
>-//
>-// This routine is used to Read the value of External Interrupt Request
>Register 3 (IRR3).
>-//
>-// Arguments :
>-//
>-// On Entry :
>-//
>-// Return Value: The current value of IRR3.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmReadIrr3, @function
>-.proc AsmReadIrr3
>-
>-AsmReadIrr3::
>- mov r8 = cr.irr3;;
>- br.ret.dpnt b0;;
>-.endp AsmReadIrr3
>-
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmReadItv
>-//
>-// This routine is used to Read the value of Interval Timer Vector Register
>(ITV).
>-//
>-// Arguments :
>-//
>-// On Entry :
>-//
>-// Return Value: The current value of ITV.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmReadItv, @function
>-.proc AsmReadItv
>-
>-AsmReadItv::
>- mov r8 = cr.itv;;
>- br.ret.dpnt b0;;
>-.endp AsmReadItv
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmWriteItv
>-//
>-// This routine is used to write the value to Interval Timer Vector Register
>(ITV).
>-//
>-// Arguments :
>-//
>-// On Entry : The value need to be written to ITV
>-//
>-// Return Value: The value written to ITV.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmWriteItv, @function
>-.proc AsmWriteItv
>-.regstk 1, 0, 0, 0
>-
>-AsmWriteItv::
>- mov cr.itv = in0
>- mov r8 = in0;;
>- srlz.d;;
>- br.ret.dpnt b0;;
>-.endp AsmWriteItv
>-
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmReadPmv
>-//
>-// This routine is used to Read the value of Performance Monitoring Vector
>Register (PMV).
>-//
>-// Arguments :
>-//
>-// On Entry :
>-//
>-// Return Value: The current value of PMV.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmReadPmv, @function
>-.proc AsmReadPmv
>-
>-AsmReadPmv::
>- mov r8 = cr.pmv;;
>- br.ret.dpnt b0;;
>-.endp AsmReadPmv
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmWritePmv
>-//
>-// This routine is used to write the value to Performance Monitoring Vector
>Register (PMV).
>-//
>-// Arguments :
>-//
>-// On Entry : The value need to be written to PMV
>-//
>-// Return Value: The value written to PMV.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmWritePmv, @function
>-.proc AsmWritePmv
>-.regstk 1, 0, 0, 0
>-
>-AsmWritePmv::
>- mov cr.pmv = in0
>- mov r8 = in0;;
>- srlz.d;;
>- br.ret.dpnt b0;;
>-.endp AsmWritePmv
>-
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmReadCmcv
>-//
>-// This routine is used to Read the value of Corrected Machine Check Vector
>Register (CMCV).
>-//
>-// Arguments :
>-//
>-// On Entry :
>-//
>-// Return Value: The current value of CMCV.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmReadCmcv, @function
>-.proc AsmReadCmcv
>-
>-AsmReadCmcv::
>- mov r8 = cr.cmcv;;
>- br.ret.dpnt b0;;
>-.endp AsmReadCmcv
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmWriteCmcv
>-//
>-// This routine is used to write the value to Corrected Machine Check Vector
>Register (CMCV).
>-//
>-// Arguments :
>-//
>-// On Entry : The value need to be written to CMCV
>-//
>-// Return Value: The value written to CMCV.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmWriteCmcv, @function
>-.proc AsmWriteCmcv
>-.regstk 1, 0, 0, 0
>-
>-AsmWriteCmcv::
>- mov cr.cmcv = in0
>- mov r8 = in0;;
>- srlz.d;;
>- br.ret.dpnt b0;;
>-.endp AsmWriteCmcv
>-
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmReadLrr0
>-//
>-// This routine is used to read the value of Local Redirection Register 0 (LRR0).
>-//
>-// Arguments :
>-//
>-// On Entry :
>-//
>-// Return Value: The current value of LRR0.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmReadLrr0, @function
>-.proc AsmReadLrr0
>-
>-AsmReadLrr0::
>- mov r8 = cr.lrr0;;
>- br.ret.dpnt b0;;
>-.endp AsmReadLrr0
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmWriteLrr0
>-//
>-// This routine is used to write the value to Local Redirection Register 0 (LRR0).
>-//
>-// Arguments :
>-//
>-// On Entry : The value need to be written to LRR0.
>-//
>-// Return Value: The value written to LRR0.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmWriteLrr0, @function
>-.proc AsmWriteLrr0
>-.regstk 1, 0, 0, 0
>-
>-AsmWriteLrr0::
>- mov cr.lrr0 = in0
>- mov r8 = in0;;
>- srlz.d;;
>- br.ret.dpnt b0;;
>-.endp AsmWriteLrr0
>-
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmReadLrr1
>-//
>-// This routine is used to read the value of Local Redirection Register 1 (LRR1).
>-//
>-// Arguments :
>-//
>-// On Entry :
>-//
>-// Return Value: The current value of LRR1.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmReadLrr1, @function
>-.proc AsmReadLrr1
>-
>-AsmReadLrr1::
>- mov r8 = cr.lrr1;;
>- br.ret.dpnt b0;;
>-.endp AsmReadLrr1
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmWriteLrr1
>-//
>-// This routine is used to write the value to Local Redirection Register 1 (LRR1).
>-//
>-// Arguments :
>-//
>-// On Entry : The value need to be written to LRR1.
>-//
>-// Return Value: The value written to LRR1.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmWriteLrr1, @function
>-.proc AsmWriteLrr1
>-.regstk 1, 0, 0, 0
>-
>-AsmWriteLrr1::
>- mov cr.lrr1 = in0
>- mov r8 = in0;;
>- srlz.d;;
>- br.ret.dpnt b0;;
>-.endp AsmWriteLrr1
>-
>diff --git a/MdePkg/Library/BaseLib/Ipf/AccessGcr.s
>b/MdePkg/Library/BaseLib/Ipf/AccessGcr.s
>deleted file mode 100644
>index d519e7d0f5..0000000000
>--- a/MdePkg/Library/BaseLib/Ipf/AccessGcr.s
>+++ /dev/null
>@@ -1,274 +0,0 @@
>-/// @file
>-/// IPF specific Global Control Registers accessing functions
>-///
>-/// Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
>-/// This program and the accompanying materials
>-/// are licensed and made available under the terms and conditions of the
>BSD License
>-/// which accompanies this distribution. The full text of the license may be
>found at
>-/// http://opensource.org/licenses/bsd-license.php.
>-///
>-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-///
>-/// Module Name: AccessGcr.s
>-///
>-///
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmReadDcr
>-//
>-// This routine is used to Read the value of Default Control Register (DCR).
>-//
>-// Arguments :
>-//
>-// On Entry :
>-//
>-// Return Value: The current value of DCR.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmReadDcr, @function
>-.proc AsmReadDcr
>-
>-AsmReadDcr::
>- mov r8 = cr.dcr;;
>- br.ret.dpnt b0;;
>-.endp AsmReadDcr
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmWriteDcr
>-//
>-// This routine is used to write the value to Default Control Register (DCR).
>-//
>-// Arguments :
>-//
>-// On Entry : The value need to be written to DCR
>-//
>-// Return Value: The value written to DCR.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmWriteDcr, @function
>-.proc AsmWriteDcr
>-.regstk 1, 0, 0, 0
>-
>-AsmWriteDcr::
>- mov cr.dcr = in0
>- mov r8 = in0;;
>- srlz.i;;
>- srlz.d;;
>- br.ret.dpnt b0;;
>-.endp AsmWriteDcr
>-
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmReadItc
>-//
>-// This routine is used to Read the value of Interval Timer Counter Register
>(ITC).
>-//
>-// Arguments :
>-//
>-// On Entry :
>-//
>-// Return Value: The current value of ITC.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmReadItc, @function
>-.proc AsmReadItc
>-
>-AsmReadItc::
>- mov r8 = ar.itc;;
>- br.ret.dpnt b0;;
>-.endp AsmReadItc
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmWriteItc
>-//
>-// This routine is used to write the value to Interval Timer Counter Register
>(ITC).
>-//
>-// Arguments :
>-//
>-// On Entry : The value need to be written to the ITC
>-//
>-// Return Value: The value written to the ITC.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmWriteItc, @function
>-.proc AsmWriteItc
>-.regstk 1, 0, 0, 0
>-
>-AsmWriteItc::
>- mov ar.itc = in0
>- mov r8 = in0;;
>- br.ret.dpnt b0;;
>-.endp AsmWriteItc
>-
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmReadItm
>-//
>-// This routine is used to Read the value of Interval Timer Match Register
>(ITM).
>-//
>-// Arguments :
>-//
>-// On Entry :
>-//
>-// Return Value: The current value of ITM.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmReadItm, @function
>-.proc AsmReadItm
>-
>-AsmReadItm::
>- mov r8 = cr.itm;;
>- br.ret.dpnt b0;;
>-.endp AsmReadItm
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmWriteItm
>-//
>-// This routine is used to write the value to Interval Timer Match Register
>(ITM).
>-//
>-// Arguments :
>-//
>-// On Entry : The value need to be written to ITM
>-//
>-// Return Value: The value written to ITM.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmWriteItm, @function
>-.proc AsmWriteItm
>-.regstk 1, 0, 0, 0
>-
>-AsmWriteItm::
>- mov cr.itm = in0
>- mov r8 = in0;;
>- srlz.d;
>- br.ret.dpnt b0;;
>-.endp AsmWriteItm
>-
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmReadIva
>-//
>-// This routine is used to read the value of Interruption Vector Address
>Register (IVA).
>-//
>-// Arguments :
>-//
>-// On Entry :
>-//
>-// Return Value: The current value of IVA.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmReadIva, @function
>-.proc AsmReadIva
>-
>-AsmReadIva::
>- mov r8 = cr.iva;;
>- br.ret.dpnt b0;;
>-.endp AsmReadIva
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmWriteIva
>-//
>-// This routine is used to write the value to Interruption Vector Address
>Register (IVA).
>-//
>-// Arguments :
>-//
>-// On Entry : The value need to be written to IVA
>-//
>-// Return Value: The value written to IVA.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmWriteIva, @function
>-.proc AsmWriteIva
>-.regstk 1, 3, 0, 0
>-
>-AsmWriteIva::
>- alloc loc1=ar.pfs,1,4,0,0 ;;
>-
>- mov loc2 = psr
>- rsm 0x6000 // Make sure interrupts are masked
>-
>- mov cr.iva = in0
>- srlz.i;;
>- mov psr.l = loc2;;
>- srlz.i;;
>- srlz.d;;
>- mov ar.pfs=loc1 ;;
>- mov r8 = in0;;
>- br.ret.dpnt b0;;
>-.endp AsmWriteIva
>-
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmReadPta
>-//
>-// This routine is used to read the value of Page Table Address Register (PTA).
>-//
>-// Arguments :
>-//
>-// On Entry :
>-//
>-// Return Value: The current value of PTA.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmReadPta, @function
>-.proc AsmReadPta
>-
>-AsmReadPta::
>- mov r8 = cr.pta;;
>- br.ret.dpnt b0;;
>-.endp AsmReadPta
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmWritePta
>-//
>-// This routine is used to write the value to Page Table Address Register
>(PTA)).
>-//
>-// Arguments :
>-//
>-// On Entry : The value need to be written to PTA
>-//
>-// Return Value: The value written to PTA.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmWritePta, @function
>-.proc AsmWritePta
>-.regstk 1, 0, 0, 0
>-
>-AsmWritePta::
>- mov cr.pta = in0
>- mov r8 = in0;;
>- srlz.i;;
>- srlz.d;;
>- br.ret.dpnt b0;;
>-.endp AsmWritePta
>diff --git a/MdePkg/Library/BaseLib/Ipf/AccessGp.s
>b/MdePkg/Library/BaseLib/Ipf/AccessGp.s
>deleted file mode 100644
>index a0e3d3fb55..0000000000
>--- a/MdePkg/Library/BaseLib/Ipf/AccessGp.s
>+++ /dev/null
>@@ -1,86 +0,0 @@
>-/// @file
>-/// IPF specific Global Pointer and Stack Pointer accessing functions
>-///
>-/// Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
>-/// This program and the accompanying materials
>-/// are licensed and made available under the terms and conditions of the
>BSD License
>-/// which accompanies this distribution. The full text of the license may be
>found at
>-/// http://opensource.org/licenses/bsd-license.php.
>-///
>-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-///
>-/// Module Name: AccessGp.s
>-///
>-///
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmReadGp
>-//
>-// This routine is used to read the current value of 64-bit Global Pointer (GP).
>-//
>-// Arguments :
>-//
>-// On Entry :
>-//
>-// Return Value: The current GP value.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmReadGp, @function
>-.proc AsmReadGp
>-
>-AsmReadGp::
>- mov r8 = gp;;
>- br.ret.dpnt b0;;
>-.endp AsmReadGp
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmWriteGp
>-//
>-// This routine is used to write the current value of 64-bit Global Pointer (GP).
>-//
>-// Arguments :
>-//
>-// On Entry : The value need to be written.
>-//
>-// Return Value: The value have been written.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmWriteGp, @function
>-.proc AsmWriteGp
>-.regstk 1, 0, 0, 0
>-
>-AsmWriteGp::
>- mov gp = in0
>- mov r8 = in0;;
>- br.ret.dpnt b0;;
>-.endp AsmWriteGp
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmReadSp
>-//
>-// This routine is used to read the current value of 64-bit Stack Pointer (SP).
>-//
>-// Arguments :
>-//
>-// On Entry :
>-//
>-// Return Value: The current SP value.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmReadSp, @function
>-.proc AsmReadSp
>-
>-AsmReadSp::
>- mov r8 = sp;;
>- br.ret.dpnt b0;;
>-.endp AsmReadSp
>diff --git a/MdePkg/Library/BaseLib/Ipf/AccessKr.s
>b/MdePkg/Library/BaseLib/Ipf/AccessKr.s
>deleted file mode 100644
>index 4d4798de76..0000000000
>--- a/MdePkg/Library/BaseLib/Ipf/AccessKr.s
>+++ /dev/null
>@@ -1,360 +0,0 @@
>-/// @file
>-/// IPF specific AsmReadKrX() and AsmWriteKrX() functions, 'X' is from '0' to
>'6'
>-///
>-/// Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
>-/// This program and the accompanying materials
>-/// are licensed and made available under the terms and conditions of the
>BSD License
>-/// which accompanies this distribution. The full text of the license may be
>found at
>-/// http://opensource.org/licenses/bsd-license.php.
>-///
>-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-///
>-/// Module Name: AccessKr.s
>-///
>-///
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmReadKr0
>-//
>-// This routine is used to get KR0.
>-//
>-// Arguments :
>-//
>-// On Entry : None.
>-//
>-// Return Value: The value store in KR0.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmReadKr0, @function
>-.proc AsmReadKr0
>-
>-AsmReadKr0::
>- mov r8 = ar.k0;;
>- br.ret.dpnt b0;;
>-.endp AsmReadKr0
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmWriteKr0
>-//
>-// This routine is used to Write KR0.
>-//
>-// Arguments :
>-//
>-// On Entry : None.
>-//
>-// Return Value: The value written to the KR0.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-
>-.text
>-.type AsmWriteKr0, @function
>-.proc AsmWriteKr0
>-.regstk 1, 3, 0, 0
>-
>-AsmWriteKr0::
>- alloc loc1=ar.pfs,1,4,0,0 ;;
>- mov loc2 = psr;;
>- rsm 0x6000;; // Masking interrupts
>- mov ar.k0 = in0
>- srlz.i;;
>- mov psr.l = loc2;;
>- srlz.i;;
>- srlz.d;;
>- mov r8 = in0;;
>- mov ar.pfs=loc1 ;;
>- br.ret.dpnt b0;;
>-.endp AsmWriteKr0
>-
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmReadKr1
>-//
>-// This routine is used to get KR1.
>-//
>-// Arguments :
>-//
>-// On Entry : None.
>-//
>-// Return Value: The value store in KR1.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmReadKr1, @function
>-.proc AsmReadKr1
>-
>-AsmReadKr1::
>- mov r8 = ar.k1;;
>- br.ret.dpnt b0;;
>-.endp AsmReadKr1
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmWriteKr1
>-//
>-// This routine is used to Write KR1.
>-//
>-// Arguments :
>-//
>-// On Entry : None.
>-//
>-// Return Value: The value written to the KR1.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmWriteKr1, @function
>-.proc AsmWriteKr1
>-
>-AsmWriteKr1::
>- mov ar.k1 = in0
>- mov r8 = in0;;
>- br.ret.dpnt b0;;
>-.endp AsmWriteKr1
>-
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmReadKr2
>-//
>-// This routine is used to get KR2.
>-//
>-// Arguments :
>-//
>-// On Entry : None.
>-//
>-// Return Value: The value store in KR2.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmReadKr2, @function
>-.proc AsmReadKr2
>-
>-AsmReadKr2::
>- mov r8 = ar.k2;;
>- br.ret.dpnt b0;;
>-.endp AsmReadKr2
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmWriteKr2
>-//
>-// This routine is used to Write KR2.
>-//
>-// Arguments :
>-//
>-// On Entry : None.
>-//
>-// Return Value: The value written to the KR2.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmWriteKr2, @function
>-.proc AsmWriteKr2
>-
>-AsmWriteKr2::
>- mov ar.k2 = in0
>- mov r8 = in0;;
>- br.ret.dpnt b0;;
>-.endp AsmWriteKr2
>-
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmReadKr3
>-//
>-// This routine is used to get KR3.
>-//
>-// Arguments :
>-//
>-// On Entry : None.
>-//
>-// Return Value: The value store in KR3.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmReadKr3, @function
>-.proc AsmReadKr3
>-
>-AsmReadKr3::
>- mov r8 = ar.k3;;
>- br.ret.dpnt b0;;
>-.endp AsmReadKr3
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmWriteKr3
>-//
>-// This routine is used to Write KR3.
>-//
>-// Arguments :
>-//
>-// On Entry : None.
>-//
>-// Return Value: The value written to the KR3.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmWriteKr3, @function
>-.proc AsmWriteKr3
>-
>-AsmWriteKr3::
>- mov ar.k3 = in0
>- mov r8 = in0;;
>- br.ret.dpnt b0;;
>-.endp AsmWriteKr3
>-
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmReadKr4
>-//
>-// This routine is used to get KR4.
>-//
>-// Arguments :
>-//
>-// On Entry : None.
>-//
>-// Return Value: The value store in KR4.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmReadKr4, @function
>-.proc AsmReadKr4
>-
>-AsmReadKr4::
>- mov r8 = ar.k4;;
>- br.ret.dpnt b0;;
>-.endp AsmReadKr4
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmWriteKr4
>-//
>-// This routine is used to Write KR4.
>-//
>-// Arguments :
>-//
>-// On Entry : None.
>-//
>-// Return Value: The value written to the KR4.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmWriteKr4, @function
>-.proc AsmWriteKr4
>-
>-AsmWriteKr4::
>- mov ar.k4 = in0
>- mov r8 = in0;;
>- br.ret.dpnt b0;;
>-.endp AsmWriteKr4
>-
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmReadKr5
>-//
>-// This routine is used to get KR5.
>-//
>-// Arguments :
>-//
>-// On Entry : None.
>-//
>-// Return Value: The value store in KR5.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmReadKr5, @function
>-.proc AsmReadKr5
>-
>-AsmReadKr5::
>- mov r8 = ar.k5;;
>- br.ret.dpnt b0;;
>-.endp AsmReadKr5
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmWriteKr5
>-//
>-// This routine is used to Write KR5.
>-//
>-// Arguments :
>-//
>-// On Entry : None.
>-//
>-// Return Value: The value written to the KR5.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmWriteKr5, @function
>-.proc AsmWriteKr5
>-
>-AsmWriteKr5::
>- mov ar.k5 = in0
>- mov r8 = in0;;
>- br.ret.dpnt b0;;
>-.endp AsmWriteKr5
>-
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmReadKr6
>-//
>-// This routine is used to get KR6.
>-//
>-// Arguments :
>-//
>-// On Entry : None.
>-//
>-// Return Value: The value store in KR6.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmReadKr6, @function
>-.proc AsmReadKr6
>-
>-AsmReadKr6::
>- mov r8 = ar.k6;;
>- br.ret.dpnt b0;;
>-.endp AsmReadKr6
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmWriteKr6
>-//
>-// This routine is used to write KR6.
>-//
>-// Arguments :
>-//
>-// On Entry : None.
>-//
>-// Return Value: The value written to the KR6.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmWriteKr6, @function
>-.proc AsmWriteKr6
>-
>-AsmWriteKr6::
>- mov ar.k6 = in0
>- mov r8 = in0;;
>- br.ret.dpnt b0;;
>-.endp AsmWriteKr6
>diff --git a/MdePkg/Library/BaseLib/Ipf/AccessKr7.s
>b/MdePkg/Library/BaseLib/Ipf/AccessKr7.s
>deleted file mode 100644
>index 66a3dbfd35..0000000000
>--- a/MdePkg/Library/BaseLib/Ipf/AccessKr7.s
>+++ /dev/null
>@@ -1,63 +0,0 @@
>-/// @file
>-/// IPF specific AsmReadKr7() and AsmWriteKr7()
>-///
>-/// Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
>-/// This program and the accompanying materials
>-/// are licensed and made available under the terms and conditions of the
>BSD License
>-/// which accompanies this distribution. The full text of the license may be
>found at
>-/// http://opensource.org/licenses/bsd-license.php.
>-///
>-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-///
>-/// Module Name: AccessKr7.s
>-///
>-///
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmReadKr7
>-//
>-// This routine is used to get KR7.
>-//
>-// Arguments :
>-//
>-// On Entry : None.
>-//
>-// Return Value: The value store in KR7.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmReadKr7, @function
>-.proc AsmReadKr7
>-
>-AsmReadKr7::
>- mov r8 = ar.k7;;
>- br.ret.dpnt b0;;
>-.endp AsmReadKr7
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmWriteKr7
>-//
>-// This routine is used to write KR7.
>-//
>-// Arguments :
>-//
>-// On Entry : None.
>-//
>-// Return Value: The value written to the KR7.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmWriteKr7, @function
>-.proc AsmWriteKr7
>-.regstk 1, 3, 0, 0
>-
>-AsmWriteKr7::
>- mov ar.k7 = in0
>- mov r8 = in0;;
>- br.ret.dpnt b0;;
>-.endp AsmWriteKr7
>diff --git a/MdePkg/Library/BaseLib/Ipf/AccessMsr.s
>b/MdePkg/Library/BaseLib/Ipf/AccessMsr.s
>deleted file mode 100644
>index 11b3f1eafb..0000000000
>--- a/MdePkg/Library/BaseLib/Ipf/AccessMsr.s
>+++ /dev/null
>@@ -1,79 +0,0 @@
>-/// @file
>-/// IPF specific Machine Specific Registers accessing functions.
>-///
>-/// Copyright (c) 2008, Intel Corporation. All rights reserved.<BR>
>-/// This program and the accompanying materials
>-/// are licensed and made available under the terms and conditions of the
>BSD License
>-/// which accompanies this distribution. The full text of the license may be
>found at
>-/// http://opensource.org/licenses/bsd-license.php.
>-///
>-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-///
>-///
>-///
>-
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmReadMsr
>-//
>-// Reads the current value of a Machine Specific Register (MSR).
>-//
>-// Reads and returns the current value of the Machine Specific Register
>specified by Index. No
>-// parameter checking is performed on Index, and if the Index value is
>beyond the implemented MSR
>-// register range, a Reserved Register/Field fault may occur. The caller must
>either guarantee that
>-// Index is valid, or the caller must set up fault handlers to catch the faults.
>This function is
>-// only available on IPF.
>-//
>-// Arguments :
>-//
>-// On Entry : The 8-bit Machine Specific Register index to read.
>-//
>-// Return Value: The current value of the Machine Specific Register specified
>by Index.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmReadMsr, @function
>-.proc AsmReadMsr
>-.regstk 1, 0, 0, 0
>-
>-AsmReadMsr::
>- mov r8=msr[in0];;
>- br.ret.sptk b0;;
>-.endp AsmReadMsr
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmWriteMsr
>-//
>-// Writes the current value of a Machine Specific Register (MSR).
>-//
>-// Writes Value to the Machine Specific Register specified by Index. Value is
>returned. No
>-// parameter checking is performed on Index, and if the Index value is
>beyond the implemented MSR
>-// register range, a Reserved Register/Field fault may occur. The caller must
>either guarantee that
>-// Index is valid, or the caller must set up fault handlers to catch the faults.
>This function is
>-// only available on IPF.
>-//
>-// Arguments :
>-//
>-// On Entry : The 8-bit Machine Specific Register index to write.
>-// The 64-bit value to write to the Machine Specific Register.
>-//
>-// Return Value: The 64-bit value to write to the Machine Specific Register.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmWriteMsr, @function
>-.proc AsmWriteMsr
>-.regstk 2, 0, 0, 0
>-
>-AsmWriteMsr::
>- mov msr[in0] = in1
>- mov r8 = in1;;
>- srlz.d;;
>- br.ret.sptk b0;;
>-.endp AsmWriteMsr
>-
>diff --git a/MdePkg/Library/BaseLib/Ipf/AccessMsrDb.s
>b/MdePkg/Library/BaseLib/Ipf/AccessMsrDb.s
>deleted file mode 100644
>index 79468e0500..0000000000
>--- a/MdePkg/Library/BaseLib/Ipf/AccessMsrDb.s
>+++ /dev/null
>@@ -1,121 +0,0 @@
>-/// @file
>-/// IPF specific Machine Specific Registers accessing functions.
>-/// This implementation uses raw data to prepresent the assembly
>instruction of
>-/// mov msr[]= and mov =msr[].
>-///
>-/// Copyright (c) 2008, Intel Corporation. All rights reserved.<BR>
>-/// This program and the accompanying materials
>-/// are licensed and made available under the terms and conditions of the
>BSD License
>-/// which accompanies this distribution. The full text of the license may be
>found at
>-/// http://opensource.org/licenses/bsd-license.php.
>-///
>-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-///
>-///
>-///
>-
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmReadMsr
>-//
>-// Reads the current value of a Machine Specific Register (MSR).
>-//
>-// Reads and returns the current value of the Machine Specific Register
>specified by Index. No
>-// parameter checking is performed on Index, and if the Index value is
>beyond the implemented MSR
>-// register range, a Reserved Register/Field fault may occur. The caller must
>either guarantee that
>-// Index is valid, or the caller must set up fault handlers to catch the faults.
>This function is
>-// only available on IPF.
>-//
>-// Arguments :
>-//
>-// On Entry : The 8-bit Machine Specific Register index to read.
>-//
>-// Return Value: The current value of the Machine Specific Register specified
>by Index.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmReadMsr, @function
>-.proc AsmReadMsr
>-.regstk 1, 0, 0, 0
>-
>-AsmReadMsr::
>-//
>-// The follow 16 bytes stand for the bundle of
>-// mov r8=msr[in0];;
>-// since MSFT tool chain does not support mov =msr[] instruction
>-//
>- data1 0x0D
>- data1 0x40
>- data1 0x00
>- data1 0x40
>- data1 0x16
>- data1 0x04
>- data1 0x00
>- data1 0x00
>- data1 0x00
>- data1 0x02
>- data1 0x00
>- data1 0x00
>- data1 0x00
>- data1 0x00
>- data1 0x04
>- data1 0x00
>- br.ret.sptk b0;;
>-.endp AsmReadMsr
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmWriteMsr
>-//
>-// Writes the current value of a Machine Specific Register (MSR).
>-//
>-// Writes Value to the Machine Specific Register specified by Index. Value is
>returned. No
>-// parameter checking is performed on Index, and if the Index value is
>beyond the implemented MSR
>-// register range, a Reserved Register/Field fault may occur. The caller must
>either guarantee that
>-// Index is valid, or the caller must set up fault handlers to catch the faults.
>This function is
>-// only available on IPF.
>-//
>-// Arguments :
>-//
>-// On Entry : The 8-bit Machine Specific Register index to write.
>-// The 64-bit value to write to the Machine Specific Register.
>-//
>-// Return Value: The 64-bit value to write to the Machine Specific Register.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmWriteMsr, @function
>-.proc AsmWriteMsr
>-.regstk 2, 0, 0, 0
>-
>-AsmWriteMsr::
>-//
>-// The follow 16 bytes stand for the bundle of
>-// mov msr[in0] = in1
>-// mov r8 = in1;;
>-// since MSFT tool chain does not support mov msr[]= instruction
>-//
>- data1 0x0D
>- data1 0x00
>- data1 0x84
>- data1 0x40
>- data1 0x06
>- data1 0x04
>- data1 0x00
>- data1 0x00
>- data1 0x00
>- data1 0x02
>- data1 0x00
>- data1 0x00
>- data1 0x01
>- data1 0x08
>- data1 0x01
>- data1 0x84
>- srlz.d;;
>- br.ret.sptk b0;;
>-.endp AsmWriteMsr
>-
>diff --git a/MdePkg/Library/BaseLib/Ipf/AccessPmr.s
>b/MdePkg/Library/BaseLib/Ipf/AccessPmr.s
>deleted file mode 100644
>index cc75b4f263..0000000000
>--- a/MdePkg/Library/BaseLib/Ipf/AccessPmr.s
>+++ /dev/null
>@@ -1,124 +0,0 @@
>-/// @file
>-/// IPF specific Performance Monitor Configuration/Data Registers accessing
>functions
>-///
>-/// Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
>-/// This program and the accompanying materials
>-/// are licensed and made available under the terms and conditions of the
>BSD License
>-/// which accompanies this distribution. The full text of the license may be
>found at
>-/// http://opensource.org/licenses/bsd-license.php.
>-///
>-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-///
>-/// Module Name: AccessPmr.s
>-///
>-///
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmReadPmc
>-//
>-// This routine is used to Reads the current value of Performance Monitor
>Configuration Register (PMC).
>-//
>-// Arguments :
>-//
>-// On Entry : The 8-bit PMC index.
>-//
>-// Return Value: The current value of PMC by Index.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmReadPmc, @function
>-.proc AsmReadPmc
>-.regstk 1, 0, 0, 0
>-
>-AsmReadPmc::
>- srlz.i;;
>- srlz.d;;
>- mov r8 = pmc[in0];;
>- br.ret.dpnt b0;;
>-.endp AsmReadPmc
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmWritePmc
>-//
>-// This routine is used to write the current value to a Performance Monitor
>Configuration Register (PMC).
>-//
>-// Arguments :
>-//
>-// On Entry : The 8-bit PMC index.
>-// The value should be written to PMC
>-//
>-// Return Value: The value written to PMC.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmWritePmc, @function
>-.proc AsmWritePmc
>-.regstk 2, 0, 0, 0
>-
>-AsmWritePmc::
>- mov pmc[in0] = in1
>- mov r8 = in1;;
>- srlz.i;;
>- srlz.d;;
>- br.ret.dpnt b0;;
>-.endp AsmWritePmc
>-
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmReadPmd
>-//
>-// This routine is used to Reads the current value of Performance Monitor
>Data Register (PMD).
>-//
>-// Arguments :
>-//
>-// On Entry : The 8-bit PMD index.
>-//
>-// Return Value: The current value of PMD by Index.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmReadPmd, @function
>-.proc AsmReadPmd
>-.regstk 1, 0, 0, 0
>-
>-AsmReadPmd::
>- srlz.i;;
>- srlz.d;;
>- mov r8 = pmd[in0];;
>- br.ret.dpnt b0;;
>-.endp AsmReadPmd
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmWritePmd
>-//
>-// This routine is used to write the current value to Performance Monitor
>Data Register (PMD).
>-//
>-// Arguments :
>-//
>-// On Entry : The 8-bit PMD index.
>-// The value should be written to PMD
>-//
>-// Return Value: The value written to PMD.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmWritePmd, @function
>-.proc AsmWritePmd
>-.regstk 2, 0, 0, 0
>-
>-AsmWritePmd::
>- mov pmd[in0] = in1
>- mov r8 = in1;;
>- srlz.i;;
>- srlz.d;;
>- br.ret.dpnt b0;;
>-.endp AsmWritePmd
>diff --git a/MdePkg/Library/BaseLib/Ipf/AccessPsr.s
>b/MdePkg/Library/BaseLib/Ipf/AccessPsr.s
>deleted file mode 100644
>index b183ba01b1..0000000000
>--- a/MdePkg/Library/BaseLib/Ipf/AccessPsr.s
>+++ /dev/null
>@@ -1,111 +0,0 @@
>-/// @file
>-/// IPF specific Processor Status Register accessing functions
>-///
>-/// Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
>-/// This program and the accompanying materials
>-/// are licensed and made available under the terms and conditions of the
>BSD License
>-/// which accompanies this distribution. The full text of the license may be
>found at
>-/// http://opensource.org/licenses/bsd-license.php.
>-///
>-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-///
>-/// Module Name: AccessPsr.s
>-///
>-///
>-
>-#define CpuModeMask 0x0000001008020000
>-
>-#define CpuInVirtualMode 0x1
>-#define CpuInPhysicalMode 0x0
>-#define CpuInMixMode (0x0 - 0x1)
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmReadPsr
>-//
>-// This routine is used to read the current value of Processor Status Register
>(PSR).
>-//
>-// Arguments :
>-//
>-// On Entry :
>-//
>-// Return Value: The current PSR value.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmReadPsr, @function
>-.proc AsmReadPsr
>-
>-AsmReadPsr::
>- mov r8 = psr;;
>- br.ret.dpnt b0;;
>-.endp AsmReadPsr
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmWritePsr
>-//
>-// This routine is used to write the value of Processor Status Register (PSR).
>-//
>-// Arguments :
>-//
>-// On Entry : The value need to be written.
>-//
>-// Return Value: The value have been written.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmWritePsr, @function
>-.proc AsmWritePsr
>-.regstk 1, 0, 0, 0
>-
>-AsmWritePsr::
>- mov psr.l = in0
>- mov r8 = in0;;
>- srlz.d;;
>- srlz.i;;
>- br.ret.dpnt b0;;
>-.endp AsmWritePsr
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmCpuVirtual
>-//
>-// This routine is used to determines if the CPU is currently executing
>-// in virtual, physical, or mixed mode.
>-//
>-// If the CPU is in virtual mode(PSR.RT=1, PSR.DT=1, PSR.IT=1), then 1 is
>returned.
>-// If the CPU is in physical mode(PSR.RT=0, PSR.DT=0, PSR.IT=0), then 0 is
>returned.
>-// If the CPU is not in physical mode or virtual mode, then it is in mixed mode,
>-// and -1 is returned.
>-//
>-// Arguments:
>-//
>-// On Entry: None
>-//
>-// Return Value: The CPU mode flag
>-// return 1 The CPU is in virtual mode.
>-// return 0 The CPU is in physical mode.
>-// return -1 The CPU is in mixed mode.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmCpuVirtual, @function
>-.proc AsmCpuVirtual
>-
>-AsmCpuVirtual::
>- mov r29 = psr
>- movl r30 = CpuModeMask;;
>- and r28 = r30, r29;;
>- cmp.eq p6, p7 = r30, r28;;
>-(p6) mov r8 = CpuInVirtualMode;;
>-(p6) br.ret.dpnt b0;;
>-(p7) cmp.eq p6, p7 = 0x0, r28;;
>-(p6) mov r8 = CpuInPhysicalMode;;
>-(p7) mov r8 = CpuInMixMode;;
>- br.ret.dpnt b0;;
>-.endp AsmCpuVirtual
>diff --git a/MdePkg/Library/BaseLib/Ipf/Asm.h
>b/MdePkg/Library/BaseLib/Ipf/Asm.h
>deleted file mode 100644
>index 54345734f1..0000000000
>--- a/MdePkg/Library/BaseLib/Ipf/Asm.h
>+++ /dev/null
>@@ -1,27 +0,0 @@
>-/** @file
>-
>- This module contains generic macros for an assembly writer.
>-
>-Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
>-This program and the accompanying materials
>-are licensed and made available under the terms and conditions of the BSD
>License
>-which accompanies this distribution. The full text of the license may be
>found at
>-http://opensource.org/licenses/bsd-license.php.
>-
>-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
>-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-**/
>-
>-#ifndef _ASM_H_
>-#define _ASM_H_
>-
>-#define TRUE 1
>-#define FALSE 0
>-#define PROCEDURE_ENTRY(name) .##text; \
>- .##type name, @function; \
>- .##proc name; \
>- name::
>-
>-#define PROCEDURE_EXIT(name) .##endp name
>-
>-#endif // _ASM_H
>diff --git a/MdePkg/Library/BaseLib/Ipf/AsmCpuMisc.s
>b/MdePkg/Library/BaseLib/Ipf/AsmCpuMisc.s
>deleted file mode 100644
>index 91075bf7b3..0000000000
>--- a/MdePkg/Library/BaseLib/Ipf/AsmCpuMisc.s
>+++ /dev/null
>@@ -1,79 +0,0 @@
>-/// @file
>-/// Contains an implementation of CallPalProcStacked on Itanium-based
>-/// architecture.
>-///
>-/// Copyright (c) 2008, Intel Corporation. All rights reserved.<BR>
>-/// This program and the accompanying materials
>-/// are licensed and made available under the terms and conditions of the
>BSD License
>-/// which accompanies this distribution. The full text of the license may be
>found at
>-/// http://opensource.org/licenses/bsd-license.php.
>-///
>-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-///
>-/// Module Name: AsmCpuMisc.s
>-///
>-///
>-
>-
>-.text
>-.proc CpuBreakpoint
>-.type CpuBreakpoint, @function
>-
>-CpuBreakpoint::
>- break.i 0;;
>- br.ret.dpnt b0;;
>-
>-.endp CpuBreakpoint
>-
>-.proc MemoryFence
>-.type MemoryFence, @function
>-
>-MemoryFence::
>- mf;; // memory access ordering
>-
>- // do we need the mf.a also here?
>- mf.a // wait for any IO to complete?
>-
>- // not sure if we need serialization here, just put it, in case...
>-
>- srlz.d;;
>- srlz.i;;
>-
>- br.ret.dpnt b0;;
>-.endp MemoryFence
>-
>-.proc DisableInterrupts
>-.type DisableInterrupts, @function
>-
>-DisableInterrupts::
>- rsm 0x4000
>- srlz.d;;
>- br.ret.dpnt b0;;
>-
>-.endp DisableInterrupts
>-
>-.proc EnableInterrupts
>-.type EnableInterrupts, @function
>-
>-EnableInterrupts::
>- ssm 0x4000
>- srlz.d;;
>- br.ret.dpnt b0;;
>-
>-.endp EnableInterrupts
>-
>-.proc EnableDisableInterrupts
>-.type EnableDisableInterrupts, @function
>-
>-EnableDisableInterrupts::
>- ssm 0x4000
>- srlz.d;;
>- srlz.i;;
>- rsm 0x4000
>- srlz.d;;
>-
>- br.ret.dpnt b0;;
>-
>-.endp EnableDisableInterrupts
>-
>diff --git a/MdePkg/Library/BaseLib/Ipf/AsmPalCall.s
>b/MdePkg/Library/BaseLib/Ipf/AsmPalCall.s
>deleted file mode 100644
>index 7fd40aa2b4..0000000000
>--- a/MdePkg/Library/BaseLib/Ipf/AsmPalCall.s
>+++ /dev/null
>@@ -1,158 +0,0 @@
>-/// @file
>-/// Contains an implementation of CallPalProcStacked on Itanium-based
>-/// architecture.
>-///
>-/// Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
>-/// This program and the accompanying materials
>-/// are licensed and made available under the terms and conditions of the
>BSD License
>-/// which accompanies this distribution. The full text of the license may be
>found at
>-/// http://opensource.org/licenses/bsd-license.php.
>-///
>-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-///
>-/// Module Name: AsmPalCall.s
>-///
>-///
>-
>-
>-//-----------------------------------------------------------------------------
>-//++
>-// AsmPalCall
>-//
>-// Makes a PAL procedure call.
>-// This is function to make a PAL procedure call. Based on the Index
>-// value this API will make static or stacked PAL call. The following table
>-// describes the usage of PAL Procedure Index Assignment. Architected
>procedures
>-// may be designated as required or optional. If a PAL procedure is specified
>-// as optional, a unique return code of 0xFFFFFFFFFFFFFFFF is returned in
>the
>-// Status field of the PAL_CALL_RETURN structure.
>-// This indicates that the procedure is not present in this PAL implementation.
>-// It is the caller's responsibility to check for this return code after calling
>-// any optional PAL procedure.
>-// No parameter checking is performed on the 5 input parameters, but there
>are
>-// some common rules that the caller should follow when making a PAL call.
>Any
>-// address passed to PAL as buffers for return parameters must be 8-byte
>aligned.
>-// Unaligned addresses may cause undefined results. For those parameters
>defined
>-// as reserved or some fields defined as reserved must be zero filled or the
>invalid
>-// argument return value may be returned or undefined result may occur
>during the
>-// execution of the procedure. If the PalEntryPoint does not point to a valid
>-// PAL entry point then the system behavior is undefined. This function is
>only
>-// available on IPF.
>-//
>-// On Entry :
>-// in0: PAL_PROC entrypoint
>-// in1-in4 : PAL_PROC arguments
>-//
>-// Return Value:
>-//
>-// As per stacked calling conventions.
>-//
>-//--
>-//---------------------------------------------------------------------------
>-
>-//
>-// PAL function calls
>-//
>-#define PAL_MC_CLEAR_LOG 0x0015
>-#define PAL_MC_DYNAMIC_STATE 0x0018
>-#define PAL_MC_ERROR_INFO 0x0019
>-#define PAL_MC_RESUME 0x001a
>-
>-
>-.text
>-.proc AsmPalCall
>-.type AsmPalCall, @function
>-
>-AsmPalCall::
>- alloc loc1 = ar.pfs,5,8,4,0
>- mov loc0 = b0
>- mov loc3 = b5
>- mov loc4 = r2
>- mov loc7 = r1
>- mov r2 = psr;;
>- mov r28 = in1
>- mov loc5 = r2;;
>-
>- movl loc6 = 0x100;;
>- cmp.ge p6,p7 = r28,loc6;;
>-
>-(p6) movl loc6 = 0x1FF;;
>-(p7) br.dpnt.few PalCallStatic;; // 0 ~ 255 make a static Pal Call
>-(p6) cmp.le p6,p7 = r28,loc6;;
>-(p6) br.dpnt.few PalCallStacked;; // 256 ~ 511 make a stacked Pal
>Call
>-(p7) movl loc6 = 0x300;;
>-(p7) cmp.ge p6,p7 = r28,loc6;;
>-(p7) br.dpnt.few PalCallStatic;; // 512 ~ 767 make a static Pal Call
>-(p6) movl loc6 = 0x3FF;;
>-(p6) cmp.le p6,p7 = r28,loc6;;
>-(p6) br.dpnt.few PalCallStacked;; // 768 ~ 1023 make a stacked Pal
>Call
>-
>-(p7) mov r8 = 0xFFFFFFFFFFFFFFFF;; // > 1024 return invalid
>-(p7) br.dpnt.few ComeBackFromPALCall;;
>-
>-PalCallStatic:
>- movl loc6 = PAL_MC_CLEAR_LOG;;
>- cmp.eq p6,p7 = r28,loc6;;
>-
>-(p7) movl loc6 = PAL_MC_DYNAMIC_STATE;;
>-(p7) cmp.eq p6,p7 = r28,loc6;;
>-
>-(p7) movl loc6 = PAL_MC_ERROR_INFO;;
>-(p7) cmp.eq p6,p7 = r28,loc6;;
>-
>-(p7) movl loc6 = PAL_MC_RESUME;;
>-(p7) cmp.eq p6,p7 = r28,loc6 ;;
>-
>- mov loc6 = 0x1;;
>-(p7) dep r2 = loc6,r2,13,1;; // psr.ic = 1
>-
>-// p6 will be true, if it is one of the MCHK calls. There has been lots of debate
>-// on psr.ic for these values. For now, do not do any thing to psr.ic
>-
>- dep r2 = r0,r2,14,1;; // psr.i = 0
>-
>- mov psr.l = r2
>- srlz.d // Needs data serailization.
>- srlz.i // Needs instruction serailization.
>-
>-StaticGetPALLocalIP:
>- mov loc2 = ip;;
>- add loc2 = ComeBackFromPALCall - StaticGetPALLocalIP,loc2;;
>- mov b0 = loc2 // return address after Pal call
>-
>- mov r29 = in2
>- mov r30 = in3
>- mov r31 = in4
>- mov b5 = in0;; // get the PalProcEntrypt from input
>- br.sptk b5;; // Take the plunge.
>-
>-PalCallStacked:
>- dep r2 = r0,r2,14,1;; // psr.i = 0
>- mov psr.l = r2;;
>- srlz.d // Needs data serailization.
>- srlz.i // Needs instruction serailization.
>-
>-StackedGetPALLocalIP:
>- mov out0 = in1
>- mov out1 = in2
>- mov out2 = in3
>- mov out3 = in4
>- mov b5 = in0 ;; // get the PalProcEntrypt from input
>- br.call.dpnt b0 = b5 ;; // Take the plunge.
>-
>-ComeBackFromPALCall:
>- mov psr.l = loc5 ;;
>- srlz.d // Needs data serailization.
>- srlz.i // Needs instruction serailization.
>-
>- mov b5 = loc3
>- mov r2 = loc4
>- mov r1 = loc7
>-
>- mov b0 = loc0
>- mov ar.pfs = loc1;;
>- br.ret.dpnt b0;;
>-
>-.endp AsmPalCall
>-
>diff --git a/MdePkg/Library/BaseLib/Ipf/CpuBreakpoint.c
>b/MdePkg/Library/BaseLib/Ipf/CpuBreakpoint.c
>deleted file mode 100644
>index 302974bd5c..0000000000
>--- a/MdePkg/Library/BaseLib/Ipf/CpuBreakpoint.c
>+++ /dev/null
>@@ -1,96 +0,0 @@
>-/** @file
>- Base Library CPU functions for Itanium
>-
>- Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
>- This program and the accompanying materials
>- are licensed and made available under the terms and conditions of the BSD
>License
>- which accompanies this distribution. The full text of the license may be
>found at
>- http://opensource.org/licenses/bsd-license.php.
>-
>- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-
>-**/
>-
>-
>-#include "BaseLibInternals.h"
>-
>-/**
>- Generates a breakpoint on the CPU.
>-
>- Generates a breakpoint on the CPU. The breakpoint must be implemented
>such
>- that code can resume normal execution after the breakpoint.
>-
>-**/
>-VOID
>-EFIAPI
>-CpuBreakpoint (
>- VOID
>- )
>-{
>- __break (0);
>-}
>-
>-/**
>- Used to serialize load and store operations.
>-
>- All loads and stores that proceed calls to this function are guaranteed to be
>- globally visible when this function returns.
>-
>-**/
>-VOID
>-EFIAPI
>-MemoryFence (
>- VOID
>- )
>-{
>- __mfa ();
>-}
>-
>-/**
>- Disables CPU interrupts.
>-
>- Disables CPU interrupts.
>-
>-**/
>-VOID
>-EFIAPI
>-DisableInterrupts (
>- VOID
>- )
>-{
>- _disable ();
>-}
>-
>-/**
>- Enables CPU interrupts.
>-
>- Enables CPU interrupts.
>-
>-**/
>-VOID
>-EFIAPI
>-EnableInterrupts (
>- VOID
>- )
>-{
>- _enable ();
>-}
>-
>-/**
>- Enables CPU interrupts for the smallest window required to capture any
>- pending interrupts.
>-
>- Enables CPU interrupts for the smallest window required to capture any
>- pending interrupts.
>-
>-**/
>-VOID
>-EFIAPI
>-EnableDisableInterrupts (
>- VOID
>- )
>-{
>- EnableInterrupts ();
>- DisableInterrupts ();
>-}
>diff --git a/MdePkg/Library/BaseLib/Ipf/CpuBreakpointMsc.c
>b/MdePkg/Library/BaseLib/Ipf/CpuBreakpointMsc.c
>deleted file mode 100644
>index 89b0acfd80..0000000000
>--- a/MdePkg/Library/BaseLib/Ipf/CpuBreakpointMsc.c
>+++ /dev/null
>@@ -1,102 +0,0 @@
>-/** @file
>- Base Library CPU functions for Itanium
>-
>- Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
>- This program and the accompanying materials
>- are licensed and made available under the terms and conditions of the BSD
>License
>- which accompanies this distribution. The full text of the license may be
>found at
>- http://opensource.org/licenses/bsd-license.php.
>-
>- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-
>-**/
>-
>-
>-#include "BaseLibInternals.h"
>-
>-#pragma intrinsic (_enable)
>-#pragma intrinsic (_disable)
>-#pragma intrinsic (__break)
>-#pragma intrinsic (__mfa)
>-
>-/**
>- Generates a breakpoint on the CPU.
>-
>- Generates a breakpoint on the CPU. The breakpoint must be implemented
>such
>- that code can resume normal execution after the breakpoint.
>-
>-**/
>-VOID
>-EFIAPI
>-CpuBreakpoint (
>- VOID
>- )
>-{
>- __break (0);
>-}
>-
>-/**
>- Used to serialize load and store operations.
>-
>- All loads and stores that proceed calls to this function are guaranteed to be
>- globally visible when this function returns.
>-
>-**/
>-VOID
>-EFIAPI
>-MemoryFence (
>- VOID
>- )
>-{
>- __mfa ();
>-}
>-
>-/**
>- Disables CPU interrupts.
>-
>- Disables CPU interrupts.
>-
>-**/
>-VOID
>-EFIAPI
>-DisableInterrupts (
>- VOID
>- )
>-{
>- _disable ();
>-}
>-
>-/**
>- Enables CPU interrupts.
>-
>- Enables CPU interrupts.
>-
>-**/
>-VOID
>-EFIAPI
>-EnableInterrupts (
>- VOID
>- )
>-{
>- _enable ();
>-}
>-
>-/**
>- Enables CPU interrupts for the smallest window required to capture any
>- pending interrupts.
>-
>- Enables CPU interrupts for the smallest window required to capture any
>- pending interrupts.
>-
>-**/
>-VOID
>-EFIAPI
>-EnableDisableInterrupts (
>- VOID
>- )
>-{
>- EnableInterrupts ();
>- DisableInterrupts ();
>-}
>-
>diff --git a/MdePkg/Library/BaseLib/Ipf/CpuPause.s
>b/MdePkg/Library/BaseLib/Ipf/CpuPause.s
>deleted file mode 100644
>index d881aaa3a0..0000000000
>--- a/MdePkg/Library/BaseLib/Ipf/CpuPause.s
>+++ /dev/null
>@@ -1,25 +0,0 @@
>-/// @file
>-/// CpuPause() function for Itanium-based architecture.
>-///
>-/// Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
>-/// This program and the accompanying materials
>-/// are licensed and made available under the terms and conditions of the
>BSD License
>-/// which accompanies this distribution. The full text of the license may be
>found at
>-/// http://opensource.org/licenses/bsd-license.php.
>-///
>-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-///
>-/// Module Name: CpuPause.s
>-///
>-///
>-
>-.auto
>-.text
>-
>-.proc CpuPause
>-.type CpuPause, @function
>-CpuPause::
>- hint.i @pause
>- br.ret.sptk.many b0
>-.endp
>diff --git a/MdePkg/Library/BaseLib/Ipf/ExecFc.s
>b/MdePkg/Library/BaseLib/Ipf/ExecFc.s
>deleted file mode 100644
>index a7c4e30e9c..0000000000
>--- a/MdePkg/Library/BaseLib/Ipf/ExecFc.s
>+++ /dev/null
>@@ -1,66 +0,0 @@
>-/// @file
>-/// IPF specific AsmFc() and AsmFci () functions
>-///
>-/// Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
>-/// This program and the accompanying materials
>-/// are licensed and made available under the terms and conditions of the
>BSD License
>-/// which accompanies this distribution. The full text of the license may be
>found at
>-/// http://opensource.org/licenses/bsd-license.php.
>-///
>-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-///
>-/// Module Name: ExecFc.s
>-///
>-///
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmFc
>-//
>-// This routine is used to execute a FC instruction on the specific address.
>-//
>-// Arguments :
>-//
>-// On Entry : The specific address need to execute FC instruction.
>-//
>-// Return Value: The specific address have been execute FC instruction.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmFc, @function
>-.proc AsmFc
>-.regstk 1, 0, 0, 0
>-
>-AsmFc::
>- fc in0
>- mov r8 = in0;;
>- br.ret.dpnt b0;;
>-.endp AsmFc
>-
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmFci
>-//
>-// This routine is used to execute a FC.i instruction on the specific address.
>-//
>-// Arguments :
>-//
>-// On Entry : The specific address need to execute FC.i instruction.
>-//
>-// Return Value: The specific address have been execute FC.i instruction.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmFci, @function
>-.proc AsmFci
>-.regstk 1, 0, 0, 0
>-
>-AsmFci::
>- fc.i in0
>- mov r8 = in0;;
>- br.ret.dpnt b0;;
>-.endp AsmFci
>diff --git a/MdePkg/Library/BaseLib/Ipf/FlushCacheRange.c
>b/MdePkg/Library/BaseLib/Ipf/FlushCacheRange.c
>deleted file mode 100644
>index 5286bebcab..0000000000
>--- a/MdePkg/Library/BaseLib/Ipf/FlushCacheRange.c
>+++ /dev/null
>@@ -1,51 +0,0 @@
>-/** @file
>- AsmFlushCacheRange() function for IPF.
>-
>- Copyright (c) 2009, Intel Corporation. All rights reserved.<BR>
>- This program and the accompanying materials
>- are licensed and made available under the terms and conditions of the BSD
>License
>- which accompanies this distribution. The full text of the license may be
>found at
>- http://opensource.org/licenses/bsd-license.php.
>-
>- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-
>-**/
>-
>-
>-#include "BaseLibInternals.h"
>-
>-/**
>- Flush a range of cache lines in the cache coherency domain of the calling
>- CPU.
>-
>- Flushes the cache lines specified by Address and Length. If Address is not
>aligned
>- on a cache line boundary, then entire cache line containing Address is
>flushed.
>- If Address + Length is not aligned on a cache line boundary, then the entire
>cache
>- line containing Address + Length - 1 is flushed. This function may choose to
>flush
>- the entire cache if that is more efficient than flushing the specified range. If
>- Length is 0, the no cache lines are flushed. Address is returned.
>- This function is only available on IPF.
>-
>- If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
>-
>- @param Address The base address of the instruction lines to invalidate. If
>- the CPU is in a physical addressing mode, then Address is a
>- physical address. If the CPU is in a virtual addressing mode,
>- then Address is a virtual address.
>-
>- @param Length The number of bytes to invalidate from the instruction
>cache.
>-
>- @return Address.
>-
>-**/
>-VOID *
>-EFIAPI
>-AsmFlushCacheRange (
>- IN VOID *Address,
>- IN UINTN Length
>- )
>-{
>- ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);
>- return InternalFlushCacheRange (Address, Length);
>-}
>diff --git a/MdePkg/Library/BaseLib/Ipf/GetInterruptState.s
>b/MdePkg/Library/BaseLib/Ipf/GetInterruptState.s
>deleted file mode 100644
>index eed6794f77..0000000000
>--- a/MdePkg/Library/BaseLib/Ipf/GetInterruptState.s
>+++ /dev/null
>@@ -1,27 +0,0 @@
>-/// @file
>-/// Retrieve of the interrupt state of the running processor for the Itanium
>-/// architecture.
>-///
>-/// Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
>-/// This program and the accompanying materials
>-/// are licensed and made available under the terms and conditions of the
>BSD License
>-/// which accompanies this distribution. The full text of the license may be
>found at
>-/// http://opensource.org/licenses/bsd-license.php.
>-///
>-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-///
>-/// Module Name: GetInterruptState.s
>-///
>-///
>-
>-.auto
>-.text
>-
>-.proc GetInterruptState
>-.type GetInterruptState, @function
>-GetInterruptState::
>- mov r8 = psr
>- extr.u r8 = r8, 14, 1
>- br.ret.sptk.many b0
>-.endp GetInterruptState
>diff --git a/MdePkg/Library/BaseLib/Ipf/Ia64gen.h
>b/MdePkg/Library/BaseLib/Ipf/Ia64gen.h
>deleted file mode 100644
>index 3439f9e670..0000000000
>--- a/MdePkg/Library/BaseLib/Ipf/Ia64gen.h
>+++ /dev/null
>@@ -1,205 +0,0 @@
>-/** @file
>-
>- Register Definition for IPF.
>-
>-Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
>-This program and the accompanying materials
>-are licensed and made available under the terms and conditions of the BSD
>License
>-which accompanies this distribution. The full text of the license may be
>found at
>-http://opensource.org/licenses/bsd-license.php.
>-
>-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
>-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-
>-**/
>-#ifndef _IA64GEN_H_
>-#define _IA64GEN_H_
>-
>-#define TT_UNAT 0
>-#define C_PSR 0
>-#define J_UNAT 0
>-#define T_TYPE 0
>-#define T_IPSR 0x8
>-#define T_ISR 0x10
>-#define T_IIP 0x18
>-#define T_IFA 0x20
>-#define T_IIPA 0x28
>-#define T_IFS 0x30
>-#define T_IIM 0x38
>-#define T_RSC 0x40
>-#define T_BSP 0x48
>-#define T_BSPSTORE 0x50
>-#define T_RNAT 0x58
>-#define T_PFS 0x60
>-#define T_KBSPSTORE 0x68
>-#define T_UNAT 0x70
>-#define T_CCV 0x78
>-#define T_DCR 0x80
>-#define T_PREDS 0x88
>-#define T_NATS 0x90
>-#define T_R1 0x98
>-#define T_GP 0x98
>-#define T_R2 0xa0
>-#define T_R3 0xa8
>-#define T_R4 0xb0
>-#define T_R5 0xb8
>-#define T_R6 0xc0
>-#define T_R7 0xc8
>-#define T_R8 0xd0
>-#define T_R9 0xd8
>-#define T_R10 0xe0
>-#define T_R11 0xe8
>-#define T_R12 0xf0
>-#define T_SP 0xf0
>-#define T_R13 0xf8
>-#define T_R14 0x100
>-#define T_R15 0x108
>-#define T_R16 0x110
>-#define T_R17 0x118
>-#define T_R18 0x120
>-#define T_R19 0x128
>-#define T_R20 0x130
>-#define T_R21 0x138
>-#define T_R22 0x140
>-#define T_R23 0x148
>-#define T_R24 0x150
>-#define T_R25 0x158
>-#define T_R26 0x160
>-#define T_R27 0x168
>-#define T_R28 0x170
>-#define T_R29 0x178
>-#define T_R30 0x180
>-#define T_R31 0x188
>-#define T_F2 0x1f0
>-#define T_F3 0x200
>-#define T_F4 0x210
>-#define T_F5 0x220
>-#define T_F6 0x230
>-#define T_F7 0x240
>-#define T_F8 0x250
>-#define T_F9 0x260
>-#define T_F10 0x270
>-#define T_F11 0x280
>-#define T_F12 0x290
>-#define T_F13 0x2a0
>-#define T_F14 0x2b0
>-#define T_F15 0x2c0
>-#define T_F16 0x2d0
>-#define T_F17 0x2e0
>-#define T_F18 0x2f0
>-#define T_F19 0x300
>-#define T_F20 0x310
>-#define T_F21 0x320
>-#define T_F22 0x330
>-#define T_F23 0x340
>-#define T_F24 0x350
>-#define T_F25 0x360
>-#define T_F26 0x370
>-#define T_F27 0x380
>-#define T_F28 0x390
>-#define T_F29 0x3a0
>-#define T_F30 0x3b0
>-#define T_F31 0x3c0
>-#define T_FPSR 0x1e0
>-#define T_B0 0x190
>-#define T_B1 0x198
>-#define T_B2 0x1a0
>-#define T_B3 0x1a8
>-#define T_B4 0x1b0
>-#define T_B5 0x1b8
>-#define T_B6 0x1c0
>-#define T_B7 0x1c8
>-#define T_EC 0x1d0
>-#define T_LC 0x1d8
>-#define J_NATS 0x8
>-#define J_PFS 0x10
>-#define J_BSP 0x18
>-#define J_RNAT 0x20
>-#define J_PREDS 0x28
>-#define J_LC 0x30
>-#define J_R4 0x38
>-#define J_R5 0x40
>-#define J_R6 0x48
>-#define J_R7 0x50
>-#define J_SP 0x58
>-#define J_F2 0x60
>-#define J_F3 0x70
>-#define J_F4 0x80
>-#define J_F5 0x90
>-#define J_F16 0xa0
>-#define J_F17 0xb0
>-#define J_F18 0xc0
>-#define J_F19 0xd0
>-#define J_F20 0xe0
>-#define J_F21 0xf0
>-#define J_F22 0x100
>-#define J_F23 0x110
>-#define J_F24 0x120
>-#define J_F25 0x130
>-#define J_F26 0x140
>-#define J_F27 0x150
>-#define J_F28 0x160
>-#define J_F29 0x170
>-#define J_F30 0x180
>-#define J_F31 0x190
>-#define J_FPSR 0x1a0
>-#define J_B0 0x1a8
>-#define J_B1 0x1b0
>-#define J_B2 0x1b8
>-#define J_B3 0x1c0
>-#define J_B4 0x1c8
>-#define J_B5 0x1d0
>-#define TRAP_FRAME_LENGTH 0x3d0
>-#define C_UNAT 0x28
>-#define C_NATS 0x30
>-#define C_PFS 0x8
>-#define C_BSPSTORE 0x10
>-#define C_RNAT 0x18
>-#define C_RSC 0x20
>-#define C_PREDS 0x38
>-#define C_LC 0x40
>-#define C_DCR 0x48
>-#define C_R1 0x50
>-#define C_GP 0x50
>-#define C_R4 0x58
>-#define C_R5 0x60
>-#define C_R6 0x68
>-#define C_R7 0x70
>-#define C_SP 0x78
>-#define C_R13 0x80
>-#define C_F2 0x90
>-#define C_F3 0xa0
>-#define C_F4 0xb0
>-#define C_F5 0xc0
>-#define C_F16 0xd0
>-#define C_F17 0xe0
>-#define C_F18 0xf0
>-#define C_F19 0x100
>-#define C_F20 0x110
>-#define C_F21 0x120
>-#define C_F22 0x130
>-#define C_F23 0x140
>-#define C_F24 0x150
>-#define C_F25 0x160
>-#define C_F26 0x170
>-#define C_F27 0x180
>-#define C_F28 0x190
>-#define C_F29 0x1a0
>-#define C_F30 0x1b0
>-#define C_F31 0x1c0
>-#define C_FPSR 0x1d0
>-#define C_B0 0x1d8
>-#define C_B1 0x1e0
>-#define C_B2 0x1e8
>-#define C_B3 0x1f0
>-#define C_B4 0x1f8
>-#define C_B5 0x200
>-#define TT_R2 0x8
>-#define TT_R3 0x10
>-#define TT_R8 0x18
>-#define TT_R9 0x20
>-#define TT_R10 0x28
>-#define TT_R11 0x30
>-#define TT_R14 0x38
>-
>-#endif _IA64GEN_H
>diff --git a/MdePkg/Library/BaseLib/Ipf/InternalFlushCacheRange.s
>b/MdePkg/Library/BaseLib/Ipf/InternalFlushCacheRange.s
>deleted file mode 100644
>index 7a0b747965..0000000000
>--- a/MdePkg/Library/BaseLib/Ipf/InternalFlushCacheRange.s
>+++ /dev/null
>@@ -1,94 +0,0 @@
>-//++
>-// Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
>-// This program and the accompanying materials
>-// are licensed and made available under the terms and conditions of the BSD
>License
>-// which accompanies this distribution. The full text of the license may be
>found at
>-// http://opensource.org/licenses/bsd-license.php.
>-//
>-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-//
>-// Module Name:
>-// InternalFlushCacheRange.s
>-//
>-// Abstract:
>-// Assemble routine to flush cache lines
>-//
>-// Revision History:
>-//
>-//--
>-.file "IpfCpuCache.s"
>-
>-#include <IpfMacro.i>
>-
>-//
>-// Internal worker function to invalidate a range of instruction cache lines
>-// in the cache coherency domain of the calling CPU.
>-//
>-// Internal worker function to invalidate the instruction cache lines specified
>-// by Address and Length. If Address is not aligned on a cache line boundary,
>-// then entire instruction cache line containing Address is invalidated. If
>-// Address + Length is not aligned on a cache line boundary, then the entire
>-// instruction cache line containing Address + Length -1 is invalidated. This
>-// function may choose to invalidate the entire instruction cache if that is
>more
>-// efficient than invalidating the specified range. If Length is 0, the no
>instruction
>-// cache lines are invalidated. Address is returned.
>-// This function is only available on IPF.
>-//
>-// @param Address The base address of the instruction cache lines to
>-// invalidate. If the CPU is in a physical addressing mode, then
>-// Address is a physical address. If the CPU is in a virtual
>-// addressing mode, then Address is a virtual address.
>-//
>-// @param Length The number of bytes to invalidate from the instruction
>cache.
>-//
>-// @return Address
>-//
>-// VOID *
>-// EFIAPI
>-// InternalFlushCacheRange (
>-// IN VOID *Address,
>-// IN UINTN Length
>-// );
>-//
>-PROCEDURE_ENTRY (InternalFlushCacheRange)
>-
>- NESTED_SETUP (5,8,0,0)
>-
>- mov loc2 = ar.lc
>-
>- mov loc3 = in0 // Start address.
>- mov loc4 = in1;; // Length in bytes.
>-
>- cmp.eq p6,p7 = loc4, r0;; // If Length is zero then don't flush any
>cache
>- (p6) br.spnt.many DoneFlushingC;;
>-
>- add loc4 = loc4,loc3
>- mov loc5 = 1;;
>- sub loc4 = loc4, loc5 ;; // the End address to flush
>-
>- dep loc3 = r0,loc3,0,5
>- dep loc4 = r0,loc4,0,5;;
>- shr loc3 = loc3,5
>- shr loc4 = loc4,5;; // 32 byte cache line
>-
>- sub loc4 = loc4,loc3;; // total flush count, It should be add 1 but
>- // the br.cloop will first execute one time
>- mov loc3 = in0
>- mov loc5 = 32
>- mov ar.lc = loc4;;
>-
>-StillFlushingC:
>- fc loc3;;
>- sync.i;;
>- srlz.i;;
>- add loc3 = loc5,loc3;;
>- br.cloop.sptk.few StillFlushingC;;
>-
>-DoneFlushingC:
>- mov ar.lc = loc2
>- mov r8 = in0 // return *Address
>- NESTED_RETURN
>-
>-PROCEDURE_EXIT (InternalFlushCacheRange)
>-
>diff --git a/MdePkg/Library/BaseLib/Ipf/InternalSwitchStack.c
>b/MdePkg/Library/BaseLib/Ipf/InternalSwitchStack.c
>deleted file mode 100644
>index 35a0905aff..0000000000
>--- a/MdePkg/Library/BaseLib/Ipf/InternalSwitchStack.c
>+++ /dev/null
>@@ -1,64 +0,0 @@
>-/** @file
>- SwitchStack() function for IPF.
>-
>- Copyright (c) 2007 - 2010, Intel Corporation. All rights reserved.<BR>
>- This program and the accompanying materials
>- are licensed and made available under the terms and conditions of the BSD
>License
>- which accompanies this distribution. The full text of the license may be
>found at
>- http://opensource.org/licenses/bsd-license.php.
>-
>- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-
>-**/
>-
>-#include "BaseLibInternals.h"
>-
>-/**
>- Transfers control to a function starting with a new stack.
>-
>- Transfers control to the function specified by EntryPoint using the
>- new stack specified by NewStack and passing in the parameters specified
>- by Context1 and Context2. Context1 and Context2 are optional and may
>- be NULL. The function EntryPoint must never return.
>- Marker will be ignored on IA-32, x64, and EBC.
>- IPF CPUs expect one additional parameter of type VOID * that specifies
>- the new backing store pointer.
>-
>- If EntryPoint is NULL, then ASSERT().
>- If NewStack is NULL, then ASSERT().
>-
>- @param EntryPoint A pointer to function to call with the new stack.
>- @param Context1 A pointer to the context to pass into the EntryPoint
>- function.
>- @param Context2 A pointer to the context to pass into the EntryPoint
>- function.
>- @param NewStack A pointer to the new stack to use for the EntryPoint
>- function.
>- @param Marker VA_LIST marker for the variable argument list.
>-
>-**/
>-VOID
>-EFIAPI
>-InternalSwitchStack (
>- IN SWITCH_STACK_ENTRY_POINT EntryPoint,
>- IN VOID *Context1, OPTIONAL
>- IN VOID *Context2, OPTIONAL
>- IN VOID *NewStack,
>- IN VA_LIST Marker
>- )
>-{
>- VOID *NewBsp;
>-
>- //
>- // Get new backing store pointer from variable list
>- //
>- NewBsp = VA_ARG (Marker, VOID *);
>-
>- //
>- // New backing store pointer should be aligned with
>CPU_STACK_ALIGNMENT
>- //
>- ASSERT (((UINTN)NewBsp & (CPU_STACK_ALIGNMENT - 1)) == 0);
>-
>- AsmSwitchStackAndBackingStore (EntryPoint, Context1, Context2,
>NewStack, NewBsp);
>-}
>diff --git a/MdePkg/Library/BaseLib/Ipf/LongJmp.s
>b/MdePkg/Library/BaseLib/Ipf/LongJmp.s
>deleted file mode 100644
>index 8b5eb6408b..0000000000
>--- a/MdePkg/Library/BaseLib/Ipf/LongJmp.s
>+++ /dev/null
>@@ -1,121 +0,0 @@
>-/// @file
>-/// Contains an implementation of longjmp for the Itanium-based
>architecture.
>-///
>-/// Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
>-/// This program and the accompanying materials
>-/// are licensed and made available under the terms and conditions of the
>BSD License
>-/// which accompanies this distribution. The full text of the license may be
>found at
>-/// http://opensource.org/licenses/bsd-license.php.
>-///
>-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-///
>-/// Module Name: longjmp.s
>-///
>-///
>-
>-.auto
>-.text
>-
>-.proc InternalLongJump
>-.type InternalLongJump, @function
>-.regstk 2, 0, 0, 0
>-InternalLongJump::
>- add r10 = 0x10*20 + 8*14, in0
>- movl r2 = ~((((1 << 14) - 1) << 16) | 3)
>-
>- ld8.nt1 r14 = [r10], -8*2 // BSP, skip PFS
>- mov r15 = ar.bspstore // BSPSTORE
>-
>- ld8.nt1 r17 = [r10], -8 // UNAT after spill
>- mov r16 = ar.rsc // RSC
>- cmp.leu p6 = r14, r15
>-
>- ld8.nt1 r18 = [r10], -8 // UNAT
>- ld8.nt1 r25 = [r10], -8 // b5
>- and r2 = r16, r2
>-
>- ldf.fill.nt1 f2 = [in0], 0x10
>- ld8.nt1 r24 = [r10], -8 // b4
>- mov b5 = r25
>-
>- mov ar.rsc = r2
>- ld8.nt1 r23 = [r10], -8 // b3
>- mov b4 = r24
>-
>- ldf.fill.nt1 f3 = [in0], 0x10
>- mov ar.unat = r17
>-(p6) br.spnt.many _skip_flushrs
>-
>- flushrs
>- mov r15 = ar.bsp // New BSPSTORE
>-
>-_skip_flushrs:
>- mov r31 = ar.rnat // RNAT
>- loadrs
>-
>- ldf.fill.nt1 f4 = [in0], 0x10
>- ld8.nt1 r22 = [r10], -8
>- dep r2 = -1, r14, 3, 6
>-
>- ldf.fill.nt1 f5 = [in0], 0x10
>- ld8.nt1 r21 = [r10], -8
>- cmp.ltu p6 = r2, r15
>-
>- ld8.nt1 r20 = [r10], -0x10 // skip sp
>-(p6) ld8.nta r31 = [r2]
>- mov b3 = r23
>-
>- ldf.fill.nt1 f16 = [in0], 0x10
>- ld8.fill.nt1 r7 = [r10], -8
>- mov b2 = r22
>-
>- ldf.fill.nt1 f17 = [in0], 0x10
>- ld8.fill.nt1 r6 = [r10], -8
>- mov b1 = r21
>-
>- ldf.fill.nt1 f18 = [in0], 0x10
>- ld8.fill.nt1 r5 = [r10], -8
>- mov b0 = r20
>-
>- ldf.fill.nt1 f19 = [in0], 0x10
>- ld8.fill.nt1 r4 = [r10], 8*13
>-
>- ldf.fill.nt1 f20 = [in0], 0x10
>- ld8.nt1 r19 = [r10], 0x10 // PFS
>-
>- ldf.fill.nt1 f21 = [in0], 0x10
>- ld8.nt1 r26 = [r10], 8 // Predicate
>- mov ar.pfs = r19
>-
>- ldf.fill.nt1 f22 = [in0], 0x10
>- ld8.nt1 r27 = [r10], 8 // LC
>- mov pr = r26, -1
>-
>- ldf.fill.nt1 f23 = [in0], 0x10
>- ld8.nt1 r28 = [r10], -17*8 - 0x10
>- mov ar.lc = r27
>-
>- ldf.fill.nt1 f24 = [in0], 0x10
>- ldf.fill.nt1 f25 = [in0], 0x10
>- mov r8 = in1
>-
>- ldf.fill.nt1 f26 = [in0], 0x10
>- ldf.fill.nt1 f31 = [r10], -0x10
>-
>- ldf.fill.nt1 f27 = [in0], 0x10
>- ldf.fill.nt1 f30 = [r10], -0x10
>-
>- ldf.fill.nt1 f28 = [in0]
>- ldf.fill.nt1 f29 = [r10], 0x10*3 + 8*4
>-
>- ld8.fill.nt1 sp = [r10]
>- mov ar.unat = r18
>-
>- mov ar.bspstore = r14
>- mov ar.rnat = r31
>-
>- invala
>- mov ar.rsc = r16
>- br.ret.sptk b0
>-.endp
>diff --git a/MdePkg/Library/BaseLib/Ipf/ReadAr.s
>b/MdePkg/Library/BaseLib/Ipf/ReadAr.s
>deleted file mode 100644
>index 36efe8b3da..0000000000
>--- a/MdePkg/Library/BaseLib/Ipf/ReadAr.s
>+++ /dev/null
>@@ -1,109 +0,0 @@
>-/// @file
>-/// IPF specific application register reading functions
>-///
>-/// Copyright (c) 2008, Intel Corporation. All rights reserved.<BR>
>-/// This program and the accompanying materials
>-/// are licensed and made available under the terms and conditions of the
>BSD License
>-/// which accompanies this distribution. The full text of the license may be
>found at
>-/// http://opensource.org/licenses/bsd-license.php.
>-///
>-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-///
>-///
>-///
>-
>-
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmReadApplicationRegister
>-//
>-// Reads a 64-bit application register.
>-//
>-// Reads and returns the application register specified by Index.
>-// If Index is invalid then 0xFFFFFFFFFFFFFFFF is returned. This function is
>only available on IPF.
>-//
>-// Arguments :
>-//
>-// On Entry : The index of the application register to read.
>-//
>-// Return Value: The application register specified by Index.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmReadApplicationRegister, @function
>-.proc AsmReadApplicationRegister
>-.regstk 1, 0, 0, 0
>-
>-AsmReadApplicationRegister::
>- //
>- // ARs are defined in the ranges 0-44 and 64-66 (with some holes).
>- // Compact this list by subtracting 16 from the top range.
>- // 0-44, 64-66 -> 0-44, 48-50
>- //
>- mov r15=2
>- mov r14=pr // save predicates
>- cmp.leu p6,p7=64,in0 // p6 = AR# >= 64
>- ;;
>- (p7) cmp.leu p7,p0=48,in0 // p7 = 32 <= AR# < 64
>- (p6) add in0=-16,in0 // if (AR >= 64) AR# -= 16
>- ;;
>- (p7) mov r15=0 // if bad range (48-63)
>- ;;
>- mov ret0=-1 // in case of illegal AR #
>- shl r15=r15,in0 // r15 = 0x2 << AR#
>- ;;
>- mov pr=r15,-1
>- ;;
>- //
>- // At this point the predicates contain a bit field of the
>- // AR desired. (The bit is the AR+1, since pr0 is always 1.)
>- //
>- .pred.rel "mutex",p1,p2,p3,p4,p5,p6,p7,p8,p17,p18,p19,p20,p22,p25,\
>- p26,p27,p28,p29,p30,p31,p33,p37,p41,p45,p49,p50,p51
>- (p1) mov ret0=ar.k0 // ar0
>- (p2) mov ret0=ar.k1 // ar1
>- (p3) mov ret0=ar.k2 // ar2
>- (p4) mov ret0=ar.k3 // ar3
>- (p5) mov ret0=ar.k4 // ar4
>- (p6) mov ret0=ar.k5 // ar5
>- (p7) mov ret0=ar.k6 // ar6
>- (p8) mov ret0=ar.k7 // ar7
>-
>- (p17) mov ret0=ar.rsc // ar16
>- (p18) mov ret0=ar.bsp // ar17
>- (p19) mov ret0=ar.bspstore // ar18
>- (p20) mov ret0=ar.rnat // ar19
>-
>- (p22) mov ret0=ar.fcr // ar21 [iA32]
>-
>- (p25) mov ret0=ar.eflag // ar24 [iA32]
>- (p26) mov ret0=ar.csd // ar25 [iA32]
>- (p27) mov ret0=ar.ssd // ar26 [iA32]
>- (p28) mov ret0=ar.cflg // ar27 [iA32]
>- (p29) mov ret0=ar.fsr // ar28 [iA32]
>- (p30) mov ret0=ar.fir // ar29 [iA32]
>- (p31) mov ret0=ar.fdr // ar30 [iA32]
>-
>- (p33) mov ret0=ar.ccv // ar32
>-
>- (p37) mov ret0=ar.unat // ar36
>-
>- (p41) mov ret0=ar.fpsr // ar40
>-
>- (p45) mov ret0=ar.itc // ar44
>-
>- //
>- // This is the translated (-16) range.
>- //
>- (p49) mov ret0=ar.pfs // ar64
>- (p50) mov ret0=ar.lc // ar65
>- (p51) mov ret0=ar.ec // ar66
>-
>- // Restore predicates and return.
>-
>- mov pr=r14,-1
>- br.ret.sptk b0
>- .endp
>diff --git a/MdePkg/Library/BaseLib/Ipf/ReadCpuid.s
>b/MdePkg/Library/BaseLib/Ipf/ReadCpuid.s
>deleted file mode 100644
>index 31023847c9..0000000000
>--- a/MdePkg/Library/BaseLib/Ipf/ReadCpuid.s
>+++ /dev/null
>@@ -1,40 +0,0 @@
>-/// @file
>-/// IPF specific AsmReadCpuid()function
>-///
>-/// Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
>-/// This program and the accompanying materials
>-/// are licensed and made available under the terms and conditions of the
>BSD License
>-/// which accompanies this distribution. The full text of the license may be
>found at
>-/// http://opensource.org/licenses/bsd-license.php.
>-///
>-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-///
>-/// Module Name: ReadCpuid.s
>-///
>-///
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmReadCpuid
>-//
>-// This routine is used to Reads the current value of Processor Identifier
>Register (CPUID).
>-//
>-// Arguments :
>-//
>-// On Entry : The 8-bit Processor Identifier Register index to read.
>-//
>-// Return Value: The current value of Processor Identifier Register specified
>by Index.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmReadCpuid, @function
>-.proc AsmReadCpuid
>-.regstk 1, 0, 0, 0
>-
>-AsmReadCpuid::
>- mov r8 = cpuid[in0];;
>- br.ret.dpnt b0;;
>-.endp AsmReadCpuid
>-
>diff --git a/MdePkg/Library/BaseLib/Ipf/ReadCr.s
>b/MdePkg/Library/BaseLib/Ipf/ReadCr.s
>deleted file mode 100644
>index ef52964e5c..0000000000
>--- a/MdePkg/Library/BaseLib/Ipf/ReadCr.s
>+++ /dev/null
>@@ -1,102 +0,0 @@
>-/// @file
>-/// IPF specific control register reading functions
>-///
>-/// Copyright (c) 2008, Intel Corporation. All rights reserved.<BR>
>-/// This program and the accompanying materials
>-/// are licensed and made available under the terms and conditions of the
>BSD License
>-/// which accompanies this distribution. The full text of the license may be
>found at
>-/// http://opensource.org/licenses/bsd-license.php.
>-///
>-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-///
>-///
>-///
>-
>-
>-
>-//---------------------------------------------------------------------------------
>-//++
>-// AsmReadControlRegister
>-//
>-// Reads a 64-bit control register.
>-//
>-// Reads and returns the control register specified by Index.
>-// If Index is invalid then 0xFFFFFFFFFFFFFFFF is returned. This function is
>only available on IPF.
>-//
>-// Arguments :
>-//
>-// On Entry : The index of the control register to read.
>-//
>-// Return Value: The control register specified by Index.
>-//
>-//--
>-//----------------------------------------------------------------------------------
>-.text
>-.type AsmReadControlRegister, @function
>-.proc AsmReadControlRegister
>-.regstk 1, 0, 0, 0
>-
>-AsmReadControlRegister::
>- //
>- // CRs are defined in the ranges 0-25 and 64-81 (with some holes).
>- // Compact this list by subtracting 32 from the top range.
>- // 0-25, 64-81 -> 0-25, 32-49
>- //
>- mov r15=2
>- mov r14=pr // save predicates
>- cmp.leu p6,p7=64,in0 // p6 = CR# >= 64
>- ;;
>- (p7) cmp.leu p7,p0=32,in0 // p7 = 32 <= CR# < 64
>- (p6) add in0=-32,in0 // if (CR >= 64) CR# -= 32
>- ;;
>- (p7) mov r15=0 // if bad range (32-63)
>- ;;
>- mov ret0=-1 // in case of illegal CR #
>- shl r15=r15,in0 // r15 = 0x2 << CR#
>- ;;
>- mov pr=r15,-1
>- ;;
>-
>- //
>- // At this point the predicates contain a bit field of the
>- // CR desired. (The bit is the CR+1, since pr0 is always 1.)
>- //
>- .pred.rel "mutex",p1,p2,p3,p9,p17,p18,p20,p21,p22,p23,p24,p25,p26,\
>- p33,p34,p35,p36,p37,p38,p39,p40,p41,p42,p43,p49,p50
>- (p1) mov ret0=cr.dcr // cr0
>- (p2) mov ret0=cr.itm // cr1
>- (p3) mov ret0=cr.iva // cr2
>- (p9) mov ret0=cr.pta // cr8
>- (p17) mov ret0=cr.ipsr // cr16
>- (p18) mov ret0=cr.isr // cr17
>- (p20) mov ret0=cr.iip // cr19
>- (p21) mov ret0=cr.ifa // cr20
>- (p22) mov ret0=cr.itir // cr21
>- (p23) mov ret0=cr.iipa // cr22
>- (p24) mov ret0=cr.ifs // cr23
>- (p25) mov ret0=cr.iim // cr24
>- (p26) mov ret0=cr.iha // cr25
>-
>- // This is the translated (-32) range.
>-
>- (p33) mov ret0=cr.lid // cr64
>- (p34) mov ret0=cr.ivr // cr65
>- (p35) mov ret0=cr.tpr // cr66
>- (p36) mov ret0=cr.eoi // cr67
>- (p37) mov ret0=cr.irr0 // cr68
>- (p38) mov ret0=cr.irr1 // cr69
>- (p39) mov ret0=cr.irr2 // cr70
>- (p40) mov ret0=cr.irr3 // cr71
>- (p41) mov ret0=cr.itv // cr72
>- (p42) mov ret0=cr.pmv // cr73
>- (p43) mov ret0=cr.cmcv // cr74
>- (p49) mov ret0=cr.lrr0 // cr80
>- (p50) mov ret0=cr.lrr1 // cr81
>-
>- //
>- // Restore predicates and return.
>- //
>- mov pr=r14,-1
>- br.ret.sptk b0
>- .endp
>diff --git a/MdePkg/Library/BaseLib/Ipf/SetJmp.s
>b/MdePkg/Library/BaseLib/Ipf/SetJmp.s
>deleted file mode 100644
>index 71467f5ce4..0000000000
>--- a/MdePkg/Library/BaseLib/Ipf/SetJmp.s
>+++ /dev/null
>@@ -1,108 +0,0 @@
>-/// @file
>-/// Contains an implementation of longjmp for the Itanium-based
>architecture.
>-///
>-/// Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
>-/// This program and the accompanying materials
>-/// are licensed and made available under the terms and conditions of the
>BSD License
>-/// which accompanies this distribution. The full text of the license may be
>found at
>-/// http://opensource.org/licenses/bsd-license.php.
>-///
>-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-///
>-/// Module Name: longjmp.s
>-///
>-///
>-
>-.auto
>-.text
>-
>-ASM_GLOBAL InternalAssertJumpBuffer
>-.type InternalAssertJumpBuffer, @function
>-
>-.proc SetJump
>-.type SetJump, @function
>-SetJump::
>- alloc loc0 = ar.pfs, 1, 2, 1, 0
>- mov loc1 = b0
>- mov out0 = in0
>-
>- brl.call.sptk.many b0 = InternalAssertJumpBuffer
>-
>- mov r14 = ar.unat
>- mov r15 = ar.bsp
>- add r10 = 0x10*20, in0
>-
>- stf.spill.nta [in0] = f2, 0x10
>- st8.spill.nta [r10] = r4, 8
>- mov r21 = b1
>-
>- stf.spill.nta [in0] = f3, 0x10
>- st8.spill.nta [r10] = r5, 8
>- mov r22 = b2
>-
>- stf.spill.nta [in0] = f4, 0x10
>- st8.spill.nta [r10] = r6, 8
>- mov r23 = b3
>-
>- stf.spill.nta [in0] = f5, 0x10
>- st8.spill.nta [r10] = r7, 8
>- mov r24 = b4
>-
>- stf.spill.nta [in0] = f16, 0x10
>- st8.spill.nta [r10] = sp, 8
>- mov r25 = b5
>-
>- stf.spill.nta [in0] = f17, 0x10
>- st8.nta [r10] = loc1, 8
>- mov r16 = pr
>-
>- stf.spill.nta [in0] = f18, 0x10
>- st8.nta [r10] = r21, 8
>- mov r17 = ar.lc
>-
>- stf.spill.nta [in0] = f19, 0x10
>- st8.nta [r10] = r22, 8
>-
>- stf.spill.nta [in0] = f20, 0x10
>- st8.nta [r10] = r23, 8
>-
>- stf.spill.nta [in0] = f21, 0x10
>- st8.nta [r10] = r24, 8
>-
>- stf.spill.nta [in0] = f22, 0x10
>- st8.nta [r10] = r25, 8
>-
>- stf.spill.nta [in0] = f23, 0x10
>- mov r18 = ar.unat
>-
>- stf.spill.nta [in0] = f24, 0x10
>- st8.nta [r10] = r14, 8 // UNAT
>-
>- stf.spill.nta [in0] = f25, 0x10
>- st8.nta [r10] = r18, 8 // UNAT after spill
>-
>- stf.spill.nta [in0] = f26, 0x10
>- st8.nta [r10] = loc0, 8 // PFS
>-
>- stf.spill.nta [in0] = f27, 0x10
>- st8.nta [r10] = r15, 8 // BSP
>- mov r8 = 0
>-
>- stf.spill.nta [in0] = f28, 0x10
>- mov r19 = ar.fpsr
>-
>- stf.spill.nta [in0] = f29, 0x10
>- st8.nta [r10] = r16, 8 // PR
>- mov ar.pfs = loc0
>-
>- stf.spill.nta [in0] = f30, 0x10
>- st8.nta [r10] = r17, 8 // LC
>- mov b0 = loc1
>-
>- stf.spill.nta [in0] = f31, 0x10
>- st8.nta [r10] = r19 // FPSR
>-
>- mov ar.unat = r14
>- br.ret.sptk b0
>-.endp SetJump
>diff --git a/MdePkg/Library/BaseLib/Ipf/SwitchStack.s
>b/MdePkg/Library/BaseLib/Ipf/SwitchStack.s
>deleted file mode 100644
>index 1236bbe947..0000000000
>--- a/MdePkg/Library/BaseLib/Ipf/SwitchStack.s
>+++ /dev/null
>@@ -1,52 +0,0 @@
>-/// @file
>-/// IPF specific SwitchStack() function
>-///
>-/// Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
>-/// This program and the accompanying materials
>-/// are licensed and made available under the terms and conditions of the
>BSD License
>-/// which accompanies this distribution. The full text of the license may be
>found at
>-/// http://opensource.org/licenses/bsd-license.php.
>-///
>-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-///
>-/// Module Name: SwitchStack.s
>-///
>-///
>-
>-.auto
>-.text
>-
>-.proc AsmSwitchStackAndBackingStore
>-.type AsmSwitchStackAndBackingStore, @function
>-.regstk 5, 0, 0, 0
>-AsmSwitchStackAndBackingStore::
>- mov r14 = ar.rsc
>- movl r2 = ~((((1 << 14) - 1) << 16) | 3)
>-
>- mov r17 = in1
>- mov r18 = in2
>- and r2 = r14, r2
>-
>- flushrs
>-
>- mov ar.rsc = r2
>- mov sp = in3
>- mov r19 = in4
>-
>- ld8.nt1 r16 = [in0], 8
>- ld8.nta gp = [in0]
>- mov r3 = -1
>-
>- loadrs
>- mov ar.bspstore = r19
>- mov b7 = r16
>-
>- alloc r2 = ar.pfs, 0, 0, 2, 0
>- mov out0 = r17
>- mov out1 = r18
>-
>- mov ar.rnat = r3
>- mov ar.rsc = r14
>- br.call.sptk.many b0 = b7
>-.endp AsmSwitchStackAndBackingStore
>diff --git a/MdePkg/Library/BaseLib/Ipf/Unaligned.c
>b/MdePkg/Library/BaseLib/Ipf/Unaligned.c
>deleted file mode 100644
>index 7d0d8ddc02..0000000000
>--- a/MdePkg/Library/BaseLib/Ipf/Unaligned.c
>+++ /dev/null
>@@ -1,243 +0,0 @@
>-/** @file
>- Unaligned access functions of BaseLib for IPF.
>-
>- Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
>- This program and the accompanying materials
>- are licensed and made available under the terms and conditions of the BSD
>License
>- which accompanies this distribution. The full text of the license may be
>found at
>- http://opensource.org/licenses/bsd-license.php.
>-
>- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-
>-**/
>-
>-#include "BaseLibInternals.h"
>-
>-/**
>- Reads a 16-bit value from memory that may be unaligned.
>-
>- This function returns the 16-bit value pointed to by Buffer. The function
>- guarantees that the read operation does not produce an alignment fault.
>-
>- If the Buffer is NULL, then ASSERT().
>-
>- @param Buffer The pointer to a 16-bit value that may be unaligned.
>-
>- @return The 16-bit value read from Buffer.
>-
>-**/
>-UINT16
>-EFIAPI
>-ReadUnaligned16 (
>- IN CONST UINT16 *Buffer
>- )
>-{
>- ASSERT (Buffer != NULL);
>-
>- return (UINT16)(((UINT8*)Buffer)[0] | (((UINT8*)Buffer)[1] << 8));
>-}
>-
>-/**
>- Writes a 16-bit value to memory that may be unaligned.
>-
>- This function writes the 16-bit value specified by Value to Buffer. Value is
>- returned. The function guarantees that the write operation does not
>produce
>- an alignment fault.
>-
>- If the Buffer is NULL, then ASSERT().
>-
>- @param Buffer The pointer to a 16-bit value that may be unaligned.
>- @param Value The 16-bit value to write to Buffer.
>-
>- @return The 16-bit value to write to Buffer.
>-
>-**/
>-UINT16
>-EFIAPI
>-WriteUnaligned16 (
>- OUT UINT16 *Buffer,
>- IN UINT16 Value
>- )
>-{
>- ASSERT (Buffer != NULL);
>-
>- ((UINT8*)Buffer)[0] = (UINT8)Value;
>- ((UINT8*)Buffer)[1] = (UINT8)(Value >> 8);
>-
>- return Value;
>-}
>-
>-/**
>- Reads a 24-bit value from memory that may be unaligned.
>-
>- This function returns the 24-bit value pointed to by Buffer. The function
>- guarantees that the read operation does not produce an alignment fault.
>-
>- If the Buffer is NULL, then ASSERT().
>-
>- @param Buffer The pointer to a 24-bit value that may be unaligned.
>-
>- @return The 24-bit value read from Buffer.
>-
>-**/
>-UINT32
>-EFIAPI
>-ReadUnaligned24 (
>- IN CONST UINT32 *Buffer
>- )
>-{
>- ASSERT (Buffer != NULL);
>-
>- return (UINT32)(
>- ReadUnaligned16 ((UINT16*)Buffer) |
>- (((UINT8*)Buffer)[2] << 16)
>- );
>-}
>-
>-/**
>- Writes a 24-bit value to memory that may be unaligned.
>-
>- This function writes the 24-bit value specified by Value to Buffer. Value is
>- returned. The function guarantees that the write operation does not
>produce
>- an alignment fault.
>-
>- If the Buffer is NULL, then ASSERT().
>-
>- @param Buffer The pointer to a 24-bit value that may be unaligned.
>- @param Value The 24-bit value to write to Buffer.
>-
>- @return The 24-bit value to write to Buffer.
>-
>-**/
>-UINT32
>-EFIAPI
>-WriteUnaligned24 (
>- OUT UINT32 *Buffer,
>- IN UINT32 Value
>- )
>-{
>- ASSERT (Buffer != NULL);
>-
>- WriteUnaligned16 ((UINT16*)Buffer, (UINT16)Value);
>- *(UINT8*)((UINT16*)Buffer + 1) = (UINT8)(Value >> 16);
>- return Value;
>-}
>-
>-/**
>- Reads a 32-bit value from memory that may be unaligned.
>-
>- This function returns the 32-bit value pointed to by Buffer. The function
>- guarantees that the read operation does not produce an alignment fault.
>-
>- If the Buffer is NULL, then ASSERT().
>-
>- @param Buffer The pointer to a 32-bit value that may be unaligned.
>-
>- @return The 32-bit value read from Buffer.
>-
>-**/
>-UINT32
>-EFIAPI
>-ReadUnaligned32 (
>- IN CONST UINT32 *Buffer
>- )
>-{
>- UINT16 LowerBytes;
>- UINT16 HigherBytes;
>-
>- ASSERT (Buffer != NULL);
>-
>- LowerBytes = ReadUnaligned16 ((UINT16*) Buffer);
>- HigherBytes = ReadUnaligned16 ((UINT16*) Buffer + 1);
>-
>- return (UINT32) (LowerBytes | (HigherBytes << 16));
>-}
>-
>-/**
>- Writes a 32-bit value to memory that may be unaligned.
>-
>- This function writes the 32-bit value specified by Value to Buffer. Value is
>- returned. The function guarantees that the write operation does not
>produce
>- an alignment fault.
>-
>- If the Buffer is NULL, then ASSERT().
>-
>- @param Buffer The pointer to a 32-bit value that may be unaligned.
>- @param Value The 32-bit value to write to Buffer.
>-
>- @return The 32-bit value to write to Buffer.
>-
>-**/
>-UINT32
>-EFIAPI
>-WriteUnaligned32 (
>- OUT UINT32 *Buffer,
>- IN UINT32 Value
>- )
>-{
>- ASSERT (Buffer != NULL);
>-
>- WriteUnaligned16 ((UINT16*)Buffer, (UINT16)Value);
>- WriteUnaligned16 ((UINT16*)Buffer + 1, (UINT16)(Value >> 16));
>- return Value;
>-}
>-
>-/**
>- Reads a 64-bit value from memory that may be unaligned.
>-
>- This function returns the 64-bit value pointed to by Buffer. The function
>- guarantees that the read operation does not produce an alignment fault.
>-
>- If the Buffer is NULL, then ASSERT().
>-
>- @param Buffer The pointer to a 64-bit value that may be unaligned.
>-
>- @return The 64-bit value read from Buffer.
>-
>-**/
>-UINT64
>-EFIAPI
>-ReadUnaligned64 (
>- IN CONST UINT64 *Buffer
>- )
>-{
>- UINT32 LowerBytes;
>- UINT32 HigherBytes;
>-
>- ASSERT (Buffer != NULL);
>-
>- LowerBytes = ReadUnaligned32 ((UINT32*) Buffer);
>- HigherBytes = ReadUnaligned32 ((UINT32*) Buffer + 1);
>-
>- return (UINT64) (LowerBytes | LShiftU64 (HigherBytes, 32));
>-}
>-
>-/**
>- Writes a 64-bit value to memory that may be unaligned.
>-
>- This function writes the 64-bit value specified by Value to Buffer. Value is
>- returned. The function guarantees that the write operation does not
>produce
>- an alignment fault.
>-
>- If the Buffer is NULL, then ASSERT().
>-
>- @param Buffer The pointer to a 64-bit value that may be unaligned.
>- @param Value The 64-bit value to write to Buffer.
>-
>- @return The 64-bit value to write to Buffer.
>-
>-**/
>-UINT64
>-EFIAPI
>-WriteUnaligned64 (
>- OUT UINT64 *Buffer,
>- IN UINT64 Value
>- )
>-{
>- ASSERT (Buffer != NULL);
>-
>- WriteUnaligned32 ((UINT32*)Buffer, (UINT32)Value);
>- WriteUnaligned32 ((UINT32*)Buffer + 1, (UINT32)RShiftU64 (Value, 32));
>- return Value;
>-}
>diff --git a/MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
>b/MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
>index 358eeed4f4..7c82ca9a19 100644
>--- a/MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
>+++ b/MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
>@@ -26,7 +26,7 @@
>
>
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC ARM AARCH64
>+# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64
> #
>
> [Sources]
>diff --git
>a/MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib/BaseOrderedColle
>ctionRedBlackTreeLib.inf
>b/MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib/BaseOrderedColle
>ctionRedBlackTreeLib.inf
>index a68afc8861..eaad44257f 100644
>---
>a/MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib/BaseOrderedColle
>ctionRedBlackTreeLib.inf
>+++
>b/MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib/BaseOrderedColle
>ctionRedBlackTreeLib.inf
>@@ -33,7 +33,7 @@
> LIBRARY_CLASS = OrderedCollectionLib
>
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
>+# VALID_ARCHITECTURES = IA32 X64 EBC
> #
>
> [Sources]
>diff --git a/MdePkg/Library/BasePalLibNull/BasePalLibNull.inf
>b/MdePkg/Library/BasePalLibNull/BasePalLibNull.inf
>deleted file mode 100644
>index 927c6d34c4..0000000000
>--- a/MdePkg/Library/BasePalLibNull/BasePalLibNull.inf
>+++ /dev/null
>@@ -1,40 +0,0 @@
>-## @file
>-# Null instance of PAL Library with empty functions.
>-#
>-# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
>-#
>-# This program and the accompanying materials
>-# are licensed and made available under the terms and conditions of the BSD
>License
>-# which accompanies this distribution. The full text of the license may be
>found at
>-# http://opensource.org/licenses/bsd-license.php.
>-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-#
>-#
>-##
>-
>-[Defines]
>- INF_VERSION = 0x00010005
>- BASE_NAME = BasePalLibNull
>- MODULE_UNI_FILE = BasePalLibNull.uni
>- FILE_GUID = 632D5625-B73D-43b8-AF30-8D225D96168E
>- MODULE_TYPE = BASE
>- VERSION_STRING = 1.0
>- LIBRARY_CLASS = PalLib
>-
>-
>-#
>-# VALID_ARCHITECTURES = IPF
>-#
>-
>-[Sources]
>- PalCall.c
>-
>-
>-[Packages]
>- MdePkg/MdePkg.dec
>-
>-
>-[LibraryClasses]
>- DebugLib
>-
>diff --git a/MdePkg/Library/BasePalLibNull/PalCall.c
>b/MdePkg/Library/BasePalLibNull/PalCall.c
>deleted file mode 100644
>index 174c28ee67..0000000000
>--- a/MdePkg/Library/BasePalLibNull/PalCall.c
>+++ /dev/null
>@@ -1,59 +0,0 @@
>-/** @file
>-
>- Template and Sample instance of PalCallLib.
>-
>- Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
>- This program and the accompanying materials
>- are licensed and made available under the terms and conditions of the BSD
>License
>- which accompanies this distribution. The full text of the license may be
>found at
>- http://opensource.org/licenses/bsd-license.php.
>-
>- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-
>-**/
>-
>-#include <Base.h>
>-#include <Library/PalLib.h>
>-#include <Library/DebugLib.h>
>-
>-/**
>- Makes a PAL procedure call.
>-
>- This is a wrapper function to make a PAL procedure call. Based on the Index
>value,
>- this API will make static or stacked PAL call. Architected procedures may be
>designated
>- as required or optional. If a PAL procedure is specified as optional, a unique
>return
>- code of 0xFFFFFFFFFFFFFFFF is returned in the Status field of the
>PAL_CALL_RETURN structure.
>- This indicates that the procedure is not present in this PAL implementation.
>It is the
>- caller's responsibility to check for this return code after calling any optional
>PAL
>- procedure. No parameter checking is performed on the 4 input parameters,
>but there are
>- some common rules that the caller should follow when making a PAL call.
>Any address
>- passed to PAL as buffers for return parameters must be 8-byte aligned.
>Unaligned addresses
>- may cause undefined results. For those parameters defined as reserved or
>some fields
>- defined as reserved must be zero filled or the invalid argument return value
>may be
>- returned or undefined result may occur during the execution of the
>procedure.
>- This function is only available on IPF.
>-
>- @param Index The PAL procedure Index number.
>- @param Arg2 The 2nd parameter for PAL procedure calls.
>- @param Arg3 The 3rd parameter for PAL procedure calls.
>- @param Arg4 The 4th parameter for PAL procedure calls.
>-
>- @return The structure returned from the PAL Call procedure, including the
>status and return value.
>-
>-**/
>-PAL_CALL_RETURN
>-EFIAPI
>-PalCall (
>- IN UINT64 Index,
>- IN UINT64 Arg2,
>- IN UINT64 Arg3,
>- IN UINT64 Arg4
>- )
>-{
>- PAL_CALL_RETURN Ret;
>-
>- Ret.Status = (UINT64) -1;
>- ASSERT (!RETURN_ERROR (RETURN_UNSUPPORTED));
>- return Ret;
>-}
>diff --git a/MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
>b/MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
>index 4b511b336c..15e19a7454 100644
>--- a/MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
>+++ b/MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
>@@ -27,7 +27,7 @@
>
>
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
>+# VALID_ARCHITECTURES = IA32 X64 EBC
> #
>
> [Sources]
>diff --git a/MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf
>b/MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf
>index 17b81e076a..e39ea3e5b8 100644
>--- a/MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf
>+++ b/MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf
>@@ -26,7 +26,7 @@
> LIBRARY_CLASS = PciCf8Lib
>
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
>+# VALID_ARCHITECTURES = IA32 X64 EBC
> #
>
> [Sources]
>diff --git a/MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
>b/MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
>index 4b14b5d89e..db817409c2 100644
>--- a/MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
>+++ b/MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
>@@ -26,7 +26,7 @@
> LIBRARY_CLASS = PciExpressLib
>
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
>+# VALID_ARCHITECTURES = IA32 X64 EBC
> #
>
> [Sources]
>diff --git a/MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf
>b/MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf
>index 9409332cb5..443534d2b8 100644
>--- a/MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf
>+++ b/MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf
>@@ -26,7 +26,7 @@
> LIBRARY_CLASS = PciLib
>
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
>+# VALID_ARCHITECTURES = IA32 X64 EBC
> #
>
> [Sources]
>diff --git a/MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
>b/MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
>index 6ccd54ff9d..05c82d1bcf 100644
>--- a/MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
>+++ b/MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
>@@ -27,7 +27,7 @@
>
>
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC ARM AARCH64
>+# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64
> #
>
> [Sources]
>diff --git
>a/MdePkg/Library/BasePciSegmentInfoLibNull/BasePciSegmentInfoLibNull.in
>f
>b/MdePkg/Library/BasePciSegmentInfoLibNull/BasePciSegmentInfoLibNull.in
>f
>index 5ae59fb2be..0d759fb8cd 100644
>---
>a/MdePkg/Library/BasePciSegmentInfoLibNull/BasePciSegmentInfoLibNull.in
>f
>+++
>b/MdePkg/Library/BasePciSegmentInfoLibNull/BasePciSegmentInfoLibNull.in
>f
>@@ -27,7 +27,7 @@
> #
> # The following information is for reference only and not required by the
>build tools.
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
>+# VALID_ARCHITECTURES = IA32 X64 EBC
> #
>
> [Sources]
>diff --git a/MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
>b/MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
>index 7dbb22282e..67a308fe71 100644
>--- a/MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
>+++ b/MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
>@@ -28,7 +28,7 @@
> #
> # The following information is for reference only and not required by the
>build tools.
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
>+# VALID_ARCHITECTURES = IA32 X64 EBC
> #
>
> [Sources]
>diff --git
>a/MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibN
>ull.inf
>b/MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibN
>ull.inf
>index ecc770aca7..f24bd01c3a 100644
>---
>a/MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibN
>ull.inf
>+++
>b/MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibN
>ull.inf
>@@ -24,7 +24,7 @@
>
>
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
>+# VALID_ARCHITECTURES = IA32 X64 EBC
> #
>
> [Sources]
>diff --git
>a/MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib
>.inf
>b/MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib
>.inf
>index b6eed82d5f..d30347ca57 100644
>---
>a/MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib
>.inf
>+++
>b/MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib
>.inf
>@@ -24,7 +24,7 @@
>
>
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
>+# VALID_ARCHITECTURES = IA32 X64 EBC
> #
>
> [Sources]
>diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
>b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
>index ff0580fbdf..fa6613241a 100644
>--- a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
>+++ b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
>@@ -33,7 +33,7 @@
>
>
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC ARM AARCH64
>+# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64
> #
>
> [Sources]
>@@ -43,9 +43,6 @@
> [Sources.IA32, Sources.X64, Sources.EBC, Sources.AARCH64]
> PeCoffLoaderEx.c
>
>-[Sources.IPF]
>- Ipf/PeCoffLoaderEx.c
>-
> [Sources.ARM]
> Arm/PeCoffLoaderEx.c
>
>diff --git a/MdePkg/Library/BasePeCoffLib/Ipf/PeCoffLoaderEx.c
>b/MdePkg/Library/BasePeCoffLib/Ipf/PeCoffLoaderEx.c
>deleted file mode 100644
>index 96e122b698..0000000000
>--- a/MdePkg/Library/BasePeCoffLib/Ipf/PeCoffLoaderEx.c
>+++ /dev/null
>@@ -1,422 +0,0 @@
>-/** @file
>- Fixes Intel Itanium(TM) specific relocation types.
>-
>- Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
>- This program and the accompanying materials
>- are licensed and made available under the terms and conditions of the BSD
>License
>- which accompanies this distribution. The full text of the license may be
>found at
>- http://opensource.org/licenses/bsd-license.php.
>-
>- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-
>-**/
>-
>-#include "BasePeCoffLibInternals.h"
>-
>-
>-
>-#define EXT_IMM64(Value, Address, Size, InstPos, ValPos) \
>- Value |= (((UINT64)((*(Address) >> InstPos) & (((UINT64)1 << Size) - 1)))
><< ValPos)
>-
>-#define INS_IMM64(Value, Address, Size, InstPos, ValPos) \
>- *(UINT32*)Address = (*(UINT32*)Address & ~(((1 << Size) - 1) << InstPos))
>| \
>- ((UINT32)((((UINT64)Value >> ValPos) & (((UINT64)1 << Size) - 1))) <<
>InstPos)
>-
>-#define IMM64_IMM7B_INST_WORD_X 3
>-#define IMM64_IMM7B_SIZE_X 7
>-#define IMM64_IMM7B_INST_WORD_POS_X 4
>-#define IMM64_IMM7B_VAL_POS_X 0
>-
>-#define IMM64_IMM9D_INST_WORD_X 3
>-#define IMM64_IMM9D_SIZE_X 9
>-#define IMM64_IMM9D_INST_WORD_POS_X 18
>-#define IMM64_IMM9D_VAL_POS_X 7
>-
>-#define IMM64_IMM5C_INST_WORD_X 3
>-#define IMM64_IMM5C_SIZE_X 5
>-#define IMM64_IMM5C_INST_WORD_POS_X 13
>-#define IMM64_IMM5C_VAL_POS_X 16
>-
>-#define IMM64_IC_INST_WORD_X 3
>-#define IMM64_IC_SIZE_X 1
>-#define IMM64_IC_INST_WORD_POS_X 12
>-#define IMM64_IC_VAL_POS_X 21
>-
>-#define IMM64_IMM41A_INST_WORD_X 1
>-#define IMM64_IMM41A_SIZE_X 10
>-#define IMM64_IMM41A_INST_WORD_POS_X 14
>-#define IMM64_IMM41A_VAL_POS_X 22
>-
>-#define IMM64_IMM41B_INST_WORD_X 1
>-#define IMM64_IMM41B_SIZE_X 8
>-#define IMM64_IMM41B_INST_WORD_POS_X 24
>-#define IMM64_IMM41B_VAL_POS_X 32
>-
>-#define IMM64_IMM41C_INST_WORD_X 2
>-#define IMM64_IMM41C_SIZE_X 23
>-#define IMM64_IMM41C_INST_WORD_POS_X 0
>-#define IMM64_IMM41C_VAL_POS_X 40
>-
>-#define IMM64_SIGN_INST_WORD_X 3
>-#define IMM64_SIGN_SIZE_X 1
>-#define IMM64_SIGN_INST_WORD_POS_X 27
>-#define IMM64_SIGN_VAL_POS_X 63
>-
>-/**
>- Performs an Itanium-based specific relocation fixup.
>-
>- @param Reloc The pointer to the relocation record.
>- @param Fixup The pointer to the address to fix up.
>- @param FixupData The pointer to a buffer to log the fixups.
>- @param Adjust The offset to adjust the fixup.
>-
>- @retval RETURN_SUCCESS Succeed to fix the relocation entry.
>- @retval RETURN_UNSUPPOTED Unrecoganized relocation entry.
>-
>-**/
>-RETURN_STATUS
>-PeCoffLoaderRelocateImageEx (
>- IN UINT16 *Reloc,
>- IN OUT CHAR8 *Fixup,
>- IN OUT CHAR8 **FixupData,
>- IN UINT64 Adjust
>- )
>-{
>- UINT64 *Fixup64;
>- UINT64 FixupVal;
>-
>- switch ((*Reloc) >> 12) {
>- case EFI_IMAGE_REL_BASED_IA64_IMM64:
>-
>- //
>- // Align it to bundle address before fixing up the
>- // 64-bit immediate value of the movl instruction.
>- //
>-
>- Fixup = (CHAR8 *)((UINTN) Fixup & (UINTN) ~(15));
>- FixupVal = (UINT64)0;
>-
>- //
>- // Extract the lower 32 bits of IMM64 from bundle
>- //
>- EXT_IMM64(FixupVal,
>- (UINT32 *)Fixup + IMM64_IMM7B_INST_WORD_X,
>- IMM64_IMM7B_SIZE_X,
>- IMM64_IMM7B_INST_WORD_POS_X,
>- IMM64_IMM7B_VAL_POS_X
>- );
>-
>- EXT_IMM64(FixupVal,
>- (UINT32 *)Fixup + IMM64_IMM9D_INST_WORD_X,
>- IMM64_IMM9D_SIZE_X,
>- IMM64_IMM9D_INST_WORD_POS_X,
>- IMM64_IMM9D_VAL_POS_X
>- );
>-
>- EXT_IMM64(FixupVal,
>- (UINT32 *)Fixup + IMM64_IMM5C_INST_WORD_X,
>- IMM64_IMM5C_SIZE_X,
>- IMM64_IMM5C_INST_WORD_POS_X,
>- IMM64_IMM5C_VAL_POS_X
>- );
>-
>- EXT_IMM64(FixupVal,
>- (UINT32 *)Fixup + IMM64_IC_INST_WORD_X,
>- IMM64_IC_SIZE_X,
>- IMM64_IC_INST_WORD_POS_X,
>- IMM64_IC_VAL_POS_X
>- );
>-
>- EXT_IMM64(FixupVal,
>- (UINT32 *)Fixup + IMM64_IMM41A_INST_WORD_X,
>- IMM64_IMM41A_SIZE_X,
>- IMM64_IMM41A_INST_WORD_POS_X,
>- IMM64_IMM41A_VAL_POS_X
>- );
>-
>- //
>- // Update 64-bit address
>- //
>- FixupVal += Adjust;
>-
>- //
>- // Insert IMM64 into bundle
>- //
>- INS_IMM64(FixupVal,
>- ((UINT32 *)Fixup + IMM64_IMM7B_INST_WORD_X),
>- IMM64_IMM7B_SIZE_X,
>- IMM64_IMM7B_INST_WORD_POS_X,
>- IMM64_IMM7B_VAL_POS_X
>- );
>-
>- INS_IMM64(FixupVal,
>- ((UINT32 *)Fixup + IMM64_IMM9D_INST_WORD_X),
>- IMM64_IMM9D_SIZE_X,
>- IMM64_IMM9D_INST_WORD_POS_X,
>- IMM64_IMM9D_VAL_POS_X
>- );
>-
>- INS_IMM64(FixupVal,
>- ((UINT32 *)Fixup + IMM64_IMM5C_INST_WORD_X),
>- IMM64_IMM5C_SIZE_X,
>- IMM64_IMM5C_INST_WORD_POS_X,
>- IMM64_IMM5C_VAL_POS_X
>- );
>-
>- INS_IMM64(FixupVal,
>- ((UINT32 *)Fixup + IMM64_IC_INST_WORD_X),
>- IMM64_IC_SIZE_X,
>- IMM64_IC_INST_WORD_POS_X,
>- IMM64_IC_VAL_POS_X
>- );
>-
>- INS_IMM64(FixupVal,
>- ((UINT32 *)Fixup + IMM64_IMM41A_INST_WORD_X),
>- IMM64_IMM41A_SIZE_X,
>- IMM64_IMM41A_INST_WORD_POS_X,
>- IMM64_IMM41A_VAL_POS_X
>- );
>-
>- INS_IMM64(FixupVal,
>- ((UINT32 *)Fixup + IMM64_IMM41B_INST_WORD_X),
>- IMM64_IMM41B_SIZE_X,
>- IMM64_IMM41B_INST_WORD_POS_X,
>- IMM64_IMM41B_VAL_POS_X
>- );
>-
>- INS_IMM64(FixupVal,
>- ((UINT32 *)Fixup + IMM64_IMM41C_INST_WORD_X),
>- IMM64_IMM41C_SIZE_X,
>- IMM64_IMM41C_INST_WORD_POS_X,
>- IMM64_IMM41C_VAL_POS_X
>- );
>-
>- INS_IMM64(FixupVal,
>- ((UINT32 *)Fixup + IMM64_SIGN_INST_WORD_X),
>- IMM64_SIGN_SIZE_X,
>- IMM64_SIGN_INST_WORD_POS_X,
>- IMM64_SIGN_VAL_POS_X
>- );
>-
>- Fixup64 = (UINT64 *) Fixup;
>- if (*FixupData != NULL) {
>- *FixupData = ALIGN_POINTER(*FixupData, sizeof(UINT64));
>- *(UINT64 *)(*FixupData) = *Fixup64;
>- *FixupData = *FixupData + sizeof(UINT64);
>- }
>- break;
>-
>- default:
>- return RETURN_UNSUPPORTED;
>- }
>-
>- return RETURN_SUCCESS;
>-}
>-
>-/**
>- Returns TRUE if the machine type of PE/COFF image is supported.
>Supported
>- does not mean the image can be executed it means the PE/COFF loader
>supports
>- loading and relocating of the image type. It's up to the caller to support
>- the entry point.
>-
>- The itanium version PE/COFF loader/relocater supports itanium and EBC
>image.
>-
>- @param Machine Machine type from the PE Header.
>-
>- @return TRUE if this PE/COFF loader can load the image
>- @return FALSE unrecoganized machine type of image.
>-
>-**/
>-BOOLEAN
>-PeCoffLoaderImageFormatSupported (
>- IN UINT16 Machine
>- )
>-{
>- if ((Machine == IMAGE_FILE_MACHINE_IA64) || (Machine ==
>IMAGE_FILE_MACHINE_EBC)) {
>- return TRUE;
>- }
>-
>- return FALSE;
>-}
>-
>-
>-/**
>- ImageRead function that operates on a memory buffer whos base is passed
>into
>- FileHandle.
>-
>- @param Reloc Ponter to baes of the input stream
>- @param Fixup Offset to the start of the buffer
>- @param FixupData The number of bytes to copy into the buffer
>- @param Adjust Location to place results of read
>-
>- @retval RETURN_SUCCESS Data is read from FileOffset from the Handle
>into
>- the buffer.
>- @retval RETURN_UNSUPPORTED Un-recoganized relocation entry
>- type.
>-**/
>-RETURN_STATUS
>-PeHotRelocateImageEx (
>- IN UINT16 *Reloc,
>- IN OUT CHAR8 *Fixup,
>- IN OUT CHAR8 **FixupData,
>- IN UINT64 Adjust
>- )
>-{
>- UINT64 *Fixup64;
>- UINT64 FixupVal;
>-
>- switch ((*Reloc) >> 12) {
>- case EFI_IMAGE_REL_BASED_DIR64:
>- Fixup64 = (UINT64 *) Fixup;
>- *FixupData = ALIGN_POINTER (*FixupData, sizeof (UINT64));
>- if (*(UINT64 *) (*FixupData) == *Fixup64) {
>- *Fixup64 = *Fixup64 + (UINT64) Adjust;
>- }
>-
>- *FixupData = *FixupData + sizeof (UINT64);
>- break;
>-
>- case EFI_IMAGE_REL_BASED_IA64_IMM64:
>- Fixup64 = (UINT64 *) Fixup;
>- *FixupData = ALIGN_POINTER (*FixupData, sizeof (UINT64));
>- if (*(UINT64 *) (*FixupData) == *Fixup64) {
>- //
>- // Align it to bundle address before fixing up the
>- // 64-bit immediate value of the movl instruction.
>- //
>- //
>- Fixup = (CHAR8 *) ((UINT64) Fixup & (UINT64)~(15));
>- FixupVal = (UINT64) 0;
>-
>- //
>- // Extract the lower 32 bits of IMM64 from bundle
>- //
>- EXT_IMM64 (
>- FixupVal,
>- (UINT32 *) Fixup + IMM64_IMM7B_INST_WORD_X,
>- IMM64_IMM7B_SIZE_X,
>- IMM64_IMM7B_INST_WORD_POS_X,
>- IMM64_IMM7B_VAL_POS_X
>- );
>-
>- EXT_IMM64 (
>- FixupVal,
>- (UINT32 *) Fixup + IMM64_IMM9D_INST_WORD_X,
>- IMM64_IMM9D_SIZE_X,
>- IMM64_IMM9D_INST_WORD_POS_X,
>- IMM64_IMM9D_VAL_POS_X
>- );
>-
>- EXT_IMM64 (
>- FixupVal,
>- (UINT32 *) Fixup + IMM64_IMM5C_INST_WORD_X,
>- IMM64_IMM5C_SIZE_X,
>- IMM64_IMM5C_INST_WORD_POS_X,
>- IMM64_IMM5C_VAL_POS_X
>- );
>-
>- EXT_IMM64 (
>- FixupVal,
>- (UINT32 *) Fixup + IMM64_IC_INST_WORD_X,
>- IMM64_IC_SIZE_X,
>- IMM64_IC_INST_WORD_POS_X,
>- IMM64_IC_VAL_POS_X
>- );
>-
>- EXT_IMM64 (
>- FixupVal,
>- (UINT32 *) Fixup + IMM64_IMM41A_INST_WORD_X,
>- IMM64_IMM41A_SIZE_X,
>- IMM64_IMM41A_INST_WORD_POS_X,
>- IMM64_IMM41A_VAL_POS_X
>- );
>-
>- //
>- // Update 64-bit address
>- //
>- FixupVal += Adjust;
>-
>- //
>- // Insert IMM64 into bundle
>- //
>- INS_IMM64 (
>- FixupVal,
>- ((UINT32 *) Fixup + IMM64_IMM7B_INST_WORD_X),
>- IMM64_IMM7B_SIZE_X,
>- IMM64_IMM7B_INST_WORD_POS_X,
>- IMM64_IMM7B_VAL_POS_X
>- );
>-
>- INS_IMM64 (
>- FixupVal,
>- ((UINT32 *) Fixup + IMM64_IMM9D_INST_WORD_X),
>- IMM64_IMM9D_SIZE_X,
>- IMM64_IMM9D_INST_WORD_POS_X,
>- IMM64_IMM9D_VAL_POS_X
>- );
>-
>- INS_IMM64 (
>- FixupVal,
>- ((UINT32 *) Fixup + IMM64_IMM5C_INST_WORD_X),
>- IMM64_IMM5C_SIZE_X,
>- IMM64_IMM5C_INST_WORD_POS_X,
>- IMM64_IMM5C_VAL_POS_X
>- );
>-
>- INS_IMM64 (
>- FixupVal,
>- ((UINT32 *) Fixup + IMM64_IC_INST_WORD_X),
>- IMM64_IC_SIZE_X,
>- IMM64_IC_INST_WORD_POS_X,
>- IMM64_IC_VAL_POS_X
>- );
>-
>- INS_IMM64 (
>- FixupVal,
>- ((UINT32 *) Fixup + IMM64_IMM41A_INST_WORD_X),
>- IMM64_IMM41A_SIZE_X,
>- IMM64_IMM41A_INST_WORD_POS_X,
>- IMM64_IMM41A_VAL_POS_X
>- );
>-
>- INS_IMM64 (
>- FixupVal,
>- ((UINT32 *) Fixup + IMM64_IMM41B_INST_WORD_X),
>- IMM64_IMM41B_SIZE_X,
>- IMM64_IMM41B_INST_WORD_POS_X,
>- IMM64_IMM41B_VAL_POS_X
>- );
>-
>- INS_IMM64 (
>- FixupVal,
>- ((UINT32 *) Fixup + IMM64_IMM41C_INST_WORD_X),
>- IMM64_IMM41C_SIZE_X,
>- IMM64_IMM41C_INST_WORD_POS_X,
>- IMM64_IMM41C_VAL_POS_X
>- );
>-
>- INS_IMM64 (
>- FixupVal,
>- ((UINT32 *) Fixup + IMM64_SIGN_INST_WORD_X),
>- IMM64_SIGN_SIZE_X,
>- IMM64_SIGN_INST_WORD_POS_X,
>- IMM64_SIGN_VAL_POS_X
>- );
>-
>- *(UINT64 *) (*FixupData) = *Fixup64;
>- }
>-
>- *FixupData = *FixupData + sizeof (UINT64);
>- break;
>-
>- default:
>- DEBUG ((EFI_D_ERROR, "PeHotRelocateEx:unknown fixed type\n"));
>- return RETURN_UNSUPPORTED;
>- }
>-
>- return RETURN_SUCCESS;
>-}
>-
>-
>-
>diff --git
>a/MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
>b/MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
>index d29b532c08..f8d468dbe3 100644
>--- a/MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
>+++ b/MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
>@@ -24,7 +24,7 @@
>
>
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
>+# VALID_ARCHITECTURES = IA32 X64 EBC
> #
>
> [Sources]
>diff --git
>a/MdePkg/Library/BasePostCodeLibDebug/BasePostCodeLibDebug.inf
>b/MdePkg/Library/BasePostCodeLibDebug/BasePostCodeLibDebug.inf
>index 1b9c8ad2c8..076cb410af 100644
>--- a/MdePkg/Library/BasePostCodeLibDebug/BasePostCodeLibDebug.inf
>+++ b/MdePkg/Library/BasePostCodeLibDebug/BasePostCodeLibDebug.inf
>@@ -27,7 +27,7 @@
>
>
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
>+# VALID_ARCHITECTURES = IA32 X64 EBC
> #
>
>
>diff --git
>a/MdePkg/Library/BasePostCodeLibPort80/BasePostCodeLibPort80.inf
>b/MdePkg/Library/BasePostCodeLibPort80/BasePostCodeLibPort80.inf
>index ebe1158728..c411faa37f 100644
>--- a/MdePkg/Library/BasePostCodeLibPort80/BasePostCodeLibPort80.inf
>+++ b/MdePkg/Library/BasePostCodeLibPort80/BasePostCodeLibPort80.inf
>@@ -26,7 +26,7 @@
>
>
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
>+# VALID_ARCHITECTURES = IA32 X64 EBC
> #
>
> [Sources]
>diff --git a/MdePkg/Library/BasePrintLib/BasePrintLib.inf
>b/MdePkg/Library/BasePrintLib/BasePrintLib.inf
>index 069b80d5e4..9b993ba906 100644
>--- a/MdePkg/Library/BasePrintLib/BasePrintLib.inf
>+++ b/MdePkg/Library/BasePrintLib/BasePrintLib.inf
>@@ -24,7 +24,7 @@
>
>
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
>+# VALID_ARCHITECTURES = IA32 X64 EBC
> #
>
>
>diff --git
>a/MdePkg/Library/BaseReportStatusCodeLibNull/BaseReportStatusCodeLibN
>ull.inf
>b/MdePkg/Library/BaseReportStatusCodeLibNull/BaseReportStatusCodeLibN
>ull.inf
>index 8ca96aab61..28b85f3636 100644
>---
>a/MdePkg/Library/BaseReportStatusCodeLibNull/BaseReportStatusCodeLibN
>ull.inf
>+++
>b/MdePkg/Library/BaseReportStatusCodeLibNull/BaseReportStatusCodeLibN
>ull.inf
>@@ -25,7 +25,7 @@
> #
> # The following information is for reference only and not required by the
>build tools.
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
>+# VALID_ARCHITECTURES = IA32 X64 EBC
> #
>
> [Sources]
>diff --git
>a/MdePkg/Library/BaseS3BootScriptLibNull/BaseS3BootScriptLibNull.inf
>b/MdePkg/Library/BaseS3BootScriptLibNull/BaseS3BootScriptLibNull.inf
>index 41e966c475..2e3f28e846 100644
>--- a/MdePkg/Library/BaseS3BootScriptLibNull/BaseS3BootScriptLibNull.inf
>+++ b/MdePkg/Library/BaseS3BootScriptLibNull/BaseS3BootScriptLibNull.inf
>@@ -31,7 +31,7 @@
> #
> # The following information is for reference only and not required by the
>build tools.
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
>+# VALID_ARCHITECTURES = IA32 X64 EBC
> #
>
> [Sources]
>diff --git a/MdePkg/Library/BaseS3IoLib/BaseS3IoLib.inf
>b/MdePkg/Library/BaseS3IoLib/BaseS3IoLib.inf
>index b6c10941ff..359d427c6b 100644
>--- a/MdePkg/Library/BaseS3IoLib/BaseS3IoLib.inf
>+++ b/MdePkg/Library/BaseS3IoLib/BaseS3IoLib.inf
>@@ -29,7 +29,7 @@
> #
> # The following information is for reference only and not required by the
>build tools.
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
>+# VALID_ARCHITECTURES = IA32 X64 EBC
> #
>
> [Sources]
>diff --git a/MdePkg/Library/BaseS3PciLib/BaseS3PciLib.inf
>b/MdePkg/Library/BaseS3PciLib/BaseS3PciLib.inf
>index 561c504d7a..6f996796e7 100644
>--- a/MdePkg/Library/BaseS3PciLib/BaseS3PciLib.inf
>+++ b/MdePkg/Library/BaseS3PciLib/BaseS3PciLib.inf
>@@ -29,7 +29,7 @@
> #
> # The following information is for reference only and not required by the
>build tools.
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
>+# VALID_ARCHITECTURES = IA32 X64 EBC
> #
>
> [Sources]
>diff --git a/MdePkg/Library/BaseS3PciSegmentLib/BaseS3PciSegmentLib.inf
>b/MdePkg/Library/BaseS3PciSegmentLib/BaseS3PciSegmentLib.inf
>index 20214f7f2b..b6684cffa0 100644
>--- a/MdePkg/Library/BaseS3PciSegmentLib/BaseS3PciSegmentLib.inf
>+++ b/MdePkg/Library/BaseS3PciSegmentLib/BaseS3PciSegmentLib.inf
>@@ -29,7 +29,7 @@
> #
> # The following information is for reference only and not required by the
>build tools.
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
>+# VALID_ARCHITECTURES = IA32 X64 EBC
> #
>
> [Sources]
>diff --git a/MdePkg/Library/BaseS3SmbusLib/BaseS3SmbusLib.inf
>b/MdePkg/Library/BaseS3SmbusLib/BaseS3SmbusLib.inf
>index 553662471f..5be1b19e28 100644
>--- a/MdePkg/Library/BaseS3SmbusLib/BaseS3SmbusLib.inf
>+++ b/MdePkg/Library/BaseS3SmbusLib/BaseS3SmbusLib.inf
>@@ -29,7 +29,7 @@
> #
> # The following information is for reference only and not required by the
>build tools.
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
>+# VALID_ARCHITECTURES = IA32 X64 EBC
> #
>
> [Sources]
>diff --git a/MdePkg/Library/BaseS3StallLib/BaseS3StallLib.inf
>b/MdePkg/Library/BaseS3StallLib/BaseS3StallLib.inf
>index a77eec512d..ad480f622f 100644
>--- a/MdePkg/Library/BaseS3StallLib/BaseS3StallLib.inf
>+++ b/MdePkg/Library/BaseS3StallLib/BaseS3StallLib.inf
>@@ -29,7 +29,7 @@
> #
> # The following information is for reference only and not required by the
>build tools.
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
>+# VALID_ARCHITECTURES = IA32 X64 EBC
> #
>
> [Sources]
>diff --git a/MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf
>b/MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf
>index 8fbdafe748..b5b1880a52 100644
>--- a/MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf
>+++ b/MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf
>@@ -48,7 +48,7 @@
> [Sources.Ia32, Sources.ARM]
> SafeIntLib32.c
>
>-[Sources.X64, Sources.IPF, Sources.AARCH64]
>+[Sources.X64, Sources.AARCH64]
> SafeIntLib64.c
>
> [Sources.EBC]
>diff --git a/MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf
>b/MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf
>index 28a7988274..4c4739ed19 100644
>--- a/MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf
>+++ b/MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf
>@@ -24,7 +24,7 @@
>
>
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
>+# VALID_ARCHITECTURES = IA32 X64 EBC
> #
>
> [Sources]
>diff --git a/MdePkg/Library/BaseSmbusLibNull/BaseSmbusLibNull.inf
>b/MdePkg/Library/BaseSmbusLibNull/BaseSmbusLibNull.inf
>index 512db33f9f..dbd9b8b6e1 100644
>--- a/MdePkg/Library/BaseSmbusLibNull/BaseSmbusLibNull.inf
>+++ b/MdePkg/Library/BaseSmbusLibNull/BaseSmbusLibNull.inf
>@@ -22,7 +22,7 @@
> LIBRARY_CLASS = SmbusLib
>
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
>+# VALID_ARCHITECTURES = IA32 X64 EBC
> #
>
> [Sources]
>diff --git
>a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
>b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
>index 03562c6e56..a26de76d7e 100755
>--- a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
>+++ b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
>@@ -24,7 +24,7 @@
> LIBRARY_CLASS = SynchronizationLib
>
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC ARM AARCH64
>+# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64
> #
> [Sources]
> BaseSynchronizationLibInternals.h
>@@ -71,19 +71,6 @@
> X64/GccInline.c | GCC
> SynchronizationGcc.c | GCC
>
>-[Sources.IPF]
>- Ipf/Synchronization.c
>- Ipf/InterlockedCompareExchange64.s
>- Ipf/InterlockedCompareExchange32.s
>- Ipf/InterlockedCompareExchange16.s
>-
>- Ipf/InternalGetSpinLockProperties.c | MSFT
>- Ipf/InternalGetSpinLockProperties.c | GCC
>-
>- Synchronization.c | INTEL
>- SynchronizationMsc.c | MSFT
>- SynchronizationGcc.c | GCC
>-
> [Sources.EBC]
> Synchronization.c
> Ebc/Synchronization.c
>diff --git
>a/MdePkg/Library/BaseSynchronizationLib/Ipf/InterlockedCompareExchange
>16.s
>b/MdePkg/Library/BaseSynchronizationLib/Ipf/InterlockedCompareExchange
>16.s
>deleted file mode 100644
>index b72a1f33dd..0000000000
>---
>a/MdePkg/Library/BaseSynchronizationLib/Ipf/InterlockedCompareExchange
>16.s
>+++ /dev/null
>@@ -1,30 +0,0 @@
>-/// @file
>-/// Contains an implementation of InterlockedCompareExchange16 on
>Itanium-
>-/// based architecture.
>-///
>-/// Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
>-/// Copyright (c) 2015, Linaro Ltd. All rights reserved.<BR>
>-/// This program and the accompanying materials
>-/// are licensed and made available under the terms and conditions of the
>BSD License
>-/// which accompanies this distribution. The full text of the license may be
>found at
>-/// http://opensource.org/licenses/bsd-license.php.
>-///
>-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-///
>-/// Module Name: InterlockedCompareExchange16.s
>-///
>-///
>-
>-.auto
>-.text
>-
>-.proc InternalSyncCompareExchange16
>-.type InternalSyncCompareExchange16, @function
>-InternalSyncCompareExchange16::
>- zxt2 r33 = r33
>- mov ar.ccv = r33
>- cmpxchg2.rel r8 = [r32], r34
>- mf
>- br.ret.sptk.many b0
>-.endp InternalSyncCompareExchange16
>diff --git
>a/MdePkg/Library/BaseSynchronizationLib/Ipf/InterlockedCompareExchange
>32.s
>b/MdePkg/Library/BaseSynchronizationLib/Ipf/InterlockedCompareExchange
>32.s
>deleted file mode 100644
>index 48273c9cfd..0000000000
>---
>a/MdePkg/Library/BaseSynchronizationLib/Ipf/InterlockedCompareExchange
>32.s
>+++ /dev/null
>@@ -1,29 +0,0 @@
>-/// @file
>-/// Contains an implementation of InterlockedCompareExchange32 on
>Itanium-
>-/// based architecture.
>-///
>-/// Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
>-/// This program and the accompanying materials
>-/// are licensed and made available under the terms and conditions of the
>BSD License
>-/// which accompanies this distribution. The full text of the license may be
>found at
>-/// http://opensource.org/licenses/bsd-license.php.
>-///
>-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-///
>-/// Module Name: InterlockedCompareExchange32.s
>-///
>-///
>-
>-.auto
>-.text
>-
>-.proc InternalSyncCompareExchange32
>-.type InternalSyncCompareExchange32, @function
>-InternalSyncCompareExchange32::
>- zxt4 r33 = r33
>- mov ar.ccv = r33
>- cmpxchg4.rel r8 = [r32], r34
>- mf
>- br.ret.sptk.many b0
>-.endp InternalSyncCompareExchange32
>diff --git
>a/MdePkg/Library/BaseSynchronizationLib/Ipf/InterlockedCompareExchange
>64.s
>b/MdePkg/Library/BaseSynchronizationLib/Ipf/InterlockedCompareExchange
>64.s
>deleted file mode 100644
>index b6ee19694e..0000000000
>---
>a/MdePkg/Library/BaseSynchronizationLib/Ipf/InterlockedCompareExchange
>64.s
>+++ /dev/null
>@@ -1,28 +0,0 @@
>-/// @file
>-/// Contains an implementation of InterlockedCompareExchange64 on
>Itanium-
>-/// based architecture.
>-///
>-/// Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
>-/// This program and the accompanying materials
>-/// are licensed and made available under the terms and conditions of the
>BSD License
>-/// which accompanies this distribution. The full text of the license may be
>found at
>-/// http://opensource.org/licenses/bsd-license.php.
>-///
>-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-///
>-/// Module Name: InterlockedCompareExchange64.s
>-///
>-///
>-
>-.auto
>-.text
>-
>-.proc InternalSyncCompareExchange64
>-.type InternalSyncCompareExchange64, @function
>-InternalSyncCompareExchange64::
>- mov ar.ccv = r33
>- cmpxchg8.rel r8 = [r32], r34
>- mf
>- br.ret.sptk.many b0
>-.endp InternalSyncCompareExchange64
>diff --git
>a/MdePkg/Library/BaseSynchronizationLib/Ipf/InternalGetSpinLockPropertie
>s.c
>b/MdePkg/Library/BaseSynchronizationLib/Ipf/InternalGetSpinLockPropertie
>s.c
>deleted file mode 100644
>index f6464c2db7..0000000000
>---
>a/MdePkg/Library/BaseSynchronizationLib/Ipf/InternalGetSpinLockPropertie
>s.c
>+++ /dev/null
>@@ -1,29 +0,0 @@
>-/** @file
>- Internal function to get spin lock alignment.
>-
>- Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
>- This program and the accompanying materials
>- are licensed and made available under the terms and conditions of the BSD
>License
>- which accompanies this distribution. The full text of the license may be
>found at
>- http://opensource.org/licenses/bsd-license.php.
>-
>- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-
>-**/
>-
>-/**
>- Internal function to retrieve the architecture specific spin lock alignment
>- requirements for optimal spin lock performance.
>-
>- @return The architecture specific spin lock alignment.
>-
>-**/
>-UINTN
>-InternalGetSpinLockProperties (
>- VOID
>- )
>-{
>- return 32;
>-}
>-
>diff --git a/MdePkg/Library/BaseSynchronizationLib/Ipf/Synchronization.c
>b/MdePkg/Library/BaseSynchronizationLib/Ipf/Synchronization.c
>deleted file mode 100644
>index 3e316e7140..0000000000
>--- a/MdePkg/Library/BaseSynchronizationLib/Ipf/Synchronization.c
>+++ /dev/null
>@@ -1,77 +0,0 @@
>-/** @file
>- Implementation of synchronization functions on Itanium.
>-
>- Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
>- This program and the accompanying materials
>- are licensed and made available under the terms and conditions of the BSD
>License
>- which accompanies this distribution. The full text of the license may be
>found at
>- http://opensource.org/licenses/bsd-license.php.
>-
>- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-
>-**/
>-
>-#include "BaseSynchronizationLibInternals.h"
>-
>-/**
>- Performs an atomic increment of an 32-bit unsigned integer.
>-
>- Performs an atomic increment of the 32-bit unsigned integer specified by
>- Value and returns the incremented value. The increment operation must be
>- performed using MP safe mechanisms. The state of the return value is not
>- guaranteed to be MP safe.
>-
>- @param Value A pointer to the 32-bit value to increment.
>-
>- @return The incremented value.
>-
>-**/
>-UINT32
>-EFIAPI
>-InternalSyncIncrement (
>- IN volatile UINT32 *Value
>- )
>-{
>- UINT32 OriginalValue;
>-
>- do {
>- OriginalValue = *Value;
>- } while (OriginalValue != InternalSyncCompareExchange32 (
>- Value,
>- OriginalValue,
>- OriginalValue + 1
>- ));
>- return OriginalValue + 1;
>-}
>-
>-/**
>- Performs an atomic decrement of an 32-bit unsigned integer.
>-
>- Performs an atomic decrement of the 32-bit unsigned integer specified by
>- Value and returns the decrement value. The decrement operation must be
>- performed using MP safe mechanisms. The state of the return value is not
>- guaranteed to be MP safe.
>-
>- @param Value A pointer to the 32-bit value to decrement.
>-
>- @return The decrement value.
>-
>-**/
>-UINT32
>-EFIAPI
>-InternalSyncDecrement (
>- IN volatile UINT32 *Value
>- )
>-{
>- UINT32 OriginalValue;
>-
>- do {
>- OriginalValue = *Value;
>- } while (OriginalValue != InternalSyncCompareExchange32 (
>- Value,
>- OriginalValue,
>- OriginalValue - 1
>- ));
>- return OriginalValue - 1;
>-}
>diff --git
>a/MdePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTemplate.inf
>b/MdePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTemplate.inf
>index e72abdd818..99625dd0a8 100644
>---
>a/MdePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTemplate.inf
>+++
>b/MdePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTemplate.inf
>@@ -29,7 +29,7 @@
>
>
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
>+# VALID_ARCHITECTURES = IA32 X64 EBC
> #
>
> [Sources]
>diff --git
>a/MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
>b/MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
>index 36d7a240c1..f0730fb7ec 100644
>--- a/MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
>+++ b/MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
>@@ -24,7 +24,7 @@
>
>
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
>+# VALID_ARCHITECTURES = IA32 X64 EBC
> #
>
> [Sources]
>diff --git a/MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
>b/MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
>index 01f64c34c7..1aa6e23619 100644
>--- a/MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
>+++ b/MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
>@@ -24,7 +24,7 @@
>
>
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC (EBC is for build only)
>+# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only)
> #
>
> [Sources]
>diff --git a/MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
>b/MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
>index ae48d9279f..0a4bfdcb99 100644
>--- a/MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
>+++ b/MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
>@@ -27,7 +27,7 @@
>
>
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC (EBC is for build only)
>+# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only)
> #
>
> [Sources]
>diff --git a/MdePkg/Library/DxeExtendedSalLib/DxeExtendedSalLib.inf
>b/MdePkg/Library/DxeExtendedSalLib/DxeExtendedSalLib.inf
>deleted file mode 100644
>index 2c4e28b039..0000000000
>--- a/MdePkg/Library/DxeExtendedSalLib/DxeExtendedSalLib.inf
>+++ /dev/null
>@@ -1,46 +0,0 @@
>-## @file
>-# The library implements the Extended SAL Library Class for boot service only
>modules.
>-#
>-# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
>-#
>-# This program and the accompanying materials
>-# are licensed and made available under the terms and conditions of the BSD
>License
>-# which accompanies this distribution. The full text of the license may be
>found at
>-# http://opensource.org/licenses/bsd-license.php.
>-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-#
>-##
>-
>-[Defines]
>- INF_VERSION = 0x00010005
>- BASE_NAME = DxeExtendedSalLib
>- MODULE_UNI_FILE = DxeExtendedSalLib.uni
>- FILE_GUID = 8FDED21D-7AB5-4c26-8CF7-20EC4DB9861D
>- MODULE_TYPE = DXE_DRIVER
>- VERSION_STRING = 1.0
>- LIBRARY_CLASS = ExtendedSalLib|DXE_DRIVER UEFI_DRIVER
>UEFI_APPLICATION
>- CONSTRUCTOR = DxeExtendedSalLibConstruct
>-
>-#
>-# The following information is for reference only and not required by the
>build tools.
>-#
>-# VALID_ARCHITECTURES = IPF
>-#
>-
>-[Sources.IPF]
>- ExtendedSalLib.c
>- Ipf/AsmExtendedSalLib.s
>-
>-[Packages]
>- MdePkg/MdePkg.dec
>-
>-[LibraryClasses]
>- UefiBootServicesTableLib
>-
>-[Protocols]
>- gEfiExtendedSalBootServiceProtocolGuid ## CONSUMES
>-
>-[Depex.common.DXE_DRIVER]
>- gEfiExtendedSalBootServiceProtocolGuid
>-
>diff --git a/MdePkg/Library/DxeExtendedSalLib/ExtendedSalLib.c
>b/MdePkg/Library/DxeExtendedSalLib/ExtendedSalLib.c
>deleted file mode 100644
>index 0f48c63f7b..0000000000
>--- a/MdePkg/Library/DxeExtendedSalLib/ExtendedSalLib.c
>+++ /dev/null
>@@ -1,1001 +0,0 @@
>-/** @file
>- The library implements the Extended SAL Library Class for boot service only
>modules.
>-
>- Copyright (c) 2007 - 2012, Intel Corporation. All rights reserved.<BR>
>- This program and the accompanying materials
>- are licensed and made available under the terms and conditions of the BSD
>License
>- which accompanies this distribution. The full text of the license may be
>found at
>- http://opensource.org/licenses/bsd-license.php.
>-
>- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-
>-**/
>-
>-#include <PiDxe.h>
>-
>-#include <Protocol/ExtendedSalBootService.h>
>-#include <Protocol/ExtendedSalServiceClasses.h>
>-
>-#include <Library/ExtendedSalLib.h>
>-#include <Library/UefiBootServicesTableLib.h>
>-#include <Library/DebugLib.h>
>-
>-/**
>- Stores the physical plabel of ESAL entrypoint.
>-
>- This assembly function stores the physical plabel of ESAL entrypoint
>- where GetEsalEntryPoint() can easily retrieve.
>-
>- @param EntryPoint Physical address of ESAL entrypoint
>- @param Gp Physical GP of ESAL entrypoint
>-
>- @return r8 = EFI_SAL_SUCCESS
>-
>-**/
>-SAL_RETURN_REGS
>-EFIAPI
>-SetEsalPhysicalEntryPoint (
>- IN UINT64 EntryPoint,
>- IN UINT64 Gp
>- );
>-
>-/**
>- Retrieves plabel of ESAL entrypoint.
>-
>- This function retrives plabel of ESAL entrypoint stored by
>- SetEsalPhysicalEntryPoint().
>-
>- @return r8 = EFI_SAL_SUCCESS
>- r9 = Physical Plabel
>- r10 = Virtual Plabel
>- r11 = PSR
>-
>-**/
>-SAL_RETURN_REGS
>-EFIAPI
>-GetEsalEntryPoint (
>- VOID
>- );
>-
>-EXTENDED_SAL_BOOT_SERVICE_PROTOCOL *mEsalBootService = NULL;
>-EFI_PLABEL mPlabel;
>-
>-/**
>- Constructor function to get Extended SAL Boot Service Protocol, and
>initializes
>- physical plabel of ESAL entrypoint.
>-
>- This function first locates Extended SAL Boot Service Protocol and caches it
>in global variable.
>- Then it initializes the physical plable of ESAL entrypoint, and stores
>- it where GetEsalEntryPoint() can easily retrieve.
>-
>- @param ImageHandle The firmware allocated handle for the EFI image.
>- @param SystemTable A pointer to the EFI System Table.
>-
>- @retval EFI_SUCCESS Plable of ESAL entrypoint successfully stored.
>-
>-**/
>-EFI_STATUS
>-EFIAPI
>-DxeExtendedSalLibConstruct (
>- IN EFI_HANDLE ImageHandle,
>- IN EFI_SYSTEM_TABLE *SystemTable
>- )
>-{
>- EFI_PLABEL *Plabel;
>- EFI_STATUS Status;
>-
>- //
>- // The protocol contains a function pointer, which is an indirect procedure
>call.
>- // An indirect procedure call goes through a plabel, and pointer to a function
>is
>- // a pointer to a plabel. To implement indirect procedure calls that can work
>in
>- // both physical and virtual mode, two plabels are required (one physical
>and one
>- // virtual). So lets grap the physical PLABEL for the EsalEntryPoint and store it
>- // away. We cache it in a module global, so we can register the vitrual
>version.
>- //
>- Status = gBS->LocateProtocol (&gEfiExtendedSalBootServiceProtocolGuid,
>NULL, (VOID **) &mEsalBootService);
>- ASSERT_EFI_ERROR (Status);
>-
>- Plabel = (EFI_PLABEL *) (UINTN) mEsalBootService->ExtendedSalProc;
>- mPlabel.EntryPoint = Plabel->EntryPoint;
>- mPlabel.GP = Plabel->GP;
>- //
>- // Stores the physical plabel of ESAL entrypoint where GetEsalEntryPoint()
>can easily retrieve.
>- //
>- SetEsalPhysicalEntryPoint (mPlabel.EntryPoint, mPlabel.GP);
>-
>- return EFI_SUCCESS;
>-}
>-
>-/**
>- Registers function of ESAL class and it's associated global.
>-
>- This function registers function of ESAL class, together with its associated
>global.
>- It is worker function for RegisterEsalClass().
>- It is only for boot time.
>-
>- @param FunctionId ID of function to register
>- @param ClassGuidLo GUID of ESAL class, lower 64-bits
>- @param ClassGuidHi GUID of ESAL class, upper 64-bits
>- @param Function Function to register with ClassGuid/FunctionId pair
>- @param ModuleGlobal Module global for the function.
>-
>- @return Status returned by RegisterExtendedSalProc() of Extended SAL
>Boot Service Protocol
>-
>-**/
>-EFI_STATUS
>-RegisterEsalFunction (
>- IN UINT64 FunctionId,
>- IN UINT64 ClassGuidLo,
>- IN UINT64 ClassGuidHi,
>- IN SAL_INTERNAL_EXTENDED_SAL_PROC Function,
>- IN VOID *ModuleGlobal
>- )
>-{
>- return mEsalBootService->RegisterExtendedSalProc (
>- mEsalBootService,
>- ClassGuidLo,
>- ClassGuidHi,
>- FunctionId,
>- Function,
>- ModuleGlobal
>- );
>-}
>-
>-/**
>- Registers ESAL Class and it's associated global.
>-
>- This function registers one or more Extended SAL services in a given
>- class along with the associated global context.
>- This function is only available prior to ExitBootServices().
>-
>- @param ClassGuidLo GUID of function class, lower 64-bits
>- @param ClassGuidHi GUID of function class, upper 64-bits
>- @param ModuleGlobal Module global for the class.
>- @param ... List of Function/FunctionId pairs, ended by NULL
>-
>- @retval EFI_SUCCESS The Extended SAL services were registered.
>- @retval EFI_UNSUPPORTED This function was called after
>ExitBootServices().
>- @retval EFI_OUT_OF_RESOURCES There are not enough resources available
>to register one or more of the specified services.
>- @retval Other ClassGuid could not be installed onto a new handle.
>-
>-**/
>-EFI_STATUS
>-EFIAPI
>-RegisterEsalClass (
>- IN CONST UINT64 ClassGuidLo,
>- IN CONST UINT64 ClassGuidHi,
>- IN VOID *ModuleGlobal, OPTIONAL
>- ...
>- )
>-{
>- VA_LIST Args;
>- EFI_STATUS Status;
>- SAL_INTERNAL_EXTENDED_SAL_PROC Function;
>- UINT64 FunctionId;
>- EFI_HANDLE NewHandle;
>- EFI_GUID ClassGuid;
>-
>- VA_START (Args, ModuleGlobal);
>-
>- //
>- // Register all functions of the class to register.
>- //
>- Status = EFI_SUCCESS;
>- while (!EFI_ERROR (Status)) {
>- Function = (SAL_INTERNAL_EXTENDED_SAL_PROC) VA_ARG (Args,
>SAL_INTERNAL_EXTENDED_SAL_PROC);
>- //
>- // NULL serves as the end mark of function list
>- //
>- if (Function == NULL) {
>- break;
>- }
>-
>- FunctionId = VA_ARG (Args, UINT64);
>-
>- Status = RegisterEsalFunction (FunctionId, ClassGuidLo, ClassGuidHi,
>Function, ModuleGlobal);
>- }
>-
>- VA_END (Args);
>-
>- if (EFI_ERROR (Status)) {
>- return Status;
>- }
>-
>- NewHandle = NULL;
>- *((UINT64 *)(&ClassGuid) + 0) = ClassGuidLo;
>- *((UINT64 *)(&ClassGuid) + 1) = ClassGuidHi;
>- return gBS->InstallProtocolInterface (
>- &NewHandle,
>- &ClassGuid,
>- EFI_NATIVE_INTERFACE,
>- NULL
>- );
>-}
>-
>-/**
>- Calls an Extended SAL Class service that was previously registered with
>RegisterEsalClass().
>-
>- This function gets the entrypoint of Extended SAL, and calls an Extended SAL
>Class service
>- that was previously registered with RegisterEsalClass() through this
>entrypoint.
>-
>- @param ClassGuidLo GUID of function, lower 64-bits
>- @param ClassGuidHi GUID of function, upper 64-bits
>- @param FunctionId Function in ClassGuid to call
>- @param Arg2 Argument 2 ClassGuid/FunctionId defined
>- @param Arg3 Argument 3 ClassGuid/FunctionId defined
>- @param Arg4 Argument 4 ClassGuid/FunctionId defined
>- @param Arg5 Argument 5 ClassGuid/FunctionId defined
>- @param Arg6 Argument 6 ClassGuid/FunctionId defined
>- @param Arg7 Argument 7 ClassGuid/FunctionId defined
>- @param Arg8 Argument 8 ClassGuid/FunctionId defined
>-
>- @retval EFI_SAL_SUCCESS ESAL procedure successfully called.
>- @retval EFI_SAL_ERROR The address of ExtendedSalProc() can not be
>correctly
>- initialized.
>- @retval Other Status returned from ExtendedSalProc() service of
>- EXTENDED_SAL_BOOT_SERVICE_PROTOCOL.
>-
>-**/
>-SAL_RETURN_REGS
>-EFIAPI
>-EsalCall (
>- IN UINT64 ClassGuidLo,
>- IN UINT64 ClassGuidHi,
>- IN UINT64 FunctionId,
>- IN UINT64 Arg2,
>- IN UINT64 Arg3,
>- IN UINT64 Arg4,
>- IN UINT64 Arg5,
>- IN UINT64 Arg6,
>- IN UINT64 Arg7,
>- IN UINT64 Arg8
>- )
>-{
>- SAL_RETURN_REGS ReturnReg;
>- EXTENDED_SAL_PROC EsalProc;
>-
>- //
>- // Get the entrypoint of Extended SAL
>- //
>- ReturnReg = GetEsalEntryPoint ();
>- if (*(UINT64 *)ReturnReg.r9 == 0 && *(UINT64 *)(ReturnReg.r9 + 8) == 0) {
>- //
>- // The ESAL Entry Point could not be initialized
>- //
>- ReturnReg.Status = EFI_SAL_ERROR;
>- return ReturnReg;
>- }
>-
>- //
>- // Test PSR.it which is BIT36
>- //
>- if ((ReturnReg.r11 & BIT36) != 0) {
>- //
>- // Virtual mode plabel to entry point
>- //
>- EsalProc = (EXTENDED_SAL_PROC) ReturnReg.r10;
>- } else {
>- //
>- // Physical mode plabel to entry point
>- //
>- EsalProc = (EXTENDED_SAL_PROC) ReturnReg.r9;
>- }
>-
>- return EsalProc (
>- ClassGuidLo,
>- ClassGuidHi,
>- FunctionId,
>- Arg2,
>- Arg3,
>- Arg4,
>- Arg5,
>- Arg6,
>- Arg7,
>- Arg8
>- );
>-}
>-
>-/**
>- Wrapper for the EsalStallFunctionId service of Extended SAL Stall Services
>Class.
>-
>- This function is a wrapper for the EsalStallFunctionId service of Extended SAL
>- Stall Services Class. See EsalStallFunctionId of Extended SAL Specification.
>-
>- @param Microseconds The number of microseconds to delay.
>-
>- @retval EFI_SAL_SUCCESS Call completed without error.
>- @retval EFI_SAL_INVALID_ARGUMENT Invalid argument.
>- @retval EFI_SAL_VIRTUAL_ADDRESS_ERROR Virtual address not registered
>-
>-**/
>-SAL_RETURN_REGS
>-EFIAPI
>-EsalStall (
>- IN UINTN Microseconds
>- )
>-{
>- return EsalCall (
>- EFI_EXTENDED_SAL_STALL_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_STALL_SERVICES_PROTOCOL_GUID_HI,
>- StallFunctionId,
>- Microseconds,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0
>- );
>-}
>-
>-/**
>- Wrapper for the EsalSetNewPalEntryFunctionId service of Extended SAL PAL
>Services Services Class.
>-
>- This function is a wrapper for the EsalSetNewPalEntryFunctionId service of
>Extended SAL
>- PAL Services Services Class. See EsalSetNewPalEntryFunctionId of Extended
>SAL Specification.
>-
>- @param PhysicalAddress If TRUE, then PalEntryPoint is a physical
>address.
>- If FALSE, then PalEntryPoint is a virtual address.
>- @param PalEntryPoint The PAL Entry Point being set.
>-
>- @retval EFI_SAL_SUCCESS The PAL Entry Point was set.
>- @retval EFI_SAL_VIRTUAL_ADDRESS_ERROR This function was called in
>virtual mode before
>- virtual mappings for the specified Extended SAL
>- Procedure are available.
>-
>-**/
>-SAL_RETURN_REGS
>-EFIAPI
>-EsalSetNewPalEntry (
>- IN BOOLEAN PhysicalAddress,
>- IN UINT64 PalEntryPoint
>- )
>-{
>- return EsalCall (
>- EFI_EXTENDED_SAL_PAL_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_PAL_SERVICES_PROTOCOL_GUID_HI,
>- SetNewPalEntryFunctionId,
>- PhysicalAddress,
>- PalEntryPoint,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0
>- );
>-}
>-
>-/**
>- Wrapper for the EsalGetNewPalEntryFunctionId service of Extended SAL
>PAL Services Services Class.
>-
>- This function is a wrapper for the EsalGetNewPalEntryFunctionId service of
>Extended SAL
>- PAL Services Services Class. See EsalGetNewPalEntryFunctionId of Extended
>SAL Specification.
>-
>- @param PhysicalAddress If TRUE, then PalEntryPoint is a physical
>address.
>- If FALSE, then PalEntryPoint is a virtual address.
>-
>- @retval EFI_SAL_SUCCESS The PAL Entry Point was retrieved and
>returned in
>- SAL_RETURN_REGS.r9.
>- @retval EFI_SAL_VIRTUAL_ADDRESS_ERROR This function was called in
>virtual mode before
>- virtual mappings for the specified Extended SAL
>- Procedure are available.
>- @return r9 PAL entry point retrieved.
>-
>-**/
>-SAL_RETURN_REGS
>-EFIAPI
>-EsalGetNewPalEntry (
>- IN BOOLEAN PhysicalAddress
>- )
>-{
>- return EsalCall (
>- EFI_EXTENDED_SAL_PAL_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_PAL_SERVICES_PROTOCOL_GUID_HI,
>- GetNewPalEntryFunctionId,
>- PhysicalAddress,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0
>- );
>-}
>-
>-/**
>- Wrapper for the EsalGetStateBufferFunctionId service of Extended SAL
>MCA Log Services Class.
>-
>- This function is a wrapper for the EsalGetStateBufferFunctionId service of
>Extended SAL
>- MCA Log Services Class. See EsalGetStateBufferFunctionId of Extended SAL
>Specification.
>-
>- @param McaType See type parameter of SAL Procedure
>SAL_GET_STATE_INFO.
>- @param McaBuffer A pointer to the base address of the returned
>buffer.
>- Copied from SAL_RETURN_REGS.r9.
>- @param BufferSize A pointer to the size, in bytes, of the returned
>buffer.
>- Copied from SAL_RETURN_REGS.r10.
>-
>- @retval EFI_SAL_SUCCESS The memory buffer to store error records was
>returned in r9 and r10.
>- @retval EFI_OUT_OF_RESOURCES A memory buffer for string error records
>in not available
>- @return r9 Base address of the returned buffer
>- @return r10 Size of the returned buffer in bytes
>-
>-**/
>-SAL_RETURN_REGS
>-EFIAPI
>-EsalGetStateBuffer (
>- IN UINT64 McaType,
>- OUT UINT8 **McaBuffer,
>- OUT UINTN *BufferSize
>- )
>-{
>- SAL_RETURN_REGS Regs;
>-
>- Regs = EsalCall (
>- EFI_EXTENDED_SAL_MCA_LOG_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_MCA_LOG_SERVICES_PROTOCOL_GUID_HI,
>- EsalGetStateBufferFunctionId,
>- McaType,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0
>- );
>-
>- *McaBuffer = (UINT8 *) Regs.r9;
>- *BufferSize = Regs.r10;
>-
>- return Regs;
>-}
>-
>-/**
>- Wrapper for the EsalSaveStateBufferFunctionId service of Extended SAL
>MCA Log Services Class.
>-
>- This function is a wrapper for the EsalSaveStateBufferFunctionId service of
>Extended SAL
>- MCA Log Services Class. See EsalSaveStateBufferFunctionId of Extended SAL
>Specification.
>-
>- @param McaType See type parameter of SAL Procedure
>SAL_GET_STATE_INFO.
>-
>- @retval EFI_SUCCESS The memory buffer containing the error record was
>written to nonvolatile storage.
>-
>-**/
>-SAL_RETURN_REGS
>-EFIAPI
>-EsalSaveStateBuffer (
>- IN UINT64 McaType
>- )
>-{
>- return EsalCall (
>- EFI_EXTENDED_SAL_MCA_LOG_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_MCA_LOG_SERVICES_PROTOCOL_GUID_HI,
>- EsalSaveStateBufferFunctionId,
>- McaType,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0
>- );
>-}
>-
>-/**
>- Wrapper for the EsalGetVectorsFunctionId service of Extended SAL Base
>Services Class.
>-
>- This function is a wrapper for the EsalGetVectorsFunctionId service of
>Extended SAL
>- Base Services Class. See EsalGetVectorsFunctionId of Extended SAL
>Specification.
>-
>- @param VectorType The vector type to retrieve.
>- 0 - MCA, 1 - BSP INIT, 2 - BOOT_RENDEZ, 3 - AP INIT.
>-
>- @retval EFI_SAL_SUCCESS Call completed without error.
>- @retval EFI_SAL_INVALID_ARGUMENT Invalid argument.
>- @retval EFI_SAL_NO_INFORMATION The requested vector has not been
>registered
>- with the SAL Procedure SAL_SET_VECTORS.
>-
>-**/
>-SAL_RETURN_REGS
>-EFIAPI
>-EsalGetVectors (
>- IN UINT64 VectorType
>- )
>-{
>- return EsalCall (
>- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_HI,
>- EsalGetVectorsFunctionId,
>- VectorType,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0
>- );
>-}
>-
>-/**
>- Wrapper for the EsalMcGetParamsFunctionId service of Extended SAL Base
>Services Class.
>-
>- This function is a wrapper for the EsalMcGetParamsFunctionId service of
>Extended SAL
>- Base Services Class. See EsalMcGetParamsFunctionId of Extended SAL
>Specification.
>-
>- @param ParamInfoType The parameter type to retrieve.
>- 1 - rendezvous interrupt
>- 2 - wake up
>- 3 - Corrected Platform Error Vector.
>-
>- @retval EFI_SAL_SUCCESS Call completed without error.
>- @retval EFI_SAL_INVALID_ARGUMENT Invalid argument.
>- @retval EFI_SAL_NO_INFORMATION The requested vector has not been
>registered
>- with the SAL Procedure SAL_MC_SET_PARAMS.
>-
>-**/
>-SAL_RETURN_REGS
>-EFIAPI
>-EsalMcGetParams (
>- IN UINT64 ParamInfoType
>- )
>-{
>- return EsalCall (
>- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_HI,
>- EsalMcGetParamsFunctionId,
>- ParamInfoType,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0
>- );
>-}
>-
>-/**
>- Wrapper for the EsalMcGetParamsFunctionId service of Extended SAL Base
>Services Class.
>-
>- This function is a wrapper for the EsalMcGetParamsFunctionId service of
>Extended SAL
>- Base Services Class. See EsalMcGetParamsFunctionId of Extended SAL
>Specification.
>-
>- @retval EFI_SAL_SUCCESS Call completed without error.
>- @retval EFI_SAL_NO_INFORMATION The requested vector has not been
>registered
>- with the SAL Procedure SAL_MC_SET_PARAMS.
>-
>-**/
>-SAL_RETURN_REGS
>-EFIAPI
>-EsalMcGetMcParams (
>- VOID
>- )
>-{
>- return EsalCall (
>- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_HI,
>- EsalMcGetMcParamsFunctionId,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0
>- );
>-}
>-
>-/**
>- Wrapper for the EsalGetMcCheckinFlagsFunctionId service of Extended SAL
>Base Services Class.
>-
>- This function is a wrapper for the EsalGetMcCheckinFlagsFunctionId service
>of Extended SAL
>- Base Services Class. See EsalGetMcCheckinFlagsFunctionId of Extended SAL
>Specification.
>-
>- @param CpuIndex The index of the CPU of set of enabled CPUs to
>check.
>-
>- @retval EFI_SAL_SUCCESS The checkin status of the requested CPU was
>returned.
>-
>-**/
>-SAL_RETURN_REGS
>-EFIAPI
>-EsalGetMcCheckinFlags (
>- IN UINT64 CpuIndex
>- )
>-{
>- return EsalCall (
>- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_HI,
>- EsalGetMcCheckinFlagsFunctionId,
>- CpuIndex,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0
>- );
>-}
>-
>-/**
>- Wrapper for the EsalAddCpuDataFunctionId service of Extended SAL MP
>Services Class.
>-
>- This function is a wrapper for the EsalAddCpuDataFunctionId service of
>Extended SAL
>- MP Services Class. See EsalAddCpuDataFunctionId of Extended SAL
>Specification.
>-
>- @param CpuGlobalId The Global ID for the CPU being added.
>- @param Enabled The enable flag for the CPU being added.
>- TRUE means the CPU is enabled.
>- FALSE means the CPU is disabled.
>- @param PalCompatibility The PAL Compatibility value for the CPU
>being added.
>-
>- @retval EFI_SAL_SUCCESS The CPU was added to the database.
>- @retval EFI_SAL_NOT_ENOUGH_SCRATCH There are not enough resource
>available to add the CPU.
>-
>-**/
>-SAL_RETURN_REGS
>-EFIAPI
>-EsalAddCpuData (
>- IN UINT64 CpuGlobalId,
>- IN BOOLEAN Enabled,
>- IN UINT64 PalCompatibility
>- )
>-{
>- return EsalCall (
>- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_HI,
>- AddCpuDataFunctionId,
>- CpuGlobalId,
>- Enabled,
>- PalCompatibility,
>- 0,
>- 0,
>- 0,
>- 0
>- );
>-}
>-
>-/**
>- Wrapper for the EsalRemoveCpuDataFunctionId service of Extended SAL
>MP Services Class.
>-
>- This function is a wrapper for the EsalRemoveCpuDataFunctionId service of
>Extended SAL
>- MP Services Class. See EsalRemoveCpuDataFunctionId of Extended SAL
>Specification.
>-
>- @param CpuGlobalId The Global ID for the CPU being removed.
>-
>- @retval EFI_SAL_SUCCESS The CPU was removed from the database.
>- @retval EFI_SAL_NO_INFORMATION The specified CPU is not in the
>database.
>-
>-**/
>-SAL_RETURN_REGS
>-EFIAPI
>-EsalRemoveCpuData (
>- IN UINT64 CpuGlobalId
>- )
>-{
>- return EsalCall (
>- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_HI,
>- RemoveCpuDataFunctionId,
>- CpuGlobalId,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0
>- );
>-}
>-
>-/**
>- Wrapper for the EsalModifyCpuDataFunctionId service of Extended SAL MP
>Services Class.
>-
>- This function is a wrapper for the EsalModifyCpuDataFunctionId service of
>Extended SAL
>- MP Services Class. See EsalModifyCpuDataFunctionId of Extended SAL
>Specification.
>-
>- @param CpuGlobalId The Global ID for the CPU being modified.
>- @param Enabled The enable flag for the CPU being modified.
>- TRUE means the CPU is enabled.
>- FALSE means the CPU is disabled.
>- @param PalCompatibility The PAL Compatibility value for the CPU being
>modified.
>-
>- @retval EFI_SAL_SUCCESS The CPU database was updated.
>- @retval EFI_SAL_NO_INFORMATION The specified CPU is not in the
>database.
>-
>-**/
>-SAL_RETURN_REGS
>-EFIAPI
>-EsalModifyCpuData (
>- IN UINT64 CpuGlobalId,
>- IN BOOLEAN Enabled,
>- IN UINT64 PalCompatibility
>- )
>-{
>- return EsalCall (
>- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_HI,
>- ModifyCpuDataFunctionId,
>- CpuGlobalId,
>- Enabled,
>- PalCompatibility,
>- 0,
>- 0,
>- 0,
>- 0
>- );
>-}
>-
>-/**
>- Wrapper for the EsalGetCpuDataByIdFunctionId service of Extended SAL MP
>Services Class.
>-
>- This function is a wrapper for the EsalGetCpuDataByIdFunctionId service of
>Extended SAL
>- MP Services Class. See EsalGetCpuDataByIdFunctionId of Extended SAL
>Specification.
>-
>- @param CpuGlobalId The Global ID for the CPU being looked up.
>- @param IndexByEnabledCpu If TRUE, then the index of set of enabled
>CPUs of database is returned.
>- If FALSE, then the index of set of all CPUs of database is
>returned.
>-
>- @retval EFI_SAL_SUCCESS The information on the specified CPU was
>returned.
>- @retval EFI_SAL_NO_INFORMATION The specified CPU is not in the
>database.
>-
>-**/
>-SAL_RETURN_REGS
>-EFIAPI
>-EsalGetCpuDataById (
>- IN UINT64 CpuGlobalId,
>- IN BOOLEAN IndexByEnabledCpu
>- )
>-{
>- return EsalCall (
>- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_HI,
>- GetCpuDataByIDFunctionId,
>- CpuGlobalId,
>- IndexByEnabledCpu,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0
>- );
>-}
>-
>-/**
>- Wrapper for the EsalGetCpuDataByIndexFunctionId service of Extended SAL
>MP Services Class.
>-
>- This function is a wrapper for the EsalGetCpuDataByIndexFunctionId service
>of Extended SAL
>- MP Services Class. See EsalGetCpuDataByIndexFunctionId of Extended SAL
>Specification.
>-
>- @param Index The Global ID for the CPU being modified.
>- @param IndexByEnabledCpu If TRUE, then the index of set of enabled
>CPUs of database is returned.
>- If FALSE, then the index of set of all CPUs of database is
>returned.
>-
>- @retval EFI_SAL_SUCCESS The information on the specified CPU was
>returned.
>- @retval EFI_SAL_NO_INFORMATION The specified CPU is not in the
>database.
>-
>-**/
>-SAL_RETURN_REGS
>-EFIAPI
>-EsalGetCpuDataByIndex (
>- IN UINT64 Index,
>- IN BOOLEAN IndexByEnabledCpu
>- )
>-{
>- return EsalCall (
>- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_HI,
>- GetCpuDataByIndexFunctionId,
>- Index,
>- IndexByEnabledCpu,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0
>- );
>-}
>-
>-/**
>- Wrapper for the EsalWhoAmIFunctionId service of Extended SAL MP
>Services Class.
>-
>- This function is a wrapper for the EsalWhoAmIFunctionId service of
>Extended SAL
>- MP Services Class. See EsalWhoAmIFunctionId of Extended SAL Specification.
>-
>- @param IndexByEnabledCpu If TRUE, then the index of set of enabled
>CPUs of database is returned.
>- If FALSE, then the index of set of all CPUs of database is
>returned.
>-
>- @retval EFI_SAL_SUCCESS The Global ID for the calling CPU was
>returned.
>- @retval EFI_SAL_NO_INFORMATION The calling CPU is not in the database.
>-
>-**/
>-SAL_RETURN_REGS
>-EFIAPI
>-EsalWhoAmI (
>- IN BOOLEAN IndexByEnabledCpu
>- )
>-{
>- return EsalCall (
>- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_HI,
>- CurrentProcInfoFunctionId,
>- IndexByEnabledCpu,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0
>- );
>-}
>-
>-/**
>- Wrapper for the EsalNumProcessors service of Extended SAL MP Services
>Class.
>-
>- This function is a wrapper for the EsalNumProcessors service of Extended
>SAL
>- MP Services Class. See EsalNumProcessors of Extended SAL Specification.
>-
>- @retval EFI_SAL_SUCCESS The information on the number of CPUs in the
>platform
>- was returned.
>-
>-**/
>-SAL_RETURN_REGS
>-EFIAPI
>-EsalNumProcessors (
>- VOID
>- )
>-{
>- return EsalCall (
>- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_HI,
>- NumProcessorsFunctionId,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0
>- );
>-}
>-
>-/**
>- Wrapper for the EsalSetMinStateFnctionId service of Extended SAL MP
>Services Class.
>-
>- This function is a wrapper for the EsalSetMinStateFnctionId service of
>Extended SAL
>- MP Services Class. See EsalSetMinStateFnctionId of Extended SAL
>Specification.
>-
>- @param CpuGlobalId The Global ID for the CPU whose MINSTATE
>pointer is being set.
>- @param MinStatePointer The physical address of the MINSTATE buffer
>for the CPU
>- specified by CpuGlobalId.
>-
>- @retval EFI_SAL_SUCCESS The MINSTATE pointer was set for the
>specified CPU.
>- @retval EFI_SAL_NO_INFORMATION The specified CPU is not in the
>database.
>-
>-**/
>-SAL_RETURN_REGS
>-EFIAPI
>-EsalSetMinState (
>- IN UINT64 CpuGlobalId,
>- IN EFI_PHYSICAL_ADDRESS MinStatePointer
>- )
>-{
>- return EsalCall (
>- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_HI,
>- SetMinStateFunctionId,
>- CpuGlobalId,
>- MinStatePointer,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0
>- );
>-}
>-
>-/**
>- Wrapper for the EsalGetMinStateFunctionId service of Extended SAL MP
>Services Class.
>-
>- This function is a wrapper for the EsalGetMinStateFunctionId service of
>Extended SAL
>- MP Services Class. See EsalGetMinStateFunctionId of Extended SAL
>Specification.
>-
>- @param CpuGlobalId The Global ID for the CPU whose MINSTATE
>pointer is being retrieved.
>-
>- @retval EFI_SAL_SUCCESS The MINSTATE pointer for the specified CPU
>was retrieved.
>- @retval EFI_SAL_NO_INFORMATION The specified CPU is not in the
>database.
>-
>-**/
>-SAL_RETURN_REGS
>-EFIAPI
>-EsalGetMinState (
>- IN UINT64 CpuGlobalId
>- )
>-{
>- return EsalCall (
>- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_HI,
>- GetMinStateFunctionId,
>- CpuGlobalId,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0
>- );
>-}
>-
>-/**
>- Wrapper for the EsalMcsGetStateInfoFunctionId service of Extended SAL
>MCA Services Class.
>-
>- This function is a wrapper for the EsalMcsGetStateInfoFunctionId service of
>Extended SAL
>- MCA Services Class. See EsalMcsGetStateInfoFunctionId of Extended SAL
>Specification.
>-
>- @param CpuGlobalId The Global ID for the CPU whose MCA state
>buffer is being retrieved.
>- @param StateBufferPointer A pointer to the returned MCA state buffer.
>- @param RequiredStateBufferSize A pointer to the size, in bytes, of the
>returned MCA state buffer.
>-
>- @retval EFI_SUCCESS MINSTATE successfully got and size calculated.
>- @retval EFI_SAL_NO_INFORMATION Fail to get MINSTATE.
>-
>-**/
>-SAL_RETURN_REGS
>-EFIAPI
>-EsalMcaGetStateInfo (
>- IN UINT64 CpuGlobalId,
>- OUT EFI_PHYSICAL_ADDRESS *StateBufferPointer,
>- OUT UINT64 *RequiredStateBufferSize
>- )
>-{
>- SAL_RETURN_REGS Regs;
>-
>- Regs = EsalCall (
>- EFI_EXTENDED_SAL_MCA_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_MCA_SERVICES_PROTOCOL_GUID_HI,
>- McaGetStateInfoFunctionId,
>- CpuGlobalId,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0
>- );
>-
>- *StateBufferPointer = (EFI_PHYSICAL_ADDRESS) Regs.r9;
>- *RequiredStateBufferSize = (UINT64) Regs.r10;
>-
>- return Regs;
>-}
>-
>-/**
>- Wrapper for the EsalMcaRegisterCpuFunctionId service of Extended SAL
>MCA Services Class.
>-
>- This function is a wrapper for the EsalMcaRegisterCpuFunctionId service of
>Extended SAL
>- MCA Services Class. See EsalMcaRegisterCpuFunctionId of Extended SAL
>Specification.
>-
>- @param CpuGlobalId The Global ID for the CPU whose MCA state
>buffer is being set.
>- @param StateBufferPointer A pointer to the MCA state buffer.
>-
>- @retval EFI_SAL_NO_INFORMATION Cannot get the processor info with
>the CpuId
>- @retval EFI_SUCCESS Save the processor's state info successfully
>-
>-**/
>-SAL_RETURN_REGS
>-EFIAPI
>-EsalMcaRegisterCpu (
>- IN UINT64 CpuGlobalId,
>- IN EFI_PHYSICAL_ADDRESS StateBufferPointer
>- )
>-{
>- return EsalCall (
>- EFI_EXTENDED_SAL_MCA_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_MCA_SERVICES_PROTOCOL_GUID_HI,
>- McaRegisterCpuFunctionId,
>- CpuGlobalId,
>- StateBufferPointer,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0
>- );
>-}
>diff --git a/MdePkg/Library/DxeExtendedSalLib/Ipf/AsmExtendedSalLib.s
>b/MdePkg/Library/DxeExtendedSalLib/Ipf/AsmExtendedSalLib.s
>deleted file mode 100644
>index f1c4366f1b..0000000000
>--- a/MdePkg/Library/DxeExtendedSalLib/Ipf/AsmExtendedSalLib.s
>+++ /dev/null
>@@ -1,97 +0,0 @@
>-/// @file
>-/// Assembly procedures to get and set ESAL entry point.
>-///
>-/// Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
>-/// This program and the accompanying materials
>-/// are licensed and made available under the terms and conditions of the
>BSD License
>-/// which accompanies this distribution. The full text of the license may be
>found at
>-/// http://opensource.org/licenses/bsd-license.php.
>-///
>-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-///
>-
>-.auto
>-.text
>-
>-#include "IpfMacro.i"
>-
>-//
>-// Exports
>-//
>-ASM_GLOBAL GetEsalEntryPoint
>-
>-//-----------------------------------------------------------------------------
>-//++
>-// GetEsalEntryPoint
>-//
>-// Return Esal global and PSR register.
>-//
>-// On Entry :
>-//
>-//
>-// Return Value:
>-// r8 = EFI_SAL_SUCCESS
>-// r9 = Physical Plabel
>-// r10 = Virtual Plabel
>-// r11 = psr
>-//
>-// As per static calling conventions.
>-//
>-//--
>-//---------------------------------------------------------------------------
>-PROCEDURE_ENTRY (GetEsalEntryPoint)
>-
>- NESTED_SETUP (0,8,0,0)
>-
>-EsalCalcStart:
>- mov r8 = ip;;
>- add r8 = (EsalEntryPoint - EsalCalcStart), r8;;
>- mov r9 = r8;;
>- add r10 = 0x10, r8;;
>- mov r11 = psr;;
>- mov r8 = r0;;
>-
>- NESTED_RETURN
>-
>-PROCEDURE_EXIT (GetEsalEntryPoint)
>-
>-//-----------------------------------------------------------------------------
>-//++
>-// SetEsalPhysicalEntryPoint
>-//
>-// Set the dispatcher entry point
>-//
>-// On Entry:
>-// in0 = Physical address of Esal Dispatcher
>-// in1 = Physical GP
>-//
>-// Return Value:
>-// r8 = EFI_SAL_SUCCESS
>-//
>-// As per static calling conventions.
>-//
>-//--
>-//---------------------------------------------------------------------------
>-PROCEDURE_ENTRY (SetEsalPhysicalEntryPoint)
>-
>- NESTED_SETUP (2,8,0,0)
>-
>-EsalCalcStart1:
>- mov r8 = ip;;
>- add r8 = (EsalEntryPoint - EsalCalcStart1), r8;;
>- st8 [r8] = in0;;
>- add r8 = 0x08, r8;;
>- st8 [r8] = in1;;
>- mov r8 = r0;;
>-
>- NESTED_RETURN
>-
>-PROCEDURE_EXIT (SetEsalPhysicalEntryPoint)
>-
>-.align 32
>-EsalEntryPoint:
>- data8 0 // Physical Entry
>- data8 0 // GP
>- data8 0 // Virtual Entry
>- data8 0 // GP
>diff --git
>a/MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.i
>nf
>b/MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.
>inf
>index c66a26b168..b46764197b 100644
>---
>a/MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.i
>nf
>+++
>b/MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.
>inf
>@@ -22,14 +22,14 @@
> FILE_GUID = f773469b-e265-4b0c-b0a6-2f971fbfe72b
> MODULE_TYPE = DXE_DRIVER
> VERSION_STRING = 1.0
>- LIBRARY_CLASS = ExtractGuidedSectionLib|DXE_CORE DXE_DRIVER
>DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER
>UEFI_APPLICATION UEFI_DRIVER
>+ LIBRARY_CLASS = ExtractGuidedSectionLib|DXE_CORE DXE_DRIVER
>DXE_RUNTIME_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER
>
> CONSTRUCTOR = DxeExtractGuidedSectionLibConstructor
>
> #
> # The following information is for reference only and not required by the
>build tools.
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
>+# VALID_ARCHITECTURES = IA32 X64 EBC
> #
>
> [Sources]
>diff --git a/MdePkg/Library/DxeHobLib/DxeHobLib.inf
>b/MdePkg/Library/DxeHobLib/DxeHobLib.inf
>index 32cd5546ab..329aec24a3 100644
>--- a/MdePkg/Library/DxeHobLib/DxeHobLib.inf
>+++ b/MdePkg/Library/DxeHobLib/DxeHobLib.inf
>@@ -23,11 +23,11 @@
> FILE_GUID = f12b59c9-76d0-4661-ad7c-f04d1bef0558
> MODULE_TYPE = DXE_DRIVER
> VERSION_STRING = 1.0
>- LIBRARY_CLASS = HobLib|DXE_DRIVER DXE_RUNTIME_DRIVER
>DXE_SAL_DRIVER SMM_CORE DXE_SMM_DRIVER UEFI_APPLICATION
>UEFI_DRIVER
>+ LIBRARY_CLASS = HobLib|DXE_DRIVER DXE_RUNTIME_DRIVER
>SMM_CORE DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER
> CONSTRUCTOR = HobLibConstructor
>
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
>+# VALID_ARCHITECTURES = IA32 X64 EBC
> #
>
> [Sources]
>diff --git a/MdePkg/Library/DxeHstiLib/DxeHstiLib.inf
>b/MdePkg/Library/DxeHstiLib/DxeHstiLib.inf
>index a694c2c8ae..44039d116d 100644
>--- a/MdePkg/Library/DxeHstiLib/DxeHstiLib.inf
>+++ b/MdePkg/Library/DxeHstiLib/DxeHstiLib.inf
>@@ -19,7 +19,7 @@
> FILE_GUID = 7DE1C620-F587-4116-A36D-40F3467B9A0C
> MODULE_TYPE = DXE_DRIVER
> VERSION_STRING = 1.0
>- LIBRARY_CLASS = HstiLib|DXE_CORE DXE_DRIVER
>DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER
>UEFI_APPLICATION UEFI_DRIVER
>+ LIBRARY_CLASS = HstiLib|DXE_CORE DXE_DRIVER
>DXE_RUNTIME_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER
>
> [Sources]
> HstiAip.c
>diff --git a/MdePkg/Library/DxeIoLibCpuIo2/DxeIoLibCpuIo2.inf
>b/MdePkg/Library/DxeIoLibCpuIo2/DxeIoLibCpuIo2.inf
>index 65031d0bd3..585d1cdda2 100644
>--- a/MdePkg/Library/DxeIoLibCpuIo2/DxeIoLibCpuIo2.inf
>+++ b/MdePkg/Library/DxeIoLibCpuIo2/DxeIoLibCpuIo2.inf
>@@ -22,13 +22,13 @@
> FILE_GUID = 33D33BF3-349E-4768-9459-836A9F7558FB
> MODULE_TYPE = DXE_DRIVER
> VERSION_STRING = 1.0
>- LIBRARY_CLASS = IoLib|DXE_DRIVER DXE_SAL_DRIVER
>+ LIBRARY_CLASS = IoLib|DXE_DRIVER
> CONSTRUCTOR = IoLibConstructor
>
> #
> # The following information is for reference only and not required by the
>build tools.
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
>+# VALID_ARCHITECTURES = IA32 X64 EBC
> #
>
> [Sources]
>diff --git a/MdePkg/Library/DxeIoLibEsal/DxeIoLibEsal.inf
>b/MdePkg/Library/DxeIoLibEsal/DxeIoLibEsal.inf
>deleted file mode 100644
>index fdfc12b945..0000000000
>--- a/MdePkg/Library/DxeIoLibEsal/DxeIoLibEsal.inf
>+++ /dev/null
>@@ -1,49 +0,0 @@
>-## @file
>-# I/O Library instance that layers on top of Itanium ESAL services.
>-#
>-# I/O Library implementation that uses Itanium ESAL services for I/O
>-# and MMIO operations.
>-#
>-# Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
>-# This program and the accompanying materials are licensed and made
>available
>-# under the terms and conditions of the BSD License which accompanies this
>-# distribution. The full text of the license may be found at
>-# http://opensource.org/licenses/bsd-license.php.
>-#
>-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-#
>-##
>-
>-[Defines]
>- INF_VERSION = 0x00010005
>- BASE_NAME = DxeIoLibEsal
>- MODULE_UNI_FILE = DxeIoLibEsal.uni
>- FILE_GUID = 0D8E6E4E-B029-475f-9122-60A3FEDBA8C0
>- MODULE_TYPE = DXE_DRIVER
>- VERSION_STRING = 1.0
>- LIBRARY_CLASS = IoLib|DXE_DRIVER DXE_RUNTIME_DRIVER
>DXE_SAL_DRIVER
>-
>-#
>-# The following information is for reference only and not required by the
>build tools.
>-#
>-# VALID_ARCHITECTURES = IPF
>-#
>-
>-[Sources]
>- IoHighLevel.c
>- IoLib.c
>- IoLibMmioBuffer.c
>- DxeIoLibEsalInternal.h
>-
>-[Packages]
>- MdePkg/MdePkg.dec
>-
>-[LibraryClasses]
>- ExtendedSalLib
>- BaseLib
>- DebugLib
>-
>-[Depex]
>- gEfiExtendedSalBaseIoServicesProtocolGuid
>-
>diff --git a/MdePkg/Library/DxeIoLibEsal/DxeIoLibEsalInternal.h
>b/MdePkg/Library/DxeIoLibEsal/DxeIoLibEsalInternal.h
>deleted file mode 100644
>index c6dd4af543..0000000000
>--- a/MdePkg/Library/DxeIoLibEsal/DxeIoLibEsalInternal.h
>+++ /dev/null
>@@ -1,28 +0,0 @@
>-/** @file
>- Internal include file for the I/O Library using ESAL services.
>-
>- Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
>- This program and the accompanying materials are licensed and made
>available
>- under the terms and conditions of the BSD License which accompanies this
>- distribution. The full text of the license may be found at
>- http://opensource.org/licenses/bsd-license.php.
>-
>- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-
>-**/
>-
>-#ifndef __DXE_IO_LIB_ESAL_INTERNAL_H_
>-#define __DXE_IO_LIB_ESAL_INTERNAL_H_
>-
>-#include <PiDxe.h>
>-
>-#include <Protocol/CpuIo2.h>
>-#include <Protocol/ExtendedSalServiceClasses.h>
>-
>-#include <Library/IoLib.h>
>-#include <Library/DebugLib.h>
>-#include <Library/BaseLib.h>
>-#include <Library/ExtendedSalLib.h>
>-
>-#endif
>diff --git a/MdePkg/Library/DxeIoLibEsal/IoHighLevel.c
>b/MdePkg/Library/DxeIoLibEsal/IoHighLevel.c
>deleted file mode 100644
>index 7b602192a4..0000000000
>--- a/MdePkg/Library/DxeIoLibEsal/IoHighLevel.c
>+++ /dev/null
>@@ -1,2303 +0,0 @@
>-/** @file
>- High-level Io/Mmio functions.
>-
>- Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
>- This program and the accompanying materials
>- are licensed and made available under the terms and conditions of the BSD
>License
>- which accompanies this distribution. The full text of the license may be
>found at
>- http://opensource.org/licenses/bsd-license.php.
>-
>- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-
>-**/
>-
>-#include "DxeIoLibEsalInternal.h"
>-
>-/**
>- Reads an 8-bit I/O port, performs a bitwise OR, and writes the
>- result back to the 8-bit I/O port.
>-
>- Reads the 8-bit I/O port specified by Port, performs a bitwise OR
>- between the read result and the value specified by OrData, and writes the
>- result to the 8-bit I/O port specified by Port. The value written to the I/O
>- port is returned. This function must guarantee that all I/O read and write
>- operations are serialized.
>-
>- If 8-bit I/O port operations are not supported, then ASSERT().
>-
>- @param Port The I/O port to write.
>- @param OrData The value to OR with the value read from the I/O port.
>-
>- @return The value written back to the I/O port.
>-
>-**/
>-UINT8
>-EFIAPI
>-IoOr8 (
>- IN UINTN Port,
>- IN UINT8 OrData
>- )
>-{
>- return IoWrite8 (Port, (UINT8)(IoRead8 (Port) | OrData));
>-}
>-
>-/**
>- Reads an 8-bit I/O port, performs a bitwise AND, and writes the result back
>- to the 8-bit I/O port.
>-
>- Reads the 8-bit I/O port specified by Port, performs a bitwise AND between
>- the read result and the value specified by AndData, and writes the result to
>- the 8-bit I/O port specified by Port. The value written to the I/O port is
>- returned. This function must guarantee that all I/O read and write
>operations
>- are serialized.
>-
>- If 8-bit I/O port operations are not supported, then ASSERT().
>-
>- @param Port The I/O port to write.
>- @param AndData The value to AND with the value read from the I/O port.
>-
>- @return The value written back to the I/O port.
>-
>-**/
>-UINT8
>-EFIAPI
>-IoAnd8 (
>- IN UINTN Port,
>- IN UINT8 AndData
>- )
>-{
>- return IoWrite8 (Port, (UINT8)(IoRead8 (Port) & AndData));
>-}
>-
>-/**
>- Reads an 8-bit I/O port, performs a bitwise AND followed by a bitwise
>- inclusive OR, and writes the result back to the 8-bit I/O port.
>-
>- Reads the 8-bit I/O port specified by Port, performs a bitwise AND between
>- the read result and the value specified by AndData, performs a bitwise OR
>- between the result of the AND operation and the value specified by OrData,
>- and writes the result to the 8-bit I/O port specified by Port. The value
>- written to the I/O port is returned. This function must guarantee that all
>- I/O read and write operations are serialized.
>-
>- If 8-bit I/O port operations are not supported, then ASSERT().
>-
>- @param Port The I/O port to write.
>- @param AndData The value to AND with the value read from the I/O port.
>- @param OrData The value to OR with the result of the AND operation.
>-
>- @return The value written back to the I/O port.
>-
>-**/
>-UINT8
>-EFIAPI
>-IoAndThenOr8 (
>- IN UINTN Port,
>- IN UINT8 AndData,
>- IN UINT8 OrData
>- )
>-{
>- return IoWrite8 (Port, (UINT8)((IoRead8 (Port) & AndData) | OrData));
>-}
>-
>-/**
>- Reads a bit field of an I/O register.
>-
>- Reads the bit field in an 8-bit I/O register. The bit field is specified by
>- the StartBit and the EndBit. The value of the bit field is returned.
>-
>- If 8-bit I/O port operations are not supported, then ASSERT().
>- If StartBit is greater than 7, then ASSERT().
>- If EndBit is greater than 7, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>-
>- @param Port The I/O port to read.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..7.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..7.
>-
>- @return The value read.
>-
>-**/
>-UINT8
>-EFIAPI
>-IoBitFieldRead8 (
>- IN UINTN Port,
>- IN UINTN StartBit,
>- IN UINTN EndBit
>- )
>-{
>- return BitFieldRead8 (IoRead8 (Port), StartBit, EndBit);
>-}
>-
>-/**
>- Writes a bit field to an I/O register.
>-
>- Writes Value to the bit field of the I/O register. The bit field is specified
>- by the StartBit and the EndBit. All other bits in the destination I/O
>- register are preserved. The value written to the I/O port is returned. Extra
>- left bits in Value are stripped.
>-
>- If 8-bit I/O port operations are not supported, then ASSERT().
>- If StartBit is greater than 7, then ASSERT().
>- If EndBit is greater than 7, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>- If Value is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>-
>- @param Port The I/O port to write.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..7.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..7.
>- @param Value New value of the bit field.
>-
>- @return The value written back to the I/O port.
>-
>-**/
>-UINT8
>-EFIAPI
>-IoBitFieldWrite8 (
>- IN UINTN Port,
>- IN UINTN StartBit,
>- IN UINTN EndBit,
>- IN UINT8 Value
>- )
>-{
>- return IoWrite8 (
>- Port,
>- BitFieldWrite8 (IoRead8 (Port), StartBit, EndBit, Value)
>- );
>-}
>-
>-/**
>- Reads a bit field in an 8-bit port, performs a bitwise OR, and writes the
>- result back to the bit field in the 8-bit port.
>-
>- Reads the 8-bit I/O port specified by Port, performs a bitwise OR
>- between the read result and the value specified by OrData, and writes the
>- result to the 8-bit I/O port specified by Port. The value written to the I/O
>- port is returned. This function must guarantee that all I/O read and write
>- operations are serialized. Extra left bits in OrData are stripped.
>-
>- If 8-bit I/O port operations are not supported, then ASSERT().
>- If StartBit is greater than 7, then ASSERT().
>- If EndBit is greater than 7, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>- If OrData is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>-
>- @param Port The I/O port to write.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..7.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..7.
>- @param OrData The value to OR with the value read from the I/O port.
>-
>- @return The value written back to the I/O port.
>-
>-**/
>-UINT8
>-EFIAPI
>-IoBitFieldOr8 (
>- IN UINTN Port,
>- IN UINTN StartBit,
>- IN UINTN EndBit,
>- IN UINT8 OrData
>- )
>-{
>- return IoWrite8 (
>- Port,
>- BitFieldOr8 (IoRead8 (Port), StartBit, EndBit, OrData)
>- );
>-}
>-
>-/**
>- Reads a bit field in an 8-bit port, performs a bitwise AND, and writes the
>- result back to the bit field in the 8-bit port.
>-
>- Reads the 8-bit I/O port specified by Port, performs a bitwise AND between
>- the read result and the value specified by AndData, and writes the result to
>- the 8-bit I/O port specified by Port. The value written to the I/O port is
>- returned. This function must guarantee that all I/O read and write
>operations
>- are serialized. Extra left bits in AndData are stripped.
>-
>- If 8-bit I/O port operations are not supported, then ASSERT().
>- If StartBit is greater than 7, then ASSERT().
>- If EndBit is greater than 7, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>- If AndData is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>-
>- @param Port The I/O port to write.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..7.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..7.
>- @param AndData The value to AND with the value read from the I/O port.
>-
>- @return The value written back to the I/O port.
>-
>-**/
>-UINT8
>-EFIAPI
>-IoBitFieldAnd8 (
>- IN UINTN Port,
>- IN UINTN StartBit,
>- IN UINTN EndBit,
>- IN UINT8 AndData
>- )
>-{
>- return IoWrite8 (
>- Port,
>- BitFieldAnd8 (IoRead8 (Port), StartBit, EndBit, AndData)
>- );
>-}
>-
>-/**
>- Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
>- bitwise OR, and writes the result back to the bit field in the
>- 8-bit port.
>-
>- Reads the 8-bit I/O port specified by Port, performs a bitwise AND followed
>- by a bitwise OR between the read result and the value specified by
>- AndData, and writes the result to the 8-bit I/O port specified by Port. The
>- value written to the I/O port is returned. This function must guarantee that
>- all I/O read and write operations are serialized. Extra left bits in both
>- AndData and OrData are stripped.
>-
>- If 8-bit I/O port operations are not supported, then ASSERT().
>- If StartBit is greater than 7, then ASSERT().
>- If EndBit is greater than 7, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>- If AndData is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>- If OrData is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>-
>- @param Port The I/O port to write.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..7.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..7.
>- @param AndData The value to AND with the value read from the I/O port.
>- @param OrData The value to OR with the result of the AND operation.
>-
>- @return The value written back to the I/O port.
>-
>-**/
>-UINT8
>-EFIAPI
>-IoBitFieldAndThenOr8 (
>- IN UINTN Port,
>- IN UINTN StartBit,
>- IN UINTN EndBit,
>- IN UINT8 AndData,
>- IN UINT8 OrData
>- )
>-{
>- return IoWrite8 (
>- Port,
>- BitFieldAndThenOr8 (IoRead8 (Port), StartBit, EndBit, AndData, OrData)
>- );
>-}
>-
>-/**
>- Reads a 16-bit I/O port, performs a bitwise OR, and writes the
>- result back to the 16-bit I/O port.
>-
>- Reads the 16-bit I/O port specified by Port, performs a bitwise OR
>- between the read result and the value specified by OrData, and writes the
>- result to the 16-bit I/O port specified by Port. The value written to the I/O
>- port is returned. This function must guarantee that all I/O read and write
>- operations are serialized.
>-
>- If 16-bit I/O port operations are not supported, then ASSERT().
>-
>- @param Port The I/O port to write.
>- @param OrData The value to OR with the value read from the I/O port.
>-
>- @return The value written back to the I/O port.
>-
>-**/
>-UINT16
>-EFIAPI
>-IoOr16 (
>- IN UINTN Port,
>- IN UINT16 OrData
>- )
>-{
>- return IoWrite16 (Port, (UINT16)(IoRead16 (Port) | OrData));
>-}
>-
>-/**
>- Reads a 16-bit I/O port, performs a bitwise AND, and writes the result back
>- to the 16-bit I/O port.
>-
>- Reads the 16-bit I/O port specified by Port, performs a bitwise AND
>between
>- the read result and the value specified by AndData, and writes the result to
>- the 16-bit I/O port specified by Port. The value written to the I/O port is
>- returned. This function must guarantee that all I/O read and write
>operations
>- are serialized.
>-
>- If 16-bit I/O port operations are not supported, then ASSERT().
>-
>- @param Port The I/O port to write.
>- @param AndData The value to AND with the value read from the I/O port.
>-
>- @return The value written back to the I/O port.
>-
>-**/
>-UINT16
>-EFIAPI
>-IoAnd16 (
>- IN UINTN Port,
>- IN UINT16 AndData
>- )
>-{
>- return IoWrite16 (Port, (UINT16)(IoRead16 (Port) & AndData));
>-}
>-
>-/**
>- Reads a 16-bit I/O port, performs a bitwise AND followed by a bitwise
>- inclusive OR, and writes the result back to the 16-bit I/O port.
>-
>- Reads the 16-bit I/O port specified by Port, performs a bitwise AND
>between
>- the read result and the value specified by AndData, performs a bitwise OR
>- between the result of the AND operation and the value specified by OrData,
>- and writes the result to the 16-bit I/O port specified by Port. The value
>- written to the I/O port is returned. This function must guarantee that all
>- I/O read and write operations are serialized.
>-
>- If 16-bit I/O port operations are not supported, then ASSERT().
>-
>- @param Port The I/O port to write.
>- @param AndData The value to AND with the value read from the I/O port.
>- @param OrData The value to OR with the result of the AND operation.
>-
>- @return The value written back to the I/O port.
>-
>-**/
>-UINT16
>-EFIAPI
>-IoAndThenOr16 (
>- IN UINTN Port,
>- IN UINT16 AndData,
>- IN UINT16 OrData
>- )
>-{
>- return IoWrite16 (Port, (UINT16)((IoRead16 (Port) & AndData) | OrData));
>-}
>-
>-/**
>- Reads a bit field of an I/O register.
>-
>- Reads the bit field in a 16-bit I/O register. The bit field is specified by
>- the StartBit and the EndBit. The value of the bit field is returned.
>-
>- If 16-bit I/O port operations are not supported, then ASSERT().
>- If StartBit is greater than 15, then ASSERT().
>- If EndBit is greater than 15, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>-
>- @param Port The I/O port to read.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..15.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..15.
>-
>- @return The value read.
>-
>-**/
>-UINT16
>-EFIAPI
>-IoBitFieldRead16 (
>- IN UINTN Port,
>- IN UINTN StartBit,
>- IN UINTN EndBit
>- )
>-{
>- return BitFieldRead16 (IoRead16 (Port), StartBit, EndBit);
>-}
>-
>-/**
>- Writes a bit field to an I/O register.
>-
>- Writes Value to the bit field of the I/O register. The bit field is specified
>- by the StartBit and the EndBit. All other bits in the destination I/O
>- register are preserved. The value written to the I/O port is returned. Extra
>- left bits in Value are stripped.
>-
>- If 16-bit I/O port operations are not supported, then ASSERT().
>- If StartBit is greater than 15, then ASSERT().
>- If EndBit is greater than 15, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>- If Value is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>-
>- @param Port The I/O port to write.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..15.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..15.
>- @param Value New value of the bit field.
>-
>- @return The value written back to the I/O port.
>-
>-**/
>-UINT16
>-EFIAPI
>-IoBitFieldWrite16 (
>- IN UINTN Port,
>- IN UINTN StartBit,
>- IN UINTN EndBit,
>- IN UINT16 Value
>- )
>-{
>- return IoWrite16 (
>- Port,
>- BitFieldWrite16 (IoRead16 (Port), StartBit, EndBit, Value)
>- );
>-}
>-
>-/**
>- Reads a bit field in a 16-bit port, performs a bitwise OR, and writes the
>- result back to the bit field in the 16-bit port.
>-
>- Reads the 16-bit I/O port specified by Port, performs a bitwise OR
>- between the read result and the value specified by OrData, and writes the
>- result to the 16-bit I/O port specified by Port. The value written to the I/O
>- port is returned. This function must guarantee that all I/O read and write
>- operations are serialized. Extra left bits in OrData are stripped.
>-
>- If 16-bit I/O port operations are not supported, then ASSERT().
>- If StartBit is greater than 15, then ASSERT().
>- If EndBit is greater than 15, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>- If OrData is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>-
>- @param Port The I/O port to write.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..15.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..15.
>- @param OrData The value to OR with the value read from the I/O port.
>-
>- @return The value written back to the I/O port.
>-
>-**/
>-UINT16
>-EFIAPI
>-IoBitFieldOr16 (
>- IN UINTN Port,
>- IN UINTN StartBit,
>- IN UINTN EndBit,
>- IN UINT16 OrData
>- )
>-{
>- return IoWrite16 (
>- Port,
>- BitFieldOr16 (IoRead16 (Port), StartBit, EndBit, OrData)
>- );
>-}
>-
>-/**
>- Reads a bit field in a 16-bit port, performs a bitwise AND, and writes the
>- result back to the bit field in the 16-bit port.
>-
>- Reads the 16-bit I/O port specified by Port, performs a bitwise AND
>between
>- the read result and the value specified by AndData, and writes the result to
>- the 16-bit I/O port specified by Port. The value written to the I/O port is
>- returned. This function must guarantee that all I/O read and write
>operations
>- are serialized. Extra left bits in AndData are stripped.
>-
>- If 16-bit I/O port operations are not supported, then ASSERT().
>- If StartBit is greater than 15, then ASSERT().
>- If EndBit is greater than 15, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>- If AndData is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>-
>- @param Port The I/O port to write.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..15.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..15.
>- @param AndData The value to AND with the value read from the I/O port.
>-
>- @return The value written back to the I/O port.
>-
>-**/
>-UINT16
>-EFIAPI
>-IoBitFieldAnd16 (
>- IN UINTN Port,
>- IN UINTN StartBit,
>- IN UINTN EndBit,
>- IN UINT16 AndData
>- )
>-{
>- return IoWrite16 (
>- Port,
>- BitFieldAnd16 (IoRead16 (Port), StartBit, EndBit, AndData)
>- );
>-}
>-
>-/**
>- Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
>- bitwise OR, and writes the result back to the bit field in the
>- 16-bit port.
>-
>- Reads the 16-bit I/O port specified by Port, performs a bitwise AND followed
>- by a bitwise OR between the read result and the value specified by
>- AndData, and writes the result to the 16-bit I/O port specified by Port. The
>- value written to the I/O port is returned. This function must guarantee that
>- all I/O read and write operations are serialized. Extra left bits in both
>- AndData and OrData are stripped.
>-
>- If 16-bit I/O port operations are not supported, then ASSERT().
>- If StartBit is greater than 15, then ASSERT().
>- If EndBit is greater than 15, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>- If AndData is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>- If OrData is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>-
>- @param Port The I/O port to write.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..15.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..15.
>- @param AndData The value to AND with the value read from the I/O port.
>- @param OrData The value to OR with the result of the AND operation.
>-
>- @return The value written back to the I/O port.
>-
>-**/
>-UINT16
>-EFIAPI
>-IoBitFieldAndThenOr16 (
>- IN UINTN Port,
>- IN UINTN StartBit,
>- IN UINTN EndBit,
>- IN UINT16 AndData,
>- IN UINT16 OrData
>- )
>-{
>- return IoWrite16 (
>- Port,
>- BitFieldAndThenOr16 (IoRead16 (Port), StartBit, EndBit, AndData,
>OrData)
>- );
>-}
>-
>-/**
>- Reads a 32-bit I/O port, performs a bitwise OR, and writes the
>- result back to the 32-bit I/O port.
>-
>- Reads the 32-bit I/O port specified by Port, performs a bitwise OR
>- between the read result and the value specified by OrData, and writes the
>- result to the 32-bit I/O port specified by Port. The value written to the I/O
>- port is returned. This function must guarantee that all I/O read and write
>- operations are serialized.
>-
>- If 32-bit I/O port operations are not supported, then ASSERT().
>-
>- @param Port The I/O port to write.
>- @param OrData The value to OR with the value read from the I/O port.
>-
>- @return The value written back to the I/O port.
>-
>-**/
>-UINT32
>-EFIAPI
>-IoOr32 (
>- IN UINTN Port,
>- IN UINT32 OrData
>- )
>-{
>- return IoWrite32 (Port, IoRead32 (Port) | OrData);
>-}
>-
>-/**
>- Reads a 32-bit I/O port, performs a bitwise AND, and writes the result back
>- to the 32-bit I/O port.
>-
>- Reads the 32-bit I/O port specified by Port, performs a bitwise AND
>between
>- the read result and the value specified by AndData, and writes the result to
>- the 32-bit I/O port specified by Port. The value written to the I/O port is
>- returned. This function must guarantee that all I/O read and write
>operations
>- are serialized.
>-
>- If 32-bit I/O port operations are not supported, then ASSERT().
>-
>- @param Port The I/O port to write.
>- @param AndData The value to AND with the value read from the I/O port.
>-
>- @return The value written back to the I/O port.
>-
>-**/
>-UINT32
>-EFIAPI
>-IoAnd32 (
>- IN UINTN Port,
>- IN UINT32 AndData
>- )
>-{
>- return IoWrite32 (Port, IoRead32 (Port) & AndData);
>-}
>-
>-/**
>- Reads a 32-bit I/O port, performs a bitwise AND followed by a bitwise
>- inclusive OR, and writes the result back to the 32-bit I/O port.
>-
>- Reads the 32-bit I/O port specified by Port, performs a bitwise AND
>between
>- the read result and the value specified by AndData, performs a bitwise OR
>- between the result of the AND operation and the value specified by OrData,
>- and writes the result to the 32-bit I/O port specified by Port. The value
>- written to the I/O port is returned. This function must guarantee that all
>- I/O read and write operations are serialized.
>-
>- If 32-bit I/O port operations are not supported, then ASSERT().
>-
>- @param Port The I/O port to write.
>- @param AndData The value to AND with the value read from the I/O port.
>- @param OrData The value to OR with the result of the AND operation.
>-
>- @return The value written back to the I/O port.
>-
>-**/
>-UINT32
>-EFIAPI
>-IoAndThenOr32 (
>- IN UINTN Port,
>- IN UINT32 AndData,
>- IN UINT32 OrData
>- )
>-{
>- return IoWrite32 (Port, (IoRead32 (Port) & AndData) | OrData);
>-}
>-
>-/**
>- Reads a bit field of an I/O register.
>-
>- Reads the bit field in a 32-bit I/O register. The bit field is specified by
>- the StartBit and the EndBit. The value of the bit field is returned.
>-
>- If 32-bit I/O port operations are not supported, then ASSERT().
>- If StartBit is greater than 31, then ASSERT().
>- If EndBit is greater than 31, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>-
>- @param Port The I/O port to read.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..31.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..31.
>-
>- @return The value read.
>-
>-**/
>-UINT32
>-EFIAPI
>-IoBitFieldRead32 (
>- IN UINTN Port,
>- IN UINTN StartBit,
>- IN UINTN EndBit
>- )
>-{
>- return BitFieldRead32 (IoRead32 (Port), StartBit, EndBit);
>-}
>-
>-/**
>- Writes a bit field to an I/O register.
>-
>- Writes Value to the bit field of the I/O register. The bit field is specified
>- by the StartBit and the EndBit. All other bits in the destination I/O
>- register are preserved. The value written to the I/O port is returned. Extra
>- left bits in Value are stripped.
>-
>- If 32-bit I/O port operations are not supported, then ASSERT().
>- If StartBit is greater than 31, then ASSERT().
>- If EndBit is greater than 31, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>- If Value is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>-
>- @param Port The I/O port to write.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..31.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..31.
>- @param Value New value of the bit field.
>-
>- @return The value written back to the I/O port.
>-
>-**/
>-UINT32
>-EFIAPI
>-IoBitFieldWrite32 (
>- IN UINTN Port,
>- IN UINTN StartBit,
>- IN UINTN EndBit,
>- IN UINT32 Value
>- )
>-{
>- return IoWrite32 (
>- Port,
>- BitFieldWrite32 (IoRead32 (Port), StartBit, EndBit, Value)
>- );
>-}
>-
>-/**
>- Reads a bit field in a 32-bit port, performs a bitwise OR, and writes the
>- result back to the bit field in the 32-bit port.
>-
>- Reads the 32-bit I/O port specified by Port, performs a bitwise OR
>- between the read result and the value specified by OrData, and writes the
>- result to the 32-bit I/O port specified by Port. The value written to the I/O
>- port is returned. This function must guarantee that all I/O read and write
>- operations are serialized. Extra left bits in OrData are stripped.
>-
>- If 32-bit I/O port operations are not supported, then ASSERT().
>- If StartBit is greater than 31, then ASSERT().
>- If EndBit is greater than 31, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>- If OrData is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>-
>- @param Port The I/O port to write.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..31.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..31.
>- @param OrData The value to OR with the value read from the I/O port.
>-
>- @return The value written back to the I/O port.
>-
>-**/
>-UINT32
>-EFIAPI
>-IoBitFieldOr32 (
>- IN UINTN Port,
>- IN UINTN StartBit,
>- IN UINTN EndBit,
>- IN UINT32 OrData
>- )
>-{
>- return IoWrite32 (
>- Port,
>- BitFieldOr32 (IoRead32 (Port), StartBit, EndBit, OrData)
>- );
>-}
>-
>-/**
>- Reads a bit field in a 32-bit port, performs a bitwise AND, and writes the
>- result back to the bit field in the 32-bit port.
>-
>- Reads the 32-bit I/O port specified by Port, performs a bitwise AND
>between
>- the read result and the value specified by AndData, and writes the result to
>- the 32-bit I/O port specified by Port. The value written to the I/O port is
>- returned. This function must guarantee that all I/O read and write
>operations
>- are serialized. Extra left bits in AndData are stripped.
>-
>- If 32-bit I/O port operations are not supported, then ASSERT().
>- If StartBit is greater than 31, then ASSERT().
>- If EndBit is greater than 31, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>- If AndData is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>-
>- @param Port The I/O port to write.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..31.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..31.
>- @param AndData The value to AND with the value read from the I/O port.
>-
>- @return The value written back to the I/O port.
>-
>-**/
>-UINT32
>-EFIAPI
>-IoBitFieldAnd32 (
>- IN UINTN Port,
>- IN UINTN StartBit,
>- IN UINTN EndBit,
>- IN UINT32 AndData
>- )
>-{
>- return IoWrite32 (
>- Port,
>- BitFieldAnd32 (IoRead32 (Port), StartBit, EndBit, AndData)
>- );
>-}
>-
>-/**
>- Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
>- bitwise OR, and writes the result back to the bit field in the
>- 32-bit port.
>-
>- Reads the 32-bit I/O port specified by Port, performs a bitwise AND followed
>- by a bitwise OR between the read result and the value specified by
>- AndData, and writes the result to the 32-bit I/O port specified by Port. The
>- value written to the I/O port is returned. This function must guarantee that
>- all I/O read and write operations are serialized. Extra left bits in both
>- AndData and OrData are stripped.
>-
>- If 32-bit I/O port operations are not supported, then ASSERT().
>- If StartBit is greater than 31, then ASSERT().
>- If EndBit is greater than 31, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>- If AndData is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>- If OrData is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>-
>- @param Port The I/O port to write.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..31.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..31.
>- @param AndData The value to AND with the value read from the I/O port.
>- @param OrData The value to OR with the result of the AND operation.
>-
>- @return The value written back to the I/O port.
>-
>-**/
>-UINT32
>-EFIAPI
>-IoBitFieldAndThenOr32 (
>- IN UINTN Port,
>- IN UINTN StartBit,
>- IN UINTN EndBit,
>- IN UINT32 AndData,
>- IN UINT32 OrData
>- )
>-{
>- return IoWrite32 (
>- Port,
>- BitFieldAndThenOr32 (IoRead32 (Port), StartBit, EndBit, AndData,
>OrData)
>- );
>-}
>-
>-/**
>- Reads a 64-bit I/O port, performs a bitwise OR, and writes the
>- result back to the 64-bit I/O port.
>-
>- Reads the 64-bit I/O port specified by Port, performs a bitwise OR
>- between the read result and the value specified by OrData, and writes the
>- result to the 64-bit I/O port specified by Port. The value written to the I/O
>- port is returned. This function must guarantee that all I/O read and write
>- operations are serialized.
>-
>- If 64-bit I/O port operations are not supported, then ASSERT().
>-
>- @param Port The I/O port to write.
>- @param OrData The value to OR with the value read from the I/O port.
>-
>- @return The value written back to the I/O port.
>-
>-**/
>-UINT64
>-EFIAPI
>-IoOr64 (
>- IN UINTN Port,
>- IN UINT64 OrData
>- )
>-{
>- return IoWrite64 (Port, IoRead64 (Port) | OrData);
>-}
>-
>-/**
>- Reads a 64-bit I/O port, performs a bitwise AND, and writes the result back
>- to the 64-bit I/O port.
>-
>- Reads the 64-bit I/O port specified by Port, performs a bitwise AND
>between
>- the read result and the value specified by AndData, and writes the result to
>- the 64-bit I/O port specified by Port. The value written to the I/O port is
>- returned. This function must guarantee that all I/O read and write
>operations
>- are serialized.
>-
>- If 64-bit I/O port operations are not supported, then ASSERT().
>-
>- @param Port The I/O port to write.
>- @param AndData The value to AND with the value read from the I/O port.
>-
>- @return The value written back to the I/O port.
>-
>-**/
>-UINT64
>-EFIAPI
>-IoAnd64 (
>- IN UINTN Port,
>- IN UINT64 AndData
>- )
>-{
>- return IoWrite64 (Port, IoRead64 (Port) & AndData);
>-}
>-
>-/**
>- Reads a 64-bit I/O port, performs a bitwise AND followed by a bitwise
>- inclusive OR, and writes the result back to the 64-bit I/O port.
>-
>- Reads the 64-bit I/O port specified by Port, performs a bitwise AND
>between
>- the read result and the value specified by AndData, performs a bitwise OR
>- between the result of the AND operation and the value specified by OrData,
>- and writes the result to the 64-bit I/O port specified by Port. The value
>- written to the I/O port is returned. This function must guarantee that all
>- I/O read and write operations are serialized.
>-
>- If 64-bit I/O port operations are not supported, then ASSERT().
>-
>- @param Port The I/O port to write.
>- @param AndData The value to AND with the value read from the I/O port.
>- @param OrData The value to OR with the result of the AND operation.
>-
>- @return The value written back to the I/O port.
>-
>-**/
>-UINT64
>-EFIAPI
>-IoAndThenOr64 (
>- IN UINTN Port,
>- IN UINT64 AndData,
>- IN UINT64 OrData
>- )
>-{
>- return IoWrite64 (Port, (IoRead64 (Port) & AndData) | OrData);
>-}
>-
>-/**
>- Reads a bit field of an I/O register.
>-
>- Reads the bit field in a 64-bit I/O register. The bit field is specified by
>- the StartBit and the EndBit. The value of the bit field is returned.
>-
>- If 64-bit I/O port operations are not supported, then ASSERT().
>- If StartBit is greater than 63, then ASSERT().
>- If EndBit is greater than 63, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>-
>- @param Port The I/O port to read.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..63.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..63.
>-
>- @return The value read.
>-
>-**/
>-UINT64
>-EFIAPI
>-IoBitFieldRead64 (
>- IN UINTN Port,
>- IN UINTN StartBit,
>- IN UINTN EndBit
>- )
>-{
>- return BitFieldRead64 (IoRead64 (Port), StartBit, EndBit);
>-}
>-
>-/**
>- Writes a bit field to an I/O register.
>-
>- Writes Value to the bit field of the I/O register. The bit field is specified
>- by the StartBit and the EndBit. All other bits in the destination I/O
>- register are preserved. The value written to the I/O port is returned. Extra
>- left bits in Value are stripped.
>-
>- If 64-bit I/O port operations are not supported, then ASSERT().
>- If StartBit is greater than 63, then ASSERT().
>- If EndBit is greater than 63, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>- If Value is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>-
>- @param Port The I/O port to write.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..63.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..63.
>- @param Value New value of the bit field.
>-
>- @return The value written back to the I/O port.
>-
>-**/
>-UINT64
>-EFIAPI
>-IoBitFieldWrite64 (
>- IN UINTN Port,
>- IN UINTN StartBit,
>- IN UINTN EndBit,
>- IN UINT64 Value
>- )
>-{
>- return IoWrite64 (
>- Port,
>- BitFieldWrite64 (IoRead64 (Port), StartBit, EndBit, Value)
>- );
>-}
>-
>-/**
>- Reads a bit field in a 64-bit port, performs a bitwise OR, and writes the
>- result back to the bit field in the 64-bit port.
>-
>- Reads the 64-bit I/O port specified by Port, performs a bitwise OR
>- between the read result and the value specified by OrData, and writes the
>- result to the 64-bit I/O port specified by Port. The value written to the I/O
>- port is returned. This function must guarantee that all I/O read and write
>- operations are serialized. Extra left bits in OrData are stripped.
>-
>- If 64-bit I/O port operations are not supported, then ASSERT().
>- If StartBit is greater than 63, then ASSERT().
>- If EndBit is greater than 63, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>- If OrData is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>-
>- @param Port The I/O port to write.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..63.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..63.
>- @param OrData The value to OR with the value read from the I/O port.
>-
>- @return The value written back to the I/O port.
>-
>-**/
>-UINT64
>-EFIAPI
>-IoBitFieldOr64 (
>- IN UINTN Port,
>- IN UINTN StartBit,
>- IN UINTN EndBit,
>- IN UINT64 OrData
>- )
>-{
>- return IoWrite64 (
>- Port,
>- BitFieldOr64 (IoRead64 (Port), StartBit, EndBit, OrData)
>- );
>-}
>-
>-/**
>- Reads a bit field in a 64-bit port, performs a bitwise AND, and writes the
>- result back to the bit field in the 64-bit port.
>-
>- Reads the 64-bit I/O port specified by Port, performs a bitwise AND
>between
>- the read result and the value specified by AndData, and writes the result to
>- the 64-bit I/O port specified by Port. The value written to the I/O port is
>- returned. This function must guarantee that all I/O read and write
>operations
>- are serialized. Extra left bits in AndData are stripped.
>-
>- If 64-bit I/O port operations are not supported, then ASSERT().
>- If StartBit is greater than 63, then ASSERT().
>- If EndBit is greater than 63, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>- If AndData is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>-
>- @param Port The I/O port to write.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..63.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..63.
>- @param AndData The value to AND with the value read from the I/O port.
>-
>- @return The value written back to the I/O port.
>-
>-**/
>-UINT64
>-EFIAPI
>-IoBitFieldAnd64 (
>- IN UINTN Port,
>- IN UINTN StartBit,
>- IN UINTN EndBit,
>- IN UINT64 AndData
>- )
>-{
>- return IoWrite64 (
>- Port,
>- BitFieldAnd64 (IoRead64 (Port), StartBit, EndBit, AndData)
>- );
>-}
>-
>-/**
>- Reads a bit field in a 64-bit port, performs a bitwise AND followed by a
>- bitwise OR, and writes the result back to the bit field in the
>- 64-bit port.
>-
>- Reads the 64-bit I/O port specified by Port, performs a bitwise AND followed
>- by a bitwise OR between the read result and the value specified by
>- AndData, and writes the result to the 64-bit I/O port specified by Port. The
>- value written to the I/O port is returned. This function must guarantee that
>- all I/O read and write operations are serialized. Extra left bits in both
>- AndData and OrData are stripped.
>-
>- If 64-bit I/O port operations are not supported, then ASSERT().
>- If StartBit is greater than 63, then ASSERT().
>- If EndBit is greater than 63, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>- If AndData is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>- If OrData is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>-
>- @param Port The I/O port to write.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..63.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..63.
>- @param AndData The value to AND with the value read from the I/O port.
>- @param OrData The value to OR with the result of the AND operation.
>-
>- @return The value written back to the I/O port.
>-
>-**/
>-UINT64
>-EFIAPI
>-IoBitFieldAndThenOr64 (
>- IN UINTN Port,
>- IN UINTN StartBit,
>- IN UINTN EndBit,
>- IN UINT64 AndData,
>- IN UINT64 OrData
>- )
>-{
>- return IoWrite64 (
>- Port,
>- BitFieldAndThenOr64 (IoRead64 (Port), StartBit, EndBit, AndData,
>OrData)
>- );
>-}
>-
>-/**
>- Reads an 8-bit MMIO register, performs a bitwise OR, and writes the
>- result back to the 8-bit MMIO register.
>-
>- Reads the 8-bit MMIO register specified by Address, performs a bitwise
>- inclusive OR between the read result and the value specified by OrData, and
>- writes the result to the 8-bit MMIO register specified by Address. The value
>- written to the MMIO register is returned. This function must guarantee that
>- all MMIO read and write operations are serialized.
>-
>- If 8-bit MMIO register operations are not supported, then ASSERT().
>-
>- @param Address The MMIO register to write.
>- @param OrData The value to OR with the value read from the MMIO
>register.
>-
>- @return The value written back to the MMIO register.
>-
>-**/
>-UINT8
>-EFIAPI
>-MmioOr8 (
>- IN UINTN Address,
>- IN UINT8 OrData
>- )
>-{
>- return MmioWrite8 (Address, (UINT8)(MmioRead8 (Address) | OrData));
>-}
>-
>-/**
>- Reads an 8-bit MMIO register, performs a bitwise AND, and writes the result
>- back to the 8-bit MMIO register.
>-
>- Reads the 8-bit MMIO register specified by Address, performs a bitwise
>AND
>- between the read result and the value specified by AndData, and writes the
>- result to the 8-bit MMIO register specified by Address. The value written to
>- the MMIO register is returned. This function must guarantee that all MMIO
>- read and write operations are serialized.
>-
>- If 8-bit MMIO register operations are not supported, then ASSERT().
>-
>- @param Address The MMIO register to write.
>- @param AndData The value to AND with the value read from the MMIO
>register.
>-
>- @return The value written back to the MMIO register.
>-
>-**/
>-UINT8
>-EFIAPI
>-MmioAnd8 (
>- IN UINTN Address,
>- IN UINT8 AndData
>- )
>-{
>- return MmioWrite8 (Address, (UINT8)(MmioRead8 (Address) & AndData));
>-}
>-
>-/**
>- Reads an 8-bit MMIO register, performs a bitwise AND followed by a bitwise
>- inclusive OR, and writes the result back to the 8-bit MMIO register.
>-
>- Reads the 8-bit MMIO register specified by Address, performs a bitwise
>AND
>- between the read result and the value specified by AndData, performs a
>- bitwise OR between the result of the AND operation and the value specified
>by
>- OrData, and writes the result to the 8-bit MMIO register specified by
>- Address. The value written to the MMIO register is returned. This function
>- must guarantee that all MMIO read and write operations are serialized.
>-
>- If 8-bit MMIO register operations are not supported, then ASSERT().
>-
>-
>- @param Address The MMIO register to write.
>- @param AndData The value to AND with the value read from the MMIO
>register.
>- @param OrData The value to OR with the result of the AND operation.
>-
>- @return The value written back to the MMIO register.
>-
>-**/
>-UINT8
>-EFIAPI
>-MmioAndThenOr8 (
>- IN UINTN Address,
>- IN UINT8 AndData,
>- IN UINT8 OrData
>- )
>-{
>- return MmioWrite8 (Address, (UINT8)((MmioRead8 (Address) & AndData) |
>OrData));
>-}
>-
>-/**
>- Reads a bit field of a MMIO register.
>-
>- Reads the bit field in an 8-bit MMIO register. The bit field is specified by
>- the StartBit and the EndBit. The value of the bit field is returned.
>-
>- If 8-bit MMIO register operations are not supported, then ASSERT().
>- If StartBit is greater than 7, then ASSERT().
>- If EndBit is greater than 7, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>-
>- @param Address MMIO register to read.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..7.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..7.
>-
>- @return The value read.
>-
>-**/
>-UINT8
>-EFIAPI
>-MmioBitFieldRead8 (
>- IN UINTN Address,
>- IN UINTN StartBit,
>- IN UINTN EndBit
>- )
>-{
>- return BitFieldRead8 (MmioRead8 (Address), StartBit, EndBit);
>-}
>-
>-/**
>- Writes a bit field to a MMIO register.
>-
>- Writes Value to the bit field of the MMIO register. The bit field is
>- specified by the StartBit and the EndBit. All other bits in the destination
>- MMIO register are preserved. The new value of the 8-bit register is
>returned.
>-
>- If 8-bit MMIO register operations are not supported, then ASSERT().
>- If StartBit is greater than 7, then ASSERT().
>- If EndBit is greater than 7, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>- If Value is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>-
>- @param Address MMIO register to write.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..7.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..7.
>- @param Value New value of the bit field.
>-
>- @return The value written back to the MMIO register.
>-
>-**/
>-UINT8
>-EFIAPI
>-MmioBitFieldWrite8 (
>- IN UINTN Address,
>- IN UINTN StartBit,
>- IN UINTN EndBit,
>- IN UINT8 Value
>- )
>-{
>- return MmioWrite8 (
>- Address,
>- BitFieldWrite8 (MmioRead8 (Address), StartBit, EndBit, Value)
>- );
>-}
>-
>-/**
>- Reads a bit field in an 8-bit MMIO register, performs a bitwise OR, and
>- writes the result back to the bit field in the 8-bit MMIO register.
>-
>- Reads the 8-bit MMIO register specified by Address, performs a bitwise
>- inclusive OR between the read result and the value specified by OrData, and
>- writes the result to the 8-bit MMIO register specified by Address. The value
>- written to the MMIO register is returned. This function must guarantee that
>- all MMIO read and write operations are serialized. Extra left bits in OrData
>- are stripped.
>-
>- If 8-bit MMIO register operations are not supported, then ASSERT().
>- If StartBit is greater than 7, then ASSERT().
>- If EndBit is greater than 7, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>- If OrData is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>-
>- @param Address MMIO register to write.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..7.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..7.
>- @param OrData The value to OR with value read from the MMIO register.
>-
>- @return The value written back to the MMIO register.
>-
>-**/
>-UINT8
>-EFIAPI
>-MmioBitFieldOr8 (
>- IN UINTN Address,
>- IN UINTN StartBit,
>- IN UINTN EndBit,
>- IN UINT8 OrData
>- )
>-{
>- return MmioWrite8 (
>- Address,
>- BitFieldOr8 (MmioRead8 (Address), StartBit, EndBit, OrData)
>- );
>-}
>-
>-/**
>- Reads a bit field in an 8-bit MMIO register, performs a bitwise AND, and
>- writes the result back to the bit field in the 8-bit MMIO register.
>-
>- Reads the 8-bit MMIO register specified by Address, performs a bitwise
>AND
>- between the read result and the value specified by AndData, and writes the
>- result to the 8-bit MMIO register specified by Address. The value written to
>- the MMIO register is returned. This function must guarantee that all MMIO
>- read and write operations are serialized. Extra left bits in AndData are
>- stripped.
>-
>- If 8-bit MMIO register operations are not supported, then ASSERT().
>- If StartBit is greater than 7, then ASSERT().
>- If EndBit is greater than 7, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>- If AndData is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>-
>- @param Address MMIO register to write.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..7.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..7.
>- @param AndData The value to AND with value read from the MMIO
>register.
>-
>- @return The value written back to the MMIO register.
>-
>-**/
>-UINT8
>-EFIAPI
>-MmioBitFieldAnd8 (
>- IN UINTN Address,
>- IN UINTN StartBit,
>- IN UINTN EndBit,
>- IN UINT8 AndData
>- )
>-{
>- return MmioWrite8 (
>- Address,
>- BitFieldAnd8 (MmioRead8 (Address), StartBit, EndBit, AndData)
>- );
>-}
>-
>-/**
>- Reads a bit field in an 8-bit MMIO register, performs a bitwise AND followed
>- by a bitwise OR, and writes the result back to the bit field in the
>- 8-bit MMIO register.
>-
>- Reads the 8-bit MMIO register specified by Address, performs a bitwise
>AND
>- followed by a bitwise OR between the read result and the value
>- specified by AndData, and writes the result to the 8-bit MMIO register
>- specified by Address. The value written to the MMIO register is returned.
>- This function must guarantee that all MMIO read and write operations are
>- serialized. Extra left bits in both AndData and OrData are stripped.
>-
>- If 8-bit MMIO register operations are not supported, then ASSERT().
>- If StartBit is greater than 7, then ASSERT().
>- If EndBit is greater than 7, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>- If AndData is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>- If OrData is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>-
>- @param Address MMIO register to write.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..7.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..7.
>- @param AndData The value to AND with value read from the MMIO
>register.
>- @param OrData The value to OR with the result of the AND operation.
>-
>- @return The value written back to the MMIO register.
>-
>-**/
>-UINT8
>-EFIAPI
>-MmioBitFieldAndThenOr8 (
>- IN UINTN Address,
>- IN UINTN StartBit,
>- IN UINTN EndBit,
>- IN UINT8 AndData,
>- IN UINT8 OrData
>- )
>-{
>- return MmioWrite8 (
>- Address,
>- BitFieldAndThenOr8 (MmioRead8 (Address), StartBit, EndBit, AndData,
>OrData)
>- );
>-}
>-
>-/**
>- Reads a 16-bit MMIO register, performs a bitwise OR, and writes the
>- result back to the 16-bit MMIO register.
>-
>- Reads the 16-bit MMIO register specified by Address, performs a bitwise
>- inclusive OR between the read result and the value specified by OrData, and
>- writes the result to the 16-bit MMIO register specified by Address. The
>value
>- written to the MMIO register is returned. This function must guarantee that
>- all MMIO read and write operations are serialized.
>-
>- If 16-bit MMIO register operations are not supported, then ASSERT().
>-
>- @param Address The MMIO register to write.
>- @param OrData The value to OR with the value read from the MMIO
>register.
>-
>- @return The value written back to the MMIO register.
>-
>-**/
>-UINT16
>-EFIAPI
>-MmioOr16 (
>- IN UINTN Address,
>- IN UINT16 OrData
>- )
>-{
>- return MmioWrite16 (Address, (UINT16)(MmioRead16 (Address) | OrData));
>-}
>-
>-/**
>- Reads a 16-bit MMIO register, performs a bitwise AND, and writes the result
>- back to the 16-bit MMIO register.
>-
>- Reads the 16-bit MMIO register specified by Address, performs a bitwise
>AND
>- between the read result and the value specified by AndData, and writes the
>- result to the 16-bit MMIO register specified by Address. The value written to
>- the MMIO register is returned. This function must guarantee that all MMIO
>- read and write operations are serialized.
>-
>- If 16-bit MMIO register operations are not supported, then ASSERT().
>-
>- @param Address The MMIO register to write.
>- @param AndData The value to AND with the value read from the MMIO
>register.
>-
>- @return The value written back to the MMIO register.
>-
>-**/
>-UINT16
>-EFIAPI
>-MmioAnd16 (
>- IN UINTN Address,
>- IN UINT16 AndData
>- )
>-{
>- return MmioWrite16 (Address, (UINT16)(MmioRead16 (Address) &
>AndData));
>-}
>-
>-/**
>- Reads a 16-bit MMIO register, performs a bitwise AND followed by a bitwise
>- inclusive OR, and writes the result back to the 16-bit MMIO register.
>-
>- Reads the 16-bit MMIO register specified by Address, performs a bitwise
>AND
>- between the read result and the value specified by AndData, performs a
>- bitwise OR between the result of the AND operation and the value specified
>by
>- OrData, and writes the result to the 16-bit MMIO register specified by
>- Address. The value written to the MMIO register is returned. This function
>- must guarantee that all MMIO read and write operations are serialized.
>-
>- If 16-bit MMIO register operations are not supported, then ASSERT().
>-
>-
>- @param Address The MMIO register to write.
>- @param AndData The value to AND with the value read from the MMIO
>register.
>- @param OrData The value to OR with the result of the AND operation.
>-
>- @return The value written back to the MMIO register.
>-
>-**/
>-UINT16
>-EFIAPI
>-MmioAndThenOr16 (
>- IN UINTN Address,
>- IN UINT16 AndData,
>- IN UINT16 OrData
>- )
>-{
>- return MmioWrite16 (Address, (UINT16)((MmioRead16 (Address) &
>AndData) | OrData));
>-}
>-
>-/**
>- Reads a bit field of a MMIO register.
>-
>- Reads the bit field in a 16-bit MMIO register. The bit field is specified by
>- the StartBit and the EndBit. The value of the bit field is returned.
>-
>- If 16-bit MMIO register operations are not supported, then ASSERT().
>- If StartBit is greater than 15, then ASSERT().
>- If EndBit is greater than 15, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>-
>- @param Address MMIO register to read.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..15.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..15.
>-
>- @return The value read.
>-
>-**/
>-UINT16
>-EFIAPI
>-MmioBitFieldRead16 (
>- IN UINTN Address,
>- IN UINTN StartBit,
>- IN UINTN EndBit
>- )
>-{
>- return BitFieldRead16 (MmioRead16 (Address), StartBit, EndBit);
>-}
>-
>-/**
>- Writes a bit field to a MMIO register.
>-
>- Writes Value to the bit field of the MMIO register. The bit field is
>- specified by the StartBit and the EndBit. All other bits in the destination
>- MMIO register are preserved. The new value of the 16-bit register is
>returned.
>-
>- If 16-bit MMIO register operations are not supported, then ASSERT().
>- If StartBit is greater than 15, then ASSERT().
>- If EndBit is greater than 15, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>- If Value is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>-
>- @param Address MMIO register to write.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..15.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..15.
>- @param Value New value of the bit field.
>-
>- @return The value written back to the MMIO register.
>-
>-**/
>-UINT16
>-EFIAPI
>-MmioBitFieldWrite16 (
>- IN UINTN Address,
>- IN UINTN StartBit,
>- IN UINTN EndBit,
>- IN UINT16 Value
>- )
>-{
>- return MmioWrite16 (
>- Address,
>- BitFieldWrite16 (MmioRead16 (Address), StartBit, EndBit, Value)
>- );
>-}
>-
>-/**
>- Reads a bit field in a 16-bit MMIO register, performs a bitwise OR, and
>- writes the result back to the bit field in the 16-bit MMIO register.
>-
>- Reads the 16-bit MMIO register specified by Address, performs a bitwise
>- inclusive OR between the read result and the value specified by OrData, and
>- writes the result to the 16-bit MMIO register specified by Address. The
>value
>- written to the MMIO register is returned. This function must guarantee that
>- all MMIO read and write operations are serialized. Extra left bits in OrData
>- are stripped.
>-
>- If 16-bit MMIO register operations are not supported, then ASSERT().
>- If StartBit is greater than 15, then ASSERT().
>- If EndBit is greater than 15, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>- If OrData is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>-
>- @param Address MMIO register to write.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..15.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..15.
>- @param OrData The value to OR with value read from the MMIO register.
>-
>- @return The value written back to the MMIO register.
>-
>-**/
>-UINT16
>-EFIAPI
>-MmioBitFieldOr16 (
>- IN UINTN Address,
>- IN UINTN StartBit,
>- IN UINTN EndBit,
>- IN UINT16 OrData
>- )
>-{
>- return MmioWrite16 (
>- Address,
>- BitFieldOr16 (MmioRead16 (Address), StartBit, EndBit, OrData)
>- );
>-}
>-
>-/**
>- Reads a bit field in a 16-bit MMIO register, performs a bitwise AND, and
>- writes the result back to the bit field in the 16-bit MMIO register.
>-
>- Reads the 16-bit MMIO register specified by Address, performs a bitwise
>AND
>- between the read result and the value specified by AndData, and writes the
>- result to the 16-bit MMIO register specified by Address. The value written to
>- the MMIO register is returned. This function must guarantee that all MMIO
>- read and write operations are serialized. Extra left bits in AndData are
>- stripped.
>-
>- If 16-bit MMIO register operations are not supported, then ASSERT().
>- If StartBit is greater than 15, then ASSERT().
>- If EndBit is greater than 15, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>- If AndData is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>-
>- @param Address MMIO register to write.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..15.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..15.
>- @param AndData The value to AND with value read from the MMIO
>register.
>-
>- @return The value written back to the MMIO register.
>-
>-**/
>-UINT16
>-EFIAPI
>-MmioBitFieldAnd16 (
>- IN UINTN Address,
>- IN UINTN StartBit,
>- IN UINTN EndBit,
>- IN UINT16 AndData
>- )
>-{
>- return MmioWrite16 (
>- Address,
>- BitFieldAnd16 (MmioRead16 (Address), StartBit, EndBit, AndData)
>- );
>-}
>-
>-/**
>- Reads a bit field in a 16-bit MMIO register, performs a bitwise AND followed
>- by a bitwise OR, and writes the result back to the bit field in the
>- 16-bit MMIO register.
>-
>- Reads the 16-bit MMIO register specified by Address, performs a bitwise
>AND
>- followed by a bitwise OR between the read result and the value
>- specified by AndData, and writes the result to the 16-bit MMIO register
>- specified by Address. The value written to the MMIO register is returned.
>- This function must guarantee that all MMIO read and write operations are
>- serialized. Extra left bits in both AndData and OrData are stripped.
>-
>- If 16-bit MMIO register operations are not supported, then ASSERT().
>- If StartBit is greater than 15, then ASSERT().
>- If EndBit is greater than 15, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>- If AndData is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>- If OrData is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>-
>- @param Address MMIO register to write.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..15.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..15.
>- @param AndData The value to AND with value read from the MMIO
>register.
>- @param OrData The value to OR with the result of the AND operation.
>-
>- @return The value written back to the MMIO register.
>-
>-**/
>-UINT16
>-EFIAPI
>-MmioBitFieldAndThenOr16 (
>- IN UINTN Address,
>- IN UINTN StartBit,
>- IN UINTN EndBit,
>- IN UINT16 AndData,
>- IN UINT16 OrData
>- )
>-{
>- return MmioWrite16 (
>- Address,
>- BitFieldAndThenOr16 (MmioRead16 (Address), StartBit, EndBit,
>AndData, OrData)
>- );
>-}
>-
>-/**
>- Reads a 32-bit MMIO register, performs a bitwise OR, and writes the
>- result back to the 32-bit MMIO register.
>-
>- Reads the 32-bit MMIO register specified by Address, performs a bitwise
>- inclusive OR between the read result and the value specified by OrData, and
>- writes the result to the 32-bit MMIO register specified by Address. The
>value
>- written to the MMIO register is returned. This function must guarantee that
>- all MMIO read and write operations are serialized.
>-
>- If 32-bit MMIO register operations are not supported, then ASSERT().
>-
>- @param Address The MMIO register to write.
>- @param OrData The value to OR with the value read from the MMIO
>register.
>-
>- @return The value written back to the MMIO register.
>-
>-**/
>-UINT32
>-EFIAPI
>-MmioOr32 (
>- IN UINTN Address,
>- IN UINT32 OrData
>- )
>-{
>- return MmioWrite32 (Address, MmioRead32 (Address) | OrData);
>-}
>-
>-/**
>- Reads a 32-bit MMIO register, performs a bitwise AND, and writes the result
>- back to the 32-bit MMIO register.
>-
>- Reads the 32-bit MMIO register specified by Address, performs a bitwise
>AND
>- between the read result and the value specified by AndData, and writes the
>- result to the 32-bit MMIO register specified by Address. The value written to
>- the MMIO register is returned. This function must guarantee that all MMIO
>- read and write operations are serialized.
>-
>- If 32-bit MMIO register operations are not supported, then ASSERT().
>-
>- @param Address The MMIO register to write.
>- @param AndData The value to AND with the value read from the MMIO
>register.
>-
>- @return The value written back to the MMIO register.
>-
>-**/
>-UINT32
>-EFIAPI
>-MmioAnd32 (
>- IN UINTN Address,
>- IN UINT32 AndData
>- )
>-{
>- return MmioWrite32 (Address, MmioRead32 (Address) & AndData);
>-}
>-
>-/**
>- Reads a 32-bit MMIO register, performs a bitwise AND followed by a bitwise
>- inclusive OR, and writes the result back to the 32-bit MMIO register.
>-
>- Reads the 32-bit MMIO register specified by Address, performs a bitwise
>AND
>- between the read result and the value specified by AndData, performs a
>- bitwise OR between the result of the AND operation and the value specified
>by
>- OrData, and writes the result to the 32-bit MMIO register specified by
>- Address. The value written to the MMIO register is returned. This function
>- must guarantee that all MMIO read and write operations are serialized.
>-
>- If 32-bit MMIO register operations are not supported, then ASSERT().
>-
>-
>- @param Address The MMIO register to write.
>- @param AndData The value to AND with the value read from the MMIO
>register.
>- @param OrData The value to OR with the result of the AND operation.
>-
>- @return The value written back to the MMIO register.
>-
>-**/
>-UINT32
>-EFIAPI
>-MmioAndThenOr32 (
>- IN UINTN Address,
>- IN UINT32 AndData,
>- IN UINT32 OrData
>- )
>-{
>- return MmioWrite32 (Address, (MmioRead32 (Address) & AndData) |
>OrData);
>-}
>-
>-/**
>- Reads a bit field of a MMIO register.
>-
>- Reads the bit field in a 32-bit MMIO register. The bit field is specified by
>- the StartBit and the EndBit. The value of the bit field is returned.
>-
>- If 32-bit MMIO register operations are not supported, then ASSERT().
>- If StartBit is greater than 31, then ASSERT().
>- If EndBit is greater than 31, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>-
>- @param Address MMIO register to read.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..31.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..31.
>-
>- @return The value read.
>-
>-**/
>-UINT32
>-EFIAPI
>-MmioBitFieldRead32 (
>- IN UINTN Address,
>- IN UINTN StartBit,
>- IN UINTN EndBit
>- )
>-{
>- return BitFieldRead32 (MmioRead32 (Address), StartBit, EndBit);
>-}
>-
>-/**
>- Writes a bit field to a MMIO register.
>-
>- Writes Value to the bit field of the MMIO register. The bit field is
>- specified by the StartBit and the EndBit. All other bits in the destination
>- MMIO register are preserved. The new value of the 32-bit register is
>returned.
>-
>- If 32-bit MMIO register operations are not supported, then ASSERT().
>- If StartBit is greater than 31, then ASSERT().
>- If EndBit is greater than 31, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>- If Value is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>-
>- @param Address MMIO register to write.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..31.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..31.
>- @param Value New value of the bit field.
>-
>- @return The value written back to the MMIO register.
>-
>-**/
>-UINT32
>-EFIAPI
>-MmioBitFieldWrite32 (
>- IN UINTN Address,
>- IN UINTN StartBit,
>- IN UINTN EndBit,
>- IN UINT32 Value
>- )
>-{
>- return MmioWrite32 (
>- Address,
>- BitFieldWrite32 (MmioRead32 (Address), StartBit, EndBit, Value)
>- );
>-}
>-
>-/**
>- Reads a bit field in a 32-bit MMIO register, performs a bitwise OR, and
>- writes the result back to the bit field in the 32-bit MMIO register.
>-
>- Reads the 32-bit MMIO register specified by Address, performs a bitwise
>- inclusive OR between the read result and the value specified by OrData, and
>- writes the result to the 32-bit MMIO register specified by Address. The
>value
>- written to the MMIO register is returned. This function must guarantee that
>- all MMIO read and write operations are serialized. Extra left bits in OrData
>- are stripped.
>-
>- If 32-bit MMIO register operations are not supported, then ASSERT().
>- If StartBit is greater than 31, then ASSERT().
>- If EndBit is greater than 31, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>- If OrData is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>-
>- @param Address MMIO register to write.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..31.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..31.
>- @param OrData The value to OR with value read from the MMIO register.
>-
>- @return The value written back to the MMIO register.
>-
>-**/
>-UINT32
>-EFIAPI
>-MmioBitFieldOr32 (
>- IN UINTN Address,
>- IN UINTN StartBit,
>- IN UINTN EndBit,
>- IN UINT32 OrData
>- )
>-{
>- return MmioWrite32 (
>- Address,
>- BitFieldOr32 (MmioRead32 (Address), StartBit, EndBit, OrData)
>- );
>-}
>-
>-/**
>- Reads a bit field in a 32-bit MMIO register, performs a bitwise AND, and
>- writes the result back to the bit field in the 32-bit MMIO register.
>-
>- Reads the 32-bit MMIO register specified by Address, performs a bitwise
>AND
>- between the read result and the value specified by AndData, and writes the
>- result to the 32-bit MMIO register specified by Address. The value written to
>- the MMIO register is returned. This function must guarantee that all MMIO
>- read and write operations are serialized. Extra left bits in AndData are
>- stripped.
>-
>- If 32-bit MMIO register operations are not supported, then ASSERT().
>- If StartBit is greater than 31, then ASSERT().
>- If EndBit is greater than 31, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>- If AndData is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>-
>- @param Address MMIO register to write.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..31.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..31.
>- @param AndData The value to AND with value read from the MMIO
>register.
>-
>- @return The value written back to the MMIO register.
>-
>-**/
>-UINT32
>-EFIAPI
>-MmioBitFieldAnd32 (
>- IN UINTN Address,
>- IN UINTN StartBit,
>- IN UINTN EndBit,
>- IN UINT32 AndData
>- )
>-{
>- return MmioWrite32 (
>- Address,
>- BitFieldAnd32 (MmioRead32 (Address), StartBit, EndBit, AndData)
>- );
>-}
>-
>-/**
>- Reads a bit field in a 32-bit MMIO register, performs a bitwise AND followed
>- by a bitwise OR, and writes the result back to the bit field in the
>- 32-bit MMIO register.
>-
>- Reads the 32-bit MMIO register specified by Address, performs a bitwise
>AND
>- followed by a bitwise OR between the read result and the value
>- specified by AndData, and writes the result to the 32-bit MMIO register
>- specified by Address. The value written to the MMIO register is returned.
>- This function must guarantee that all MMIO read and write operations are
>- serialized. Extra left bits in both AndData and OrData are stripped.
>-
>- If 32-bit MMIO register operations are not supported, then ASSERT().
>- If StartBit is greater than 31, then ASSERT().
>- If EndBit is greater than 31, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>- If AndData is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>- If OrData is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>-
>- @param Address MMIO register to write.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..31.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..31.
>- @param AndData The value to AND with value read from the MMIO
>register.
>- @param OrData The value to OR with the result of the AND operation.
>-
>- @return The value written back to the MMIO register.
>-
>-**/
>-UINT32
>-EFIAPI
>-MmioBitFieldAndThenOr32 (
>- IN UINTN Address,
>- IN UINTN StartBit,
>- IN UINTN EndBit,
>- IN UINT32 AndData,
>- IN UINT32 OrData
>- )
>-{
>- return MmioWrite32 (
>- Address,
>- BitFieldAndThenOr32 (MmioRead32 (Address), StartBit, EndBit,
>AndData, OrData)
>- );
>-}
>-
>-/**
>- Reads a 64-bit MMIO register, performs a bitwise OR, and writes the
>- result back to the 64-bit MMIO register.
>-
>- Reads the 64-bit MMIO register specified by Address, performs a bitwise
>- inclusive OR between the read result and the value specified by OrData, and
>- writes the result to the 64-bit MMIO register specified by Address. The
>value
>- written to the MMIO register is returned. This function must guarantee that
>- all MMIO read and write operations are serialized.
>-
>- If 64-bit MMIO register operations are not supported, then ASSERT().
>-
>- @param Address The MMIO register to write.
>- @param OrData The value to OR with the value read from the MMIO
>register.
>-
>- @return The value written back to the MMIO register.
>-
>-**/
>-UINT64
>-EFIAPI
>-MmioOr64 (
>- IN UINTN Address,
>- IN UINT64 OrData
>- )
>-{
>- return MmioWrite64 (Address, MmioRead64 (Address) | OrData);
>-}
>-
>-/**
>- Reads a 64-bit MMIO register, performs a bitwise AND, and writes the result
>- back to the 64-bit MMIO register.
>-
>- Reads the 64-bit MMIO register specified by Address, performs a bitwise
>AND
>- between the read result and the value specified by AndData, and writes the
>- result to the 64-bit MMIO register specified by Address. The value written to
>- the MMIO register is returned. This function must guarantee that all MMIO
>- read and write operations are serialized.
>-
>- If 64-bit MMIO register operations are not supported, then ASSERT().
>-
>- @param Address The MMIO register to write.
>- @param AndData The value to AND with the value read from the MMIO
>register.
>-
>- @return The value written back to the MMIO register.
>-
>-**/
>-UINT64
>-EFIAPI
>-MmioAnd64 (
>- IN UINTN Address,
>- IN UINT64 AndData
>- )
>-{
>- return MmioWrite64 (Address, MmioRead64 (Address) & AndData);
>-}
>-
>-/**
>- Reads a 64-bit MMIO register, performs a bitwise AND followed by a bitwise
>- inclusive OR, and writes the result back to the 64-bit MMIO register.
>-
>- Reads the 64-bit MMIO register specified by Address, performs a bitwise
>AND
>- between the read result and the value specified by AndData, performs a
>- bitwise OR between the result of the AND operation and the value specified
>by
>- OrData, and writes the result to the 64-bit MMIO register specified by
>- Address. The value written to the MMIO register is returned. This function
>- must guarantee that all MMIO read and write operations are serialized.
>-
>- If 64-bit MMIO register operations are not supported, then ASSERT().
>-
>-
>- @param Address The MMIO register to write.
>- @param AndData The value to AND with the value read from the MMIO
>register.
>- @param OrData The value to OR with the result of the AND operation.
>-
>- @return The value written back to the MMIO register.
>-
>-**/
>-UINT64
>-EFIAPI
>-MmioAndThenOr64 (
>- IN UINTN Address,
>- IN UINT64 AndData,
>- IN UINT64 OrData
>- )
>-{
>- return MmioWrite64 (Address, (MmioRead64 (Address) & AndData) |
>OrData);
>-}
>-
>-/**
>- Reads a bit field of a MMIO register.
>-
>- Reads the bit field in a 64-bit MMIO register. The bit field is specified by
>- the StartBit and the EndBit. The value of the bit field is returned.
>-
>- If 64-bit MMIO register operations are not supported, then ASSERT().
>- If StartBit is greater than 63, then ASSERT().
>- If EndBit is greater than 63, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>-
>- @param Address MMIO register to read.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..63.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..63.
>-
>- @return The value read.
>-
>-**/
>-UINT64
>-EFIAPI
>-MmioBitFieldRead64 (
>- IN UINTN Address,
>- IN UINTN StartBit,
>- IN UINTN EndBit
>- )
>-{
>- return BitFieldRead64 (MmioRead64 (Address), StartBit, EndBit);
>-}
>-
>-/**
>- Writes a bit field to a MMIO register.
>-
>- Writes Value to the bit field of the MMIO register. The bit field is
>- specified by the StartBit and the EndBit. All other bits in the destination
>- MMIO register are preserved. The new value of the 64-bit register is
>returned.
>-
>- If 64-bit MMIO register operations are not supported, then ASSERT().
>- If StartBit is greater than 63, then ASSERT().
>- If EndBit is greater than 63, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>- If Value is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>-
>- @param Address MMIO register to write.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..63.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..63.
>- @param Value New value of the bit field.
>-
>- @return The value written back to the MMIO register.
>-
>-**/
>-UINT64
>-EFIAPI
>-MmioBitFieldWrite64 (
>- IN UINTN Address,
>- IN UINTN StartBit,
>- IN UINTN EndBit,
>- IN UINT64 Value
>- )
>-{
>- return MmioWrite64 (
>- Address,
>- BitFieldWrite64 (MmioRead64 (Address), StartBit, EndBit, Value)
>- );
>-}
>-
>-/**
>- Reads a bit field in a 64-bit MMIO register, performs a bitwise OR, and
>- writes the result back to the bit field in the 64-bit MMIO register.
>-
>- Reads the 64-bit MMIO register specified by Address, performs a bitwise
>- inclusive OR between the read result and the value specified by OrData, and
>- writes the result to the 64-bit MMIO register specified by Address. The
>value
>- written to the MMIO register is returned. This function must guarantee that
>- all MMIO read and write operations are serialized. Extra left bits in OrData
>- are stripped.
>-
>- If 64-bit MMIO register operations are not supported, then ASSERT().
>- If StartBit is greater than 63, then ASSERT().
>- If EndBit is greater than 63, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>- If OrData is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>-
>- @param Address MMIO register to write.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..63.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..63.
>- @param OrData The value to OR with value read from the MMIO register.
>-
>- @return The value written back to the MMIO register.
>-
>-**/
>-UINT64
>-EFIAPI
>-MmioBitFieldOr64 (
>- IN UINTN Address,
>- IN UINTN StartBit,
>- IN UINTN EndBit,
>- IN UINT64 OrData
>- )
>-{
>- return MmioWrite64 (
>- Address,
>- BitFieldOr64 (MmioRead64 (Address), StartBit, EndBit, OrData)
>- );
>-}
>-
>-/**
>- Reads a bit field in a 64-bit MMIO register, performs a bitwise AND, and
>- writes the result back to the bit field in the 64-bit MMIO register.
>-
>- Reads the 64-bit MMIO register specified by Address, performs a bitwise
>AND
>- between the read result and the value specified by AndData, and writes the
>- result to the 64-bit MMIO register specified by Address. The value written to
>- the MMIO register is returned. This function must guarantee that all MMIO
>- read and write operations are serialized. Extra left bits in AndData are
>- stripped.
>-
>- If 64-bit MMIO register operations are not supported, then ASSERT().
>- If StartBit is greater than 63, then ASSERT().
>- If EndBit is greater than 63, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>- If AndData is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>-
>- @param Address MMIO register to write.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..63.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..63.
>- @param AndData The value to AND with value read from the MMIO
>register.
>-
>- @return The value written back to the MMIO register.
>-
>-**/
>-UINT64
>-EFIAPI
>-MmioBitFieldAnd64 (
>- IN UINTN Address,
>- IN UINTN StartBit,
>- IN UINTN EndBit,
>- IN UINT64 AndData
>- )
>-{
>- return MmioWrite64 (
>- Address,
>- BitFieldAnd64 (MmioRead64 (Address), StartBit, EndBit, AndData)
>- );
>-}
>-
>-/**
>- Reads a bit field in a 64-bit MMIO register, performs a bitwise AND followed
>- by a bitwise OR, and writes the result back to the bit field in the
>- 64-bit MMIO register.
>-
>- Reads the 64-bit MMIO register specified by Address, performs a bitwise
>AND
>- followed by a bitwise OR between the read result and the value
>- specified by AndData, and writes the result to the 64-bit MMIO register
>- specified by Address. The value written to the MMIO register is returned.
>- This function must guarantee that all MMIO read and write operations are
>- serialized. Extra left bits in both AndData and OrData are stripped.
>-
>- If 64-bit MMIO register operations are not supported, then ASSERT().
>- If StartBit is greater than 63, then ASSERT().
>- If EndBit is greater than 63, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>- If AndData is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>- If OrData is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>-
>- @param Address MMIO register to write.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..63.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..63.
>- @param AndData The value to AND with value read from the MMIO
>register.
>- @param OrData The value to OR with the result of the AND operation.
>-
>- @return The value written back to the MMIO register.
>-
>-**/
>-UINT64
>-EFIAPI
>-MmioBitFieldAndThenOr64 (
>- IN UINTN Address,
>- IN UINTN StartBit,
>- IN UINTN EndBit,
>- IN UINT64 AndData,
>- IN UINT64 OrData
>- )
>-{
>- return MmioWrite64 (
>- Address,
>- BitFieldAndThenOr64 (MmioRead64 (Address), StartBit, EndBit,
>AndData, OrData)
>- );
>-}
>diff --git a/MdePkg/Library/DxeIoLibEsal/IoLib.c
>b/MdePkg/Library/DxeIoLibEsal/IoLib.c
>deleted file mode 100644
>index ab186a6d32..0000000000
>--- a/MdePkg/Library/DxeIoLibEsal/IoLib.c
>+++ /dev/null
>@@ -1,879 +0,0 @@
>-/** @file
>- I/O Library basic function implementation and worker functions.
>-
>- Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
>- Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
>-
>- This program and the accompanying materials
>- are licensed and made available under the terms and conditions of the BSD
>License
>- which accompanies this distribution. The full text of the license may be
>found at
>- http://opensource.org/licenses/bsd-license.php.
>-
>- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-
>-**/
>-
>-#include "DxeIoLibEsalInternal.h"
>-
>-/**
>- Reads registers in the EFI CPU I/O space.
>-
>- Reads the I/O port specified by Port with registers width specified by Width.
>- The read value is returned.
>-
>- This function must guarantee that all I/O read and write operations are
>serialized.
>- If such operations are not supported, then ASSERT().
>-
>- @param Port The base address of the I/O operation.
>- The caller is responsible for aligning the Address if required.
>- @param Width The width of the I/O operation.
>-
>- @return Data read from registers in the EFI CPU I/O space.
>-
>-**/
>-UINT64
>-EFIAPI
>-IoReadWorker (
>- IN UINTN Port,
>- IN EFI_CPU_IO_PROTOCOL_WIDTH Width
>- )
>-{
>- SAL_RETURN_REGS ReturnReg;
>- UINT64 Data;
>-
>- Data = 0;
>-
>- ReturnReg = EsalCall (
>- EFI_EXTENDED_SAL_BASE_IO_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_BASE_IO_SERVICES_PROTOCOL_GUID_HI,
>- IoReadFunctionId,
>- (UINT64)Width,
>- Port,
>- 1,
>- (UINT64)&Data,
>- 0,
>- 0,
>- 0
>- );
>- ASSERT (ReturnReg.Status == EFI_SAL_SUCCESS);
>- return Data;
>-}
>-
>-/**
>- Writes registers in the EFI CPU I/O space.
>-
>- Writes the I/O port specified by Port with registers width and value specified
>by Width
>- and Data respectively. Data is returned.
>-
>- This function must guarantee that all I/O read and write operations are
>serialized.
>- If such operations are not supported, then ASSERT().
>-
>- @param Port The base address of the I/O operation.
>- The caller is responsible for aligning the Address if required.
>- @param Width The width of the I/O operation.
>- @param Data The value to write to the I/O port.
>-
>- @return The parameter of Data.
>-
>-**/
>-UINT64
>-EFIAPI
>-IoWriteWorker (
>- IN UINTN Port,
>- IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
>- IN UINT64 Data
>- )
>-{
>- SAL_RETURN_REGS ReturnReg;
>-
>- ReturnReg = EsalCall (
>- EFI_EXTENDED_SAL_BASE_IO_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_BASE_IO_SERVICES_PROTOCOL_GUID_HI,
>- IoWriteFunctionId,
>- (UINT64)Width,
>- Port,
>- 1,
>- (UINT64)&Data,
>- 0,
>- 0,
>- 0
>- );
>- ASSERT (ReturnReg.Status == EFI_SAL_SUCCESS);
>- return Data;
>-}
>-
>-/**
>- Reads registers in the EFI CPU I/O space.
>-
>- Reads the I/O port specified by Port with registers width specified by Width.
>- The port is read Count times, and the read data is stored in the provided
>Buffer.
>-
>- This function must guarantee that all I/O read and write operations are
>serialized.
>- If such operations are not supported, then ASSERT().
>-
>- @param Port The base address of the I/O operation.
>- The caller is responsible for aligning the Address if required.
>- @param Width The width of the I/O operation.
>- @param Count The number of times to read I/O port.
>- @param Buffer The buffer to store the read data into.
>-
>-**/
>-VOID
>-EFIAPI
>-IoReadFifoWorker (
>- IN UINTN Port,
>- IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
>- IN UINTN Count,
>- IN VOID *Buffer
>- )
>-{
>- SAL_RETURN_REGS ReturnReg;
>-
>- ReturnReg = EsalCall (
>- EFI_EXTENDED_SAL_BASE_IO_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_BASE_IO_SERVICES_PROTOCOL_GUID_HI,
>- IoReadFunctionId,
>- (UINT64)Width,
>- Port,
>- Count,
>- (UINT64)Buffer,
>- 0,
>- 0,
>- 0
>- );
>- ASSERT (ReturnReg.Status == EFI_SAL_SUCCESS);
>-}
>-
>-/**
>- Writes registers in the EFI CPU I/O space.
>-
>- Writes the I/O port specified by Port with registers width specified by Width.
>- The port is written Count times, and the write data is retrieved from the
>provided Buffer.
>-
>- This function must guarantee that all I/O read and write operations are
>serialized.
>- If such operations are not supported, then ASSERT().
>-
>- @param Port The base address of the I/O operation.
>- The caller is responsible for aligning the Address if required.
>- @param Width The width of the I/O operation.
>- @param Count The number of times to write I/O port.
>- @param Buffer The buffer to store the read data into.
>-
>-**/
>-VOID
>-EFIAPI
>-IoWriteFifoWorker (
>- IN UINTN Port,
>- IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
>- IN UINTN Count,
>- IN VOID *Buffer
>- )
>-{
>- SAL_RETURN_REGS ReturnReg;
>-
>- ReturnReg = EsalCall (
>- EFI_EXTENDED_SAL_BASE_IO_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_BASE_IO_SERVICES_PROTOCOL_GUID_HI,
>- IoWriteFunctionId,
>- (UINT64)Width,
>- Port,
>- Count,
>- (UINT64)Buffer,
>- 0,
>- 0,
>- 0
>- );
>- ASSERT (ReturnReg.Status == EFI_SAL_SUCCESS);
>-}
>-
>-/**
>- Reads memory-mapped registers in the EFI system memory space.
>-
>- Reads the MMIO registers specified by Address with registers width
>specified by Width.
>- The read value is returned. If such operations are not supported, then
>ASSERT().
>- This function must guarantee that all MMIO read and write operations are
>serialized.
>-
>- @param Address The MMIO register to read.
>- The caller is responsible for aligning the Address if required.
>- @param Width The width of the I/O operation.
>-
>- @return Data read from registers in the EFI system memory space.
>-
>-**/
>-UINT64
>-EFIAPI
>-MmioReadWorker (
>- IN UINTN Address,
>- IN EFI_CPU_IO_PROTOCOL_WIDTH Width
>- )
>-{
>- SAL_RETURN_REGS ReturnReg;
>- UINT64 Data;
>-
>- Data = 0;
>-
>- ReturnReg = EsalCall (
>- EFI_EXTENDED_SAL_BASE_IO_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_BASE_IO_SERVICES_PROTOCOL_GUID_HI,
>- MemReadFunctionId,
>- (UINT64)Width,
>- Address,
>- 1,
>- (UINT64)&Data,
>- 0,
>- 0,
>- 0
>- );
>- ASSERT (ReturnReg.Status == EFI_SAL_SUCCESS);
>- return Data;
>-}
>-
>-/**
>- Writes memory-mapped registers in the EFI system memory space.
>-
>- Writes the MMIO registers specified by Address with registers width and
>value specified by Width
>- and Data respectively. Data is returned. If such operations are not
>supported, then ASSERT().
>- This function must guarantee that all MMIO read and write operations are
>serialized.
>-
>- @param Address The MMIO register to read.
>- The caller is responsible for aligning the Address if required.
>- @param Width The width of the I/O operation.
>- @param Data The value to write to memory-mapped registers
>-
>- @return Data read from registers in the EFI system memory space.
>-
>-**/
>-UINT64
>-EFIAPI
>-MmioWriteWorker (
>- IN UINTN Address,
>- IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
>- IN UINT64 Data
>- )
>-{
>- SAL_RETURN_REGS ReturnReg;
>-
>- ReturnReg = EsalCall (
>- EFI_EXTENDED_SAL_BASE_IO_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_BASE_IO_SERVICES_PROTOCOL_GUID_HI,
>- MemWriteFunctionId,
>- (UINT64)Width,
>- Address,
>- 1,
>- (UINT64)&Data,
>- 0,
>- 0,
>- 0
>- );
>- ASSERT (ReturnReg.Status == EFI_SAL_SUCCESS);
>- return Data;
>-}
>-
>-/**
>- Reads an 8-bit I/O port.
>-
>- Reads the 8-bit I/O port specified by Port. The 8-bit read value is returned.
>- This function must guarantee that all I/O read and write operations are
>- serialized.
>-
>- If 8-bit I/O port operations are not supported, then ASSERT().
>-
>- @param Port The I/O port to read.
>-
>- @return The value read.
>-
>-**/
>-UINT8
>-EFIAPI
>-IoRead8 (
>- IN UINTN Port
>- )
>-{
>- return (UINT8)IoReadWorker (Port, EfiCpuIoWidthUint8);
>-}
>-
>-/**
>- Writes an 8-bit I/O port.
>-
>- Writes the 8-bit I/O port specified by Port with the value specified by Value
>- and returns Value. This function must guarantee that all I/O read and write
>- operations are serialized.
>-
>- If 8-bit I/O port operations are not supported, then ASSERT().
>-
>- @param Port The I/O port to write.
>- @param Value The value to write to the I/O port.
>-
>- @return The value written the I/O port.
>-
>-**/
>-UINT8
>-EFIAPI
>-IoWrite8 (
>- IN UINTN Port,
>- IN UINT8 Value
>- )
>-{
>- return (UINT8)IoWriteWorker (Port, EfiCpuIoWidthUint8, Value);
>-}
>-
>-/**
>- Reads a 16-bit I/O port.
>-
>- Reads the 16-bit I/O port specified by Port. The 16-bit read value is returned.
>- This function must guarantee that all I/O read and write operations are
>- serialized.
>-
>- If 16-bit I/O port operations are not supported, then ASSERT().
>-
>- @param Port The I/O port to read.
>-
>- @return The value read.
>-
>-**/
>-UINT16
>-EFIAPI
>-IoRead16 (
>- IN UINTN Port
>- )
>-{
>- //
>- // Make sure Port is aligned on a 16-bit boundary.
>- //
>- ASSERT ((Port & 1) == 0);
>- return (UINT16)IoReadWorker (Port, EfiCpuIoWidthUint16);
>-}
>-
>-/**
>- Writes a 16-bit I/O port.
>-
>- Writes the 16-bit I/O port specified by Port with the value specified by Value
>- and returns Value. This function must guarantee that all I/O read and write
>- operations are serialized.
>-
>- If 16-bit I/O port operations are not supported, then ASSERT().
>-
>- @param Port The I/O port to write.
>- @param Value The value to write to the I/O port.
>-
>- @return The value written the I/O port.
>-
>-**/
>-UINT16
>-EFIAPI
>-IoWrite16 (
>- IN UINTN Port,
>- IN UINT16 Value
>- )
>-{
>- //
>- // Make sure Port is aligned on a 16-bit boundary.
>- //
>- ASSERT ((Port & 1) == 0);
>- return (UINT16)IoWriteWorker (Port, EfiCpuIoWidthUint16, Value);
>-}
>-
>-/**
>- Reads a 32-bit I/O port.
>-
>- Reads the 32-bit I/O port specified by Port. The 32-bit read value is returned.
>- This function must guarantee that all I/O read and write operations are
>- serialized.
>-
>- If 32-bit I/O port operations are not supported, then ASSERT().
>-
>- @param Port The I/O port to read.
>-
>- @return The value read.
>-
>-**/
>-UINT32
>-EFIAPI
>-IoRead32 (
>- IN UINTN Port
>- )
>-{
>- //
>- // Make sure Port is aligned on a 32-bit boundary.
>- //
>- ASSERT ((Port & 3) == 0);
>- return (UINT32)IoReadWorker (Port, EfiCpuIoWidthUint32);
>-}
>-
>-/**
>- Writes a 32-bit I/O port.
>-
>- Writes the 32-bit I/O port specified by Port with the value specified by Value
>- and returns Value. This function must guarantee that all I/O read and write
>- operations are serialized.
>-
>- If 32-bit I/O port operations are not supported, then ASSERT().
>-
>- @param Port The I/O port to write.
>- @param Value The value to write to the I/O port.
>-
>- @return The value written the I/O port.
>-
>-**/
>-UINT32
>-EFIAPI
>-IoWrite32 (
>- IN UINTN Port,
>- IN UINT32 Value
>- )
>-{
>- //
>- // Make sure Port is aligned on a 32-bit boundary.
>- //
>- ASSERT ((Port & 3) == 0);
>- return (UINT32)IoWriteWorker (Port, EfiCpuIoWidthUint32, Value);
>-}
>-
>-/**
>- Reads a 64-bit I/O port.
>-
>- Reads the 64-bit I/O port specified by Port. The 64-bit read value is returned.
>- This function must guarantee that all I/O read and write operations are
>- serialized.
>-
>- If 64-bit I/O port operations are not supported, then ASSERT().
>-
>- @param Port The I/O port to read.
>-
>- @return The value read.
>-
>-**/
>-UINT64
>-EFIAPI
>-IoRead64 (
>- IN UINTN Port
>- )
>-{
>- //
>- // Make sure Port is aligned on a 64-bit boundary.
>- //
>- ASSERT ((Port & 7) == 0);
>- return IoReadWorker (Port, EfiCpuIoWidthUint64);
>-}
>-
>-/**
>- Writes a 64-bit I/O port.
>-
>- Writes the 64-bit I/O port specified by Port with the value specified by Value
>- and returns Value. This function must guarantee that all I/O read and write
>- operations are serialized.
>-
>- If 64-bit I/O port operations are not supported, then ASSERT().
>-
>- @param Port The I/O port to write.
>- @param Value The value to write to the I/O port.
>-
>- @return The value written the I/O port.
>-
>-**/
>-UINT64
>-EFIAPI
>-IoWrite64 (
>- IN UINTN Port,
>- IN UINT64 Value
>- )
>-{
>- //
>- // Make sure Port is aligned on a 64-bit boundary.
>- //
>- ASSERT ((Port & 7) == 0);
>- return IoWriteWorker (Port, EfiCpuIoWidthUint64, Value);
>-}
>-
>-/**
>- Reads an 8-bit I/O port fifo into a block of memory.
>-
>- Reads the 8-bit I/O fifo port specified by Port.
>- The port is read Count times, and the read data is
>- stored in the provided Buffer.
>-
>- This function must guarantee that all I/O read and write operations are
>- serialized.
>-
>- If 8-bit I/O port operations are not supported, then ASSERT().
>-
>- @param Port The I/O port to read.
>- @param Count The number of times to read I/O port.
>- @param Buffer The buffer to store the read data into.
>-
>-**/
>-VOID
>-EFIAPI
>-IoReadFifo8 (
>- IN UINTN Port,
>- IN UINTN Count,
>- OUT VOID *Buffer
>- )
>-{
>- IoReadFifoWorker (Port, EfiCpuIoWidthFifoUint8, Count, Buffer);
>-}
>-
>-/**
>- Writes a block of memory into an 8-bit I/O port fifo.
>-
>- Writes the 8-bit I/O fifo port specified by Port.
>- The port is written Count times, and the write data is
>- retrieved from the provided Buffer.
>-
>- This function must guarantee that all I/O write and write operations are
>- serialized.
>-
>- If 8-bit I/O port operations are not supported, then ASSERT().
>-
>- @param Port The I/O port to write.
>- @param Count The number of times to write I/O port.
>- @param Buffer The buffer to retrieve the write data from.
>-
>-**/
>-VOID
>-EFIAPI
>-IoWriteFifo8 (
>- IN UINTN Port,
>- IN UINTN Count,
>- IN VOID *Buffer
>- )
>-{
>- IoWriteFifoWorker (Port, EfiCpuIoWidthFifoUint8, Count, Buffer);
>-}
>-
>-/**
>- Reads a 16-bit I/O port fifo into a block of memory.
>-
>- Reads the 16-bit I/O fifo port specified by Port.
>- The port is read Count times, and the read data is
>- stored in the provided Buffer.
>-
>- This function must guarantee that all I/O read and write operations are
>- serialized.
>-
>- If 16-bit I/O port operations are not supported, then ASSERT().
>-
>- @param Port The I/O port to read.
>- @param Count The number of times to read I/O port.
>- @param Buffer The buffer to store the read data into.
>-
>-**/
>-VOID
>-EFIAPI
>-IoReadFifo16 (
>- IN UINTN Port,
>- IN UINTN Count,
>- OUT VOID *Buffer
>- )
>-{
>- //
>- // Make sure Port is aligned on a 16-bit boundary.
>- //
>- ASSERT ((Port & 1) == 0);
>- IoReadFifoWorker (Port, EfiCpuIoWidthFifoUint16, Count, Buffer);
>-}
>-
>-/**
>- Writes a block of memory into a 16-bit I/O port fifo.
>-
>- Writes the 16-bit I/O fifo port specified by Port.
>- The port is written Count times, and the write data is
>- retrieved from the provided Buffer.
>-
>- This function must guarantee that all I/O write and write operations are
>- serialized.
>-
>- If 16-bit I/O port operations are not supported, then ASSERT().
>-
>- @param Port The I/O port to write.
>- @param Count The number of times to write I/O port.
>- @param Buffer The buffer to retrieve the write data from.
>-
>-**/
>-VOID
>-EFIAPI
>-IoWriteFifo16 (
>- IN UINTN Port,
>- IN UINTN Count,
>- IN VOID *Buffer
>- )
>-{
>- //
>- // Make sure Port is aligned on a 16-bit boundary.
>- //
>- ASSERT ((Port & 1) == 0);
>- IoWriteFifoWorker (Port, EfiCpuIoWidthFifoUint16, Count, Buffer);
>-}
>-
>-/**
>- Reads a 32-bit I/O port fifo into a block of memory.
>-
>- Reads the 32-bit I/O fifo port specified by Port.
>- The port is read Count times, and the read data is
>- stored in the provided Buffer.
>-
>- This function must guarantee that all I/O read and write operations are
>- serialized.
>-
>- If 32-bit I/O port operations are not supported, then ASSERT().
>-
>- @param Port The I/O port to read.
>- @param Count The number of times to read I/O port.
>- @param Buffer The buffer to store the read data into.
>-
>-**/
>-VOID
>-EFIAPI
>-IoReadFifo32 (
>- IN UINTN Port,
>- IN UINTN Count,
>- OUT VOID *Buffer
>- )
>-{
>- //
>- // Make sure Port is aligned on a 32-bit boundary.
>- //
>- ASSERT ((Port & 3) == 0);
>- IoReadFifoWorker (Port, EfiCpuIoWidthFifoUint32, Count, Buffer);
>-}
>-
>-/**
>- Writes a block of memory into a 32-bit I/O port fifo.
>-
>- Writes the 32-bit I/O fifo port specified by Port.
>- The port is written Count times, and the write data is
>- retrieved from the provided Buffer.
>-
>- This function must guarantee that all I/O write and write operations are
>- serialized.
>-
>- If 32-bit I/O port operations are not supported, then ASSERT().
>-
>- @param Port The I/O port to write.
>- @param Count The number of times to write I/O port.
>- @param Buffer The buffer to retrieve the write data from.
>-
>-**/
>-VOID
>-EFIAPI
>-IoWriteFifo32 (
>- IN UINTN Port,
>- IN UINTN Count,
>- IN VOID *Buffer
>- )
>-{
>- //
>- // Make sure Port is aligned on a 32-bit boundary.
>- //
>- ASSERT ((Port & 3) == 0);
>- IoWriteFifoWorker (Port, EfiCpuIoWidthFifoUint32, Count, Buffer);
>-}
>-
>-/**
>- Reads an 8-bit MMIO register.
>-
>- Reads the 8-bit MMIO register specified by Address. The 8-bit read value is
>- returned. This function must guarantee that all MMIO read and write
>- operations are serialized.
>-
>- If 8-bit MMIO register operations are not supported, then ASSERT().
>-
>- @param Address The MMIO register to read.
>-
>- @return The value read.
>-
>-**/
>-UINT8
>-EFIAPI
>-MmioRead8 (
>- IN UINTN Address
>- )
>-{
>- return (UINT8)MmioReadWorker (Address, EfiCpuIoWidthUint8);
>-}
>-
>-/**
>- Writes an 8-bit MMIO register.
>-
>- Writes the 8-bit MMIO register specified by Address with the value specified
>- by Value and returns Value. This function must guarantee that all MMIO
>read
>- and write operations are serialized.
>-
>- If 8-bit MMIO register operations are not supported, then ASSERT().
>-
>- @param Address The MMIO register to write.
>- @param Value The value to write to the MMIO register.
>-
>-**/
>-UINT8
>-EFIAPI
>-MmioWrite8 (
>- IN UINTN Address,
>- IN UINT8 Value
>- )
>-{
>- return (UINT8)MmioWriteWorker (Address, EfiCpuIoWidthUint8, Value);
>-}
>-
>-/**
>- Reads a 16-bit MMIO register.
>-
>- Reads the 16-bit MMIO register specified by Address. The 16-bit read value
>is
>- returned. This function must guarantee that all MMIO read and write
>- operations are serialized.
>-
>- If 16-bit MMIO register operations are not supported, then ASSERT().
>-
>- @param Address The MMIO register to read.
>-
>- @return The value read.
>-
>-**/
>-UINT16
>-EFIAPI
>-MmioRead16 (
>- IN UINTN Address
>- )
>-{
>- //
>- // Make sure Address is aligned on a 16-bit boundary.
>- //
>- ASSERT ((Address & 1) == 0);
>- return (UINT16)MmioReadWorker (Address, EfiCpuIoWidthUint16);
>-}
>-
>-/**
>- Writes a 16-bit MMIO register.
>-
>- Writes the 16-bit MMIO register specified by Address with the value
>specified
>- by Value and returns Value. This function must guarantee that all MMIO
>read
>- and write operations are serialized.
>-
>- If 16-bit MMIO register operations are not supported, then ASSERT().
>-
>- @param Address The MMIO register to write.
>- @param Value The value to write to the MMIO register.
>-
>-**/
>-UINT16
>-EFIAPI
>-MmioWrite16 (
>- IN UINTN Address,
>- IN UINT16 Value
>- )
>-{
>- //
>- // Make sure Address is aligned on a 16-bit boundary.
>- //
>- ASSERT ((Address & 1) == 0);
>- return (UINT16)MmioWriteWorker (Address, EfiCpuIoWidthUint16, Value);
>-}
>-
>-/**
>- Reads a 32-bit MMIO register.
>-
>- Reads the 32-bit MMIO register specified by Address. The 32-bit read value
>is
>- returned. This function must guarantee that all MMIO read and write
>- operations are serialized.
>-
>- If 32-bit MMIO register operations are not supported, then ASSERT().
>-
>- @param Address The MMIO register to read.
>-
>- @return The value read.
>-
>-**/
>-UINT32
>-EFIAPI
>-MmioRead32 (
>- IN UINTN Address
>- )
>-{
>- //
>- // Make sure Address is aligned on a 32-bit boundary.
>- //
>- ASSERT ((Address & 3) == 0);
>- return (UINT32)MmioReadWorker (Address, EfiCpuIoWidthUint32);
>-}
>-
>-/**
>- Writes a 32-bit MMIO register.
>-
>- Writes the 32-bit MMIO register specified by Address with the value
>specified
>- by Value and returns Value. This function must guarantee that all MMIO
>read
>- and write operations are serialized.
>-
>- If 32-bit MMIO register operations are not supported, then ASSERT().
>-
>- @param Address The MMIO register to write.
>- @param Value The value to write to the MMIO register.
>-
>-**/
>-UINT32
>-EFIAPI
>-MmioWrite32 (
>- IN UINTN Address,
>- IN UINT32 Value
>- )
>-{
>- //
>- // Make sure Address is aligned on a 32-bit boundary.
>- //
>- ASSERT ((Address & 3) == 0);
>- return (UINT32)MmioWriteWorker (Address, EfiCpuIoWidthUint32, Value);
>-}
>-
>-/**
>- Reads a 64-bit MMIO register.
>-
>- Reads the 64-bit MMIO register specified by Address. The 64-bit read value
>is
>- returned. This function must guarantee that all MMIO read and write
>- operations are serialized.
>-
>- If 64-bit MMIO register operations are not supported, then ASSERT().
>-
>- @param Address The MMIO register to read.
>-
>- @return The value read.
>-
>-**/
>-UINT64
>-EFIAPI
>-MmioRead64 (
>- IN UINTN Address
>- )
>-{
>- //
>- // Make sure Address is aligned on a 64-bit boundary.
>- //
>- ASSERT ((Address & 7) == 0);
>- return (UINT64)MmioReadWorker (Address, EfiCpuIoWidthUint64);
>-}
>-
>-/**
>- Writes a 64-bit MMIO register.
>-
>- Writes the 64-bit MMIO register specified by Address with the value
>specified
>- by Value and returns Value. This function must guarantee that all MMIO
>read
>- and write operations are serialized.
>-
>- If 64-bit MMIO register operations are not supported, then ASSERT().
>-
>- @param Address The MMIO register to write.
>- @param Value The value to write to the MMIO register.
>-
>-**/
>-UINT64
>-EFIAPI
>-MmioWrite64 (
>- IN UINTN Address,
>- IN UINT64 Value
>- )
>-{
>- //
>- // Make sure Address is aligned on a 64-bit boundary.
>- //
>- ASSERT ((Address & 7) == 0);
>- return (UINT64)MmioWriteWorker (Address, EfiCpuIoWidthUint64, Value);
>-}
>diff --git a/MdePkg/Library/DxeIoLibEsal/IoLibMmioBuffer.c
>b/MdePkg/Library/DxeIoLibEsal/IoLibMmioBuffer.c
>deleted file mode 100644
>index 5addef2291..0000000000
>--- a/MdePkg/Library/DxeIoLibEsal/IoLibMmioBuffer.c
>+++ /dev/null
>@@ -1,411 +0,0 @@
>-/** @file
>- I/O Library MMIO Buffer Functions.
>-
>- Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
>- This program and the accompanying materials
>- are licensed and made available under the terms and conditions of the BSD
>License
>- which accompanies this distribution. The full text of the license may be
>found at
>- http://opensource.org/licenses/bsd-license.php.
>-
>- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-
>-**/
>-
>-#include "DxeIoLibEsalInternal.h"
>-
>-/**
>- Copy data from MMIO region to system memory by using 8-bit access.
>-
>- Copy data from MMIO region specified by starting address StartAddress
>- to system memory specified by Buffer by using 8-bit access. The total
>- number of byte to be copied is specified by Length. Buffer is returned.
>-
>- If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().
>- If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
>-
>-
>- @param StartAddress Starting address for the MMIO region to be copied
>from.
>- @param Length Size in bytes of the copy.
>- @param Buffer Pointer to a system memory buffer receiving the data
>read.
>-
>- @return Buffer
>-
>-**/
>-UINT8 *
>-EFIAPI
>-MmioReadBuffer8 (
>- IN UINTN StartAddress,
>- IN UINTN Length,
>- OUT UINT8 *Buffer
>- )
>-{
>- UINT8 *ReturnBuffer;
>-
>- ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));
>- ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));
>-
>- ReturnBuffer = Buffer;
>-
>- while (Length-- > 0) {
>- *(Buffer++) = MmioRead8 (StartAddress++);
>- }
>-
>- return ReturnBuffer;
>-}
>-
>-/**
>- Copy data from MMIO region to system memory by using 16-bit access.
>-
>- Copy data from MMIO region specified by starting address StartAddress
>- to system memory specified by Buffer by using 16-bit access. The total
>- number of byte to be copied is specified by Length. Buffer is returned.
>-
>- If StartAddress is not aligned on a 16-bit boundary, then ASSERT().
>-
>- If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().
>- If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
>-
>- If Length is not aligned on a 16-bit boundary, then ASSERT().
>- If Buffer is not aligned on a 16-bit boundary, then ASSERT().
>-
>- @param StartAddress Starting address for the MMIO region to be copied
>from.
>- @param Length Size in bytes of the copy.
>- @param Buffer Pointer to a system memory buffer receiving the data
>read.
>-
>- @return Buffer
>-
>-**/
>-UINT16 *
>-EFIAPI
>-MmioReadBuffer16 (
>- IN UINTN StartAddress,
>- IN UINTN Length,
>- OUT UINT16 *Buffer
>- )
>-{
>- UINT16 *ReturnBuffer;
>-
>- ASSERT ((StartAddress & (sizeof (UINT16) - 1)) == 0);
>-
>- ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));
>- ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));
>-
>- ASSERT ((Length & (sizeof (UINT16) - 1)) == 0);
>- ASSERT (((UINTN) Buffer & (sizeof (UINT16) - 1)) == 0);
>-
>- ReturnBuffer = Buffer;
>-
>- while (Length > 0) {
>- *(Buffer++) = MmioRead16 (StartAddress);
>- StartAddress += sizeof (UINT16);
>- Length -= sizeof (UINT16);
>- }
>-
>- return ReturnBuffer;
>-}
>-
>-/**
>- Copy data from MMIO region to system memory by using 32-bit access.
>-
>- Copy data from MMIO region specified by starting address StartAddress
>- to system memory specified by Buffer by using 32-bit access. The total
>- number of byte to be copied is specified by Length. Buffer is returned.
>-
>- If StartAddress is not aligned on a 32-bit boundary, then ASSERT().
>-
>- If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().
>- If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
>-
>- If Length is not aligned on a 32-bit boundary, then ASSERT().
>- If Buffer is not aligned on a 32-bit boundary, then ASSERT().
>-
>- @param StartAddress Starting address for the MMIO region to be copied
>from.
>- @param Length Size in bytes of the copy.
>- @param Buffer Pointer to a system memory buffer receiving the data
>read.
>-
>- @return Buffer
>-
>-**/
>-UINT32 *
>-EFIAPI
>-MmioReadBuffer32 (
>- IN UINTN StartAddress,
>- IN UINTN Length,
>- OUT UINT32 *Buffer
>- )
>-{
>- UINT32 *ReturnBuffer;
>-
>- ASSERT ((StartAddress & (sizeof (UINT32) - 1)) == 0);
>-
>- ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));
>- ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));
>-
>- ASSERT ((Length & (sizeof (UINT32) - 1)) == 0);
>- ASSERT (((UINTN) Buffer & (sizeof (UINT32) - 1)) == 0);
>-
>- ReturnBuffer = Buffer;
>-
>- while (Length > 0) {
>- *(Buffer++) = MmioRead32 (StartAddress);
>- StartAddress += sizeof (UINT32);
>- Length -= sizeof (UINT32);
>- }
>-
>- return ReturnBuffer;
>-}
>-
>-/**
>- Copy data from MMIO region to system memory by using 64-bit access.
>-
>- Copy data from MMIO region specified by starting address StartAddress
>- to system memory specified by Buffer by using 64-bit access. The total
>- number of byte to be copied is specified by Length. Buffer is returned.
>-
>- If StartAddress is not aligned on a 64-bit boundary, then ASSERT().
>-
>- If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().
>- If Length is greater than (MAX_ADDRESS - Buffer + 1), then ASSERT().
>-
>- If Length is not aligned on a 64-bit boundary, then ASSERT().
>- If Buffer is not aligned on a 64-bit boundary, then ASSERT().
>-
>- @param StartAddress Starting address for the MMIO region to be copied
>from.
>- @param Length Size in bytes of the copy.
>- @param Buffer Pointer to a system memory buffer receiving the data
>read.
>-
>- @return Buffer
>-
>-**/
>-UINT64 *
>-EFIAPI
>-MmioReadBuffer64 (
>- IN UINTN StartAddress,
>- IN UINTN Length,
>- OUT UINT64 *Buffer
>- )
>-{
>- UINT64 *ReturnBuffer;
>-
>- ASSERT ((StartAddress & (sizeof (UINT64) - 1)) == 0);
>-
>- ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));
>- ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));
>-
>- ASSERT ((Length & (sizeof (UINT64) - 1)) == 0);
>- ASSERT (((UINTN) Buffer & (sizeof (UINT64) - 1)) == 0);
>-
>- ReturnBuffer = Buffer;
>-
>- while (Length > 0) {
>- *(Buffer++) = MmioRead64 (StartAddress);
>- StartAddress += sizeof (UINT64);
>- Length -= sizeof (UINT64);
>- }
>-
>- return ReturnBuffer;
>-}
>-
>-
>-/**
>- Copy data from system memory to MMIO region by using 8-bit access.
>-
>- Copy data from system memory specified by Buffer to MMIO region
>specified
>- by starting address StartAddress by using 8-bit access. The total number
>- of byte to be copied is specified by Length. Buffer is returned.
>-
>- If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().
>- If Length is greater than (MAX_ADDRESS -Buffer + 1), then ASSERT().
>-
>-
>- @param StartAddress Starting address for the MMIO region to be copied
>to.
>- @param Length Size in bytes of the copy.
>- @param Buffer Pointer to a system memory buffer containing the data
>to write.
>-
>- @return Buffer
>-
>-**/
>-UINT8 *
>-EFIAPI
>-MmioWriteBuffer8 (
>- IN UINTN StartAddress,
>- IN UINTN Length,
>- IN CONST UINT8 *Buffer
>- )
>-{
>- VOID* ReturnBuffer;
>-
>- ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));
>- ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));
>-
>- ReturnBuffer = (UINT8 *) Buffer;
>-
>- while (Length-- > 0) {
>- MmioWrite8 (StartAddress++, *(Buffer++));
>- }
>-
>- return ReturnBuffer;
>-
>-}
>-
>-/**
>- Copy data from system memory to MMIO region by using 16-bit access.
>-
>- Copy data from system memory specified by Buffer to MMIO region
>specified
>- by starting address StartAddress by using 16-bit access. The total number
>- of byte to be copied is specified by Length. Buffer is returned.
>-
>- If StartAddress is not aligned on a 16-bit boundary, then ASSERT().
>-
>- If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().
>- If Length is greater than (MAX_ADDRESS -Buffer + 1), then ASSERT().
>-
>- If Length is not aligned on a 16-bit boundary, then ASSERT().
>-
>- If Buffer is not aligned on a 16-bit boundary, then ASSERT().
>-
>- @param StartAddress Starting address for the MMIO region to be copied
>to.
>- @param Length Size in bytes of the copy.
>- @param Buffer Pointer to a system memory buffer containing the data
>to write.
>-
>- @return Buffer
>-
>-**/
>-UINT16 *
>-EFIAPI
>-MmioWriteBuffer16 (
>- IN UINTN StartAddress,
>- IN UINTN Length,
>- IN CONST UINT16 *Buffer
>- )
>-{
>- UINT16 *ReturnBuffer;
>-
>- ASSERT ((StartAddress & (sizeof (UINT16) - 1)) == 0);
>-
>- ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));
>- ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));
>-
>- ASSERT ((Length & (sizeof (UINT16) - 1)) == 0);
>- ASSERT (((UINTN) Buffer & (sizeof (UINT16) - 1)) == 0);
>-
>- ReturnBuffer = (UINT16 *) Buffer;
>-
>- while (Length > 0) {
>- MmioWrite16 (StartAddress, *(Buffer++));
>-
>- StartAddress += sizeof (UINT16);
>- Length -= sizeof (UINT16);
>- }
>-
>- return ReturnBuffer;
>-}
>-
>-
>-/**
>- Copy data from system memory to MMIO region by using 32-bit access.
>-
>- Copy data from system memory specified by Buffer to MMIO region
>specified
>- by starting address StartAddress by using 32-bit access. The total number
>- of byte to be copied is specified by Length. Buffer is returned.
>-
>- If StartAddress is not aligned on a 32-bit boundary, then ASSERT().
>-
>- If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().
>- If Length is greater than (MAX_ADDRESS -Buffer + 1), then ASSERT().
>-
>- If Length is not aligned on a 32-bit boundary, then ASSERT().
>-
>- If Buffer is not aligned on a 32-bit boundary, then ASSERT().
>-
>- @param StartAddress Starting address for the MMIO region to be copied
>to.
>- @param Length Size in bytes of the copy.
>- @param Buffer Pointer to a system memory buffer containing the data
>to write.
>-
>- @return Buffer
>-
>-**/
>-UINT32 *
>-EFIAPI
>-MmioWriteBuffer32 (
>- IN UINTN StartAddress,
>- IN UINTN Length,
>- IN CONST UINT32 *Buffer
>- )
>-{
>- UINT32 *ReturnBuffer;
>-
>- ASSERT ((StartAddress & (sizeof (UINT32) - 1)) == 0);
>-
>- ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));
>- ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));
>-
>- ASSERT ((Length & (sizeof (UINT32) - 1)) == 0);
>- ASSERT (((UINTN) Buffer & (sizeof (UINT32) - 1)) == 0);
>-
>- ReturnBuffer = (UINT32 *) Buffer;
>-
>- while (Length > 0) {
>- MmioWrite32 (StartAddress, *(Buffer++));
>-
>- StartAddress += sizeof (UINT32);
>- Length -= sizeof (UINT32);
>- }
>-
>- return ReturnBuffer;
>-}
>-
>-/**
>- Copy data from system memory to MMIO region by using 64-bit access.
>-
>- Copy data from system memory specified by Buffer to MMIO region
>specified
>- by starting address StartAddress by using 64-bit access. The total number
>- of byte to be copied is specified by Length. Buffer is returned.
>-
>- If StartAddress is not aligned on a 64-bit boundary, then ASSERT().
>-
>- If Length is greater than (MAX_ADDRESS - StartAddress + 1), then ASSERT().
>- If Length is greater than (MAX_ADDRESS -Buffer + 1), then ASSERT().
>-
>- If Length is not aligned on a 64-bit boundary, then ASSERT().
>-
>- If Buffer is not aligned on a 64-bit boundary, then ASSERT().
>-
>- @param StartAddress Starting address for the MMIO region to be copied
>to.
>- @param Length Size in bytes of the copy.
>- @param Buffer Pointer to a system memory buffer containing the data
>to write.
>-
>- @return Buffer
>-
>-**/
>-UINT64 *
>-EFIAPI
>-MmioWriteBuffer64 (
>- IN UINTN StartAddress,
>- IN UINTN Length,
>- IN CONST UINT64 *Buffer
>- )
>-{
>- UINT64 *ReturnBuffer;
>-
>- ASSERT ((StartAddress & (sizeof (UINT64) - 1)) == 0);
>-
>- ASSERT ((Length - 1) <= (MAX_ADDRESS - StartAddress));
>- ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN) Buffer));
>-
>- ASSERT ((Length & (sizeof (UINT64) - 1)) == 0);
>- ASSERT (((UINTN) Buffer & (sizeof (UINT64) - 1)) == 0);
>-
>- ReturnBuffer = (UINT64 *) Buffer;
>-
>- while (Length > 0) {
>- MmioWrite64 (StartAddress, *(Buffer++));
>-
>- StartAddress += sizeof (UINT64);
>- Length -= sizeof (UINT64);
>- }
>-
>- return ReturnBuffer;
>-}
>-
>diff --git a/MdePkg/Library/DxePalLibEsal/DxePalLibEsal.c
>b/MdePkg/Library/DxePalLibEsal/DxePalLibEsal.c
>deleted file mode 100644
>index 6500320456..0000000000
>--- a/MdePkg/Library/DxePalLibEsal/DxePalLibEsal.c
>+++ /dev/null
>@@ -1,73 +0,0 @@
>-/** @file
>- PAL Library Class implementation built upon Extended SAL Procedures.
>-
>- Copyright (c) 2007 - 2011, Intel Corporation. All rights reserved.<BR>
>- This program and the accompanying materials
>- are licensed and made available under the terms and conditions of the BSD
>License
>- which accompanies this distribution. The full text of the license may be
>found at
>- http://opensource.org/licenses/bsd-license.php.
>-
>- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-
>-**/
>-
>-#include <PiDxe.h>
>-
>-#include <Protocol/ExtendedSalServiceClasses.h>
>-
>-#include <Library/PalLib.h>
>-#include <Library/ExtendedSalLib.h>
>-
>-/**
>- Makes a PAL procedure call.
>-
>- This is a wrapper function to make a PAL procedure call. Based on the Index
>value,
>- this API will make static or stacked PAL call. Architected procedures may be
>designated
>- as required or optional. If a PAL procedure is specified as optional, a unique
>return
>- code of 0xFFFFFFFFFFFFFFFF is returned in the Status field of the
>PAL_CALL_RETURN structure.
>- This indicates that the procedure is not present in this PAL implementation.
>It is the
>- caller's responsibility to check for this return code after calling any optional
>PAL
>- procedure. No parameter checking is performed on the 4 input parameters,
>but there are
>- some common rules that the caller should follow when making a PAL call.
>Any address
>- passed to PAL as buffers for return parameters must be 8-byte aligned.
>Unaligned addresses
>- may cause undefined results. For those parameters defined as reserved or
>some fields
>- defined as reserved must be zero filled or the invalid argument return value
>may be
>- returned or undefined result may occur during the execution of the
>procedure.
>- This function is only available on IPF.
>-
>- @param Index - The PAL procedure Index number.
>- @param Arg2 - The 2nd parameter for PAL procedure calls.
>- @param Arg3 - The 3rd parameter for PAL procedure calls.
>- @param Arg4 - The 4th parameter for PAL procedure calls.
>-
>- @return structure returned from the PAL Call procedure, including the
>status and return value.
>-
>-**/
>-PAL_CALL_RETURN
>-EFIAPI
>-PalCall (
>- IN UINT64 Index,
>- IN UINT64 Arg2,
>- IN UINT64 Arg3,
>- IN UINT64 Arg4
>- )
>-{
>- SAL_RETURN_REGS SalReturn;
>- PAL_CALL_RETURN *PalReturn;
>-
>- SalReturn = EsalCall (
>- EFI_EXTENDED_SAL_PAL_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_PAL_SERVICES_PROTOCOL_GUID_HI,
>- PalProcFunctionId,
>- Index,
>- Arg2,
>- Arg3,
>- Arg4,
>- 0,
>- 0,
>- 0
>- );
>- PalReturn = (PAL_CALL_RETURN *) (UINTN) (&SalReturn);
>- return *PalReturn;
>-}
>diff --git a/MdePkg/Library/DxePalLibEsal/DxePalLibEsal.inf
>b/MdePkg/Library/DxePalLibEsal/DxePalLibEsal.inf
>deleted file mode 100644
>index 1340d2902b..0000000000
>--- a/MdePkg/Library/DxePalLibEsal/DxePalLibEsal.inf
>+++ /dev/null
>@@ -1,41 +0,0 @@
>-## @file
>-# Instance of PAL Library Class using Extended SAL functions
>-#
>-# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
>-#
>-# This program and the accompanying materials
>-# are licensed and made available under the terms and conditions of the BSD
>License
>-# which accompanies this distribution. The full text of the license may be
>found at
>-# http://opensource.org/licenses/bsd-license.php.
>-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-#
>-##
>-
>-[Defines]
>- INF_VERSION = 0x00010005
>- BASE_NAME = DxePalLibEsal
>- MODULE_UNI_FILE = DxePalLibEsal.uni
>- FILE_GUID = 8BA65DE3-39E1-4afd-A8FE-7DD0BAFEFCC0
>- MODULE_TYPE = DXE_DRIVER
>- VERSION_STRING = 1.0
>- LIBRARY_CLASS = PalLib|DXE_DRIVER DXE_RUNTIME_DRIVER
>DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
>-
>-#
>-# The following information is for reference only and not required by the
>build tools.
>-#
>-# VALID_ARCHITECTURES = IPF
>-#
>-
>-[Sources.IPF]
>- DxePalLibEsal.c
>-
>-[Packages]
>- MdePkg/MdePkg.dec
>-
>-[LibraryClasses]
>- ExtendedSalLib
>-
>-[Depex.common.DXE_DRIVER, Depex.common.DXE_RUNTIME_DRIVER,
>Depex.common.DXE_SAL_DRIVER, Depex.common.DXE_SMM_DRIVER]
>- gEfiExtendedSalPalServicesProtocolGuid
>-
>diff --git a/MdePkg/Library/DxePcdLib/DxePcdLib.inf
>b/MdePkg/Library/DxePcdLib/DxePcdLib.inf
>index 23cd5d6e70..9c6d76669b 100644
>--- a/MdePkg/Library/DxePcdLib/DxePcdLib.inf
>+++ b/MdePkg/Library/DxePcdLib/DxePcdLib.inf
>@@ -37,10 +37,10 @@
> FILE_GUID = af97eb89-4cc6-45f8-a514-ca025b346480
> MODULE_TYPE = DXE_DRIVER
> VERSION_STRING = 1.0
>- LIBRARY_CLASS = PcdLib|DXE_CORE DXE_DRIVER
>DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER SMM_CORE
>UEFI_APPLICATION UEFI_DRIVER
>+ LIBRARY_CLASS = PcdLib|DXE_CORE DXE_DRIVER
>DXE_RUNTIME_DRIVER DXE_SMM_DRIVER SMM_CORE UEFI_APPLICATION
>UEFI_DRIVER
>
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
>+# VALID_ARCHITECTURES = IA32 X64 EBC
> #
>
> [Sources]
>diff --git a/MdePkg/Library/DxePciLibEsal/DxePciLibEsal.inf
>b/MdePkg/Library/DxePciLibEsal/DxePciLibEsal.inf
>deleted file mode 100644
>index da7772d9c3..0000000000
>--- a/MdePkg/Library/DxePciLibEsal/DxePciLibEsal.inf
>+++ /dev/null
>@@ -1,40 +0,0 @@
>-## @file
>-# PCI Library that uses ESAL services to perform PCI Configuration cycles.
>-#
>-# Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
>-#
>-# This program and the accompanying materials
>-# are licensed and made available under the terms and conditions of the BSD
>License
>-# which accompanies this distribution. The full text of the license may be
>found at
>-# http://opensource.org/licenses/bsd-license.php.
>-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-#
>-##
>-
>-[Defines]
>- INF_VERSION = 0x00010005
>- BASE_NAME = DxePciLibEsal
>- MODULE_UNI_FILE = DxePciLibEsal.uni
>- FILE_GUID = E3441740-3B41-4c90-9C9D-964056C7417D
>- MODULE_TYPE = DXE_DRIVER
>- VERSION_STRING = 1.0
>- LIBRARY_CLASS = PciLib|DXE_DRIVER DXE_RUNTIME_DRIVER
>DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
>-
>-#
>-# The following information is for reference only and not required by the
>build tools.
>-#
>-# VALID_ARCHITECTURES = IPF
>-#
>-
>-[Sources]
>- PciLib.c
>-
>-[Packages]
>- MdePkg/MdePkg.dec
>-
>-[LibraryClasses]
>- ExtendedSalLib
>- DebugLib
>- BaseLib
>-
>diff --git a/MdePkg/Library/DxePciLibEsal/PciLib.c
>b/MdePkg/Library/DxePciLibEsal/PciLib.c
>deleted file mode 100644
>index 28b01c905e..0000000000
>--- a/MdePkg/Library/DxePciLibEsal/PciLib.c
>+++ /dev/null
>@@ -1,1464 +0,0 @@
>-/** @file
>- DXE PCI Library instance layered on top of ESAL services.
>-
>- Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
>- This program and the accompanying materials
>- are licensed and made available under the terms and conditions of the BSD
>License
>- which accompanies this distribution. The full text of the license may be
>found at
>- http://opensource.org/licenses/bsd-license.php.
>-
>- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-
>-**/
>-
>-#include <PiDxe.h>
>-
>-#include <Protocol/ExtendedSalServiceClasses.h>
>-
>-#include <Library/PciLib.h>
>-#include <Library/BaseLib.h>
>-#include <Library/DebugLib.h>
>-#include <Library/ExtendedSalLib.h>
>-
>-/**
>- Assert the validity of a PCI address. A valid PCI address should contain 1's
>- only in the low 28 bits.
>-
>- @param A The address to validate.
>- @param M Additional bits to assert to be zero.
>-
>-**/
>-#define ASSERT_INVALID_PCI_ADDRESS(A,M) \
>- ASSERT (((A) & (~0xfffffff | (M))) == 0)
>-
>-/**
>- Converts a PCI Library Address to a ESAL PCI Service Address.
>- Based on SAL Spec 3.2, there are two SAL PCI Address:
>-
>- If address type = 0
>- Bits 0..7 - Register address
>- Bits 8..10 - Function number
>- Bits 11..15 - Device number
>- Bits 16..23 - Bus number
>- Bits 24..31 - PCI segment group
>- Bits 32..63 - Reserved (0)
>-
>- If address type = 1
>- Bits 0..7 - Register address
>- Bits 8..11 - Extended Register address
>- Bits 12..14 - Function number
>- Bits 15..19 - Device number
>- Bits 20..27 - Bus number
>- Bits 28..43 - PCI segment group
>- Bits 44..63 - Reserved (0)
>-
>- @param A The PCI Library Address to convert.
>-
>-**/
>-#define CONVERT_PCI_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS0(Address)
>((((Address) >> 4) & 0x00ffff00) | ((Address) & 0xff))
>-#define CONVERT_PCI_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS1(Address)
>(Address)
>-
>-/**
>- Check a PCI Library Address is a PCI Compatible Address or not.
>-**/
>-#define IS_PCI_COMPATIBLE_ADDRESS(Address) (((Address) & 0xf00) == 0)
>-
>-/**
>- Internal worker function to read a PCI configuration register.
>-
>- This function wraps EsalPciConfigRead function of Extended SAL PCI
>- Services Class.
>- It reads and returns the PCI configuration register specified by Address,
>- the width of data is specified by Width.
>-
>- @param Address Address that encodes the PCI Bus, Device, Function and
>- Register.
>- @param Width Width of data to read
>-
>- @return The value read from the PCI configuration register.
>-
>-**/
>-UINT32
>-DxePciLibEsalReadWorker (
>- IN UINTN Address,
>- IN UINTN Width
>- )
>-{
>- SAL_RETURN_REGS Return;
>-
>- if (IS_PCI_COMPATIBLE_ADDRESS(Address)) {
>- Return = EsalCall (
>- EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_HI,
>- SalPciConfigReadFunctionId,
>- CONVERT_PCI_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS0 (Address),
>- Width,
>- EFI_SAL_PCI_COMPATIBLE_ADDRESS,
>- 0,
>- 0,
>- 0,
>- 0
>- );
>- } else {
>- Return = EsalCall (
>- EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_HI,
>- SalPciConfigReadFunctionId,
>- CONVERT_PCI_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS1 (Address),
>- Width,
>- EFI_SAL_PCI_EXTENDED_REGISTER_ADDRESS,
>- 0,
>- 0,
>- 0,
>- 0
>- );
>- }
>-
>- return (UINT32) Return.r9;
>-}
>-
>-/**
>- Internal worker function to writes a PCI configuration register.
>-
>- This function wraps EsalPciConfigWrite function of Extended SAL PCI
>- Services Class.
>- It writes the PCI configuration register specified by Address with the
>- value specified by Data. The width of data is specified by Width.
>- Data is returned.
>-
>- @param Address Address that encodes the PCI Bus, Device, Function and
>- Register.
>- @param Width Width of data to write
>- @param Data The value to write.
>-
>- @return The value written to the PCI configuration register.
>-
>-**/
>-UINT32
>-DxePciLibEsalWriteWorker (
>- IN UINTN Address,
>- IN UINTN Width,
>- IN UINT32 Data
>- )
>-{
>- if (IS_PCI_COMPATIBLE_ADDRESS(Address)) {
>- EsalCall (
>- EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_HI,
>- SalPciConfigWriteFunctionId,
>- CONVERT_PCI_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS0 (Address),
>- Width,
>- Data,
>- EFI_SAL_PCI_COMPATIBLE_ADDRESS,
>- 0,
>- 0,
>- 0
>- );
>- } else {
>- EsalCall (
>- EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_HI,
>- SalPciConfigWriteFunctionId,
>- CONVERT_PCI_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS1 (Address),
>- Width,
>- Data,
>- EFI_SAL_PCI_EXTENDED_REGISTER_ADDRESS,
>- 0,
>- 0,
>- 0
>- );
>- }
>-
>- return Data;
>-}
>-
>-/**
>- Register a PCI device so PCI configuration registers may be accessed after
>- SetVirtualAddressMap().
>-
>- If Address > 0x0FFFFFFF, then ASSERT().
>-
>- @param Address Address that encodes the PCI Bus, Device, Function and
>- Register.
>-
>- @retval RETURN_SUCCESS The PCI device was registered for runtime
>access.
>- @retval RETURN_UNSUPPORTED An attempt was made to call this
>function
>- after ExitBootServices().
>- @retval RETURN_UNSUPPORTED The resources required to access the
>PCI device
>- at runtime could not be mapped.
>- @retval RETURN_OUT_OF_RESOURCES There are not enough resources
>available to
>- complete the registration.
>-
>-**/
>-RETURN_STATUS
>-EFIAPI
>-PciRegisterForRuntimeAccess (
>- IN UINTN Address
>- )
>-{
>- ASSERT_INVALID_PCI_ADDRESS (Address, 0);
>- return RETURN_SUCCESS;
>-}
>-
>-/**
>- Reads an 8-bit PCI configuration register.
>-
>- Reads and returns the 8-bit PCI configuration register specified by Address.
>- This function must guarantee that all PCI read and write operations are
>- serialized.
>-
>- If Address > 0x0FFFFFFF, then ASSERT().
>-
>- @param Address Address that encodes the PCI Bus, Device, Function and
>- Register.
>-
>- @return The value read from the PCI configuration register.
>-
>-**/
>-UINT8
>-EFIAPI
>-PciRead8 (
>- IN UINTN Address
>- )
>-{
>- ASSERT_INVALID_PCI_ADDRESS (Address, 0);
>-
>- return (UINT8) DxePciLibEsalReadWorker (Address, 1);
>-}
>-
>-/**
>- Writes an 8-bit PCI configuration register.
>-
>- Writes the 8-bit PCI configuration register specified by Address with the
>- value specified by Value. Value is returned. This function must guarantee
>- that all PCI read and write operations are serialized.
>-
>- If Address > 0x0FFFFFFF, then ASSERT().
>-
>- @param Address Address that encodes the PCI Bus, Device, Function and
>- Register.
>- @param Data The value to write.
>-
>- @return The value written to the PCI configuration register.
>-
>-**/
>-UINT8
>-EFIAPI
>-PciWrite8 (
>- IN UINTN Address,
>- IN UINT8 Data
>- )
>-{
>- ASSERT_INVALID_PCI_ADDRESS (Address, 0);
>-
>- return (UINT8) DxePciLibEsalWriteWorker (Address, 1, Data);
>-}
>-
>-/**
>- Performs a bitwise OR of an 8-bit PCI configuration register with
>- an 8-bit value.
>-
>- Reads the 8-bit PCI configuration register specified by Address, performs a
>- bitwise OR between the read result and the value specified by
>- OrData, and writes the result to the 8-bit PCI configuration register
>- specified by Address. The value written to the PCI configuration register is
>- returned. This function must guarantee that all PCI read and write
>operations
>- are serialized.
>-
>- If Address > 0x0FFFFFFF, then ASSERT().
>-
>- @param Address Address that encodes the PCI Bus, Device, Function and
>- Register.
>- @param OrData The value to OR with the PCI configuration register.
>-
>- @return The value written back to the PCI configuration register.
>-
>-**/
>-UINT8
>-EFIAPI
>-PciOr8 (
>- IN UINTN Address,
>- IN UINT8 OrData
>- )
>-{
>- return PciWrite8 (Address, (UINT8)(PciRead8 (Address) | OrData));
>-}
>-
>-/**
>- Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
>- value.
>-
>- Reads the 8-bit PCI configuration register specified by Address, performs a
>- bitwise AND between the read result and the value specified by AndData,
>and
>- writes the result to the 8-bit PCI configuration register specified by
>- Address. The value written to the PCI configuration register is returned.
>- This function must guarantee that all PCI read and write operations are
>- serialized.
>-
>- If Address > 0x0FFFFFFF, then ASSERT().
>-
>- @param Address Address that encodes the PCI Bus, Device, Function and
>- Register.
>- @param AndData The value to AND with the PCI configuration register.
>-
>- @return The value written back to the PCI configuration register.
>-
>-**/
>-UINT8
>-EFIAPI
>-PciAnd8 (
>- IN UINTN Address,
>- IN UINT8 AndData
>- )
>-{
>- return PciWrite8 (Address, (UINT8)(PciRead8 (Address) & AndData));
>-}
>-
>-/**
>- Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
>- value, followed a bitwise OR with another 8-bit value.
>-
>- Reads the 8-bit PCI configuration register specified by Address, performs a
>- bitwise AND between the read result and the value specified by AndData,
>- performs a bitwise OR between the result of the AND operation and
>- the value specified by OrData, and writes the result to the 8-bit PCI
>- configuration register specified by Address. The value written to the PCI
>- configuration register is returned. This function must guarantee that all PCI
>- read and write operations are serialized.
>-
>- If Address > 0x0FFFFFFF, then ASSERT().
>-
>- @param Address Address that encodes the PCI Bus, Device, Function and
>- Register.
>- @param AndData The value to AND with the PCI configuration register.
>- @param OrData The value to OR with the result of the AND operation.
>-
>- @return The value written back to the PCI configuration register.
>-
>-**/
>-UINT8
>-EFIAPI
>-PciAndThenOr8 (
>- IN UINTN Address,
>- IN UINT8 AndData,
>- IN UINT8 OrData
>- )
>-{
>- return PciWrite8 (Address, (UINT8)((PciRead8 (Address) & AndData) |
>OrData));
>-}
>-
>-/**
>- Reads a bit field of a PCI configuration register.
>-
>- Reads the bit field in an 8-bit PCI configuration register. The bit field is
>- specified by the StartBit and the EndBit. The value of the bit field is
>- returned.
>-
>- If Address > 0x0FFFFFFF, then ASSERT().
>- If StartBit is greater than 7, then ASSERT().
>- If EndBit is greater than 7, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>-
>- @param Address PCI configuration register to read.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..7.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..7.
>-
>- @return The value of the bit field read from the PCI configuration register.
>-
>-**/
>-UINT8
>-EFIAPI
>-PciBitFieldRead8 (
>- IN UINTN Address,
>- IN UINTN StartBit,
>- IN UINTN EndBit
>- )
>-{
>- return BitFieldRead8 (PciRead8 (Address), StartBit, EndBit);
>-}
>-
>-/**
>- Writes a bit field to a PCI configuration register.
>-
>- Writes Value to the bit field of the PCI configuration register. The bit
>- field is specified by the StartBit and the EndBit. All other bits in the
>- destination PCI configuration register are preserved. The new value of the
>- 8-bit register is returned.
>-
>- If Address > 0x0FFFFFFF, then ASSERT().
>- If StartBit is greater than 7, then ASSERT().
>- If EndBit is greater than 7, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>- If Value is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>-
>- @param Address PCI configuration register to write.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..7.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..7.
>- @param Value New value of the bit field.
>-
>- @return The value written back to the PCI configuration register.
>-
>-**/
>-UINT8
>-EFIAPI
>-PciBitFieldWrite8 (
>- IN UINTN Address,
>- IN UINTN StartBit,
>- IN UINTN EndBit,
>- IN UINT8 Value
>- )
>-{
>- return PciWrite8 (
>- Address,
>- BitFieldWrite8 (PciRead8 (Address), StartBit, EndBit, Value)
>- );
>-}
>-
>-/**
>- Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
>- writes the result back to the bit field in the 8-bit port.
>-
>- Reads the 8-bit PCI configuration register specified by Address, performs a
>- bitwise OR between the read result and the value specified by
>- OrData, and writes the result to the 8-bit PCI configuration register
>- specified by Address. The value written to the PCI configuration register is
>- returned. This function must guarantee that all PCI read and write
>operations
>- are serialized. Extra left bits in OrData are stripped.
>-
>- If Address > 0x0FFFFFFF, then ASSERT().
>- If StartBit is greater than 7, then ASSERT().
>- If EndBit is greater than 7, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>- If OrData is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>-
>- @param Address PCI configuration register to write.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..7.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..7.
>- @param OrData The value to OR with the PCI configuration register.
>-
>- @return The value written back to the PCI configuration register.
>-
>-**/
>-UINT8
>-EFIAPI
>-PciBitFieldOr8 (
>- IN UINTN Address,
>- IN UINTN StartBit,
>- IN UINTN EndBit,
>- IN UINT8 OrData
>- )
>-{
>- return PciWrite8 (
>- Address,
>- BitFieldOr8 (PciRead8 (Address), StartBit, EndBit, OrData)
>- );
>-}
>-
>-/**
>- Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
>- AND, and writes the result back to the bit field in the 8-bit register.
>-
>- Reads the 8-bit PCI configuration register specified by Address, performs a
>- bitwise AND between the read result and the value specified by AndData,
>and
>- writes the result to the 8-bit PCI configuration register specified by
>- Address. The value written to the PCI configuration register is returned.
>- This function must guarantee that all PCI read and write operations are
>- serialized. Extra left bits in AndData are stripped.
>-
>- If Address > 0x0FFFFFFF, then ASSERT().
>- If StartBit is greater than 7, then ASSERT().
>- If EndBit is greater than 7, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>- If AndData is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>-
>- @param Address PCI configuration register to write.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..7.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..7.
>- @param AndData The value to AND with the PCI configuration register.
>-
>- @return The value written back to the PCI configuration register.
>-
>-**/
>-UINT8
>-EFIAPI
>-PciBitFieldAnd8 (
>- IN UINTN Address,
>- IN UINTN StartBit,
>- IN UINTN EndBit,
>- IN UINT8 AndData
>- )
>-{
>- return PciWrite8 (
>- Address,
>- BitFieldAnd8 (PciRead8 (Address), StartBit, EndBit, AndData)
>- );
>-}
>-
>-/**
>- Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
>- bitwise OR, and writes the result back to the bit field in the
>- 8-bit port.
>-
>- Reads the 8-bit PCI configuration register specified by Address, performs a
>- bitwise AND followed by a bitwise OR between the read result and
>- the value specified by AndData, and writes the result to the 8-bit PCI
>- configuration register specified by Address. The value written to the PCI
>- configuration register is returned. This function must guarantee that all PCI
>- read and write operations are serialized. Extra left bits in both AndData and
>- OrData are stripped.
>-
>- If Address > 0x0FFFFFFF, then ASSERT().
>- If StartBit is greater than 7, then ASSERT().
>- If EndBit is greater than 7, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>- If AndData is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>- If OrData is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>-
>- @param Address PCI configuration register to write.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..7.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..7.
>- @param AndData The value to AND with the PCI configuration register.
>- @param OrData The value to OR with the result of the AND operation.
>-
>- @return The value written back to the PCI configuration register.
>-
>-**/
>-UINT8
>-EFIAPI
>-PciBitFieldAndThenOr8 (
>- IN UINTN Address,
>- IN UINTN StartBit,
>- IN UINTN EndBit,
>- IN UINT8 AndData,
>- IN UINT8 OrData
>- )
>-{
>- return PciWrite8 (
>- Address,
>- BitFieldAndThenOr8 (PciRead8 (Address), StartBit, EndBit, AndData,
>OrData)
>- );
>-}
>-
>-/**
>- Reads a 16-bit PCI configuration register.
>-
>- Reads and returns the 16-bit PCI configuration register specified by Address.
>- This function must guarantee that all PCI read and write operations are
>- serialized.
>-
>- If Address > 0x0FFFFFFF, then ASSERT().
>- If Address is not aligned on a 16-bit boundary, then ASSERT().
>-
>- @param Address Address that encodes the PCI Bus, Device, Function and
>- Register.
>-
>- @return The value read from the PCI configuration register.
>-
>-**/
>-UINT16
>-EFIAPI
>-PciRead16 (
>- IN UINTN Address
>- )
>-{
>- ASSERT_INVALID_PCI_ADDRESS (Address, 1);
>-
>- return (UINT16) DxePciLibEsalReadWorker (Address, 2);
>-}
>-
>-/**
>- Writes a 16-bit PCI configuration register.
>-
>- Writes the 16-bit PCI configuration register specified by Address with the
>- value specified by Value. Value is returned. This function must guarantee
>- that all PCI read and write operations are serialized.
>-
>- If Address > 0x0FFFFFFF, then ASSERT().
>- If Address is not aligned on a 16-bit boundary, then ASSERT().
>-
>- @param Address Address that encodes the PCI Bus, Device, Function and
>- Register.
>- @param Data The value to write.
>-
>- @return The value written to the PCI configuration register.
>-
>-**/
>-UINT16
>-EFIAPI
>-PciWrite16 (
>- IN UINTN Address,
>- IN UINT16 Data
>- )
>-{
>- ASSERT_INVALID_PCI_ADDRESS (Address, 1);
>-
>- return (UINT16) DxePciLibEsalWriteWorker (Address, 2, Data);
>-}
>-
>-/**
>- Performs a bitwise OR of a 16-bit PCI configuration register with
>- a 16-bit value.
>-
>- Reads the 16-bit PCI configuration register specified by Address, performs a
>- bitwise OR between the read result and the value specified by
>- OrData, and writes the result to the 16-bit PCI configuration register
>- specified by Address. The value written to the PCI configuration register is
>- returned. This function must guarantee that all PCI read and write
>operations
>- are serialized.
>-
>- If Address > 0x0FFFFFFF, then ASSERT().
>- If Address is not aligned on a 16-bit boundary, then ASSERT().
>-
>- @param Address Address that encodes the PCI Bus, Device, Function and
>- Register.
>- @param OrData The value to OR with the PCI configuration register.
>-
>- @return The value written back to the PCI configuration register.
>-
>-**/
>-UINT16
>-EFIAPI
>-PciOr16 (
>- IN UINTN Address,
>- IN UINT16 OrData
>- )
>-{
>- return PciWrite16 (Address, (UINT16)(PciRead16 (Address) | OrData));
>-}
>-
>-/**
>- Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
>- value.
>-
>- Reads the 16-bit PCI configuration register specified by Address, performs a
>- bitwise AND between the read result and the value specified by AndData,
>and
>- writes the result to the 16-bit PCI configuration register specified by
>- Address. The value written to the PCI configuration register is returned.
>- This function must guarantee that all PCI read and write operations are
>- serialized.
>-
>- If Address > 0x0FFFFFFF, then ASSERT().
>- If Address is not aligned on a 16-bit boundary, then ASSERT().
>-
>- @param Address Address that encodes the PCI Bus, Device, Function and
>- Register.
>- @param AndData The value to AND with the PCI configuration register.
>-
>- @return The value written back to the PCI configuration register.
>-
>-**/
>-UINT16
>-EFIAPI
>-PciAnd16 (
>- IN UINTN Address,
>- IN UINT16 AndData
>- )
>-{
>- return PciWrite16 (Address, (UINT16)(PciRead16 (Address) & AndData));
>-}
>-
>-/**
>- Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
>- value, followed a bitwise OR with another 16-bit value.
>-
>- Reads the 16-bit PCI configuration register specified by Address, performs a
>- bitwise AND between the read result and the value specified by AndData,
>- performs a bitwise OR between the result of the AND operation and
>- the value specified by OrData, and writes the result to the 16-bit PCI
>- configuration register specified by Address. The value written to the PCI
>- configuration register is returned. This function must guarantee that all PCI
>- read and write operations are serialized.
>-
>- If Address > 0x0FFFFFFF, then ASSERT().
>- If Address is not aligned on a 16-bit boundary, then ASSERT().
>-
>- @param Address Address that encodes the PCI Bus, Device, Function and
>- Register.
>- @param AndData The value to AND with the PCI configuration register.
>- @param OrData The value to OR with the result of the AND operation.
>-
>- @return The value written back to the PCI configuration register.
>-
>-**/
>-UINT16
>-EFIAPI
>-PciAndThenOr16 (
>- IN UINTN Address,
>- IN UINT16 AndData,
>- IN UINT16 OrData
>- )
>-{
>- return PciWrite16 (Address, (UINT16)((PciRead16 (Address) & AndData) |
>OrData));
>-}
>-
>-/**
>- Reads a bit field of a PCI configuration register.
>-
>- Reads the bit field in a 16-bit PCI configuration register. The bit field is
>- specified by the StartBit and the EndBit. The value of the bit field is
>- returned.
>-
>- If Address > 0x0FFFFFFF, then ASSERT().
>- If Address is not aligned on a 16-bit boundary, then ASSERT().
>- If StartBit is greater than 15, then ASSERT().
>- If EndBit is greater than 15, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>-
>- @param Address PCI configuration register to read.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..15.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..15.
>-
>- @return The value of the bit field read from the PCI configuration register.
>-
>-**/
>-UINT16
>-EFIAPI
>-PciBitFieldRead16 (
>- IN UINTN Address,
>- IN UINTN StartBit,
>- IN UINTN EndBit
>- )
>-{
>- return BitFieldRead16 (PciRead16 (Address), StartBit, EndBit);
>-}
>-
>-/**
>- Writes a bit field to a PCI configuration register.
>-
>- Writes Value to the bit field of the PCI configuration register. The bit
>- field is specified by the StartBit and the EndBit. All other bits in the
>- destination PCI configuration register are preserved. The new value of the
>- 16-bit register is returned.
>-
>- If Address > 0x0FFFFFFF, then ASSERT().
>- If Address is not aligned on a 16-bit boundary, then ASSERT().
>- If StartBit is greater than 15, then ASSERT().
>- If EndBit is greater than 15, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>- If Value is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>-
>- @param Address PCI configuration register to write.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..15.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..15.
>- @param Value New value of the bit field.
>-
>- @return The value written back to the PCI configuration register.
>-
>-**/
>-UINT16
>-EFIAPI
>-PciBitFieldWrite16 (
>- IN UINTN Address,
>- IN UINTN StartBit,
>- IN UINTN EndBit,
>- IN UINT16 Value
>- )
>-{
>- return PciWrite16 (
>- Address,
>- BitFieldWrite16 (PciRead16 (Address), StartBit, EndBit, Value)
>- );
>-}
>-
>-/**
>- Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
>- writes the result back to the bit field in the 16-bit port.
>-
>- Reads the 16-bit PCI configuration register specified by Address, performs a
>- bitwise OR between the read result and the value specified by
>- OrData, and writes the result to the 16-bit PCI configuration register
>- specified by Address. The value written to the PCI configuration register is
>- returned. This function must guarantee that all PCI read and write
>operations
>- are serialized. Extra left bits in OrData are stripped.
>-
>- If Address > 0x0FFFFFFF, then ASSERT().
>- If Address is not aligned on a 16-bit boundary, then ASSERT().
>- If StartBit is greater than 15, then ASSERT().
>- If EndBit is greater than 15, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>- If OrData is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>-
>- @param Address PCI configuration register to write.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..15.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..15.
>- @param OrData The value to OR with the PCI configuration register.
>-
>- @return The value written back to the PCI configuration register.
>-
>-**/
>-UINT16
>-EFIAPI
>-PciBitFieldOr16 (
>- IN UINTN Address,
>- IN UINTN StartBit,
>- IN UINTN EndBit,
>- IN UINT16 OrData
>- )
>-{
>- return PciWrite16 (
>- Address,
>- BitFieldOr16 (PciRead16 (Address), StartBit, EndBit, OrData)
>- );
>-}
>-
>-/**
>- Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
>- AND, and writes the result back to the bit field in the 16-bit register.
>-
>- Reads the 16-bit PCI configuration register specified by Address, performs a
>- bitwise AND between the read result and the value specified by AndData,
>and
>- writes the result to the 16-bit PCI configuration register specified by
>- Address. The value written to the PCI configuration register is returned.
>- This function must guarantee that all PCI read and write operations are
>- serialized. Extra left bits in AndData are stripped.
>-
>- If Address > 0x0FFFFFFF, then ASSERT().
>- If Address is not aligned on a 16-bit boundary, then ASSERT().
>- If StartBit is greater than 15, then ASSERT().
>- If EndBit is greater than 15, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>- If AndData is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>-
>- @param Address PCI configuration register to write.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..15.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..15.
>- @param AndData The value to AND with the PCI configuration register.
>-
>- @return The value written back to the PCI configuration register.
>-
>-**/
>-UINT16
>-EFIAPI
>-PciBitFieldAnd16 (
>- IN UINTN Address,
>- IN UINTN StartBit,
>- IN UINTN EndBit,
>- IN UINT16 AndData
>- )
>-{
>- return PciWrite16 (
>- Address,
>- BitFieldAnd16 (PciRead16 (Address), StartBit, EndBit, AndData)
>- );
>-}
>-
>-/**
>- Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
>- bitwise OR, and writes the result back to the bit field in the
>- 16-bit port.
>-
>- Reads the 16-bit PCI configuration register specified by Address, performs a
>- bitwise AND followed by a bitwise OR between the read result and
>- the value specified by AndData, and writes the result to the 16-bit PCI
>- configuration register specified by Address. The value written to the PCI
>- configuration register is returned. This function must guarantee that all PCI
>- read and write operations are serialized. Extra left bits in both AndData and
>- OrData are stripped.
>-
>- If Address > 0x0FFFFFFF, then ASSERT().
>- If Address is not aligned on a 16-bit boundary, then ASSERT().
>- If StartBit is greater than 15, then ASSERT().
>- If EndBit is greater than 15, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>- If AndData is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>- If OrData is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>-
>- @param Address PCI configuration register to write.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..15.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..15.
>- @param AndData The value to AND with the PCI configuration register.
>- @param OrData The value to OR with the result of the AND operation.
>-
>- @return The value written back to the PCI configuration register.
>-
>-**/
>-UINT16
>-EFIAPI
>-PciBitFieldAndThenOr16 (
>- IN UINTN Address,
>- IN UINTN StartBit,
>- IN UINTN EndBit,
>- IN UINT16 AndData,
>- IN UINT16 OrData
>- )
>-{
>- return PciWrite16 (
>- Address,
>- BitFieldAndThenOr16 (PciRead16 (Address), StartBit, EndBit, AndData,
>OrData)
>- );
>-}
>-
>-/**
>- Reads a 32-bit PCI configuration register.
>-
>- Reads and returns the 32-bit PCI configuration register specified by Address.
>- This function must guarantee that all PCI read and write operations are
>- serialized.
>-
>- If Address > 0x0FFFFFFF, then ASSERT().
>- If Address is not aligned on a 32-bit boundary, then ASSERT().
>-
>- @param Address Address that encodes the PCI Bus, Device, Function and
>- Register.
>-
>- @return The value read from the PCI configuration register.
>-
>-**/
>-UINT32
>-EFIAPI
>-PciRead32 (
>- IN UINTN Address
>- )
>-{
>- ASSERT_INVALID_PCI_ADDRESS (Address, 3);
>-
>- return DxePciLibEsalReadWorker (Address, 4);
>-}
>-
>-/**
>- Writes a 32-bit PCI configuration register.
>-
>- Writes the 32-bit PCI configuration register specified by Address with the
>- value specified by Value. Value is returned. This function must guarantee
>- that all PCI read and write operations are serialized.
>-
>- If Address > 0x0FFFFFFF, then ASSERT().
>- If Address is not aligned on a 32-bit boundary, then ASSERT().
>-
>- @param Address Address that encodes the PCI Bus, Device, Function and
>- Register.
>- @param Data The value to write.
>-
>- @return The value written to the PCI configuration register.
>-
>-**/
>-UINT32
>-EFIAPI
>-PciWrite32 (
>- IN UINTN Address,
>- IN UINT32 Data
>- )
>-{
>- ASSERT_INVALID_PCI_ADDRESS (Address, 3);
>-
>- return DxePciLibEsalWriteWorker (Address, 4, Data);
>-}
>-
>-/**
>- Performs a bitwise OR of a 32-bit PCI configuration register with
>- a 32-bit value.
>-
>- Reads the 32-bit PCI configuration register specified by Address, performs a
>- bitwise OR between the read result and the value specified by
>- OrData, and writes the result to the 32-bit PCI configuration register
>- specified by Address. The value written to the PCI configuration register is
>- returned. This function must guarantee that all PCI read and write
>operations
>- are serialized.
>-
>- If Address > 0x0FFFFFFF, then ASSERT().
>- If Address is not aligned on a 32-bit boundary, then ASSERT().
>-
>- @param Address Address that encodes the PCI Bus, Device, Function and
>- Register.
>- @param OrData The value to OR with the PCI configuration register.
>-
>- @return The value written back to the PCI configuration register.
>-
>-**/
>-UINT32
>-EFIAPI
>-PciOr32 (
>- IN UINTN Address,
>- IN UINT32 OrData
>- )
>-{
>- return PciWrite32 (Address, PciRead32 (Address) | OrData);
>-}
>-
>-/**
>- Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
>- value.
>-
>- Reads the 32-bit PCI configuration register specified by Address, performs a
>- bitwise AND between the read result and the value specified by AndData,
>and
>- writes the result to the 32-bit PCI configuration register specified by
>- Address. The value written to the PCI configuration register is returned.
>- This function must guarantee that all PCI read and write operations are
>- serialized.
>-
>- If Address > 0x0FFFFFFF, then ASSERT().
>- If Address is not aligned on a 32-bit boundary, then ASSERT().
>-
>- @param Address Address that encodes the PCI Bus, Device, Function and
>- Register.
>- @param AndData The value to AND with the PCI configuration register.
>-
>- @return The value written back to the PCI configuration register.
>-
>-**/
>-UINT32
>-EFIAPI
>-PciAnd32 (
>- IN UINTN Address,
>- IN UINT32 AndData
>- )
>-{
>- return PciWrite32 (Address, PciRead32 (Address) & AndData);
>-}
>-
>-/**
>- Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
>- value, followed a bitwise OR with another 32-bit value.
>-
>- Reads the 32-bit PCI configuration register specified by Address, performs a
>- bitwise AND between the read result and the value specified by AndData,
>- performs a bitwise OR between the result of the AND operation and
>- the value specified by OrData, and writes the result to the 32-bit PCI
>- configuration register specified by Address. The value written to the PCI
>- configuration register is returned. This function must guarantee that all PCI
>- read and write operations are serialized.
>-
>- If Address > 0x0FFFFFFF, then ASSERT().
>- If Address is not aligned on a 32-bit boundary, then ASSERT().
>-
>- @param Address Address that encodes the PCI Bus, Device, Function and
>- Register.
>- @param AndData The value to AND with the PCI configuration register.
>- @param OrData The value to OR with the result of the AND operation.
>-
>- @return The value written back to the PCI configuration register.
>-
>-**/
>-UINT32
>-EFIAPI
>-PciAndThenOr32 (
>- IN UINTN Address,
>- IN UINT32 AndData,
>- IN UINT32 OrData
>- )
>-{
>- return PciWrite32 (Address, (PciRead32 (Address) & AndData) | OrData);
>-}
>-
>-/**
>- Reads a bit field of a PCI configuration register.
>-
>- Reads the bit field in a 32-bit PCI configuration register. The bit field is
>- specified by the StartBit and the EndBit. The value of the bit field is
>- returned.
>-
>- If Address > 0x0FFFFFFF, then ASSERT().
>- If Address is not aligned on a 32-bit boundary, then ASSERT().
>- If StartBit is greater than 31, then ASSERT().
>- If EndBit is greater than 31, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>-
>- @param Address PCI configuration register to read.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..31.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..31.
>-
>- @return The value of the bit field read from the PCI configuration register.
>-
>-**/
>-UINT32
>-EFIAPI
>-PciBitFieldRead32 (
>- IN UINTN Address,
>- IN UINTN StartBit,
>- IN UINTN EndBit
>- )
>-{
>- return BitFieldRead32 (PciRead32 (Address), StartBit, EndBit);
>-}
>-
>-/**
>- Writes a bit field to a PCI configuration register.
>-
>- Writes Value to the bit field of the PCI configuration register. The bit
>- field is specified by the StartBit and the EndBit. All other bits in the
>- destination PCI configuration register are preserved. The new value of the
>- 32-bit register is returned.
>-
>- If Address > 0x0FFFFFFF, then ASSERT().
>- If Address is not aligned on a 32-bit boundary, then ASSERT().
>- If StartBit is greater than 31, then ASSERT().
>- If EndBit is greater than 31, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>- If Value is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>-
>- @param Address PCI configuration register to write.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..31.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..31.
>- @param Value New value of the bit field.
>-
>- @return The value written back to the PCI configuration register.
>-
>-**/
>-UINT32
>-EFIAPI
>-PciBitFieldWrite32 (
>- IN UINTN Address,
>- IN UINTN StartBit,
>- IN UINTN EndBit,
>- IN UINT32 Value
>- )
>-{
>- return PciWrite32 (
>- Address,
>- BitFieldWrite32 (PciRead32 (Address), StartBit, EndBit, Value)
>- );
>-}
>-
>-/**
>- Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
>- writes the result back to the bit field in the 32-bit port.
>-
>- Reads the 32-bit PCI configuration register specified by Address, performs a
>- bitwise OR between the read result and the value specified by
>- OrData, and writes the result to the 32-bit PCI configuration register
>- specified by Address. The value written to the PCI configuration register is
>- returned. This function must guarantee that all PCI read and write
>operations
>- are serialized. Extra left bits in OrData are stripped.
>-
>- If Address > 0x0FFFFFFF, then ASSERT().
>- If Address is not aligned on a 32-bit boundary, then ASSERT().
>- If StartBit is greater than 31, then ASSERT().
>- If EndBit is greater than 31, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>- If OrData is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>-
>- @param Address PCI configuration register to write.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..31.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..31.
>- @param OrData The value to OR with the PCI configuration register.
>-
>- @return The value written back to the PCI configuration register.
>-
>-**/
>-UINT32
>-EFIAPI
>-PciBitFieldOr32 (
>- IN UINTN Address,
>- IN UINTN StartBit,
>- IN UINTN EndBit,
>- IN UINT32 OrData
>- )
>-{
>- return PciWrite32 (
>- Address,
>- BitFieldOr32 (PciRead32 (Address), StartBit, EndBit, OrData)
>- );
>-}
>-
>-/**
>- Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
>- AND, and writes the result back to the bit field in the 32-bit register.
>-
>- Reads the 32-bit PCI configuration register specified by Address, performs a
>- bitwise AND between the read result and the value specified by AndData,
>and
>- writes the result to the 32-bit PCI configuration register specified by
>- Address. The value written to the PCI configuration register is returned.
>- This function must guarantee that all PCI read and write operations are
>- serialized. Extra left bits in AndData are stripped.
>-
>- If Address > 0x0FFFFFFF, then ASSERT().
>- If Address is not aligned on a 32-bit boundary, then ASSERT().
>- If StartBit is greater than 31, then ASSERT().
>- If EndBit is greater than 31, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>- If AndData is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>-
>- @param Address PCI configuration register to write.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..31.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..31.
>- @param AndData The value to AND with the PCI configuration register.
>-
>- @return The value written back to the PCI configuration register.
>-
>-**/
>-UINT32
>-EFIAPI
>-PciBitFieldAnd32 (
>- IN UINTN Address,
>- IN UINTN StartBit,
>- IN UINTN EndBit,
>- IN UINT32 AndData
>- )
>-{
>- return PciWrite32 (
>- Address,
>- BitFieldAnd32 (PciRead32 (Address), StartBit, EndBit, AndData)
>- );
>-}
>-
>-/**
>- Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
>- bitwise OR, and writes the result back to the bit field in the
>- 32-bit port.
>-
>- Reads the 32-bit PCI configuration register specified by Address, performs a
>- bitwise AND followed by a bitwise OR between the read result and
>- the value specified by AndData, and writes the result to the 32-bit PCI
>- configuration register specified by Address. The value written to the PCI
>- configuration register is returned. This function must guarantee that all PCI
>- read and write operations are serialized. Extra left bits in both AndData and
>- OrData are stripped.
>-
>- If Address > 0x0FFFFFFF, then ASSERT().
>- If Address is not aligned on a 32-bit boundary, then ASSERT().
>- If StartBit is greater than 31, then ASSERT().
>- If EndBit is greater than 31, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>- If AndData is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>- If OrData is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>-
>- @param Address PCI configuration register to write.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..31.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..31.
>- @param AndData The value to AND with the PCI configuration register.
>- @param OrData The value to OR with the result of the AND operation.
>-
>- @return The value written back to the PCI configuration register.
>-
>-**/
>-UINT32
>-EFIAPI
>-PciBitFieldAndThenOr32 (
>- IN UINTN Address,
>- IN UINTN StartBit,
>- IN UINTN EndBit,
>- IN UINT32 AndData,
>- IN UINT32 OrData
>- )
>-{
>- return PciWrite32 (
>- Address,
>- BitFieldAndThenOr32 (PciRead32 (Address), StartBit, EndBit, AndData,
>OrData)
>- );
>-}
>-
>-/**
>- Reads a range of PCI configuration registers into a caller supplied buffer.
>-
>- Reads the range of PCI configuration registers specified by StartAddress and
>- Size into the buffer specified by Buffer. This function only allows the PCI
>- configuration registers from a single PCI function to be read. Size is
>- returned. When possible 32-bit PCI configuration read cycles are used to
>read
>- from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
>- and 16-bit PCI configuration read cycles may be used at the beginning and
>the
>- end of the range.
>-
>- If StartAddress > 0x0FFFFFFF, then ASSERT().
>- If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
>- If Size > 0 and Buffer is NULL, then ASSERT().
>-
>- @param StartAddress Starting address that encodes the PCI Bus, Device,
>- Function and Register.
>- @param Size Size in bytes of the transfer.
>- @param Buffer Pointer to a buffer receiving the data read.
>-
>- @return Size
>-
>-**/
>-UINTN
>-EFIAPI
>-PciReadBuffer (
>- IN UINTN StartAddress,
>- IN UINTN Size,
>- OUT VOID *Buffer
>- )
>-{
>- UINTN ReturnValue;
>-
>- ASSERT_INVALID_PCI_ADDRESS (StartAddress, 0);
>- ASSERT (((StartAddress & 0xFFF) + Size) <= 0x100);
>-
>- if (Size == 0) {
>- return Size;
>- }
>-
>- ASSERT (Buffer != NULL);
>-
>- //
>- // Save Size for return
>- //
>- ReturnValue = Size;
>-
>- if ((StartAddress & 1) != 0) {
>- //
>- // Read a byte if StartAddress is byte aligned
>- //
>- *(volatile UINT8 *)Buffer = PciRead8 (StartAddress);
>- StartAddress += sizeof (UINT8);
>- Size -= sizeof (UINT8);
>- Buffer = (UINT8*)Buffer + 1;
>- }
>-
>- if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {
>- //
>- // Read a word if StartAddress is word aligned
>- //
>- *(volatile UINT16 *)Buffer = PciRead16 (StartAddress);
>- StartAddress += sizeof (UINT16);
>- Size -= sizeof (UINT16);
>- Buffer = (UINT16*)Buffer + 1;
>- }
>-
>- while (Size >= sizeof (UINT32)) {
>- //
>- // Read as many double words as possible
>- //
>- *(volatile UINT32 *)Buffer = PciRead32 (StartAddress);
>- StartAddress += sizeof (UINT32);
>- Size -= sizeof (UINT32);
>- Buffer = (UINT32*)Buffer + 1;
>- }
>-
>- if (Size >= sizeof (UINT16)) {
>- //
>- // Read the last remaining word if exist
>- //
>- *(volatile UINT16 *)Buffer = PciRead16 (StartAddress);
>- StartAddress += sizeof (UINT16);
>- Size -= sizeof (UINT16);
>- Buffer = (UINT16*)Buffer + 1;
>- }
>-
>- if (Size >= sizeof (UINT8)) {
>- //
>- // Read the last remaining byte if exist
>- //
>- *(volatile UINT8 *)Buffer = PciRead8 (StartAddress);
>- }
>-
>- return ReturnValue;
>-}
>-
>-/**
>- Copies the data in a caller supplied buffer to a specified range of PCI
>- configuration space.
>-
>- Writes the range of PCI configuration registers specified by StartAddress and
>- Size from the buffer specified by Buffer. This function only allows the PCI
>- configuration registers from a single PCI function to be written. Size is
>- returned. When possible 32-bit PCI configuration write cycles are used to
>- write from StartAdress to StartAddress + Size. Due to alignment restrictions,
>- 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
>- and the end of the range.
>-
>- If StartAddress > 0x0FFFFFFF, then ASSERT().
>- If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
>- If Size > 0 and Buffer is NULL, then ASSERT().
>-
>- @param StartAddress Starting address that encodes the PCI Bus, Device,
>- Function and Register.
>- @param Size Size in bytes of the transfer.
>- @param Buffer Pointer to a buffer containing the data to write.
>-
>- @return Size
>-
>-**/
>-UINTN
>-EFIAPI
>-PciWriteBuffer (
>- IN UINTN StartAddress,
>- IN UINTN Size,
>- IN VOID *Buffer
>- )
>-{
>- UINTN ReturnValue;
>-
>- ASSERT_INVALID_PCI_ADDRESS (StartAddress, 0);
>- ASSERT (((StartAddress & 0xFFF) + Size) <= 0x100);
>-
>- if (Size == 0) {
>- return 0;
>- }
>-
>- ASSERT (Buffer != NULL);
>-
>- //
>- // Save Size for return
>- //
>- ReturnValue = Size;
>-
>- if ((StartAddress & 1) != 0) {
>- //
>- // Write a byte if StartAddress is byte aligned
>- //
>- PciWrite8 (StartAddress, *(UINT8*)Buffer);
>- StartAddress += sizeof (UINT8);
>- Size -= sizeof (UINT8);
>- Buffer = (UINT8*)Buffer + 1;
>- }
>-
>- if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {
>- //
>- // Write a word if StartAddress is word aligned
>- //
>- PciWrite16 (StartAddress, *(UINT16*)Buffer);
>- StartAddress += sizeof (UINT16);
>- Size -= sizeof (UINT16);
>- Buffer = (UINT16*)Buffer + 1;
>- }
>-
>- while (Size >= sizeof (UINT32)) {
>- //
>- // Write as many double words as possible
>- //
>- PciWrite32 (StartAddress, *(UINT32*)Buffer);
>- StartAddress += sizeof (UINT32);
>- Size -= sizeof (UINT32);
>- Buffer = (UINT32*)Buffer + 1;
>- }
>-
>- if (Size >= sizeof (UINT16)) {
>- //
>- // Write the last remaining word if exist
>- //
>- PciWrite16 (StartAddress, *(UINT16*)Buffer);
>- StartAddress += sizeof (UINT16);
>- Size -= sizeof (UINT16);
>- Buffer = (UINT16*)Buffer + 1;
>- }
>-
>- if (Size >= sizeof (UINT8)) {
>- //
>- // Write the last remaining byte if exist
>- //
>- PciWrite8 (StartAddress, *(UINT8*)Buffer);
>- }
>-
>- return ReturnValue;
>-}
>diff --git a/MdePkg/Library/DxePciSegmentLibEsal/DxePciSegmentLibEsal.inf
>b/MdePkg/Library/DxePciSegmentLibEsal/DxePciSegmentLibEsal.inf
>deleted file mode 100644
>index dad1cecf78..0000000000
>--- a/MdePkg/Library/DxePciSegmentLibEsal/DxePciSegmentLibEsal.inf
>+++ /dev/null
>@@ -1,40 +0,0 @@
>-## @file
>-# PCI Segment Library that uses ESAL services to perform PCI Configuration
>cycles.
>-#
>-# Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
>-#
>-# This program and the accompanying materials
>-# are licensed and made available under the terms and conditions of the BSD
>License
>-# which accompanies this distribution. The full text of the license may be
>found at
>-# http://opensource.org/licenses/bsd-license.php.
>-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-#
>-##
>-
>-[Defines]
>- INF_VERSION = 0x00010005
>- BASE_NAME = DxePciSegementLibEsal
>- MODULE_UNI_FILE = DxePciSegementLibEsal.uni
>- FILE_GUID = 6D497A7A-D7DA-467c-B485-B7FB3493C41F
>- MODULE_TYPE = DXE_DRIVER
>- VERSION_STRING = 1.0
>- LIBRARY_CLASS = PciSegmentLib|DXE_DRIVER
>DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER
>UEFI_APPLICATION
>-
>-#
>-# The following information is for reference only and not required by the
>build tools.
>-#
>-# VALID_ARCHITECTURES = IPF
>-#
>-
>-[Sources]
>- PciLib.c
>-
>-[Packages]
>- MdePkg/MdePkg.dec
>-
>-[LibraryClasses]
>- ExtendedSalLib
>- DebugLib
>- BaseLib
>-
>diff --git a/MdePkg/Library/DxePciSegmentLibEsal/PciLib.c
>b/MdePkg/Library/DxePciSegmentLibEsal/PciLib.c
>deleted file mode 100644
>index fe0fb8b624..0000000000
>--- a/MdePkg/Library/DxePciSegmentLibEsal/PciLib.c
>+++ /dev/null
>@@ -1,1416 +0,0 @@
>-/** @file
>- DXE PCI Segment Library instance layered on top of ESAL services.
>-
>- Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
>- This program and the accompanying materials
>- are licensed and made available under the terms and conditions of the BSD
>License
>- which accompanies this distribution. The full text of the license may be
>found at
>- http://opensource.org/licenses/bsd-license.php.
>-
>- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-
>-**/
>-
>-#include <PiDxe.h>
>-
>-#include <Protocol/ExtendedSalServiceClasses.h>
>-
>-#include <Library/PciSegmentLib.h>
>-#include <Library/BaseLib.h>
>-#include <Library/DebugLib.h>
>-#include <Library/ExtendedSalLib.h>
>-
>-/**
>- Assert the validity of a PCI Segment address.
>- A valid PCI Segment address should not contain 1's in bits 31:28
>-
>- @param A The address to validate.
>- @param M Additional bits to assert to be zero.
>-
>-**/
>-#define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A,M) \
>- ASSERT (((A) & (0xf0000000 | (M))) == 0)
>-
>-/**
>- Converts a PCI Library Address to a ESAL PCI Service Address.
>- Based on SAL Spec 3.2, there are two SAL PCI Address:
>-
>- If address type = 0
>- Bits 0..7 - Register address
>- Bits 8..10 - Function number
>- Bits 11..15 - Device number
>- Bits 16..23 - Bus number
>- Bits 24..31 - PCI segment group
>- Bits 32..63 - Reserved (0)
>-
>- If address type = 1
>- Bits 0..7 - Register address
>- Bits 8..11 - Extended Register address
>- Bits 12..14 - Function number
>- Bits 15..19 - Device number
>- Bits 20..27 - Bus number
>- Bits 28..43 - PCI segment group
>- Bits 44..63 - Reserved (0)
>-
>- @param A The PCI Library Address to convert.
>-
>-**/
>-#define
>CONVERT_PCI_SEGMENT_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS0(Address)
>(((Address >> 8) & 0xff000000) | (((Address) >> 4) & 0x00ffff00) | ((Address)
>& 0xff))
>-#define
>CONVERT_PCI_SEGMENT_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS1(Address)
>(((Address >> 4) & 0xffff0000000) | ((Address) & 0xfffffff))
>-
>-/**
>- Check a PCI Library Address is a PCI Compatible Address or not.
>-**/
>-#define IS_PCI_COMPATIBLE_ADDRESS(Address) (((Address) & 0xf00) == 0)
>-
>-/**
>- Internal worker function to read a PCI configuration register.
>-
>- This function wraps EsalPciConfigRead function of Extended SAL PCI
>- Services Class.
>- It reads and returns the PCI configuration register specified by Address,
>- the width of data is specified by Width.
>-
>- @param Address Address that encodes the PCI Bus, Device, Function and
>- Register.
>- @param Width Width of data to read
>-
>- @return The value read from the PCI configuration register.
>-
>-**/
>-UINT32
>-DxePciSegmentLibEsalReadWorker (
>- IN UINT64 Address,
>- IN UINTN Width
>- )
>-{
>- SAL_RETURN_REGS Return;
>-
>- if (IS_PCI_COMPATIBLE_ADDRESS(Address)) {
>- Return = EsalCall (
>- EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_HI,
>- SalPciConfigReadFunctionId,
>- CONVERT_PCI_SEGMENT_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS0
>(Address),
>- Width,
>- EFI_SAL_PCI_COMPATIBLE_ADDRESS,
>- 0,
>- 0,
>- 0,
>- 0
>- );
>- } else {
>- Return = EsalCall (
>- EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_HI,
>- SalPciConfigReadFunctionId,
>- CONVERT_PCI_SEGMENT_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS1
>(Address),
>- Width,
>- EFI_SAL_PCI_EXTENDED_REGISTER_ADDRESS,
>- 0,
>- 0,
>- 0,
>- 0
>- );
>- }
>-
>- return (UINT32) Return.r9;
>-}
>-
>-/**
>- Internal worker function to writes a PCI configuration register.
>-
>- This function wraps EsalPciConfigWrite function of Extended SAL PCI
>- Services Class.
>- It writes the PCI configuration register specified by Address with the
>- value specified by Data. The width of data is specified by Width.
>- Data is returned.
>-
>- @param Address Address that encodes the PCI Bus, Device, Function and
>- Register.
>- @param Width Width of data to write
>- @param Data The value to write.
>-
>- @return The value written to the PCI configuration register.
>-
>-**/
>-UINT32
>-DxePciSegmentLibEsalWriteWorker (
>- IN UINT64 Address,
>- IN UINTN Width,
>- IN UINT32 Data
>- )
>-{
>- if (IS_PCI_COMPATIBLE_ADDRESS(Address)) {
>- EsalCall (
>- EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_HI,
>- SalPciConfigWriteFunctionId,
>- CONVERT_PCI_SEGMENT_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS0
>(Address),
>- Width,
>- Data,
>- EFI_SAL_PCI_COMPATIBLE_ADDRESS,
>- 0,
>- 0,
>- 0
>- );
>- } else {
>- EsalCall (
>- EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_HI,
>- SalPciConfigWriteFunctionId,
>- CONVERT_PCI_SEGMENT_LIB_ADDRESS_TO_PCI_ESAL_ADDRESS1
>(Address),
>- Width,
>- Data,
>- EFI_SAL_PCI_EXTENDED_REGISTER_ADDRESS,
>- 0,
>- 0,
>- 0
>- );
>- }
>-
>- return Data;
>-}
>-
>-/**
>- Reads an 8-bit PCI configuration register.
>-
>- Reads and returns the 8-bit PCI configuration register specified by Address.
>- This function must guarantee that all PCI read and write operations are
>- serialized.
>-
>- If any reserved bits in Address are set, then ASSERT().
>-
>- @param Address Address that encodes the PCI Segment, Bus, Device,
>Function and
>- Register.
>-
>- @return The value read from the PCI configuration register.
>-
>-**/
>-UINT8
>-EFIAPI
>-PciSegmentRead8 (
>- IN UINT64 Address
>- )
>-{
>- ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
>-
>- return (UINT8) DxePciSegmentLibEsalReadWorker (Address, 1);
>-}
>-
>-/**
>- Writes an 8-bit PCI configuration register.
>-
>- Writes the 8-bit PCI configuration register specified by Address with the
>- value specified by Value. Value is returned. This function must guarantee
>- that all PCI read and write operations are serialized.
>-
>- If any reserved bits in Address are set, then ASSERT().
>-
>- @param Address Address that encodes the PCI Segment, Bus, Device,
>Function and
>- Register.
>- @param Data The value to write.
>-
>- @return The value written to the PCI configuration register.
>-
>-**/
>-UINT8
>-EFIAPI
>-PciSegmentWrite8 (
>- IN UINT64 Address,
>- IN UINT8 Data
>- )
>-{
>- ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);
>-
>- return (UINT8) DxePciSegmentLibEsalWriteWorker (Address, 1, Data);
>-}
>-
>-/**
>- Performs a bitwise OR of an 8-bit PCI configuration register with
>- an 8-bit value.
>-
>- Reads the 8-bit PCI configuration register specified by Address, performs a
>- bitwise OR between the read result and the value specified by
>- OrData, and writes the result to the 8-bit PCI configuration register
>- specified by Address. The value written to the PCI configuration register is
>- returned. This function must guarantee that all PCI read and write
>operations
>- are serialized.
>-
>- If any reserved bits in Address are set, then ASSERT().
>-
>- @param Address Address that encodes the PCI Segment, Bus, Device,
>Function and
>- Register.
>- @param OrData The value to OR with the PCI configuration register.
>-
>- @return The value written back to the PCI configuration register.
>-
>-**/
>-UINT8
>-EFIAPI
>-PciSegmentOr8 (
>- IN UINT64 Address,
>- IN UINT8 OrData
>- )
>-{
>- return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) |
>OrData));
>-}
>-
>-/**
>- Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
>- value.
>-
>- Reads the 8-bit PCI configuration register specified by Address, performs a
>- bitwise AND between the read result and the value specified by AndData,
>and
>- writes the result to the 8-bit PCI configuration register specified by
>- Address. The value written to the PCI configuration register is returned.
>- This function must guarantee that all PCI read and write operations are
>- serialized.
>-
>- If any reserved bits in Address are set, then ASSERT().
>-
>- @param Address Address that encodes the PCI Segment, Bus, Device,
>Function and
>- Register.
>- @param AndData The value to AND with the PCI configuration register.
>-
>- @return The value written back to the PCI configuration register.
>-
>-**/
>-UINT8
>-EFIAPI
>-PciSegmentAnd8 (
>- IN UINT64 Address,
>- IN UINT8 AndData
>- )
>-{
>- return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) &
>AndData));
>-}
>-
>-/**
>- Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
>- value, followed a bitwise OR with another 8-bit value.
>-
>- Reads the 8-bit PCI configuration register specified by Address, performs a
>- bitwise AND between the read result and the value specified by AndData,
>- performs a bitwise OR between the result of the AND operation and
>- the value specified by OrData, and writes the result to the 8-bit PCI
>- configuration register specified by Address. The value written to the PCI
>- configuration register is returned. This function must guarantee that all PCI
>- read and write operations are serialized.
>-
>- If any reserved bits in Address are set, then ASSERT().
>-
>- @param Address Address that encodes the PCI Segment, Bus, Device,
>Function and
>- Register.
>- @param AndData The value to AND with the PCI configuration register.
>- @param OrData The value to OR with the result of the AND operation.
>-
>- @return The value written back to the PCI configuration register.
>-
>-**/
>-UINT8
>-EFIAPI
>-PciSegmentAndThenOr8 (
>- IN UINT64 Address,
>- IN UINT8 AndData,
>- IN UINT8 OrData
>- )
>-{
>- return PciSegmentWrite8 (Address, (UINT8) ((PciSegmentRead8 (Address)
>& AndData) | OrData));
>-}
>-
>-/**
>- Reads a bit field of a PCI configuration register.
>-
>- Reads the bit field in an 8-bit PCI configuration register. The bit field is
>- specified by the StartBit and the EndBit. The value of the bit field is
>- returned.
>-
>- If any reserved bits in Address are set, then ASSERT().
>- If StartBit is greater than 7, then ASSERT().
>- If EndBit is greater than 7, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>-
>- @param Address PCI configuration register to read.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..7.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..7.
>-
>- @return The value of the bit field read from the PCI configuration register.
>-
>-**/
>-UINT8
>-EFIAPI
>-PciSegmentBitFieldRead8 (
>- IN UINT64 Address,
>- IN UINTN StartBit,
>- IN UINTN EndBit
>- )
>-{
>- return BitFieldRead8 (PciSegmentRead8 (Address), StartBit, EndBit);
>-}
>-
>-/**
>- Writes a bit field to a PCI configuration register.
>-
>- Writes Value to the bit field of the PCI configuration register. The bit
>- field is specified by the StartBit and the EndBit. All other bits in the
>- destination PCI configuration register are preserved. The new value of the
>- 8-bit register is returned.
>-
>- If any reserved bits in Address are set, then ASSERT().
>- If StartBit is greater than 7, then ASSERT().
>- If EndBit is greater than 7, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>- If Value is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>-
>- @param Address PCI configuration register to write.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..7.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..7.
>- @param Value New value of the bit field.
>-
>- @return The value written back to the PCI configuration register.
>-
>-**/
>-UINT8
>-EFIAPI
>-PciSegmentBitFieldWrite8 (
>- IN UINT64 Address,
>- IN UINTN StartBit,
>- IN UINTN EndBit,
>- IN UINT8 Value
>- )
>-{
>- return PciSegmentWrite8 (
>- Address,
>- BitFieldWrite8 (PciSegmentRead8 (Address), StartBit, EndBit, Value)
>- );
>-}
>-
>-/**
>- Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
>- writes the result back to the bit field in the 8-bit port.
>-
>- Reads the 8-bit PCI configuration register specified by Address, performs a
>- bitwise OR between the read result and the value specified by
>- OrData, and writes the result to the 8-bit PCI configuration register
>- specified by Address. The value written to the PCI configuration register is
>- returned. This function must guarantee that all PCI read and write
>operations
>- are serialized. Extra left bits in OrData are stripped.
>-
>- If any reserved bits in Address are set, then ASSERT().
>- If StartBit is greater than 7, then ASSERT().
>- If EndBit is greater than 7, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>- If OrData is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>-
>- @param Address PCI configuration register to write.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..7.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..7.
>- @param OrData The value to OR with the PCI configuration register.
>-
>- @return The value written back to the PCI configuration register.
>-
>-**/
>-UINT8
>-EFIAPI
>-PciSegmentBitFieldOr8 (
>- IN UINT64 Address,
>- IN UINTN StartBit,
>- IN UINTN EndBit,
>- IN UINT8 OrData
>- )
>-{
>- return PciSegmentWrite8 (
>- Address,
>- BitFieldOr8 (PciSegmentRead8 (Address), StartBit, EndBit, OrData)
>- );
>-}
>-
>-/**
>- Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
>- AND, and writes the result back to the bit field in the 8-bit register.
>-
>- Reads the 8-bit PCI configuration register specified by Address, performs a
>- bitwise AND between the read result and the value specified by AndData,
>and
>- writes the result to the 8-bit PCI configuration register specified by
>- Address. The value written to the PCI configuration register is returned.
>- This function must guarantee that all PCI read and write operations are
>- serialized. Extra left bits in AndData are stripped.
>-
>- If any reserved bits in Address are set, then ASSERT().
>- If StartBit is greater than 7, then ASSERT().
>- If EndBit is greater than 7, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>- If AndData is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>-
>- @param Address PCI configuration register to write.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..7.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..7.
>- @param AndData The value to AND with the PCI configuration register.
>-
>- @return The value written back to the PCI configuration register.
>-
>-**/
>-UINT8
>-EFIAPI
>-PciSegmentBitFieldAnd8 (
>- IN UINT64 Address,
>- IN UINTN StartBit,
>- IN UINTN EndBit,
>- IN UINT8 AndData
>- )
>-{
>- return PciSegmentWrite8 (
>- Address,
>- BitFieldAnd8 (PciSegmentRead8 (Address), StartBit, EndBit, AndData)
>- );
>-}
>-
>-/**
>- Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
>- bitwise OR, and writes the result back to the bit field in the
>- 8-bit port.
>-
>- Reads the 8-bit PCI configuration register specified by Address, performs a
>- bitwise AND followed by a bitwise OR between the read result and
>- the value specified by AndData, and writes the result to the 8-bit PCI
>- configuration register specified by Address. The value written to the PCI
>- configuration register is returned. This function must guarantee that all PCI
>- read and write operations are serialized. Extra left bits in both AndData and
>- OrData are stripped.
>-
>- If any reserved bits in Address are set, then ASSERT().
>- If StartBit is greater than 7, then ASSERT().
>- If EndBit is greater than 7, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>- If AndData is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>- If OrData is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>-
>- @param Address PCI configuration register to write.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..7.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..7.
>- @param AndData The value to AND with the PCI configuration register.
>- @param OrData The value to OR with the result of the AND operation.
>-
>- @return The value written back to the PCI configuration register.
>-
>-**/
>-UINT8
>-EFIAPI
>-PciSegmentBitFieldAndThenOr8 (
>- IN UINT64 Address,
>- IN UINTN StartBit,
>- IN UINTN EndBit,
>- IN UINT8 AndData,
>- IN UINT8 OrData
>- )
>-{
>- return PciSegmentWrite8 (
>- Address,
>- BitFieldAndThenOr8 (PciSegmentRead8 (Address), StartBit, EndBit,
>AndData, OrData)
>- );
>-}
>-
>-/**
>- Reads a 16-bit PCI configuration register.
>-
>- Reads and returns the 16-bit PCI configuration register specified by Address.
>- This function must guarantee that all PCI read and write operations are
>- serialized.
>-
>- If any reserved bits in Address are set, then ASSERT().
>-
>- @param Address Address that encodes the PCI Segment, Bus, Device,
>Function and
>- Register.
>-
>- @return The value read from the PCI configuration register.
>-
>-**/
>-UINT16
>-EFIAPI
>-PciSegmentRead16 (
>- IN UINT64 Address
>- )
>-{
>- ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);
>-
>- return (UINT16) DxePciSegmentLibEsalReadWorker (Address, 2);
>-}
>-
>-/**
>- Writes a 16-bit PCI configuration register.
>-
>- Writes the 16-bit PCI configuration register specified by Address with the
>- value specified by Value. Value is returned. This function must guarantee
>- that all PCI read and write operations are serialized.
>-
>- If any reserved bits in Address are set, then ASSERT().
>-
>- @param Address Address that encodes the PCI Segment, Bus, Device,
>Function and
>- Register.
>- @param Data The value to write.
>-
>- @return The value written to the PCI configuration register.
>-
>-**/
>-UINT16
>-EFIAPI
>-PciSegmentWrite16 (
>- IN UINT64 Address,
>- IN UINT16 Data
>- )
>-{
>- ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);
>-
>- return (UINT16) DxePciSegmentLibEsalWriteWorker (Address, 2, Data);
>-}
>-
>-/**
>- Performs a bitwise OR of a 16-bit PCI configuration register with
>- a 16-bit value.
>-
>- Reads the 16-bit PCI configuration register specified by Address, performs a
>- bitwise OR between the read result and the value specified by
>- OrData, and writes the result to the 16-bit PCI configuration register
>- specified by Address. The value written to the PCI configuration register is
>- returned. This function must guarantee that all PCI read and write
>operations
>- are serialized.
>-
>- If any reserved bits in Address are set, then ASSERT().
>-
>- @param Address Address that encodes the PCI Segment, Bus, Device,
>Function and
>- Register.
>- @param OrData The value to OR with the PCI configuration register.
>-
>- @return The value written back to the PCI configuration register.
>-
>-**/
>-UINT16
>-EFIAPI
>-PciSegmentOr16 (
>- IN UINT64 Address,
>- IN UINT16 OrData
>- )
>-{
>- return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address)
>| OrData));
>-}
>-
>-/**
>- Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
>- value.
>-
>- Reads the 16-bit PCI configuration register specified by Address, performs a
>- bitwise AND between the read result and the value specified by AndData,
>and
>- writes the result to the 16-bit PCI configuration register specified by
>- Address. The value written to the PCI configuration register is returned.
>- This function must guarantee that all PCI read and write operations are
>- serialized.
>-
>- If any reserved bits in Address are set, then ASSERT().
>-
>- @param Address Address that encodes the PCI Segment, Bus, Device,
>Function and
>- Register.
>- @param AndData The value to AND with the PCI configuration register.
>-
>- @return The value written back to the PCI configuration register.
>-
>-**/
>-UINT16
>-EFIAPI
>-PciSegmentAnd16 (
>- IN UINT64 Address,
>- IN UINT16 AndData
>- )
>-{
>- return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address)
>& AndData));
>-}
>-
>-/**
>- Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
>- value, followed a bitwise OR with another 16-bit value.
>-
>- Reads the 16-bit PCI configuration register specified by Address, performs a
>- bitwise AND between the read result and the value specified by AndData,
>- performs a bitwise OR between the result of the AND operation and
>- the value specified by OrData, and writes the result to the 16-bit PCI
>- configuration register specified by Address. The value written to the PCI
>- configuration register is returned. This function must guarantee that all PCI
>- read and write operations are serialized.
>-
>- If any reserved bits in Address are set, then ASSERT().
>-
>- @param Address Address that encodes the PCI Segment, Bus, Device,
>Function and
>- Register.
>- @param AndData The value to AND with the PCI configuration register.
>- @param OrData The value to OR with the result of the AND operation.
>-
>- @return The value written back to the PCI configuration register.
>-
>-**/
>-UINT16
>-EFIAPI
>-PciSegmentAndThenOr16 (
>- IN UINT64 Address,
>- IN UINT16 AndData,
>- IN UINT16 OrData
>- )
>-{
>- return PciSegmentWrite16 (Address, (UINT16) ((PciSegmentRead16
>(Address) & AndData) | OrData));
>-}
>-
>-/**
>- Reads a bit field of a PCI configuration register.
>-
>- Reads the bit field in a 16-bit PCI configuration register. The bit field is
>- specified by the StartBit and the EndBit. The value of the bit field is
>- returned.
>-
>- If any reserved bits in Address are set, then ASSERT().
>- If StartBit is greater than 15, then ASSERT().
>- If EndBit is greater than 15, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>-
>- @param Address PCI configuration register to read.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..15.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..15.
>-
>- @return The value of the bit field read from the PCI configuration register.
>-
>-**/
>-UINT16
>-EFIAPI
>-PciSegmentBitFieldRead16 (
>- IN UINT64 Address,
>- IN UINTN StartBit,
>- IN UINTN EndBit
>- )
>-{
>- return BitFieldRead16 (PciSegmentRead16 (Address), StartBit, EndBit);
>-}
>-
>-/**
>- Writes a bit field to a PCI configuration register.
>-
>- Writes Value to the bit field of the PCI configuration register. The bit
>- field is specified by the StartBit and the EndBit. All other bits in the
>- destination PCI configuration register are preserved. The new value of the
>- 16-bit register is returned.
>-
>- If any reserved bits in Address are set, then ASSERT().
>- If StartBit is greater than 15, then ASSERT().
>- If EndBit is greater than 15, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>- If Value is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>-
>- @param Address PCI configuration register to write.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..15.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..15.
>- @param Value New value of the bit field.
>-
>- @return The value written back to the PCI configuration register.
>-
>-**/
>-UINT16
>-EFIAPI
>-PciSegmentBitFieldWrite16 (
>- IN UINT64 Address,
>- IN UINTN StartBit,
>- IN UINTN EndBit,
>- IN UINT16 Value
>- )
>-{
>- return PciSegmentWrite16 (
>- Address,
>- BitFieldWrite16 (PciSegmentRead16 (Address), StartBit, EndBit, Value)
>- );
>-}
>-
>-/**
>- Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
>- writes the result back to the bit field in the 16-bit port.
>-
>- Reads the 16-bit PCI configuration register specified by Address, performs a
>- bitwise OR between the read result and the value specified by
>- OrData, and writes the result to the 16-bit PCI configuration register
>- specified by Address. The value written to the PCI configuration register is
>- returned. This function must guarantee that all PCI read and write
>operations
>- are serialized. Extra left bits in OrData are stripped.
>-
>- If any reserved bits in Address are set, then ASSERT().
>- If StartBit is greater than 15, then ASSERT().
>- If EndBit is greater than 15, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>- If OrData is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>-
>- @param Address PCI configuration register to write.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..15.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..15.
>- @param OrData The value to OR with the PCI configuration register.
>-
>- @return The value written back to the PCI configuration register.
>-
>-**/
>-UINT16
>-EFIAPI
>-PciSegmentBitFieldOr16 (
>- IN UINT64 Address,
>- IN UINTN StartBit,
>- IN UINTN EndBit,
>- IN UINT16 OrData
>- )
>-{
>- return PciSegmentWrite16 (
>- Address,
>- BitFieldOr16 (PciSegmentRead16 (Address), StartBit, EndBit, OrData)
>- );
>-}
>-
>-/**
>- Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
>- AND, and writes the result back to the bit field in the 16-bit register.
>-
>- Reads the 16-bit PCI configuration register specified by Address, performs a
>- bitwise AND between the read result and the value specified by AndData,
>and
>- writes the result to the 16-bit PCI configuration register specified by
>- Address. The value written to the PCI configuration register is returned.
>- This function must guarantee that all PCI read and write operations are
>- serialized. Extra left bits in AndData are stripped.
>-
>- If any reserved bits in Address are set, then ASSERT().
>- If StartBit is greater than 15, then ASSERT().
>- If EndBit is greater than 15, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>- If AndData is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>-
>- @param Address PCI configuration register to write.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..15.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..15.
>- @param AndData The value to AND with the PCI configuration register.
>-
>- @return The value written back to the PCI configuration register.
>-
>-**/
>-UINT16
>-EFIAPI
>-PciSegmentBitFieldAnd16 (
>- IN UINT64 Address,
>- IN UINTN StartBit,
>- IN UINTN EndBit,
>- IN UINT16 AndData
>- )
>-{
>- return PciSegmentWrite16 (
>- Address,
>- BitFieldAnd16 (PciSegmentRead16 (Address), StartBit, EndBit, AndData)
>- );
>-}
>-
>-/**
>- Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
>- bitwise OR, and writes the result back to the bit field in the
>- 16-bit port.
>-
>- Reads the 16-bit PCI configuration register specified by Address, performs a
>- bitwise AND followed by a bitwise OR between the read result and
>- the value specified by AndData, and writes the result to the 16-bit PCI
>- configuration register specified by Address. The value written to the PCI
>- configuration register is returned. This function must guarantee that all PCI
>- read and write operations are serialized. Extra left bits in both AndData and
>- OrData are stripped.
>-
>- If any reserved bits in Address are set, then ASSERT().
>- If StartBit is greater than 15, then ASSERT().
>- If EndBit is greater than 15, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>- If AndData is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>- If OrData is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>-
>- @param Address PCI configuration register to write.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..15.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..15.
>- @param AndData The value to AND with the PCI configuration register.
>- @param OrData The value to OR with the result of the AND operation.
>-
>- @return The value written back to the PCI configuration register.
>-
>-**/
>-UINT16
>-EFIAPI
>-PciSegmentBitFieldAndThenOr16 (
>- IN UINT64 Address,
>- IN UINTN StartBit,
>- IN UINTN EndBit,
>- IN UINT16 AndData,
>- IN UINT16 OrData
>- )
>-{
>- return PciSegmentWrite16 (
>- Address,
>- BitFieldAndThenOr16 (PciSegmentRead16 (Address), StartBit, EndBit,
>AndData, OrData)
>- );
>-}
>-
>-/**
>- Reads a 32-bit PCI configuration register.
>-
>- Reads and returns the 32-bit PCI configuration register specified by Address.
>- This function must guarantee that all PCI read and write operations are
>- serialized.
>-
>- If any reserved bits in Address are set, then ASSERT().
>-
>- @param Address Address that encodes the PCI Segment, Bus, Device,
>Function and
>- Register.
>-
>- @return The value read from the PCI configuration register.
>-
>-**/
>-UINT32
>-EFIAPI
>-PciSegmentRead32 (
>- IN UINT64 Address
>- )
>-{
>- ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);
>-
>- return DxePciSegmentLibEsalReadWorker (Address, 4);
>-}
>-
>-/**
>- Writes a 32-bit PCI configuration register.
>-
>- Writes the 32-bit PCI configuration register specified by Address with the
>- value specified by Value. Value is returned. This function must guarantee
>- that all PCI read and write operations are serialized.
>-
>- If any reserved bits in Address are set, then ASSERT().
>-
>- @param Address Address that encodes the PCI Segment, Bus, Device,
>Function and
>- Register.
>- @param Data The value to write.
>-
>- @return The value written to the PCI configuration register.
>-
>-**/
>-UINT32
>-EFIAPI
>-PciSegmentWrite32 (
>- IN UINT64 Address,
>- IN UINT32 Data
>- )
>-{
>- ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);
>-
>- return DxePciSegmentLibEsalWriteWorker (Address, 4, Data);
>-}
>-
>-/**
>- Performs a bitwise OR of a 32-bit PCI configuration register with
>- a 32-bit value.
>-
>- Reads the 32-bit PCI configuration register specified by Address, performs a
>- bitwise OR between the read result and the value specified by
>- OrData, and writes the result to the 32-bit PCI configuration register
>- specified by Address. The value written to the PCI configuration register is
>- returned. This function must guarantee that all PCI read and write
>operations
>- are serialized.
>-
>- If any reserved bits in Address are set, then ASSERT().
>-
>- @param Address Address that encodes the PCI Segment, Bus, Device,
>Function and
>- Register.
>- @param OrData The value to OR with the PCI configuration register.
>-
>- @return The value written back to the PCI configuration register.
>-
>-**/
>-UINT32
>-EFIAPI
>-PciSegmentOr32 (
>- IN UINT64 Address,
>- IN UINT32 OrData
>- )
>-{
>- return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) |
>OrData);
>-}
>-
>-/**
>- Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
>- value.
>-
>- Reads the 32-bit PCI configuration register specified by Address, performs a
>- bitwise AND between the read result and the value specified by AndData,
>and
>- writes the result to the 32-bit PCI configuration register specified by
>- Address. The value written to the PCI configuration register is returned.
>- This function must guarantee that all PCI read and write operations are
>- serialized.
>-
>- If any reserved bits in Address are set, then ASSERT().
>-
>- @param Address Address that encodes the PCI Segment, Bus, Device,
>Function and
>- Register.
>- @param AndData The value to AND with the PCI configuration register.
>-
>- @return The value written back to the PCI configuration register.
>-
>-**/
>-UINT32
>-EFIAPI
>-PciSegmentAnd32 (
>- IN UINT64 Address,
>- IN UINT32 AndData
>- )
>-{
>- return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) &
>AndData);
>-}
>-
>-/**
>- Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
>- value, followed a bitwise OR with another 32-bit value.
>-
>- Reads the 32-bit PCI configuration register specified by Address, performs a
>- bitwise AND between the read result and the value specified by AndData,
>- performs a bitwise OR between the result of the AND operation and
>- the value specified by OrData, and writes the result to the 32-bit PCI
>- configuration register specified by Address. The value written to the PCI
>- configuration register is returned. This function must guarantee that all PCI
>- read and write operations are serialized.
>-
>- If any reserved bits in Address are set, then ASSERT().
>-
>- @param Address Address that encodes the PCI Segment, Bus, Device,
>Function and
>- Register.
>- @param AndData The value to AND with the PCI configuration register.
>- @param OrData The value to OR with the result of the AND operation.
>-
>- @return The value written back to the PCI configuration register.
>-
>-**/
>-UINT32
>-EFIAPI
>-PciSegmentAndThenOr32 (
>- IN UINT64 Address,
>- IN UINT32 AndData,
>- IN UINT32 OrData
>- )
>-{
>- return PciSegmentWrite32 (Address, (PciSegmentRead32 (Address) &
>AndData) | OrData);
>-}
>-
>-/**
>- Reads a bit field of a PCI configuration register.
>-
>- Reads the bit field in a 32-bit PCI configuration register. The bit field is
>- specified by the StartBit and the EndBit. The value of the bit field is
>- returned.
>-
>- If any reserved bits in Address are set, then ASSERT().
>- If StartBit is greater than 31, then ASSERT().
>- If EndBit is greater than 31, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>-
>- @param Address PCI configuration register to read.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..31.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..31.
>-
>- @return The value of the bit field read from the PCI configuration register.
>-
>-**/
>-UINT32
>-EFIAPI
>-PciSegmentBitFieldRead32 (
>- IN UINT64 Address,
>- IN UINTN StartBit,
>- IN UINTN EndBit
>- )
>-{
>- return BitFieldRead32 (PciSegmentRead32 (Address), StartBit, EndBit);
>-}
>-
>-/**
>- Writes a bit field to a PCI configuration register.
>-
>- Writes Value to the bit field of the PCI configuration register. The bit
>- field is specified by the StartBit and the EndBit. All other bits in the
>- destination PCI configuration register are preserved. The new value of the
>- 32-bit register is returned.
>-
>- If any reserved bits in Address are set, then ASSERT().
>- If StartBit is greater than 31, then ASSERT().
>- If EndBit is greater than 31, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>- If Value is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>-
>- @param Address PCI configuration register to write.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..31.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..31.
>- @param Value New value of the bit field.
>-
>- @return The value written back to the PCI configuration register.
>-
>-**/
>-UINT32
>-EFIAPI
>-PciSegmentBitFieldWrite32 (
>- IN UINT64 Address,
>- IN UINTN StartBit,
>- IN UINTN EndBit,
>- IN UINT32 Value
>- )
>-{
>- return PciSegmentWrite32 (
>- Address,
>- BitFieldWrite32 (PciSegmentRead32 (Address), StartBit, EndBit, Value)
>- );
>-}
>-
>-/**
>- Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
>- writes the result back to the bit field in the 32-bit port.
>-
>- Reads the 32-bit PCI configuration register specified by Address, performs a
>- bitwise OR between the read result and the value specified by
>- OrData, and writes the result to the 32-bit PCI configuration register
>- specified by Address. The value written to the PCI configuration register is
>- returned. This function must guarantee that all PCI read and write
>operations
>- are serialized. Extra left bits in OrData are stripped.
>-
>- If any reserved bits in Address are set, then ASSERT().
>- If StartBit is greater than 31, then ASSERT().
>- If EndBit is greater than 31, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>- If OrData is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>-
>- @param Address PCI configuration register to write.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..31.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..31.
>- @param OrData The value to OR with the PCI configuration register.
>-
>- @return The value written back to the PCI configuration register.
>-
>-**/
>-UINT32
>-EFIAPI
>-PciSegmentBitFieldOr32 (
>- IN UINT64 Address,
>- IN UINTN StartBit,
>- IN UINTN EndBit,
>- IN UINT32 OrData
>- )
>-{
>- return PciSegmentWrite32 (
>- Address,
>- BitFieldOr32 (PciSegmentRead32 (Address), StartBit, EndBit, OrData)
>- );
>-}
>-
>-/**
>- Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
>- AND, and writes the result back to the bit field in the 32-bit register.
>-
>- Reads the 32-bit PCI configuration register specified by Address, performs a
>- bitwise AND between the read result and the value specified by AndData,
>and
>- writes the result to the 32-bit PCI configuration register specified by
>- Address. The value written to the PCI configuration register is returned.
>- This function must guarantee that all PCI read and write operations are
>- serialized. Extra left bits in AndData are stripped.
>-
>- If any reserved bits in Address are set, then ASSERT().
>- If StartBit is greater than 31, then ASSERT().
>- If EndBit is greater than 31, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>- If AndData is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>-
>- @param Address PCI configuration register to write.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..31.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..31.
>- @param AndData The value to AND with the PCI configuration register.
>-
>- @return The value written back to the PCI configuration register.
>-
>-**/
>-UINT32
>-EFIAPI
>-PciSegmentBitFieldAnd32 (
>- IN UINT64 Address,
>- IN UINTN StartBit,
>- IN UINTN EndBit,
>- IN UINT32 AndData
>- )
>-{
>- return PciSegmentWrite32 (
>- Address,
>- BitFieldAnd32 (PciSegmentRead32 (Address), StartBit, EndBit, AndData)
>- );
>-}
>-
>-/**
>- Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
>- bitwise OR, and writes the result back to the bit field in the
>- 32-bit port.
>-
>- Reads the 32-bit PCI configuration register specified by Address, performs a
>- bitwise AND followed by a bitwise OR between the read result and
>- the value specified by AndData, and writes the result to the 32-bit PCI
>- configuration register specified by Address. The value written to the PCI
>- configuration register is returned. This function must guarantee that all PCI
>- read and write operations are serialized. Extra left bits in both AndData and
>- OrData are stripped.
>-
>- If any reserved bits in Address are set, then ASSERT().
>- If StartBit is greater than 31, then ASSERT().
>- If EndBit is greater than 31, then ASSERT().
>- If EndBit is less than StartBit, then ASSERT().
>- If AndData is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>- If OrData is larger than the bitmask value range specified by StartBit and
>EndBit, then ASSERT().
>-
>- @param Address PCI configuration register to write.
>- @param StartBit The ordinal of the least significant bit in the bit field.
>- Range 0..31.
>- @param EndBit The ordinal of the most significant bit in the bit field.
>- Range 0..31.
>- @param AndData The value to AND with the PCI configuration register.
>- @param OrData The value to OR with the result of the AND operation.
>-
>- @return The value written back to the PCI configuration register.
>-
>-**/
>-UINT32
>-EFIAPI
>-PciSegmentBitFieldAndThenOr32 (
>- IN UINT64 Address,
>- IN UINTN StartBit,
>- IN UINTN EndBit,
>- IN UINT32 AndData,
>- IN UINT32 OrData
>- )
>-{
>- return PciSegmentWrite32 (
>- Address,
>- BitFieldAndThenOr32 (PciSegmentRead32 (Address), StartBit, EndBit,
>AndData, OrData)
>- );
>-}
>-
>-/**
>- Reads a range of PCI configuration registers into a caller supplied buffer.
>-
>- Reads the range of PCI configuration registers specified by StartAddress and
>- Size into the buffer specified by Buffer. This function only allows the PCI
>- configuration registers from a single PCI function to be read. Size is
>- returned. When possible 32-bit PCI configuration read cycles are used to
>read
>- from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
>- and 16-bit PCI configuration read cycles may be used at the beginning and
>the
>- end of the range.
>-
>- If StartAddress > 0x0FFFFFFF, then ASSERT().
>- If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
>- If Size > 0 and Buffer is NULL, then ASSERT().
>-
>- @param StartAddress Starting Address that encodes the PCI Segment, Bus,
>Device,
>- Function and Register.
>- @param Size Size in bytes of the transfer.
>- @param Buffer Pointer to a buffer receiving the data read.
>-
>- @return Size
>-
>-**/
>-UINTN
>-EFIAPI
>-PciSegmentReadBuffer (
>- IN UINT64 StartAddress,
>- IN UINTN Size,
>- OUT VOID *Buffer
>- )
>-{
>- UINTN ReturnValue;
>-
>- ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);
>- ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
>-
>- if (Size == 0) {
>- return Size;
>- }
>-
>- ASSERT (Buffer != NULL);
>-
>- //
>- // Save Size for return
>- //
>- ReturnValue = Size;
>-
>- if ((StartAddress & 1) != 0) {
>- //
>- // Read a byte if StartAddress is byte aligned
>- //
>- *(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress);
>- StartAddress += sizeof (UINT8);
>- Size -= sizeof (UINT8);
>- Buffer = (UINT8*)Buffer + 1;
>- }
>-
>- if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {
>- //
>- // Read a word if StartAddress is word aligned
>- //
>- *(volatile UINT16 *)Buffer = PciSegmentRead16 (StartAddress);
>- StartAddress += sizeof (UINT16);
>- Size -= sizeof (UINT16);
>- Buffer = (UINT16*)Buffer + 1;
>- }
>-
>- while (Size >= sizeof (UINT32)) {
>- //
>- // Read as many double words as possible
>- //
>- *(volatile UINT32 *)Buffer = PciSegmentRead32 (StartAddress);
>- StartAddress += sizeof (UINT32);
>- Size -= sizeof (UINT32);
>- Buffer = (UINT32*)Buffer + 1;
>- }
>-
>- if (Size >= sizeof (UINT16)) {
>- //
>- // Read the last remaining word if exist
>- //
>- *(volatile UINT16 *)Buffer = PciSegmentRead16 (StartAddress);
>- StartAddress += sizeof (UINT16);
>- Size -= sizeof (UINT16);
>- Buffer = (UINT16*)Buffer + 1;
>- }
>-
>- if (Size >= sizeof (UINT8)) {
>- //
>- // Read the last remaining byte if exist
>- //
>- *(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress);
>- }
>-
>- return ReturnValue;
>-}
>-
>-/**
>- Copies the data in a caller supplied buffer to a specified range of PCI
>- configuration space.
>-
>- Writes the range of PCI configuration registers specified by StartAddress and
>- Size from the buffer specified by Buffer. This function only allows the PCI
>- configuration registers from a single PCI function to be written. Size is
>- returned. When possible 32-bit PCI configuration write cycles are used to
>- write from StartAdress to StartAddress + Size. Due to alignment restrictions,
>- 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
>- and the end of the range.
>-
>- If StartAddress > 0x0FFFFFFF, then ASSERT().
>- If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
>- If Size > 0 and Buffer is NULL, then ASSERT().
>-
>- @param StartAddress Starting Address that encodes the PCI Segment, Bus,
>Device,
>- Function and Register.
>- @param Size Size in bytes of the transfer.
>- @param Buffer Pointer to a buffer containing the data to write.
>-
>- @return Size
>-
>-**/
>-UINTN
>-EFIAPI
>-PciSegmentWriteBuffer (
>- IN UINT64 StartAddress,
>- IN UINTN Size,
>- IN VOID *Buffer
>- )
>-{
>- UINTN ReturnValue;
>-
>- ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);
>- ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
>-
>- if (Size == 0) {
>- return 0;
>- }
>-
>- ASSERT (Buffer != NULL);
>-
>- //
>- // Save Size for return
>- //
>- ReturnValue = Size;
>-
>- if ((StartAddress & 1) != 0) {
>- //
>- // Write a byte if StartAddress is byte aligned
>- //
>- PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer);
>- StartAddress += sizeof (UINT8);
>- Size -= sizeof (UINT8);
>- Buffer = (UINT8*)Buffer + 1;
>- }
>-
>- if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {
>- //
>- // Write a word if StartAddress is word aligned
>- //
>- PciSegmentWrite16 (StartAddress, *(UINT16*)Buffer);
>- StartAddress += sizeof (UINT16);
>- Size -= sizeof (UINT16);
>- Buffer = (UINT16*)Buffer + 1;
>- }
>-
>- while (Size >= sizeof (UINT32)) {
>- //
>- // Write as many double words as possible
>- //
>- PciSegmentWrite32 (StartAddress, *(UINT32*)Buffer);
>- StartAddress += sizeof (UINT32);
>- Size -= sizeof (UINT32);
>- Buffer = (UINT32*)Buffer + 1;
>- }
>-
>- if (Size >= sizeof (UINT16)) {
>- //
>- // Write the last remaining word if exist
>- //
>- PciSegmentWrite16 (StartAddress, *(UINT16*)Buffer);
>- StartAddress += sizeof (UINT16);
>- Size -= sizeof (UINT16);
>- Buffer = (UINT16*)Buffer + 1;
>- }
>-
>- if (Size >= sizeof (UINT8)) {
>- //
>- // Write the last remaining byte if exist
>- //
>- PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer);
>- }
>-
>- return ReturnValue;
>-}
>diff --git
>a/MdePkg/Library/DxeRuntimeDebugLibSerialPort/DxeRuntimeDebugLibSeri
>alPort.inf
>b/MdePkg/Library/DxeRuntimeDebugLibSerialPort/DxeRuntimeDebugLibSeri
>alPort.inf
>index 8133580969..5050a8aaca 100644
>---
>a/MdePkg/Library/DxeRuntimeDebugLibSerialPort/DxeRuntimeDebugLibSeri
>alPort.inf
>+++
>b/MdePkg/Library/DxeRuntimeDebugLibSerialPort/DxeRuntimeDebugLibSeri
>alPort.inf
>@@ -29,7 +29,7 @@
> DESTRUCTOR = DxeRuntimeDebugLibSerialPortDestructor
>
> #
>-# VALID_ARCHITECTURES = AARCH64 ARM IA32 X64 IPF EBC
>+# VALID_ARCHITECTURES = AARCH64 ARM IA32 X64 EBC
> #
>
> [Sources]
>diff --git
>a/MdePkg/Library/DxeRuntimeExtendedSalLib/DxeRuntimeExtendedSalLib.in
>f
>b/MdePkg/Library/DxeRuntimeExtendedSalLib/DxeRuntimeExtendedSalLib.i
>nf
>deleted file mode 100644
>index 4bc09f9308..0000000000
>---
>a/MdePkg/Library/DxeRuntimeExtendedSalLib/DxeRuntimeExtendedSalLib.in
>f
>+++ /dev/null
>@@ -1,52 +0,0 @@
>-## @file
>-# This library implements the Extended SAL Library Class for use in boot
>services and runtime.
>-#
>-# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
>-#
>-# This program and the accompanying materials
>-# are licensed and made available under the terms and conditions of the BSD
>License
>-# which accompanies this distribution. The full text of the license may be
>found at
>-# http://opensource.org/licenses/bsd-license.php.
>-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-#
>-##
>-
>-[Defines]
>- INF_VERSION = 0x00010005
>- BASE_NAME = DxeRuntimeExtendedSalLib
>- MODULE_UNI_FILE = DxeRuntimeExtendedSalLib.uni
>- FILE_GUID = AE66715B-75F5-4423-8FAD-A4AFB3C53ACF
>- MODULE_TYPE = DXE_RUNTIME_DRIVER
>- VERSION_STRING = 1.0
>- LIBRARY_CLASS = ExtendedSalLib|DXE_RUNTIME_DRIVER
>DXE_SAL_DRIVER
>- CONSTRUCTOR = DxeRuntimeExtendedSalLibConstruct
>- DESTRUCTOR = DxeRuntimeExtendedSalLibDeconstruct
>-
>-#
>-# The following information is for reference only and not required by the
>build tools.
>-#
>-# VALID_ARCHITECTURES = IPF
>-#
>-
>-[Sources.IPF]
>- ExtendedSalLib.c
>- Ipf/AsmExtendedSalLib.s
>-
>-[Packages]
>- MdePkg/MdePkg.dec
>-
>-[LibraryClasses]
>- UefiBootServicesTableLib
>- UefiRuntimeServicesTableLib
>- DebugLib
>-
>-[Protocols]
>- gEfiExtendedSalBootServiceProtocolGuid ## CONSUMES
>-
>-[Guids]
>- gEfiEventVirtualAddressChangeGuid ## CONSUMES ## Event
>-
>-[Depex]
>- gEfiExtendedSalBootServiceProtocolGuid
>-
>diff --git a/MdePkg/Library/DxeRuntimeExtendedSalLib/ExtendedSalLib.c
>b/MdePkg/Library/DxeRuntimeExtendedSalLib/ExtendedSalLib.c
>deleted file mode 100644
>index f9e974b373..0000000000
>--- a/MdePkg/Library/DxeRuntimeExtendedSalLib/ExtendedSalLib.c
>+++ /dev/null
>@@ -1,1124 +0,0 @@
>-/** @file
>- This library implements the Extended SAL Library Class for use in boot
>services and runtime.
>-
>- Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
>- This program and the accompanying materials
>- are licensed and made available under the terms and conditions of the BSD
>License
>- which accompanies this distribution. The full text of the license may be
>found at
>- http://opensource.org/licenses/bsd-license.php.
>-
>- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-
>-**/
>-
>-#include <PiDxe.h>
>-
>-#include <Protocol/ExtendedSalBootService.h>
>-#include <Protocol/ExtendedSalServiceClasses.h>
>-#include <Guid/EventGroup.h>
>-
>-#include <Library/ExtendedSalLib.h>
>-#include <Library/UefiBootServicesTableLib.h>
>-#include <Library/UefiRuntimeServicesTableLib.h>
>-#include <Library/UefiRuntimeLib.h>
>-#include <Library/DebugLib.h>
>-
>-/**
>- Stores the virtual plabel of ESAL entrypoint.
>-
>- This assembly function stores the virtual plabel of ESAL entrypoint
>- where GetEsalEntryPoint() can easily retrieve.
>-
>- @param EntryPoint Virtual address of ESAL entrypoint
>- @param Gp Virtual GP of ESAL entrypoint
>-
>- @return r8 = EFI_SAL_SUCCESS
>-
>-**/
>-SAL_RETURN_REGS
>-EFIAPI
>-SetEsalVirtualEntryPoint (
>- IN UINT64 EntryPoint,
>- IN UINT64 Gp
>- );
>-
>-/**
>- Stores the physical plabel of ESAL entrypoint.
>-
>- This assembly function stores the physical plabel of ESAL entrypoint
>- where GetEsalEntryPoint() can easily retrieve.
>-
>- @param EntryPoint Physical address of ESAL entrypoint
>- @param Gp Physical GP of ESAL entrypoint
>-
>- @return r8 = EFI_SAL_SUCCESS
>-
>-**/
>-SAL_RETURN_REGS
>-EFIAPI
>-SetEsalPhysicalEntryPoint (
>- IN UINT64 EntryPoint,
>- IN UINT64 Gp
>- );
>-
>-/**
>- Retrieves plabel of ESAL entrypoint.
>-
>- This function retrives plabel of ESAL entrypoint stored by
>- SetEsalPhysicalEntryPoint().
>-
>- @return r8 = EFI_SAL_SUCCESS
>- r9 = Physical Plabel
>- r10 = Virtual Plabel
>- r11 = PSR
>-
>-**/
>-SAL_RETURN_REGS
>-EFIAPI
>-GetEsalEntryPoint (
>- VOID
>- );
>-
>-EXTENDED_SAL_BOOT_SERVICE_PROTOCOL *mEsalBootService = NULL;
>-EFI_PLABEL mPlabel;
>-EFI_EVENT mEfiVirtualNotifyEvent;
>-
>-/**
>- Notification function of EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE to set
>virtual plabel of
>- ESAL entrypoint.
>-
>- This is a notification function registered on
>EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE event.
>- It converts physical plabel of ESAL entrypoint to virtual plabel and stores it
>where
>- GetEsalEntryPoint() can easily retrieve.
>-
>- @param Event Event whose notification function is being invoked.
>- @param Context Pointer to the notification function's context
>-
>-**/
>-VOID
>-EFIAPI
>-ExtendedSalVirtualNotifyEvent (
>- IN EFI_EVENT Event,
>- IN VOID *Context
>- )
>-{
>- UINT64 PhysicalEntryPoint;
>-
>- PhysicalEntryPoint = mPlabel.EntryPoint;
>-
>- gRT->ConvertPointer (0x0, (VOID **) &mPlabel.EntryPoint);
>-
>- mPlabel.GP += mPlabel.EntryPoint - PhysicalEntryPoint;
>-
>- SetEsalVirtualEntryPoint (mPlabel.EntryPoint, mPlabel.GP);
>-}
>-
>-/**
>- Gets Extended SAL Boot Service Protocol, and initializes physical plabel of
>- ESAL entrypoint.
>-
>- This function first locates Extended SAL Boot Service Protocol and caches it
>in global variable.
>- Then it initializes the physical plable of ESAL entrypoint, and stores
>- it where GetEsalEntryPoint() can easily retrieve.
>-
>- @retval EFI_SUCCESS Plable of ESAL entrypoint successfully stored.
>-
>-**/
>-EFI_STATUS
>-DxeSalLibInitialize (
>- VOID
>- )
>-{
>- EFI_PLABEL *Plabel;
>- EFI_STATUS Status;
>-
>- //
>- // The protocol contains a function pointer, which is an indirect procedure
>call.
>- // An indirect procedure call goes through a plabel, and pointer to a function
>is
>- // a pointer to a plabel. To implement indirect procedure calls that can work
>in
>- // both physical and virtual mode, two plabels are required (one physical
>and one
>- // virtual). So lets grap the physical PLABEL for the EsalEntryPoint and store it
>- // away. We cache it in a module global, so we can register the vitrual
>version.
>- //
>- Status = gBS->LocateProtocol (&gEfiExtendedSalBootServiceProtocolGuid,
>NULL, (VOID **) &mEsalBootService);
>- ASSERT_EFI_ERROR (Status);
>-
>- Plabel = (EFI_PLABEL *) (UINTN) mEsalBootService->ExtendedSalProc;
>- mPlabel.EntryPoint = Plabel->EntryPoint;
>- mPlabel.GP = Plabel->GP;
>- //
>- // Stores the physical plabel of ESAL entrypoint where GetEsalEntryPoint()
>can easily retrieve.
>- //
>- SetEsalPhysicalEntryPoint (mPlabel.EntryPoint, mPlabel.GP);
>-
>- return EFI_SUCCESS;
>-}
>-
>-/**
>- Constructor function to initializes physical plabel of ESAL entrypoint and
>register an event
>- for initialization of virtual plabel of ESAL entrypoint.
>-
>- This is the library constructor function to call a function to initialize physical
>plabel of ESAL entrypoint
>- and to register notification function for
>- EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE, which sets virtual plabel of ESAL
>entrypoint.
>-
>- @param ImageHandle The firmware allocated handle for the EFI image.
>- @param SystemTable A pointer to the EFI System Table.
>-
>- @retval EFI_SUCCESS Notification function successfully registered.
>-
>-**/
>-EFI_STATUS
>-EFIAPI
>-DxeRuntimeExtendedSalLibConstruct (
>- IN EFI_HANDLE ImageHandle,
>- IN EFI_SYSTEM_TABLE *SystemTable
>- )
>-{
>- EFI_STATUS Status;
>-
>- //
>- // Register notify function for EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE
>- //
>- ASSERT (gBS != NULL);
>-
>- DxeSalLibInitialize ();
>-
>- Status = gBS->CreateEventEx (
>- EVT_NOTIFY_SIGNAL,
>- TPL_NOTIFY,
>- ExtendedSalVirtualNotifyEvent,
>- NULL,
>- &gEfiEventVirtualAddressChangeGuid,
>- &mEfiVirtualNotifyEvent
>- );
>-
>- ASSERT_EFI_ERROR (Status);
>-
>- return EFI_SUCCESS;
>-}
>-
>-/**
>- Destructor function to close the event created by the library constructor
>-
>- This is the library destructor function to close the event with type of
>- EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE, which is created by the library
>constructor.
>-
>- @param ImageHandle The firmware allocated handle for the EFI image.
>- @param SystemTable A pointer to the EFI System Table.
>-
>- @retval EFI_SUCCESS Event successfully closed.
>-
>-**/
>-EFI_STATUS
>-EFIAPI
>-DxeRuntimeExtendedSalLibDeconstruct (
>- IN EFI_HANDLE ImageHandle,
>- IN EFI_SYSTEM_TABLE *SystemTable
>- )
>-{
>- EFI_STATUS Status;
>-
>- //
>- // Close SetVirtualAddressMap () notify function
>- //
>- ASSERT (gBS != NULL);
>- Status = gBS->CloseEvent (mEfiVirtualNotifyEvent);
>- ASSERT_EFI_ERROR (Status);
>-
>- return EFI_SUCCESS;
>-}
>-
>-/**
>- Registers function of ESAL class and it's associated global.
>-
>- This function registers function of ESAL class, together with its associated
>global.
>- It is worker function for RegisterEsalClass().
>- It is only for boot time.
>-
>- @param FunctionId ID of function to register
>- @param ClassGuidLo GUID of ESAL class, lower 64-bits
>- @param ClassGuidHi GUID of ESAL class, upper 64-bits
>- @param Function Function to register with ClassGuid/FunctionId pair
>- @param ModuleGlobal Module global for the function.
>-
>- @return Status returned by RegisterExtendedSalProc() of Extended SAL
>Boot Service Protocol
>-
>-**/
>-EFI_STATUS
>-RegisterEsalFunction (
>- IN UINT64 FunctionId,
>- IN UINT64 ClassGuidLo,
>- IN UINT64 ClassGuidHi,
>- IN SAL_INTERNAL_EXTENDED_SAL_PROC Function,
>- IN VOID *ModuleGlobal
>- )
>-{
>- return mEsalBootService->RegisterExtendedSalProc (
>- mEsalBootService,
>- ClassGuidLo,
>- ClassGuidHi,
>- FunctionId,
>- Function,
>- ModuleGlobal
>- );
>-}
>-
>-/**
>- Registers ESAL Class and it's associated global.
>-
>- This function registers one or more Extended SAL services in a given
>- class along with the associated global context.
>- This function is only available prior to ExitBootServices().
>-
>- @param ClassGuidLo GUID of function class, lower 64-bits
>- @param ClassGuidHi GUID of function class, upper 64-bits
>- @param ModuleGlobal Module global for the class.
>- @param ... List of Function/FunctionId pairs, ended by NULL
>-
>- @retval EFI_SUCCESS The Extended SAL services were registered.
>- @retval EFI_UNSUPPORTED This function was called after
>ExitBootServices().
>- @retval EFI_OUT_OF_RESOURCES There are not enough resources available
>to register one or more of the specified services.
>- @retval Other ClassGuid could not be installed onto a new handle.
>-
>-**/
>-EFI_STATUS
>-EFIAPI
>-RegisterEsalClass (
>- IN CONST UINT64 ClassGuidLo,
>- IN CONST UINT64 ClassGuidHi,
>- IN VOID *ModuleGlobal, OPTIONAL
>- ...
>- )
>-{
>- VA_LIST Args;
>- EFI_STATUS Status;
>- SAL_INTERNAL_EXTENDED_SAL_PROC Function;
>- UINT64 FunctionId;
>- EFI_HANDLE NewHandle;
>- EFI_GUID ClassGuid;
>-
>- VA_START (Args, ModuleGlobal);
>-
>- //
>- // Register all functions of the class to register.
>- //
>- Status = EFI_SUCCESS;
>- while (!EFI_ERROR (Status)) {
>- Function = (SAL_INTERNAL_EXTENDED_SAL_PROC) VA_ARG (Args,
>SAL_INTERNAL_EXTENDED_SAL_PROC);
>- //
>- // NULL serves as the end mark of function list
>- //
>- if (Function == NULL) {
>- break;
>- }
>-
>- FunctionId = VA_ARG (Args, UINT64);
>-
>- Status = RegisterEsalFunction (FunctionId, ClassGuidLo, ClassGuidHi,
>Function, ModuleGlobal);
>- }
>-
>- VA_END (Args);
>-
>- if (EFI_ERROR (Status)) {
>- return Status;
>- }
>-
>- NewHandle = NULL;
>- *((UINT64 *)(&ClassGuid) + 0) = ClassGuidLo;
>- *((UINT64 *)(&ClassGuid) + 1) = ClassGuidHi;
>- return gBS->InstallProtocolInterface (
>- &NewHandle,
>- &ClassGuid,
>- EFI_NATIVE_INTERFACE,
>- NULL
>- );
>-}
>-
>-/**
>- Calls an Extended SAL Class service that was previously registered with
>RegisterEsalClass().
>-
>- This function gets the entrypoint of Extended SAL, and calls an Extended SAL
>Class service
>- that was previously registered with RegisterEsalClass() through this
>entrypoint.
>-
>- @param ClassGuidLo GUID of function, lower 64-bits
>- @param ClassGuidHi GUID of function, upper 64-bits
>- @param FunctionId Function in ClassGuid to call
>- @param Arg2 Argument 2 ClassGuid/FunctionId defined
>- @param Arg3 Argument 3 ClassGuid/FunctionId defined
>- @param Arg4 Argument 4 ClassGuid/FunctionId defined
>- @param Arg5 Argument 5 ClassGuid/FunctionId defined
>- @param Arg6 Argument 6 ClassGuid/FunctionId defined
>- @param Arg7 Argument 7 ClassGuid/FunctionId defined
>- @param Arg8 Argument 8 ClassGuid/FunctionId defined
>-
>- @retval EFI_SAL_SUCCESS ESAL procedure successfully called.
>- @retval EFI_SAL_ERROR The address of ExtendedSalProc() can not be
>correctly
>- initialized.
>- @retval Other Status returned from ExtendedSalProc() service of
>- EXTENDED_SAL_BOOT_SERVICE_PROTOCOL.
>-
>-**/
>-SAL_RETURN_REGS
>-EFIAPI
>-EsalCall (
>- IN UINT64 ClassGuidLo,
>- IN UINT64 ClassGuidHi,
>- IN UINT64 FunctionId,
>- IN UINT64 Arg2,
>- IN UINT64 Arg3,
>- IN UINT64 Arg4,
>- IN UINT64 Arg5,
>- IN UINT64 Arg6,
>- IN UINT64 Arg7,
>- IN UINT64 Arg8
>- )
>-{
>- SAL_RETURN_REGS ReturnReg;
>- EXTENDED_SAL_PROC EsalProc;
>-
>- //
>- // Get the entrypoint of Extended SAL
>- //
>- ReturnReg = GetEsalEntryPoint ();
>- if (*(UINT64 *)ReturnReg.r9 == 0 && *(UINT64 *)(ReturnReg.r9 + 8) == 0) {
>- //
>- // The ESAL Entry Point could not be initialized
>- //
>- ReturnReg.Status = EFI_SAL_ERROR;
>- return ReturnReg;
>- }
>-
>- //
>- // Test PSR.it which is BIT36
>- //
>- if ((ReturnReg.r11 & BIT36) != 0) {
>- //
>- // Virtual mode plabel to entry point
>- //
>- EsalProc = (EXTENDED_SAL_PROC) ReturnReg.r10;
>- } else {
>- //
>- // Physical mode plabel to entry point
>- //
>- EsalProc = (EXTENDED_SAL_PROC) ReturnReg.r9;
>- }
>-
>- return EsalProc (
>- ClassGuidLo,
>- ClassGuidHi,
>- FunctionId,
>- Arg2,
>- Arg3,
>- Arg4,
>- Arg5,
>- Arg6,
>- Arg7,
>- Arg8
>- );
>-}
>-
>-/**
>- Wrapper for the EsalStallFunctionId service of Extended SAL Stall Services
>Class.
>-
>- This function is a wrapper for the EsalStallFunctionId service of Extended SAL
>- Stall Services Class. See EsalStallFunctionId of Extended SAL Specification.
>-
>- @param Microseconds The number of microseconds to delay.
>-
>- @retval EFI_SAL_SUCCESS Call completed without error.
>- @retval EFI_SAL_INVALID_ARGUMENT Invalid argument.
>- @retval EFI_SAL_VIRTUAL_ADDRESS_ERROR Virtual address not registered
>-
>-**/
>-SAL_RETURN_REGS
>-EFIAPI
>-EsalStall (
>- IN UINTN Microseconds
>- )
>-{
>- return EsalCall (
>- EFI_EXTENDED_SAL_STALL_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_STALL_SERVICES_PROTOCOL_GUID_HI,
>- StallFunctionId,
>- Microseconds,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0
>- );
>-}
>-
>-/**
>- Wrapper for the EsalSetNewPalEntryFunctionId service of Extended SAL PAL
>Services Services Class.
>-
>- This function is a wrapper for the EsalSetNewPalEntryFunctionId service of
>Extended SAL
>- PAL Services Services Class. See EsalSetNewPalEntryFunctionId of Extended
>SAL Specification.
>-
>- @param PhysicalAddress If TRUE, then PalEntryPoint is a physical
>address.
>- If FALSE, then PalEntryPoint is a virtual address.
>- @param PalEntryPoint The PAL Entry Point being set.
>-
>- @retval EFI_SAL_SUCCESS The PAL Entry Point was set.
>- @retval EFI_SAL_VIRTUAL_ADDRESS_ERROR This function was called in
>virtual mode before
>- virtual mappings for the specified Extended SAL
>- Procedure are available.
>-
>-**/
>-SAL_RETURN_REGS
>-EFIAPI
>-EsalSetNewPalEntry (
>- IN BOOLEAN PhysicalAddress,
>- IN UINT64 PalEntryPoint
>- )
>-{
>- return EsalCall (
>- EFI_EXTENDED_SAL_PAL_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_PAL_SERVICES_PROTOCOL_GUID_HI,
>- SetNewPalEntryFunctionId,
>- PhysicalAddress,
>- PalEntryPoint,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0
>- );
>-}
>-
>-/**
>- Wrapper for the EsalGetNewPalEntryFunctionId service of Extended SAL
>PAL Services Services Class.
>-
>- This function is a wrapper for the EsalGetNewPalEntryFunctionId service of
>Extended SAL
>- PAL Services Services Class. See EsalGetNewPalEntryFunctionId of Extended
>SAL Specification.
>-
>- @param PhysicalAddress If TRUE, then PalEntryPoint is a physical
>address.
>- If FALSE, then PalEntryPoint is a virtual address.
>-
>- @retval EFI_SAL_SUCCESS The PAL Entry Point was retrieved and
>returned in
>- SAL_RETURN_REGS.r9.
>- @retval EFI_SAL_VIRTUAL_ADDRESS_ERROR This function was called in
>virtual mode before
>- virtual mappings for the specified Extended SAL
>- Procedure are available.
>- @return r9 PAL entry point retrieved.
>-
>-**/
>-SAL_RETURN_REGS
>-EFIAPI
>-EsalGetNewPalEntry (
>- IN BOOLEAN PhysicalAddress
>- )
>-{
>- return EsalCall (
>- EFI_EXTENDED_SAL_PAL_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_PAL_SERVICES_PROTOCOL_GUID_HI,
>- GetNewPalEntryFunctionId,
>- PhysicalAddress,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0
>- );
>-}
>-
>-/**
>- Wrapper for the EsalGetStateBufferFunctionId service of Extended SAL
>MCA Log Services Class.
>-
>- This function is a wrapper for the EsalGetStateBufferFunctionId service of
>Extended SAL
>- MCA Log Services Class. See EsalGetStateBufferFunctionId of Extended SAL
>Specification.
>-
>- @param McaType See type parameter of SAL Procedure
>SAL_GET_STATE_INFO.
>- @param McaBuffer A pointer to the base address of the returned
>buffer.
>- Copied from SAL_RETURN_REGS.r9.
>- @param BufferSize A pointer to the size, in bytes, of the returned
>buffer.
>- Copied from SAL_RETURN_REGS.r10.
>-
>- @retval EFI_SAL_SUCCESS The memory buffer to store error records was
>returned in r9 and r10.
>- @retval EFI_OUT_OF_RESOURCES A memory buffer for string error records
>in not available
>- @return r9 Base address of the returned buffer
>- @return r10 Size of the returned buffer in bytes
>-
>-**/
>-SAL_RETURN_REGS
>-EFIAPI
>-EsalGetStateBuffer (
>- IN UINT64 McaType,
>- OUT UINT8 **McaBuffer,
>- OUT UINTN *BufferSize
>- )
>-{
>- SAL_RETURN_REGS Regs;
>-
>- Regs = EsalCall (
>- EFI_EXTENDED_SAL_MCA_LOG_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_MCA_LOG_SERVICES_PROTOCOL_GUID_HI,
>- EsalGetStateBufferFunctionId,
>- McaType,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0
>- );
>-
>- *McaBuffer = (UINT8 *) Regs.r9;
>- *BufferSize = Regs.r10;
>-
>- return Regs;
>-}
>-
>-/**
>- Wrapper for the EsalSaveStateBufferFunctionId service of Extended SAL
>MCA Log Services Class.
>-
>- This function is a wrapper for the EsalSaveStateBufferFunctionId service of
>Extended SAL
>- MCA Log Services Class. See EsalSaveStateBufferFunctionId of Extended SAL
>Specification.
>-
>- @param McaType See type parameter of SAL Procedure
>SAL_GET_STATE_INFO.
>-
>- @retval EFI_SUCCESS The memory buffer containing the error record was
>written to nonvolatile storage.
>-
>-**/
>-SAL_RETURN_REGS
>-EFIAPI
>-EsalSaveStateBuffer (
>- IN UINT64 McaType
>- )
>-{
>- return EsalCall (
>- EFI_EXTENDED_SAL_MCA_LOG_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_MCA_LOG_SERVICES_PROTOCOL_GUID_HI,
>- EsalSaveStateBufferFunctionId,
>- McaType,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0
>- );
>-}
>-
>-/**
>- Wrapper for the EsalGetVectorsFunctionId service of Extended SAL Base
>Services Class.
>-
>- This function is a wrapper for the EsalGetVectorsFunctionId service of
>Extended SAL
>- Base Services Class. See EsalGetVectorsFunctionId of Extended SAL
>Specification.
>-
>- @param VectorType The vector type to retrieve.
>- 0 - MCA, 1 - BSP INIT, 2 - BOOT_RENDEZ, 3 - AP INIT.
>-
>- @retval EFI_SAL_SUCCESS Call completed without error.
>- @retval EFI_SAL_INVALID_ARGUMENT Invalid argument.
>- @retval EFI_SAL_NO_INFORMATION The requested vector has not been
>registered
>- with the SAL Procedure SAL_SET_VECTORS.
>-
>-**/
>-SAL_RETURN_REGS
>-EFIAPI
>-EsalGetVectors (
>- IN UINT64 VectorType
>- )
>-{
>- return EsalCall (
>- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_HI,
>- EsalGetVectorsFunctionId,
>- VectorType,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0
>- );
>-}
>-
>-/**
>- Wrapper for the EsalMcGetParamsFunctionId service of Extended SAL Base
>Services Class.
>-
>- This function is a wrapper for the EsalMcGetParamsFunctionId service of
>Extended SAL
>- Base Services Class. See EsalMcGetParamsFunctionId of Extended SAL
>Specification.
>-
>- @param ParamInfoType The parameter type to retrieve.
>- 1 - rendezvous interrupt
>- 2 - wake up
>- 3 - Corrected Platform Error Vector.
>-
>- @retval EFI_SAL_SUCCESS Call completed without error.
>- @retval EFI_SAL_INVALID_ARGUMENT Invalid argument.
>- @retval EFI_SAL_NO_INFORMATION The requested vector has not been
>registered
>- with the SAL Procedure SAL_MC_SET_PARAMS.
>-
>-**/
>-SAL_RETURN_REGS
>-EFIAPI
>-EsalMcGetParams (
>- IN UINT64 ParamInfoType
>- )
>-{
>- return EsalCall (
>- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_HI,
>- EsalMcGetParamsFunctionId,
>- ParamInfoType,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0
>- );
>-}
>-
>-/**
>- Wrapper for the EsalMcGetParamsFunctionId service of Extended SAL Base
>Services Class.
>-
>- This function is a wrapper for the EsalMcGetParamsFunctionId service of
>Extended SAL
>- Base Services Class. See EsalMcGetParamsFunctionId of Extended SAL
>Specification.
>-
>- @retval EFI_SAL_SUCCESS Call completed without error.
>- @retval EFI_SAL_NO_INFORMATION The requested vector has not been
>registered
>- with the SAL Procedure SAL_MC_SET_PARAMS.
>-
>-**/
>-SAL_RETURN_REGS
>-EFIAPI
>-EsalMcGetMcParams (
>- VOID
>- )
>-{
>- return EsalCall (
>- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_HI,
>- EsalMcGetMcParamsFunctionId,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0
>- );
>-}
>-
>-/**
>- Wrapper for the EsalGetMcCheckinFlagsFunctionId service of Extended SAL
>Base Services Class.
>-
>- This function is a wrapper for the EsalGetMcCheckinFlagsFunctionId service
>of Extended SAL
>- Base Services Class. See EsalGetMcCheckinFlagsFunctionId of Extended SAL
>Specification.
>-
>- @param CpuIndex The index of the CPU of set of enabled CPUs to
>check.
>-
>- @retval EFI_SAL_SUCCESS The checkin status of the requested CPU was
>returned.
>-
>-**/
>-SAL_RETURN_REGS
>-EFIAPI
>-EsalGetMcCheckinFlags (
>- IN UINT64 CpuIndex
>- )
>-{
>- return EsalCall (
>- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_HI,
>- EsalGetMcCheckinFlagsFunctionId,
>- CpuIndex,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0
>- );
>-}
>-
>-/**
>- Wrapper for the EsalAddCpuDataFunctionId service of Extended SAL MP
>Services Class.
>-
>- This function is a wrapper for the EsalAddCpuDataFunctionId service of
>Extended SAL
>- MP Services Class. See EsalAddCpuDataFunctionId of Extended SAL
>Specification.
>-
>- @param CpuGlobalId The Global ID for the CPU being added.
>- @param Enabled The enable flag for the CPU being added.
>- TRUE means the CPU is enabled.
>- FALSE means the CPU is disabled.
>- @param PalCompatibility The PAL Compatibility value for the CPU being
>added.
>-
>- @retval EFI_SAL_SUCCESS The CPU was added to the database.
>- @retval EFI_SAL_NOT_ENOUGH_SCRATCH There are not enough resource
>available to add the CPU.
>-
>-**/
>-SAL_RETURN_REGS
>-EFIAPI
>-EsalAddCpuData (
>- IN UINT64 CpuGlobalId,
>- IN BOOLEAN Enabled,
>- IN UINT64 PalCompatibility
>- )
>-{
>- return EsalCall (
>- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_HI,
>- AddCpuDataFunctionId,
>- CpuGlobalId,
>- Enabled,
>- PalCompatibility,
>- 0,
>- 0,
>- 0,
>- 0
>- );
>-}
>-
>-/**
>- Wrapper for the EsalRemoveCpuDataFunctionId service of Extended SAL
>MP Services Class.
>-
>- This function is a wrapper for the EsalRemoveCpuDataFunctionId service of
>Extended SAL
>- MP Services Class. See EsalRemoveCpuDataFunctionId of Extended SAL
>Specification.
>-
>- @param CpuGlobalId The Global ID for the CPU being removed.
>-
>- @retval EFI_SAL_SUCCESS The CPU was removed from the database.
>- @retval EFI_SAL_NO_INFORMATION The specified CPU is not in the
>database.
>-
>-**/
>-SAL_RETURN_REGS
>-EFIAPI
>-EsalRemoveCpuData (
>- IN UINT64 CpuGlobalId
>- )
>-{
>- return EsalCall (
>- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_HI,
>- RemoveCpuDataFunctionId,
>- CpuGlobalId,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0
>- );
>-}
>-
>-/**
>- Wrapper for the EsalModifyCpuDataFunctionId service of Extended SAL MP
>Services Class.
>-
>- This function is a wrapper for the EsalModifyCpuDataFunctionId service of
>Extended SAL
>- MP Services Class. See EsalModifyCpuDataFunctionId of Extended SAL
>Specification.
>-
>- @param CpuGlobalId The Global ID for the CPU being modified.
>- @param Enabled The enable flag for the CPU being modified.
>- TRUE means the CPU is enabled.
>- FALSE means the CPU is disabled.
>- @param PalCompatibility The PAL Compatibility value for the CPU being
>modified.
>-
>- @retval EFI_SAL_SUCCESS The CPU database was updated.
>- @retval EFI_SAL_NO_INFORMATION The specified CPU is not in the
>database.
>-
>-**/
>-SAL_RETURN_REGS
>-EFIAPI
>-EsalModifyCpuData (
>- IN UINT64 CpuGlobalId,
>- IN BOOLEAN Enabled,
>- IN UINT64 PalCompatibility
>- )
>-{
>- return EsalCall (
>- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_HI,
>- ModifyCpuDataFunctionId,
>- CpuGlobalId,
>- Enabled,
>- PalCompatibility,
>- 0,
>- 0,
>- 0,
>- 0
>- );
>-}
>-
>-/**
>- Wrapper for the EsalGetCpuDataByIdFunctionId service of Extended SAL MP
>Services Class.
>-
>- This function is a wrapper for the EsalGetCpuDataByIdFunctionId service of
>Extended SAL
>- MP Services Class. See EsalGetCpuDataByIdFunctionId of Extended SAL
>Specification.
>-
>- @param CpuGlobalId The Global ID for the CPU being looked up.
>- @param IndexByEnabledCpu If TRUE, then the index of set of enabled
>CPUs of database is returned.
>- If FALSE, then the index of set of all CPUs of database is
>returned.
>-
>- @retval EFI_SAL_SUCCESS The information on the specified CPU was
>returned.
>- @retval EFI_SAL_NO_INFORMATION The specified CPU is not in the
>database.
>-
>-**/
>-SAL_RETURN_REGS
>-EFIAPI
>-EsalGetCpuDataById (
>- IN UINT64 CpuGlobalId,
>- IN BOOLEAN IndexByEnabledCpu
>- )
>-{
>- return EsalCall (
>- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_HI,
>- GetCpuDataByIDFunctionId,
>- CpuGlobalId,
>- IndexByEnabledCpu,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0
>- );
>-}
>-
>-/**
>- Wrapper for the EsalGetCpuDataByIndexFunctionId service of Extended SAL
>MP Services Class.
>-
>- This function is a wrapper for the EsalGetCpuDataByIndexFunctionId service
>of Extended SAL
>- MP Services Class. See EsalGetCpuDataByIndexFunctionId of Extended SAL
>Specification.
>-
>- @param Index The Global ID for the CPU being modified.
>- @param IndexByEnabledCpu If TRUE, then the index of set of enabled
>CPUs of database is returned.
>- If FALSE, then the index of set of all CPUs of database is
>returned.
>-
>- @retval EFI_SAL_SUCCESS The information on the specified CPU was
>returned.
>- @retval EFI_SAL_NO_INFORMATION The specified CPU is not in the
>database.
>-
>-**/
>-SAL_RETURN_REGS
>-EFIAPI
>-EsalGetCpuDataByIndex (
>- IN UINT64 Index,
>- IN BOOLEAN IndexByEnabledCpu
>- )
>-{
>- return EsalCall (
>- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_HI,
>- GetCpuDataByIndexFunctionId,
>- Index,
>- IndexByEnabledCpu,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0
>- );
>-}
>-
>-/**
>- Wrapper for the EsalWhoAmIFunctionId service of Extended SAL MP
>Services Class.
>-
>- This function is a wrapper for the EsalWhoAmIFunctionId service of
>Extended SAL
>- MP Services Class. See EsalWhoAmIFunctionId of Extended SAL Specification.
>-
>- @param IndexByEnabledCpu If TRUE, then the index of set of enabled
>CPUs of database is returned.
>- If FALSE, then the index of set of all CPUs of database is
>returned.
>-
>- @retval EFI_SAL_SUCCESS The Global ID for the calling CPU was
>returned.
>- @retval EFI_SAL_NO_INFORMATION The calling CPU is not in the database.
>-
>-**/
>-SAL_RETURN_REGS
>-EFIAPI
>-EsalWhoAmI (
>- IN BOOLEAN IndexByEnabledCpu
>- )
>-{
>- return EsalCall (
>- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_HI,
>- CurrentProcInfoFunctionId,
>- IndexByEnabledCpu,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0
>- );
>-}
>-
>-/**
>- Wrapper for the EsalNumProcessors service of Extended SAL MP Services
>Class.
>-
>- This function is a wrapper for the EsalNumProcessors service of Extended
>SAL
>- MP Services Class. See EsalNumProcessors of Extended SAL Specification.
>-
>- @retval EFI_SAL_SUCCESS The information on the number of CPUs in the
>platform
>- was returned.
>-
>-**/
>-SAL_RETURN_REGS
>-EFIAPI
>-EsalNumProcessors (
>- VOID
>- )
>-{
>- return EsalCall (
>- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_HI,
>- NumProcessorsFunctionId,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0
>- );
>-}
>-
>-/**
>- Wrapper for the EsalSetMinStateFnctionId service of Extended SAL MP
>Services Class.
>-
>- This function is a wrapper for the EsalSetMinStateFnctionId service of
>Extended SAL
>- MP Services Class. See EsalSetMinStateFnctionId of Extended SAL
>Specification.
>-
>- @param CpuGlobalId The Global ID for the CPU whose MINSTATE
>pointer is being set.
>- @param MinStatePointer The physical address of the MINSTATE buffer
>for the CPU
>- specified by CpuGlobalId.
>-
>- @retval EFI_SAL_SUCCESS The MINSTATE pointer was set for the
>specified CPU.
>- @retval EFI_SAL_NO_INFORMATION The specified CPU is not in the
>database.
>-
>-**/
>-SAL_RETURN_REGS
>-EFIAPI
>-EsalSetMinState (
>- IN UINT64 CpuGlobalId,
>- IN EFI_PHYSICAL_ADDRESS MinStatePointer
>- )
>-{
>- return EsalCall (
>- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_HI,
>- SetMinStateFunctionId,
>- CpuGlobalId,
>- MinStatePointer,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0
>- );
>-}
>-
>-/**
>- Wrapper for the EsalGetMinStateFunctionId service of Extended SAL MP
>Services Class.
>-
>- This function is a wrapper for the EsalGetMinStateFunctionId service of
>Extended SAL
>- MP Services Class. See EsalGetMinStateFunctionId of Extended SAL
>Specification.
>-
>- @param CpuGlobalId The Global ID for the CPU whose MINSTATE pointer
>is being retrieved.
>-
>- @retval EFI_SAL_SUCCESS The MINSTATE pointer for the specified CPU
>was retrieved.
>- @retval EFI_SAL_NO_INFORMATION The specified CPU is not in the
>database.
>-
>-**/
>-SAL_RETURN_REGS
>-EFIAPI
>-EsalGetMinState (
>- IN UINT64 CpuGlobalId
>- )
>-{
>- return EsalCall (
>- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_HI,
>- GetMinStateFunctionId,
>- CpuGlobalId,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0
>- );
>-}
>-
>-/**
>- Wrapper for the EsalMcsGetStateInfoFunctionId service of Extended SAL
>MCA Services Class.
>-
>- This function is a wrapper for the EsalMcsGetStateInfoFunctionId service of
>Extended SAL
>- MCA Services Class. See EsalMcsGetStateInfoFunctionId of Extended SAL
>Specification.
>-
>- @param CpuGlobalId The Global ID for the CPU whose MCA state
>buffer is being retrieved.
>- @param StateBufferPointer A pointer to the returned MCA state buffer.
>- @param RequiredStateBufferSize A pointer to the size, in bytes, of the
>returned MCA state buffer.
>-
>- @retval EFI_SUCCESS MINSTATE successfully got and size calculated.
>- @retval EFI_SAL_NO_INFORMATION Fail to get MINSTATE.
>-
>-**/
>-SAL_RETURN_REGS
>-EFIAPI
>-EsalMcaGetStateInfo (
>- IN UINT64 CpuGlobalId,
>- OUT EFI_PHYSICAL_ADDRESS *StateBufferPointer,
>- OUT UINT64 *RequiredStateBufferSize
>- )
>-{
>- SAL_RETURN_REGS Regs;
>-
>- Regs = EsalCall (
>- EFI_EXTENDED_SAL_MCA_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_MCA_SERVICES_PROTOCOL_GUID_HI,
>- McaGetStateInfoFunctionId,
>- CpuGlobalId,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0
>- );
>-
>- *StateBufferPointer = (EFI_PHYSICAL_ADDRESS) Regs.r9;
>- *RequiredStateBufferSize = (UINT64) Regs.r10;
>-
>- return Regs;
>-}
>-
>-/**
>- Wrapper for the EsalMcaRegisterCpuFunctionId service of Extended SAL
>MCA Services Class.
>-
>- This function is a wrapper for the EsalMcaRegisterCpuFunctionId service of
>Extended SAL
>- MCA Services Class. See EsalMcaRegisterCpuFunctionId of Extended SAL
>Specification.
>-
>- @param CpuGlobalId The Global ID for the CPU whose MCA state
>buffer is being set.
>- @param StateBufferPointer A pointer to the MCA state buffer.
>-
>- @retval EFI_SAL_NO_INFORMATION Cannot get the processor info with
>the CpuId
>- @retval EFI_SUCCESS Save the processor's state info successfully
>-
>-**/
>-SAL_RETURN_REGS
>-EFIAPI
>-EsalMcaRegisterCpu (
>- IN UINT64 CpuGlobalId,
>- IN EFI_PHYSICAL_ADDRESS StateBufferPointer
>- )
>-{
>- return EsalCall (
>- EFI_EXTENDED_SAL_MCA_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_MCA_SERVICES_PROTOCOL_GUID_HI,
>- McaRegisterCpuFunctionId,
>- CpuGlobalId,
>- StateBufferPointer,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0
>- );
>-}
>diff --git
>a/MdePkg/Library/DxeRuntimeExtendedSalLib/Ipf/AsmExtendedSalLib.s
>b/MdePkg/Library/DxeRuntimeExtendedSalLib/Ipf/AsmExtendedSalLib.s
>deleted file mode 100644
>index ddabc76e0d..0000000000
>--- a/MdePkg/Library/DxeRuntimeExtendedSalLib/Ipf/AsmExtendedSalLib.s
>+++ /dev/null
>@@ -1,131 +0,0 @@
>-/// @file
>-/// Assembly procedures to get and set ESAL entry point.
>-///
>-/// Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
>-/// This program and the accompanying materials
>-/// are licensed and made available under the terms and conditions of the
>BSD License
>-/// which accompanies this distribution. The full text of the license may be
>found at
>-/// http://opensource.org/licenses/bsd-license.php.
>-///
>-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-///
>-
>-.auto
>-.text
>-
>-#include "IpfMacro.i"
>-
>-//
>-// Exports
>-//
>-ASM_GLOBAL GetEsalEntryPoint
>-
>-//-----------------------------------------------------------------------------
>-//++
>-// GetEsalEntryPoint
>-//
>-// Return Esal global and PSR register.
>-//
>-// On Entry :
>-//
>-//
>-// Return Value:
>-// r8 = EFI_SAL_SUCCESS
>-// r9 = Physical Plabel
>-// r10 = Virtual Plabel
>-// r11 = psr
>-//
>-// As per static calling conventions.
>-//
>-//--
>-//---------------------------------------------------------------------------
>-PROCEDURE_ENTRY (GetEsalEntryPoint)
>-
>- NESTED_SETUP (0,8,0,0)
>-
>-EsalCalcStart:
>- mov r8 = ip;;
>- add r8 = (EsalEntryPoint - EsalCalcStart), r8;;
>- mov r9 = r8;;
>- add r10 = 0x10, r8;;
>- mov r11 = psr;;
>- mov r8 = r0;;
>-
>- NESTED_RETURN
>-
>-PROCEDURE_EXIT (GetEsalEntryPoint)
>-
>-//-----------------------------------------------------------------------------
>-//++
>-// SetEsalPhysicalEntryPoint
>-//
>-// Set the dispatcher entry point
>-//
>-// On Entry:
>-// in0 = Physical address of Esal Dispatcher
>-// in1 = Physical GP
>-//
>-// Return Value:
>-// r8 = EFI_SAL_SUCCESS
>-//
>-// As per static calling conventions.
>-//
>-//--
>-//---------------------------------------------------------------------------
>-PROCEDURE_ENTRY (SetEsalPhysicalEntryPoint)
>-
>- NESTED_SETUP (2,8,0,0)
>-
>-EsalCalcStart1:
>- mov r8 = ip;;
>- add r8 = (EsalEntryPoint - EsalCalcStart1), r8;;
>- st8 [r8] = in0;;
>- add r8 = 0x08, r8;;
>- st8 [r8] = in1;;
>- mov r8 = r0;;
>-
>- NESTED_RETURN
>-
>-PROCEDURE_EXIT (SetEsalPhysicalEntryPoint)
>-
>-//-----------------------------------------------------------------------------
>-//++
>-// SetEsalVirtualEntryPoint
>-//
>-// Register physical address of Esal globals.
>-//
>-// On Entry :
>-// in0 = Virtual address of Esal Dispatcher
>-// in1 = Virtual GP
>-//
>-// Return Value:
>-// r8 = EFI_SAL_ERROR
>-//
>-// As per static calling conventions.
>-//
>-//--
>-//---------------------------------------------------------------------------
>-PROCEDURE_ENTRY (SetEsalVirtualEntryPoint)
>-
>- NESTED_SETUP (2,8,0,0)
>-
>-EsalCalcStart2:
>- mov r8 = ip;;
>- add r8 = (EsalEntryPoint - EsalCalcStart2), r8;;
>- add r8 = 0x10, r8;;
>- st8 [r8] = in0;;
>- add r8 = 0x08, r8;;
>- st8 [r8] = in1;;
>- mov r8 = r0;;
>-
>- NESTED_RETURN
>-
>-PROCEDURE_EXIT (SetEsalVirtualEntryPoint)
>-
>-.align 32
>-EsalEntryPoint:
>- data8 0 // Physical Entry
>- data8 0 // GP
>- data8 0 // Virtual Entry
>- data8 0 // GP
>diff --git
>a/MdePkg/Library/DxeRuntimePciExpressLib/DxeRuntimePciExpressLib.inf
>b/MdePkg/Library/DxeRuntimePciExpressLib/DxeRuntimePciExpressLib.inf
>index 5d7357035b..48848496cb 100644
>--- a/MdePkg/Library/DxeRuntimePciExpressLib/DxeRuntimePciExpressLib.inf
>+++
>b/MdePkg/Library/DxeRuntimePciExpressLib/DxeRuntimePciExpressLib.inf
>@@ -31,7 +31,7 @@
> DESTRUCTOR = DxeRuntimePciExpressLibDestructor
>
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
>+# VALID_ARCHITECTURES = IA32 X64 EBC
> #
>
> [Sources]
>diff --git a/MdePkg/Library/DxeSalLibEsal/DxeSalLibEsal.c
>b/MdePkg/Library/DxeSalLibEsal/DxeSalLibEsal.c
>deleted file mode 100644
>index 8d1dd9ae15..0000000000
>--- a/MdePkg/Library/DxeSalLibEsal/DxeSalLibEsal.c
>+++ /dev/null
>@@ -1,286 +0,0 @@
>-/** @file
>- This library implements the SAL Library Class using Extended SAL functions
>-
>- Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
>- This program and the accompanying materials
>- are licensed and made available under the terms and conditions of the BSD
>License
>- which accompanies this distribution. The full text of the license may be
>found at
>- http://opensource.org/licenses/bsd-license.php.
>-
>- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-
>-**/
>-
>-#include <PiDxe.h>
>-
>-#include <Protocol/ExtendedSalServiceClasses.h>
>-
>-#include <Library/SalLib.h>
>-#include <Library/ExtendedSalLib.h>
>-
>-/**
>- Makes a SAL procedure call.
>-
>- This is a wrapper function to make a SAL procedure call.
>- No parameter checking is performed on the 8 input parameters,
>- but there are some common rules that the caller should follow
>- when making a SAL call. Any address passed to SAL as buffers
>- for return parameters must be 8-byte aligned. Unaligned
>- addresses may cause undefined results. For those parameters
>- defined as reserved or some fields defined as reserved must be
>- zero filled or the invalid argument return value may be returned
>- or undefined result may occur during the execution of the procedure.
>- This function is only available on IPF.
>-
>- @param Index The SAL procedure Index number
>- @param Arg2 The 2nd parameter for SAL procedure calls
>- @param Arg3 The 3rd parameter for SAL procedure calls
>- @param Arg4 The 4th parameter for SAL procedure calls
>- @param Arg5 The 5th parameter for SAL procedure calls
>- @param Arg6 The 6th parameter for SAL procedure calls
>- @param Arg7 The 7th parameter for SAL procedure calls
>- @param Arg8 The 8th parameter for SAL procedure calls
>-
>- @return SAL returned registers.
>-
>-**/
>-SAL_RETURN_REGS
>-EFIAPI
>-SalCall (
>- IN UINT64 Index,
>- IN UINT64 Arg2,
>- IN UINT64 Arg3,
>- IN UINT64 Arg4,
>- IN UINT64 Arg5,
>- IN UINT64 Arg6,
>- IN UINT64 Arg7,
>- IN UINT64 Arg8
>- )
>-{
>- SAL_RETURN_REGS Regs;
>-
>- //
>- // Initial all members in this structure.
>- //
>- Regs.r9 = 0;
>- Regs.r10 = 0;
>- Regs.r11 = 0;
>- Regs.Status = EFI_SAL_INVALID_ARGUMENT;
>-
>- switch (Index) {
>- case EFI_SAL_SET_VECTORS:
>- return EsalCall (
>- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_HI,
>- SalSetVectorsFunctionId,
>- Arg2,
>- Arg3,
>- Arg4,
>- Arg5,
>- Arg6,
>- Arg7,
>- Arg8
>- );
>- break;
>-
>- case EFI_SAL_GET_STATE_INFO:
>- return EsalCall (
>- EFI_EXTENDED_SAL_MCA_LOG_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_MCA_LOG_SERVICES_PROTOCOL_GUID_HI,
>- SalGetStateInfoFunctionId,
>- Arg2,
>- Arg3,
>- Arg4,
>- Arg5,
>- Arg6,
>- Arg7,
>- Arg8
>- );
>- break;
>-
>- case EFI_SAL_GET_STATE_INFO_SIZE:
>- return EsalCall (
>- EFI_EXTENDED_SAL_MCA_LOG_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_MCA_LOG_SERVICES_PROTOCOL_GUID_HI,
>- SalGetStateInfoSizeFunctionId,
>- Arg2,
>- Arg3,
>- Arg4,
>- Arg5,
>- Arg6,
>- Arg7,
>- Arg8
>- );
>- break;
>-
>- case EFI_SAL_CLEAR_STATE_INFO:
>- return EsalCall (
>- EFI_EXTENDED_SAL_MCA_LOG_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_MCA_LOG_SERVICES_PROTOCOL_GUID_HI,
>- SalClearStateInfoFunctionId,
>- Arg2,
>- Arg3,
>- Arg4,
>- Arg5,
>- Arg6,
>- Arg7,
>- Arg8
>- );
>- break;
>-
>- case EFI_SAL_MC_RENDEZ:
>- return EsalCall (
>- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_HI,
>- SalMcRendezFunctionId,
>- Arg2,
>- Arg3,
>- Arg4,
>- Arg5,
>- Arg6,
>- Arg7,
>- Arg8
>- );
>- break;
>-
>- case EFI_SAL_MC_SET_PARAMS:
>- return EsalCall (
>- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_HI,
>- SalMcSetParamsFunctionId,
>- Arg2,
>- Arg3,
>- Arg4,
>- Arg5,
>- Arg6,
>- Arg7,
>- Arg8
>- );
>- break;
>-
>- case EFI_SAL_REGISTER_PHYSICAL_ADDR:
>- return EsalCall (
>- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_HI,
>- EsalRegisterPhysicalAddrFunctionId,
>- Arg2,
>- Arg3,
>- Arg4,
>- Arg5,
>- Arg6,
>- Arg7,
>- Arg8
>- );
>- break;
>-
>- case EFI_SAL_CACHE_FLUSH:
>- return EsalCall (
>- EFI_EXTENDED_SAL_CACHE_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_CACHE_SERVICES_PROTOCOL_GUID_HI,
>- SalCacheFlushFunctionId,
>- Arg2,
>- Arg3,
>- Arg4,
>- Arg5,
>- Arg6,
>- Arg7,
>- Arg8
>- );
>- break;
>-
>- case EFI_SAL_CACHE_INIT:
>- return EsalCall (
>- EFI_EXTENDED_SAL_CACHE_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_CACHE_SERVICES_PROTOCOL_GUID_HI,
>- SalCacheInitFunctionId,
>- Arg2,
>- Arg3,
>- Arg4,
>- Arg5,
>- Arg6,
>- Arg7,
>- Arg8
>- );
>- break;
>-
>- case EFI_SAL_PCI_CONFIG_READ:
>- return EsalCall (
>- EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_HI,
>- SalPciConfigReadFunctionId,
>- Arg2,
>- Arg3,
>- Arg4,
>- Arg5,
>- Arg6,
>- Arg7,
>- Arg8
>- );
>- break;
>-
>- case EFI_SAL_PCI_CONFIG_WRITE:
>- return EsalCall (
>- EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_HI,
>- SalPciConfigWriteFunctionId,
>- Arg2,
>- Arg3,
>- Arg4,
>- Arg5,
>- Arg6,
>- Arg7,
>- Arg8
>- );
>- break;
>-
>- case EFI_SAL_FREQ_BASE:
>- return EsalCall (
>- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_HI,
>- EsalGetPlatformBaseFreqFunctionId,
>- Arg2,
>- Arg3,
>- Arg4,
>- Arg5,
>- Arg6,
>- Arg7,
>- Arg8
>- );
>- break;
>-
>- case EFI_SAL_PHYSICAL_ID_INFO:
>- return EsalCall (
>- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_HI,
>- EsalPhysicalIdInfoFunctionId,
>- Arg2,
>- Arg3,
>- Arg4,
>- Arg5,
>- Arg6,
>- Arg7,
>- Arg8
>- );
>- break;
>-
>- case EFI_SAL_UPDATE_PAL:
>- return EsalCall (
>- EFI_EXTENDED_SAL_PAL_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_PAL_SERVICES_PROTOCOL_GUID_HI,
>- EsalUpdatePalFunctionId,
>- Arg2,
>- Arg3,
>- Arg4,
>- Arg5,
>- Arg6,
>- Arg7,
>- Arg8
>- );
>- break;
>-
>- default:
>- return Regs;
>- break;
>- }
>-}
>diff --git a/MdePkg/Library/DxeSalLibEsal/DxeSalLibEsal.inf
>b/MdePkg/Library/DxeSalLibEsal/DxeSalLibEsal.inf
>deleted file mode 100644
>index 656d949574..0000000000
>--- a/MdePkg/Library/DxeSalLibEsal/DxeSalLibEsal.inf
>+++ /dev/null
>@@ -1,38 +0,0 @@
>-## @file
>-# This library implements the SAL Library Class using Extended SAL functions
>-#
>-# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
>-#
>-# This program and the accompanying materials
>-# are licensed and made available under the terms and conditions of the BSD
>License
>-# which accompanies this distribution. The full text of the license may be
>found at
>-# http://opensource.org/licenses/bsd-license.php.
>-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-#
>-##
>-
>-[Defines]
>- INF_VERSION = 0x00010005
>- BASE_NAME = DxeSalLibEsal
>- MODULE_UNI_FILE = DxeSalLibEsal.uni
>- FILE_GUID = 2B73B074-2E67-498b-82AC-CE38FB770FFC
>- MODULE_TYPE = DXE_DRIVER
>- VERSION_STRING = 1.0
>- LIBRARY_CLASS = SalLib|DXE_DRIVER DXE_RUNTIME_DRIVER
>DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
>-
>-#
>-# The following information is for reference only and not required by the
>build tools.
>-#
>-# VALID_ARCHITECTURES = IPF
>-#
>-
>-[Sources.IPF]
>- DxeSalLibEsal.c
>-
>-[Packages]
>- MdePkg/MdePkg.dec
>-
>-[LibraryClasses]
>- ExtendedSalLib
>-
>diff --git a/MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
>b/MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
>index 50ae24f8ee..ab53ffbd3c 100644
>--- a/MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
>+++ b/MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
>@@ -24,16 +24,16 @@
> FILE_GUID = EE680C58-FFC0-4a5d-858F-66FF9C84BC9F
> MODULE_TYPE = DXE_DRIVER
> VERSION_STRING = 1.0
>- LIBRARY_CLASS = DxeServicesLib|DXE_CORE DXE_DRIVER
>DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER SMM_CORE
>UEFI_APPLICATION UEFI_DRIVER
>+ LIBRARY_CLASS = DxeServicesLib|DXE_CORE DXE_DRIVER
>DXE_RUNTIME_DRIVER DXE_SMM_DRIVER SMM_CORE UEFI_APPLICATION
>UEFI_DRIVER
>
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC ARM AARCH64
>+# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64
> #
>
> [Sources]
> DxeServicesLib.c
>
>-[Sources.IA32, Sources.IPF, Sources.EBC, Sources.ARM, Sources.AARCH64]
>+[Sources.IA32, Sources.EBC, Sources.ARM, Sources.AARCH64]
> Allocate.c
>
> [Sources.X64]
>diff --git a/MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
>b/MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
>index 8ad198c2f3..7a34716e4a 100644
>--- a/MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
>+++ b/MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
>@@ -23,12 +23,12 @@
> FILE_GUID = baa1baa3-0a8d-402c-8042-985115fae953
> MODULE_TYPE = DXE_DRIVER
> VERSION_STRING = 1.0
>- LIBRARY_CLASS = DxeServicesTableLib|DXE_DRIVER
>DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER
>UEFI_APPLICATION UEFI_DRIVER SMM_CORE
>+ LIBRARY_CLASS = DxeServicesTableLib|DXE_DRIVER
>DXE_RUNTIME_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER
>SMM_CORE
>
> CONSTRUCTOR = DxeServicesTableLibConstructor
>
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
>+# VALID_ARCHITECTURES = IA32 X64 EBC
> #
>
> [Sources]
>diff --git a/MdePkg/Library/DxeSmbusLib/DxeSmbusLib.inf
>b/MdePkg/Library/DxeSmbusLib/DxeSmbusLib.inf
>index d4f082ec4c..c8eca3d73d 100644
>--- a/MdePkg/Library/DxeSmbusLib/DxeSmbusLib.inf
>+++ b/MdePkg/Library/DxeSmbusLib/DxeSmbusLib.inf
>@@ -20,12 +20,12 @@
> FILE_GUID = 4F369FB1-31A7-423c-960E-B3EFD337894F
> MODULE_TYPE = DXE_DRIVER
> VERSION_STRING = 1.0
>- LIBRARY_CLASS = SmbusLib|DXE_DRIVER DXE_RUNTIME_DRIVER
>DXE_SAL_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER
>+ LIBRARY_CLASS = SmbusLib|DXE_DRIVER DXE_RUNTIME_DRIVER
>DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER
>
> CONSTRUCTOR = SmbusLibConstructor
>
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
>+# VALID_ARCHITECTURES = IA32 X64 EBC
> #
>
> [Sources]
>diff --git a/MdePkg/Library/DxeTimerLibEsal/DxeTimerLibEsal.c
>b/MdePkg/Library/DxeTimerLibEsal/DxeTimerLibEsal.c
>deleted file mode 100644
>index 8ca3ec6f8b..0000000000
>--- a/MdePkg/Library/DxeTimerLibEsal/DxeTimerLibEsal.c
>+++ /dev/null
>@@ -1,223 +0,0 @@
>-/** @file
>- This library implements the Timer Library using the Extended SAL Stall
>Services Class.
>-
>- Copyright (c) 2007 - 2011, Intel Corporation. All rights reserved.<BR>
>- This program and the accompanying materials
>- are licensed and made available under the terms and conditions of the BSD
>License
>- which accompanies this distribution. The full text of the license may be
>found at
>- http://opensource.org/licenses/bsd-license.php.
>-
>- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-
>-**/
>-
>-#include <PiDxe.h>
>-
>-#include <Protocol/ExtendedSalServiceClasses.h>
>-
>-#include <Library/TimerLib.h>
>-#include <Library/BaseLib.h>
>-#include <Library/ExtendedSalLib.h>
>-#include <Library/DebugLib.h>
>-#include <Library/PalLib.h>
>-
>-/**
>- Stalls the CPU for at least the given number of microseconds.
>-
>- This function wraps EsalStall function of Extended SAL Stall Services Class.
>- It stalls the CPU for the number of microseconds specified by MicroSeconds.
>-
>- @param MicroSeconds The minimum number of microseconds to delay.
>-
>- @return MicroSeconds
>-
>-**/
>-UINTN
>-EFIAPI
>-MicroSecondDelay (
>- IN UINTN MicroSeconds
>- )
>-{
>- EsalCall (
>- EFI_EXTENDED_SAL_STALL_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_STALL_SERVICES_PROTOCOL_GUID_HI,
>- StallFunctionId,
>- MicroSeconds,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0
>- );
>- return MicroSeconds;
>-}
>-
>-/**
>- Stalls the CPU for at least the given number of nanoseconds.
>-
>- This function wraps EsalStall function of Extended SAL Stall Services Class.
>- It stalls the CPU for the number of nanoseconds specified by NanoSeconds.
>-
>- @param NanoSeconds The minimum number of nanoseconds to delay.
>-
>- @return NanoSeconds
>-
>-**/
>-UINTN
>-EFIAPI
>-NanoSecondDelay (
>- IN UINTN NanoSeconds
>- )
>-{
>- UINT64 MicroSeconds;
>-
>- //
>- // The unit of ESAL Stall service is microsecond, so we turn the time interval
>- // from nanosecond to microsecond, using the ceiling value to ensure
>stalling
>- // at least the given number of nanoseconds.
>- //
>- MicroSeconds = DivU64x32 (NanoSeconds + 999, 1000);
>- EsalCall (
>- EFI_EXTENDED_SAL_STALL_SERVICES_PROTOCOL_GUID_LO,
>- EFI_EXTENDED_SAL_STALL_SERVICES_PROTOCOL_GUID_HI,
>- StallFunctionId,
>- MicroSeconds,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0,
>- 0
>- );
>- return NanoSeconds;
>-}
>-
>-/**
>- Retrieves the current value of a 64-bit free running performance counter.
>-
>- Retrieves the current value of a 64-bit free running performance counter.
>The
>- counter can either count up by 1 or count down by 1. If the physical
>- performance counter counts by a larger increment, then the counter values
>- must be translated. The properties of the counter can be retrieved from
>- GetPerformanceCounterProperties().
>-
>- @return The current value of the free running performance counter.
>-
>-**/
>-UINT64
>-EFIAPI
>-GetPerformanceCounter (
>- VOID
>- )
>-{
>- return AsmReadItc ();
>-}
>-
>-/**
>- Retrieves the 64-bit frequency in Hz and the range of performance counter
>- values.
>-
>- If StartValue is not NULL, then the value that the performance counter
>starts
>- with immediately after is it rolls over is returned in StartValue. If
>- EndValue is not NULL, then the value that the performance counter end
>with
>- immediately before it rolls over is returned in EndValue. The 64-bit
>- frequency of the performance counter in Hz is always returned. If
>StartValue
>- is less than EndValue, then the performance counter counts up. If
>StartValue
>- is greater than EndValue, then the performance counter counts down. For
>- example, a 64-bit free running counter that counts up would have a
>StartValue
>- of 0 and an EndValue of 0xFFFFFFFFFFFFFFFF. A 24-bit free running counter
>- that counts down would have a StartValue of 0xFFFFFF and an EndValue of 0.
>-
>- @param StartValue The value the performance counter starts with when it
>- rolls over.
>- @param EndValue The value that the performance counter ends with
>before
>- it rolls over.
>-
>- @return The frequency in Hz.
>-
>-**/
>-UINT64
>-EFIAPI
>-GetPerformanceCounterProperties (
>- OUT UINT64 *StartValue, OPTIONAL
>- OUT UINT64 *EndValue OPTIONAL
>- )
>-{
>- PAL_CALL_RETURN PalRet;
>- UINT64 BaseFrequence;
>-
>- //
>- // Get processor base frequency
>- //
>- PalRet = PalCall (PAL_FREQ_BASE, 0, 0, 0);
>- ASSERT (PalRet.Status == 0);
>- BaseFrequence = PalRet.r9;
>-
>- //
>- // Get processor frequency ratio
>- //
>- PalRet = PalCall (PAL_FREQ_RATIOS, 0, 0, 0);
>- ASSERT (PalRet.Status == 0);
>-
>- //
>- // Start value of counter is 0
>- //
>- if (StartValue != NULL) {
>- *StartValue = 0;
>- }
>-
>- //
>- // End value of counter is 0xFFFFFFFFFFFFFFFF
>- //
>- if (EndValue != NULL) {
>- *EndValue = (UINT64)(-1);
>- }
>-
>- return BaseFrequence * (PalRet.r11 >> 32) / (UINT32)PalRet.r11;
>-}
>-
>-/**
>- Converts elapsed ticks of performance counter to time in nanoseconds.
>-
>- This function converts the elapsed ticks of running performance counter to
>- time value in unit of nanoseconds.
>-
>- @param Ticks The number of elapsed ticks of running performance
>counter.
>-
>- @return The elapsed time in nanoseconds.
>-
>-**/
>-UINT64
>-EFIAPI
>-GetTimeInNanoSecond (
>- IN UINT64 Ticks
>- )
>-{
>- UINT64 Frequency;
>- UINT64 NanoSeconds;
>- UINT64 Remainder;
>- INTN Shift;
>-
>- Frequency = GetPerformanceCounterProperties (NULL, NULL);
>-
>- //
>- // Ticks
>- // Time = --------- x 1,000,000,000
>- // Frequency
>- //
>- NanoSeconds = MultU64x32 (DivU64x64Remainder (Ticks, Frequency,
>&Remainder), 1000000000u);
>-
>- //
>- // Ensure (Remainder * 1,000,000,000) will not overflow 64-bit.
>- // Since 2^29 < 1,000,000,000 = 0x3B9ACA00 < 2^30, Remainder should <
>2^(64-30) = 2^34,
>- // i.e. highest bit set in Remainder should <= 33.
>- //
>- Shift = MAX (0, HighBitSet64 (Remainder) - 33);
>- Remainder = RShiftU64 (Remainder, (UINTN) Shift);
>- Frequency = RShiftU64 (Frequency, (UINTN) Shift);
>- NanoSeconds += DivU64x64Remainder (MultU64x32 (Remainder,
>1000000000u), Frequency, NULL);
>-
>- return NanoSeconds;
>-}
>diff --git a/MdePkg/Library/DxeTimerLibEsal/DxeTimerLibEsal.inf
>b/MdePkg/Library/DxeTimerLibEsal/DxeTimerLibEsal.inf
>deleted file mode 100644
>index 0f24989ab9..0000000000
>--- a/MdePkg/Library/DxeTimerLibEsal/DxeTimerLibEsal.inf
>+++ /dev/null
>@@ -1,41 +0,0 @@
>-## @file
>-# This library implements the Timer Library using the Extended SAL Stall
>Services Class.
>-#
>-# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
>-#
>-# This program and the accompanying materials
>-# are licensed and made available under the terms and conditions of the BSD
>License
>-# which accompanies this distribution. The full text of the license may be
>found at
>-# http://opensource.org/licenses/bsd-license.php.
>-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-#
>-##
>-
>-[Defines]
>- INF_VERSION = 0x00010005
>- BASE_NAME = DxeTimerLibEsal
>- MODULE_UNI_FILE = DxeTimerLibEsal.uni
>- FILE_GUID = F672AE85-3769-4fb8-A5A0-70B38FB0A7C4
>- MODULE_TYPE = DXE_DRIVER
>- VERSION_STRING = 1.0
>- LIBRARY_CLASS = TimerLib|DXE_DRIVER DXE_RUNTIME_DRIVER
>DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
>-
>-#
>-# The following information is for reference only and not required by the
>build tools.
>-#
>-# VALID_ARCHITECTURES = IPF
>-#
>-
>-[Sources]
>- DxeTimerLibEsal.c
>-
>-[Packages]
>- MdePkg/MdePkg.dec
>-
>-[LibraryClasses]
>- DebugLib
>- ExtendedSalLib
>- BaseLib
>- PalLib
>-
>diff --git
>a/MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLibSegmentI
>nfo.inf
>b/MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLibSegmentI
>nfo.inf
>index 9cd60764dc..d18cc97e54 100644
>---
>a/MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLibSegmentI
>nfo.inf
>+++
>b/MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLibSegmentI
>nfo.inf
>@@ -28,7 +28,7 @@
> #
> # The following information is for reference only and not required by the
>build tools.
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
>+# VALID_ARCHITECTURES = IA32 X64 EBC
> #
>
> [Sources]
>diff --git
>a/MdePkg/Library/PciSegmentLibSegmentInfo/DxeRuntimePciSegmentLibSe
>gmentInfo.inf
>b/MdePkg/Library/PciSegmentLibSegmentInfo/DxeRuntimePciSegmentLibSe
>gmentInfo.inf
>index e484af5b06..21bc412f8c 100644
>---
>a/MdePkg/Library/PciSegmentLibSegmentInfo/DxeRuntimePciSegmentLibSe
>gmentInfo.inf
>+++
>b/MdePkg/Library/PciSegmentLibSegmentInfo/DxeRuntimePciSegmentLibSe
>gmentInfo.inf
>@@ -30,7 +30,7 @@
> #
> # The following information is for reference only and not required by the
>build tools.
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
>+# VALID_ARCHITECTURES = IA32 X64 EBC
> #
>
> [Sources]
>diff --git a/MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
>b/MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
>index d920306713..f04f388e96 100644
>--- a/MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
>+++ b/MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
>@@ -23,7 +23,7 @@
> LIBRARY_CLASS = PeiCoreEntryPoint|PEI_CORE
>
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC (EBC is for build only)
>+# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only)
> #
>
> [Sources]
>diff --git
>a/MdePkg/Library/PeiDxePostCodeLibReportStatusCode/PeiDxePostCodeLib
>ReportStatusCode.inf
>b/MdePkg/Library/PeiDxePostCodeLibReportStatusCode/PeiDxePostCodeLib
>ReportStatusCode.inf
>index dc162c2ddb..97013361df 100644
>---
>a/MdePkg/Library/PeiDxePostCodeLibReportStatusCode/PeiDxePostCodeLib
>ReportStatusCode.inf
>+++
>b/MdePkg/Library/PeiDxePostCodeLibReportStatusCode/PeiDxePostCodeLib
>ReportStatusCode.inf
>@@ -22,11 +22,11 @@
> FILE_GUID = e062c52d-78dc-4cc5-b246-b13497a8123c
> MODULE_TYPE = PEIM
> VERSION_STRING = 1.0
>- LIBRARY_CLASS = PostCodeLib|DXE_CORE DXE_DRIVER
>DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER PEIM PEI_CORE
>UEFI_APPLICATION UEFI_DRIVER
>+ LIBRARY_CLASS = PostCodeLib|DXE_CORE DXE_DRIVER
>DXE_RUNTIME_DRIVER DXE_SMM_DRIVER PEIM PEI_CORE
>UEFI_APPLICATION UEFI_DRIVER
>
>
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
>+# VALID_ARCHITECTURES = IA32 X64 EBC
> #
>
> [Sources]
>diff --git
>a/MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.in
>f
>b/MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.in
>f
>index 1b6e6a8680..9d47a8e5c1 100644
>---
>a/MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.in
>f
>+++
>b/MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.in
>f
>@@ -27,7 +27,7 @@
> #
> # The following information is for reference only and not required by the
>build tools.
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC (EBC is for build only)
>+# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only)
> #
>
> [Sources]
>diff --git a/MdePkg/Library/PeiHobLib/PeiHobLib.inf
>b/MdePkg/Library/PeiHobLib/PeiHobLib.inf
>index 027ba6f856..2817c113f6 100644
>--- a/MdePkg/Library/PeiHobLib/PeiHobLib.inf
>+++ b/MdePkg/Library/PeiHobLib/PeiHobLib.inf
>@@ -26,7 +26,7 @@
>
>
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC (EBC is for build only)
>+# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only)
> #
>
> [Sources]
>diff --git a/MdePkg/Library/PeiIoLibCpuIo/PeiIoLibCpuIo.inf
>b/MdePkg/Library/PeiIoLibCpuIo/PeiIoLibCpuIo.inf
>index d12418127e..c34b3760a7 100644
>--- a/MdePkg/Library/PeiIoLibCpuIo/PeiIoLibCpuIo.inf
>+++ b/MdePkg/Library/PeiIoLibCpuIo/PeiIoLibCpuIo.inf
>@@ -27,7 +27,7 @@
>
>
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC (EBC is for build only)
>+# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only)
> #
>
> [Sources]
>diff --git
>a/MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
>b/MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
>index db158135b8..ceac7a9ee1 100644
>--- a/MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
>+++ b/MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
>@@ -27,7 +27,7 @@
>
>
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC (EBC is for build only)
>+# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only)
> #
>
> [Sources]
>diff --git a/MdePkg/Library/PeiMemoryLib/PeiMemoryLib.inf
>b/MdePkg/Library/PeiMemoryLib/PeiMemoryLib.inf
>index 56d584dad6..68b8919001 100644
>--- a/MdePkg/Library/PeiMemoryLib/PeiMemoryLib.inf
>+++ b/MdePkg/Library/PeiMemoryLib/PeiMemoryLib.inf
>@@ -27,7 +27,7 @@
>
>
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC (EBC is for build only)
>+# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only)
> #
>
> [Sources]
>diff --git a/MdePkg/Library/PeiPalLib/PeiPalLib.c
>b/MdePkg/Library/PeiPalLib/PeiPalLib.c
>deleted file mode 100644
>index 8209e1d478..0000000000
>--- a/MdePkg/Library/PeiPalLib/PeiPalLib.c
>+++ /dev/null
>@@ -1,99 +0,0 @@
>-/** @file
>- PAL Call Services Function.
>-
>- Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
>- This program and the accompanying materials
>- are licensed and made available under the terms and conditions of the BSD
>License
>- which accompanies this distribution. The full text of the license may be
>found at
>- http://opensource.org/licenses/bsd-license.php.
>-
>- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-
>-**/
>-
>-
>-#include <PiPei.h>
>-
>-#include <Ppi/SecPlatformInformation.h>
>-
>-#include <Library/PalLib.h>
>-#include <Library/PeiServicesTablePointerLib.h>
>-#include <Library/PeiServicesLib.h>
>-#include <Library/BaseLib.h>
>-#include <Library/DebugLib.h>
>-
>-/**
>- Makes a PAL procedure call.
>-
>- This is a wrapper function to make a PAL procedure call. Based on the Index
>value,
>- this API will make static or stacked PAL call. Architected procedures may be
>designated
>- as required or optional. If a PAL procedure is specified as optional, a unique
>return
>- code of 0xFFFFFFFFFFFFFFFF is returned in the Status field of the
>PAL_CALL_RETURN structure.
>- This indicates that the procedure is not present in this PAL implementation.
>It is the
>- caller's responsibility to check for this return code after calling any optional
>PAL
>- procedure. No parameter checking is performed on the 4 input parameters,
>but there are
>- some common rules that the caller should follow when making a PAL call.
>Any address
>- passed to PAL as buffers for return parameters must be 8-byte aligned.
>Unaligned addresses
>- may cause undefined results. For those parameters defined as reserved or
>some fields
>- defined as reserved must be zero filled or the invalid argument return value
>may be
>- returned or undefined result may occur during the execution of the
>procedure.
>- This function is only available on IPF.
>-
>- @param Index The PAL procedure Index number.
>- @param Arg2 The 2nd parameter for PAL procedure calls.
>- @param Arg3 The 3rd parameter for PAL procedure calls.
>- @param Arg4 The 4th parameter for PAL procedure calls.
>-
>- @return Structure returned from the PAL Call procedure, including the
>status and return value.
>-
>-**/
>-PAL_CALL_RETURN
>-EFIAPI
>-PalCall (
>- IN UINT64 Index,
>- IN UINT64 Arg2,
>- IN UINT64 Arg3,
>- IN UINT64 Arg4
>- )
>-{
>- UINT64 PalCallAddress;
>- PAL_CALL_RETURN ReturnVal;
>- CONST EFI_PEI_SERVICES **PeiServices;
>- EFI_STATUS Status;
>- EFI_SEC_PLATFORM_INFORMATION_PPI *SecPlatformPpi;
>- EFI_SEC_PLATFORM_INFORMATION_RECORD SecPlatformInfoRecord;
>- UINT64 RecordSize;
>-
>- //
>- // Get PEI Service Table Pointer
>- //
>- PeiServices = GetPeiServicesTablePointer ();
>-
>- //
>- // Locate SEC Platform Information PPI
>- //
>- Status = PeiServicesLocatePpi (
>- &gEfiSecPlatformInformationPpiGuid,
>- 0,
>- NULL,
>- (VOID **)&SecPlatformPpi
>- );
>- ASSERT_EFI_ERROR (Status);
>-
>- //
>- // Retrieve PAL call address from platform information reported by the PPI
>- //
>- RecordSize = sizeof (SecPlatformInfoRecord);
>- SecPlatformPpi->PlatformInformation (
>- PeiServices,
>- &RecordSize,
>- &SecPlatformInfoRecord
>- );
>- PalCallAddress = SecPlatformInfoRecord.ItaniumHealthFlags.PalCallAddress;
>-
>- ReturnVal = AsmPalCall (PalCallAddress, Index, Arg2, Arg3, Arg4);
>-
>- return ReturnVal;
>-}
>-
>diff --git a/MdePkg/Library/PeiPalLib/PeiPalLib.inf
>b/MdePkg/Library/PeiPalLib/PeiPalLib.inf
>deleted file mode 100644
>index 6b49f6e502..0000000000
>--- a/MdePkg/Library/PeiPalLib/PeiPalLib.inf
>+++ /dev/null
>@@ -1,51 +0,0 @@
>-## @file
>-# Instance of PAL Library using a PPI for PAL entrypoint.
>-#
>-# Instance of PAL Library that uses a PPI to retrieve the PAL
>-# Entry Point and layers on top of AsmPalCall() in the Base Library
>-#
>-# Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
>-#
>-# This program and the accompanying materials
>-# are licensed and made available under the terms and conditions of the BSD
>License
>-# which accompanies this distribution. The full text of the license may be
>found at
>-# http://opensource.org/licenses/bsd-license.php.
>-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-#
>-#
>-##
>-
>-[Defines]
>- INF_VERSION = 0x00010005
>- BASE_NAME = PeiPalLib
>- MODULE_UNI_FILE = PeiPalLib.uni
>- FILE_GUID = B53DC524-6B98-4584-940B-8F1363DEF09E
>- MODULE_TYPE = PEIM
>- VERSION_STRING = 1.0
>- LIBRARY_CLASS = PalLib|PEIM SEC PEI_CORE
>-
>-
>-#
>-# The following information is for reference only and not required by the
>build tools.
>-#
>-# VALID_ARCHITECTURES = IPF
>-#
>-
>-[Sources]
>- PeiPalLib.c
>-
>-
>-[Packages]
>- MdePkg/MdePkg.dec
>-
>-
>-[LibraryClasses]
>- BaseLib
>- PeiServicesLib
>- PeiServicesTablePointerLib
>-
>-
>-[Ppis]
>- gEfiSecPlatformInformationPpiGuid ## CONSUMES
>-
>diff --git a/MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
>b/MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
>index 75786c1d4f..f2f1f593aa 100644
>--- a/MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
>+++ b/MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
>@@ -38,7 +38,7 @@
>
>
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC (EBC is for build only)
>+# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only)
> #
>
> [Sources]
>diff --git a/MdePkg/Library/PeiPciLibPciCfg2/PeiPciLibPciCfg2.inf
>b/MdePkg/Library/PeiPciLibPciCfg2/PeiPciLibPciCfg2.inf
>index 2a6168522f..12ef7fa7ae 100644
>--- a/MdePkg/Library/PeiPciLibPciCfg2/PeiPciLibPciCfg2.inf
>+++ b/MdePkg/Library/PeiPciLibPciCfg2/PeiPciLibPciCfg2.inf
>@@ -31,7 +31,7 @@
> #
> # The following information is for reference only and not required by the
>build tools.
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC (EBC is for build only)
>+# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only)
> #
>
> [Sources]
>diff --git
>a/MdePkg/Library/PeiPciSegmentLibPciCfg2/PeiPciSegmentLibPciCfg2.inf
>b/MdePkg/Library/PeiPciSegmentLibPciCfg2/PeiPciSegmentLibPciCfg2.inf
>index 3458bc6227..bce771a7c5 100644
>--- a/MdePkg/Library/PeiPciSegmentLibPciCfg2/PeiPciSegmentLibPciCfg2.inf
>+++ b/MdePkg/Library/PeiPciSegmentLibPciCfg2/PeiPciSegmentLibPciCfg2.inf
>@@ -30,7 +30,7 @@
> #
> # The following information is for reference only and not required by the
>build tools.
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC (EBC is for build only)
>+# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only)
> #
>
> [Sources]
>diff --git
>a/MdePkg/Library/PeiResourcePublicationLib/PeiResourcePublicationLib.inf
>b/MdePkg/Library/PeiResourcePublicationLib/PeiResourcePublicationLib.inf
>index b09f48b86a..435e96f9d9 100644
>---
>a/MdePkg/Library/PeiResourcePublicationLib/PeiResourcePublicationLib.inf
>+++
>b/MdePkg/Library/PeiResourcePublicationLib/PeiResourcePublicationLib.inf
>@@ -26,7 +26,7 @@
>
>
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC (EBC is for build only)
>+# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only)
> #
>
> [Sources]
>diff --git a/MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
>b/MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
>index ed992661d6..9990972e44 100644
>--- a/MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
>+++ b/MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
>@@ -24,7 +24,7 @@
> PI_SPECIFICATION_VERSION = 0x0001000A
>
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC (EBC is for build only)
>+# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only)
> #
>
> [Sources]
>diff --git
>a/MdePkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
>b/MdePkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
>index 5925f13937..6fb1770e04 100644
>---
>a/MdePkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
>+++
>b/MdePkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
>@@ -29,7 +29,7 @@
> CONSTRUCTOR = PeiServicesTablePointerLibConstructor
>
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC (EBC is for build only)
>+# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only)
> #
>
> [Sources]
>diff --git
>a/MdePkg/Library/PeiServicesTablePointerLibKr7/PeiServicesTablePointer.c
>b/MdePkg/Library/PeiServicesTablePointerLibKr7/PeiServicesTablePointer.c
>deleted file mode 100644
>index 66cf7bc471..0000000000
>---
>a/MdePkg/Library/PeiServicesTablePointerLibKr7/PeiServicesTablePointer.c
>+++ /dev/null
>@@ -1,91 +0,0 @@
>-/** @file
>- PEI Services Table Pointer Library implementation for IPF that uses Kernel
>- Register 7 to store the pointer.
>-
>- Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
>- This program and the accompanying materials
>- are licensed and made available under the terms and conditions of the BSD
>License
>- which accompanies this distribution. The full text of the license may be
>found at
>- http://opensource.org/licenses/bsd-license.php.
>-
>- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-
>-**/
>-
>-#include <PiPei.h>
>-#include <Library/BaseLib.h>
>-#include <Library/DebugLib.h>
>-
>-/**
>- Retrieves the cached value of the PEI Services Table pointer.
>-
>- Returns the cached value of the PEI Services Table pointer in a CPU specific
>manner
>- as specified in the CPU binding section of the Platform Initialization Pre-EFI
>- Initialization Core Interface Specification.
>-
>- If the cached PEI Services Table pointer is NULL, then ASSERT().
>-
>- @return The pointer to PeiServices.
>-
>-**/
>-CONST EFI_PEI_SERVICES **
>-EFIAPI
>-GetPeiServicesTablePointer (
>- VOID
>- )
>-{
>- CONST EFI_PEI_SERVICES **PeiServices;
>-
>- PeiServices = (CONST EFI_PEI_SERVICES **)(UINTN)AsmReadKr7 ();
>- ASSERT (PeiServices != NULL);
>- return PeiServices;
>-}
>-
>-
>-/**
>- Caches a pointer PEI Services Table.
>-
>- Caches the pointer to the PEI Services Table specified by
>PeiServicesTablePointer
>- in a CPU specific manner as specified in the CPU binding section of the
>Platform Initialization
>- Pre-EFI Initialization Core Interface Specification.
>- The function set the pointer of PEI services in KR7 register
>- according to PI specification.
>-
>- If PeiServicesTablePointer is NULL, then ASSERT().
>-
>- @param PeiServicesTablePointer The address of PeiServices pointer.
>-**/
>-VOID
>-EFIAPI
>-SetPeiServicesTablePointer (
>- IN CONST EFI_PEI_SERVICES ** PeiServicesTablePointer
>- )
>-{
>- ASSERT (PeiServicesTablePointer != NULL);
>- AsmWriteKr7 ((UINT64)(UINTN)PeiServicesTablePointer);
>-}
>-
>-/**
>- Perform CPU specific actions required to migrate the PEI Services Table
>- pointer from temporary RAM to permanent RAM.
>-
>- For IA32 CPUs, the PEI Services Table pointer is stored in the 4 bytes
>- immediately preceding the Interrupt Descriptor Table (IDT) in memory.
>- For X64 CPUs, the PEI Services Table pointer is stored in the 8 bytes
>- immediately preceding the Interrupt Descriptor Table (IDT) in memory.
>- For Itanium and ARM CPUs, a the PEI Services Table Pointer is stored in
>- a dedicated CPU register. This means that there is no memory storage
>- associated with storing the PEI Services Table pointer, so no additional
>- migration actions are required for Itanium or ARM CPUs.
>-
>-**/
>-VOID
>-EFIAPI
>-MigratePeiServicesTablePointer (
>- VOID
>- )
>-{
>- return;
>-}
>-
>diff --git
>a/MdePkg/Library/PeiServicesTablePointerLibKr7/PeiServicesTablePointerLib
>Kr7.inf
>b/MdePkg/Library/PeiServicesTablePointerLibKr7/PeiServicesTablePointerLib
>Kr7.inf
>deleted file mode 100644
>index ae38fc0046..0000000000
>---
>a/MdePkg/Library/PeiServicesTablePointerLibKr7/PeiServicesTablePointerLib
>Kr7.inf
>+++ /dev/null
>@@ -1,42 +0,0 @@
>-## @file
>-# Instance of PEI Services Table Pointer Library using KR7 for the table pointer.
>-#
>-# PEI Services Table Pointer Library implementation that retrieves a pointer
>to the PEI
>-# Services Table from KR7 on IPF.
>-#
>-# Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
>-#
>-# This program and the accompanying materials
>-# are licensed and made available under the terms and conditions of the BSD
>License
>-# which accompanies this distribution. The full text of the license may be
>found at
>-# http://opensource.org/licenses/bsd-license.php.
>-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-#
>-#
>-##
>-
>-[Defines]
>- INF_VERSION = 0x00010005
>- BASE_NAME = PeiServicesTablePointerLibKr7
>- MODULE_UNI_FILE = PeiServicesTablePointerLibKr7.uni
>- FILE_GUID = E0E7D776-E7EB-4e5f-9AA8-54CF3AA64A43
>- MODULE_TYPE = PEIM
>- VERSION_STRING = 1.0
>- LIBRARY_CLASS = PeiServicesTablePointerLib|SEC PEIM PEI_CORE
>-
>-
>-#
>-# VALID_ARCHITECTURES = IPF
>-#
>-
>-[Sources.Ipf]
>- PeiServicesTablePointer.c
>-
>-[Packages]
>- MdePkg/MdePkg.dec
>-
>-[LibraryClasses]
>- DebugLib
>- BaseLib
>-
>diff --git
>a/MdePkg/Library/PeiSmbusLibSmbus2Ppi/PeiSmbusLibSmbus2Ppi.inf
>b/MdePkg/Library/PeiSmbusLibSmbus2Ppi/PeiSmbusLibSmbus2Ppi.inf
>index cef8e03ad8..b50335a0fc 100644
>--- a/MdePkg/Library/PeiSmbusLibSmbus2Ppi/PeiSmbusLibSmbus2Ppi.inf
>+++ b/MdePkg/Library/PeiSmbusLibSmbus2Ppi/PeiSmbusLibSmbus2Ppi.inf
>@@ -24,7 +24,7 @@
>
>
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC (EBC is for build only)
>+# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only)
> #
>
> [Sources]
>diff --git a/MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
>b/MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
>index a2db9e058b..b36a5f2ba5 100644
>--- a/MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
>+++ b/MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
>@@ -23,7 +23,7 @@
> LIBRARY_CLASS = PeimEntryPoint|PEIM
>
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC (EBC is for build only)
>+# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only)
> #
>
> [Sources]
>diff --git a/MdePkg/Library/SecPeiDxeTimerLibCpu/IpfTimerLib.c
>b/MdePkg/Library/SecPeiDxeTimerLibCpu/IpfTimerLib.c
>deleted file mode 100644
>index 714b99eec4..0000000000
>--- a/MdePkg/Library/SecPeiDxeTimerLibCpu/IpfTimerLib.c
>+++ /dev/null
>@@ -1,216 +0,0 @@
>-/** @file
>- Timer Library functions built upon ITC on IPF.
>-
>- Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
>- This program and the accompanying materials
>- are licensed and made available under the terms and conditions of the BSD
>License
>- which accompanies this distribution. The full text of the license may be
>found at
>- http://opensource.org/licenses/bsd-license.php.
>-
>- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-
>-**/
>-
>-#include <Base.h>
>-#include <Library/TimerLib.h>
>-#include <Library/BaseLib.h>
>-#include <Library/PalLib.h>
>-
>-
>-/**
>- Performs a delay measured as number of ticks.
>-
>- An internal function to perform a delay measured as number of ticks. It's
>- invoked by MicroSecondDelay() and NanoSecondDelay().
>-
>- @param Delay The number of ticks to delay.
>-
>-**/
>-VOID
>-EFIAPI
>-InternalIpfDelay (
>- IN INT64 Delay
>- )
>-{
>- INT64 Ticks;
>-
>- //
>- // The target timer count is calculated here
>- //
>- Ticks = (INT64)AsmReadItc () + Delay;
>-
>- //
>- // Wait until time out
>- // Delay > 2^63 could not be handled by this function
>- // Timer wrap-arounds are handled correctly by this function
>- //
>- while (Ticks - (INT64)AsmReadItc() >= 0);
>-}
>-
>-/**
>- Stalls the CPU for at least the given number of microseconds.
>-
>- Stalls the CPU for the number of microseconds specified by MicroSeconds.
>-
>- @param MicroSeconds The minimum number of microseconds to delay.
>-
>- @return The value of MicroSeconds inputted.
>-
>-**/
>-UINTN
>-EFIAPI
>-MicroSecondDelay (
>- IN UINTN MicroSeconds
>- )
>-{
>- InternalIpfDelay (
>- GetPerformanceCounterProperties (NULL, NULL) *
>- MicroSeconds /
>- 1000000
>- );
>- return MicroSeconds;
>-}
>-
>-/**
>- Stalls the CPU for at least the given number of nanoseconds.
>-
>- Stalls the CPU for the number of nanoseconds specified by NanoSeconds.
>-
>- @param NanoSeconds The minimum number of nanoseconds to delay.
>-
>- @return The value of NanoSeconds inputted.
>-
>-**/
>-UINTN
>-EFIAPI
>-NanoSecondDelay (
>- IN UINTN NanoSeconds
>- )
>-{
>- InternalIpfDelay (
>- GetPerformanceCounterProperties (NULL, NULL) *
>- NanoSeconds /
>- 1000000000
>- );
>- return NanoSeconds;
>-}
>-
>-/**
>- Retrieves the current value of a 64-bit free running performance counter.
>-
>- The counter can either count up by 1 or count down by 1. If the physical
>- performance counter counts by a larger increment, then the counter values
>- must be translated. The properties of the counter can be retrieved from
>- GetPerformanceCounterProperties().
>-
>- @return The current value of the free running performance counter.
>-
>-**/
>-UINT64
>-EFIAPI
>-GetPerformanceCounter (
>- VOID
>- )
>-{
>- return AsmReadItc ();
>-}
>-
>-/**
>- Retrieves the 64-bit frequency in Hz and the range of performance counter
>- values.
>-
>- If StartValue is not NULL, then the value that the performance counter
>starts
>- with immediately after is it rolls over is returned in StartValue. If
>- EndValue is not NULL, then the value that the performance counter end
>with
>- immediately before it rolls over is returned in EndValue. The 64-bit
>- frequency of the performance counter in Hz is always returned. If
>StartValue
>- is less than EndValue, then the performance counter counts up. If
>StartValue
>- is greater than EndValue, then the performance counter counts down. For
>- example, a 64-bit free running counter that counts up would have a
>StartValue
>- of 0 and an EndValue of 0xFFFFFFFFFFFFFFFF. A 24-bit free running counter
>- that counts down would have a StartValue of 0xFFFFFF and an EndValue of 0.
>-
>- @param StartValue The value the performance counter starts with when it
>- rolls over.
>- @param EndValue The value that the performance counter ends with
>before
>- it rolls over.
>-
>- @return The frequency in Hz.
>-
>-**/
>-UINT64
>-EFIAPI
>-GetPerformanceCounterProperties (
>- OUT UINT64 *StartValue, OPTIONAL
>- OUT UINT64 *EndValue OPTIONAL
>- )
>-{
>- PAL_CALL_RETURN PalRet;
>- UINT64 BaseFrequence;
>-
>- if (StartValue != NULL) {
>- *StartValue = 0;
>- }
>-
>- if (EndValue != NULL) {
>- *EndValue = (UINT64)(-1);
>- }
>-
>- PalRet = PalCall (PAL_FREQ_BASE, 0, 0, 0);
>- if (PalRet.Status != 0) {
>- return 1000000;
>- }
>- BaseFrequence = PalRet.r9;
>-
>- PalRet = PalCall (PAL_FREQ_RATIOS, 0, 0, 0);
>- if (PalRet.Status != 0) {
>- return 1000000;
>- }
>-
>- return BaseFrequence * (PalRet.r11 >> 32) / (UINT32)PalRet.r11;
>-}
>-
>-/**
>- Converts elapsed ticks of performance counter to time in nanoseconds.
>-
>- This function converts the elapsed ticks of running performance counter to
>- time value in unit of nanoseconds.
>-
>- @param Ticks The number of elapsed ticks of running performance
>counter.
>-
>- @return The elapsed time in nanoseconds.
>-
>-**/
>-UINT64
>-EFIAPI
>-GetTimeInNanoSecond (
>- IN UINT64 Ticks
>- )
>-{
>- UINT64 Frequency;
>- UINT64 NanoSeconds;
>- UINT64 Remainder;
>- INTN Shift;
>-
>- Frequency = GetPerformanceCounterProperties (NULL, NULL);
>-
>- //
>- // Ticks
>- // Time = --------- x 1,000,000,000
>- // Frequency
>- //
>- NanoSeconds = MultU64x32 (DivU64x64Remainder (Ticks, Frequency,
>&Remainder), 1000000000u);
>-
>- //
>- // Ensure (Remainder * 1,000,000,000) will not overflow 64-bit.
>- // Since 2^29 < 1,000,000,000 = 0x3B9ACA00 < 2^30, Remainder should <
>2^(64-30) = 2^34,
>- // i.e. highest bit set in Remainder should <= 33.
>- //
>- Shift = MAX (0, HighBitSet64 (Remainder) - 33);
>- Remainder = RShiftU64 (Remainder, (UINTN) Shift);
>- Frequency = RShiftU64 (Frequency, (UINTN) Shift);
>- NanoSeconds += DivU64x64Remainder (MultU64x32 (Remainder,
>1000000000u), Frequency, NULL);
>-
>- return NanoSeconds;
>-}
>diff --git a/MdePkg/Library/SecPeiDxeTimerLibCpu/SecPeiDxeTimerLibCpu.inf
>b/MdePkg/Library/SecPeiDxeTimerLibCpu/SecPeiDxeTimerLibCpu.inf
>index a00ebb0eeb..780ef9d9b7 100644
>--- a/MdePkg/Library/SecPeiDxeTimerLibCpu/SecPeiDxeTimerLibCpu.inf
>+++ b/MdePkg/Library/SecPeiDxeTimerLibCpu/SecPeiDxeTimerLibCpu.inf
>@@ -36,16 +36,12 @@
>
>
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF
>+# VALID_ARCHITECTURES = IA32 X64
> #
>
> [Sources.Ia32, Sources.X64]
> X86TimerLib.c
>
>-[Sources.IPF]
>- IpfTimerLib.c
>-
>-
> [Packages]
> MdePkg/MdePkg.dec
>
>@@ -58,10 +54,6 @@
> IoLib
> DebugLib
>
>-[LibraryClasses.IPF]
>- PalLib
>-
>-
> [Pcd.IA32, Pcd.X64]
> gEfiMdePkgTokenSpaceGuid.PcdFSBClock ## CONSUMES
>
>diff --git
>a/MdePkg/Library/SmiHandlerProfileLibNull/SmiHandlerProfileLibNull.inf
>b/MdePkg/Library/SmiHandlerProfileLibNull/SmiHandlerProfileLibNull.inf
>index 82208345ee..f5dfd307e6 100644
>--- a/MdePkg/Library/SmiHandlerProfileLibNull/SmiHandlerProfileLibNull.inf
>+++ b/MdePkg/Library/SmiHandlerProfileLibNull/SmiHandlerProfileLibNull.inf
>@@ -25,7 +25,7 @@
> #
> # The following information is for reference only and not required by the
>build tools.
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
>+# VALID_ARCHITECTURES = IA32 X64 EBC
> #
>
> [Sources]
>diff --git a/MdePkg/Library/SmmLibNull/SmmLibNull.inf
>b/MdePkg/Library/SmmLibNull/SmmLibNull.inf
>index 597b884df2..cd905d5e38 100644
>--- a/MdePkg/Library/SmmLibNull/SmmLibNull.inf
>+++ b/MdePkg/Library/SmmLibNull/SmmLibNull.inf
>@@ -25,7 +25,7 @@
> #
> # The following information is for reference only and not required by the
>build tools.
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
>+# VALID_ARCHITECTURES = IA32 X64 EBC
> #
>
> [Sources]
>diff --git
>a/MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
>b/MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
>index be92b3dc07..087607606f 100644
>---
>a/MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
>+++
>b/MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
>@@ -23,7 +23,7 @@
> LIBRARY_CLASS = UefiApplicationEntryPoint|UEFI_APPLICATION
>
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
>+# VALID_ARCHITECTURES = IA32 X64 EBC
> #
>
> [Sources]
>diff --git
>a/MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
>b/MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
>index 22a2d634fe..7c2e24fe58 100644
>--- a/MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
>+++
>b/MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
>@@ -20,12 +20,12 @@
> FILE_GUID = ff5c7a2c-ab7a-4366-8616-11c6e53247b6
> MODULE_TYPE = UEFI_DRIVER
> VERSION_STRING = 1.0
>- LIBRARY_CLASS = UefiBootServicesTableLib|DXE_CORE
>DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER
>UEFI_APPLICATION UEFI_DRIVER SMM_CORE
>+ LIBRARY_CLASS = UefiBootServicesTableLib|DXE_CORE
>DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION
>UEFI_DRIVER SMM_CORE
>
> CONSTRUCTOR = UefiBootServicesTableLibConstructor
>
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
>+# VALID_ARCHITECTURES = IA32 X64 EBC
> #
>
> [Sources]
>diff --git a/MdePkg/Library/UefiDebugLibConOut/UefiDebugLibConOut.inf
>b/MdePkg/Library/UefiDebugLibConOut/UefiDebugLibConOut.inf
>index 583872f54e..fc5635b6c9 100644
>--- a/MdePkg/Library/UefiDebugLibConOut/UefiDebugLibConOut.inf
>+++ b/MdePkg/Library/UefiDebugLibConOut/UefiDebugLibConOut.inf
>@@ -22,11 +22,11 @@
> FILE_GUID = 5cddfaf3-e9a7-4d16-bdce-1e002df475bb
> MODULE_TYPE = UEFI_DRIVER
> VERSION_STRING = 1.0
>- LIBRARY_CLASS = DebugLib|DXE_CORE DXE_DRIVER
>DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER
>UEFI_APPLICATION UEFI_DRIVER
>+ LIBRARY_CLASS = DebugLib|DXE_CORE DXE_DRIVER
>DXE_RUNTIME_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER
>
>
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
>+# VALID_ARCHITECTURES = IA32 X64 EBC
> #
>
>
>diff --git
>a/MdePkg/Library/UefiDebugLibDebugPortProtocol/UefiDebugLibDebugPort
>Protocol.inf
>b/MdePkg/Library/UefiDebugLibDebugPortProtocol/UefiDebugLibDebugPort
>Protocol.inf
>index 0f18c27a11..9d9f9f372f 100644
>---
>a/MdePkg/Library/UefiDebugLibDebugPortProtocol/UefiDebugLibDebugPort
>Protocol.inf
>+++
>b/MdePkg/Library/UefiDebugLibDebugPortProtocol/UefiDebugLibDebugPort
>Protocol.inf
>@@ -22,11 +22,11 @@
> FILE_GUID = 102287b4-6b12-4D41-91e1-ebee1f3aa614
> MODULE_TYPE = UEFI_DRIVER
> VERSION_STRING = 1.0
>- LIBRARY_CLASS = DebugLib|DXE_CORE DXE_DRIVER
>DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER
>UEFI_APPLICATION UEFI_DRIVER
>+ LIBRARY_CLASS = DebugLib|DXE_CORE DXE_DRIVER
>DXE_RUNTIME_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER
>
>
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
>+# VALID_ARCHITECTURES = IA32 X64 EBC
> #
>
>
>diff --git a/MdePkg/Library/UefiDebugLibStdErr/UefiDebugLibStdErr.inf
>b/MdePkg/Library/UefiDebugLibStdErr/UefiDebugLibStdErr.inf
>index 196487cf8c..7d8efea98e 100644
>--- a/MdePkg/Library/UefiDebugLibStdErr/UefiDebugLibStdErr.inf
>+++ b/MdePkg/Library/UefiDebugLibStdErr/UefiDebugLibStdErr.inf
>@@ -22,11 +22,11 @@
> FILE_GUID = b57a1df6-ffdb-4247-a3df-3a562176751a
> MODULE_TYPE = UEFI_DRIVER
> VERSION_STRING = 1.0
>- LIBRARY_CLASS = DebugLib|DXE_CORE DXE_DRIVER
>DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER
>UEFI_APPLICATION UEFI_DRIVER
>+ LIBRARY_CLASS = DebugLib|DXE_CORE DXE_DRIVER
>DXE_RUNTIME_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER
>
>
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
>+# VALID_ARCHITECTURES = IA32 X64 EBC
> #
>
> [Sources]
>diff --git a/MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
>b/MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
>index c76275b9d7..ea1af21d0b 100644
>--- a/MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
>+++ b/MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
>@@ -22,11 +22,11 @@
> FILE_GUID = 91c1677a-e57f-4191-8b8e-eb7711a716e0
> MODULE_TYPE = UEFI_DRIVER
> VERSION_STRING = 1.0
>- LIBRARY_CLASS = DevicePathLib|DXE_CORE DXE_DRIVER
>DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER
>UEFI_APPLICATION UEFI_DRIVER SMM_CORE
>+ LIBRARY_CLASS = DevicePathLib|DXE_CORE DXE_DRIVER
>DXE_RUNTIME_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER
>SMM_CORE
>
>
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
>+# VALID_ARCHITECTURES = IA32 X64 EBC
> #
>
> [Sources]
>diff --git
>a/MdePkg/Library/UefiDevicePathLib/UefiDevicePathLibOptionalDevicePathP
>rotocol.inf
>b/MdePkg/Library/UefiDevicePathLib/UefiDevicePathLibOptionalDevicePath
>Protocol.inf
>index 9e3029cd1c..50006f0095 100644
>---
>a/MdePkg/Library/UefiDevicePathLib/UefiDevicePathLibOptionalDevicePathP
>rotocol.inf
>+++
>b/MdePkg/Library/UefiDevicePathLib/UefiDevicePathLibOptionalDevicePath
>Protocol.inf
>@@ -24,12 +24,12 @@
> FILE_GUID = 3E1C696D-FCF0-45a7-85A7-E86C2A1C1080
> MODULE_TYPE = UEFI_DRIVER
> VERSION_STRING = 1.0
>- LIBRARY_CLASS = DevicePathLib|DXE_DRIVER
>DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER
>UEFI_APPLICATION UEFI_DRIVER SMM_CORE
>+ LIBRARY_CLASS = DevicePathLib|DXE_DRIVER
>DXE_RUNTIME_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER
>SMM_CORE
>
> CONSTRUCTOR =
>UefiDevicePathLibOptionalDevicePathProtocolConstructor
>
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
>+# VALID_ARCHITECTURES = IA32 X64 EBC
> #
>
> [Sources]
>@@ -86,4 +86,4 @@
>
> [Depex.common.DXE_DRIVER, Depex.common.DXE_RUNTIME_DRIVER,
>Depex.common.DXE_SAL_DRIVER, Depex.common.DXE_SMM_DRIVER]
> gEfiDevicePathUtilitiesProtocolGuid
>-
>\ No newline at end of file
>+
>diff --git
>a/MdePkg/Library/UefiDevicePathLibDevicePathProtocol/UefiDevicePathLibD
>evicePathProtocol.inf
>b/MdePkg/Library/UefiDevicePathLibDevicePathProtocol/UefiDevicePathLib
>DevicePathProtocol.inf
>index 5cab72ebfe..a365a527a1 100644
>---
>a/MdePkg/Library/UefiDevicePathLibDevicePathProtocol/UefiDevicePathLibD
>evicePathProtocol.inf
>+++
>b/MdePkg/Library/UefiDevicePathLibDevicePathProtocol/UefiDevicePathLib
>DevicePathProtocol.inf
>@@ -23,12 +23,12 @@
> FILE_GUID = 050EB8C6-C12E-4b86-892B-40985E8B3137
> MODULE_TYPE = UEFI_DRIVER
> VERSION_STRING = 1.0
>- LIBRARY_CLASS = DevicePathLib|DXE_DRIVER
>DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER
>UEFI_APPLICATION UEFI_DRIVER SMM_CORE
>+ LIBRARY_CLASS = DevicePathLib|DXE_DRIVER
>DXE_RUNTIME_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER
>SMM_CORE
>
> CONSTRUCTOR = DevicePathLibConstructor
>
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
>+# VALID_ARCHITECTURES = IA32 X64 EBC
> #
>
> [Sources]
>diff --git a/MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
>b/MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
>index 7a9dcbcd4d..0be4a2721f 100644
>--- a/MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
>+++ b/MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
>@@ -20,12 +20,12 @@
> FILE_GUID = 331deb15-454b-48d8-9b74-70d01f3f3556
> MODULE_TYPE = UEFI_DRIVER
> VERSION_STRING = 1.0
>- LIBRARY_CLASS = UefiDriverEntryPoint|DXE_DRIVER
>DXE_RUNTIME_DRIVER DXE_SAL_DRIVER UEFI_DRIVER SMM_CORE
>DXE_SMM_DRIVER
>+ LIBRARY_CLASS = UefiDriverEntryPoint|DXE_DRIVER
>DXE_RUNTIME_DRIVER UEFI_DRIVER SMM_CORE DXE_SMM_DRIVER
>
> #
> # The following information is for reference only and not required by the
>build tools.
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
>+# VALID_ARCHITECTURES = IA32 X64 EBC
> #
>
> [Sources]
>diff --git a/MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
>b/MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
>index 811d769ae9..5b6b488db6 100644
>--- a/MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
>+++ b/MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
>@@ -21,7 +21,7 @@
> LIBRARY_CLASS = FileHandleLib|DXE_DRIVER UEFI_APPLICATION
>UEFI_DRIVER DXE_RUNTIME_DRIVER
>
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
>+# VALID_ARCHITECTURES = IA32 X64 EBC
> #
>
> [Sources.common]
>diff --git a/MdePkg/Library/UefiLib/UefiLib.inf
>b/MdePkg/Library/UefiLib/UefiLib.inf
>index 8284dc58af..74f4b31e6e 100644
>--- a/MdePkg/Library/UefiLib/UefiLib.inf
>+++ b/MdePkg/Library/UefiLib/UefiLib.inf
>@@ -26,12 +26,12 @@
> FILE_GUID = 3a004ba5-efe0-4a61-9f1a-267a46ae5ba9
> MODULE_TYPE = UEFI_DRIVER
> VERSION_STRING = 1.0
>- LIBRARY_CLASS = UefiLib|DXE_CORE DXE_DRIVER
>DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER
>UEFI_APPLICATION UEFI_DRIVER SMM_CORE
>+ LIBRARY_CLASS = UefiLib|DXE_CORE DXE_DRIVER
>DXE_RUNTIME_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER
>SMM_CORE
> CONSTRUCTOR = UefiLibConstructor
>
>
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
>+# VALID_ARCHITECTURES = IA32 X64 EBC
> #
>
> [Sources]
>diff --git
>a/MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
>b/MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
>index e5936ed40a..ea287ab63d 100644
>--- a/MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
>+++
>b/MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
>@@ -23,10 +23,10 @@
> FILE_GUID = 4674739d-3195-4fb2-8094-ac1d22d00194
> MODULE_TYPE = UEFI_DRIVER
> VERSION_STRING = 1.0
>- LIBRARY_CLASS = MemoryAllocationLib|DXE_DRIVER
>DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER
>UEFI_APPLICATION UEFI_DRIVER
>+ LIBRARY_CLASS = MemoryAllocationLib|DXE_DRIVER
>DXE_RUNTIME_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER
>
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
>+# VALID_ARCHITECTURES = IA32 X64 EBC
> #
>
> [Sources]
>diff --git a/MdePkg/Library/UefiMemoryLib/UefiMemoryLib.inf
>b/MdePkg/Library/UefiMemoryLib/UefiMemoryLib.inf
>index 7382204f63..abac73fa15 100644
>--- a/MdePkg/Library/UefiMemoryLib/UefiMemoryLib.inf
>+++ b/MdePkg/Library/UefiMemoryLib/UefiMemoryLib.inf
>@@ -23,11 +23,11 @@
> FILE_GUID = f1bbe03d-2f28-4dee-bec7-d98d7a30c36a
> MODULE_TYPE = UEFI_DRIVER
> VERSION_STRING = 1.0
>- LIBRARY_CLASS = BaseMemoryLib|DXE_DRIVER
>DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER
>UEFI_APPLICATION UEFI_DRIVER
>+ LIBRARY_CLASS = BaseMemoryLib|DXE_DRIVER
>DXE_RUNTIME_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER
>
>
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
>+# VALID_ARCHITECTURES = IA32 X64 EBC
> #
>
> [Sources]
>diff --git a/MdePkg/Library/UefiPalLib/UefiPalLib.c
>b/MdePkg/Library/UefiPalLib/UefiPalLib.c
>deleted file mode 100644
>index df52a9125f..0000000000
>--- a/MdePkg/Library/UefiPalLib/UefiPalLib.c
>+++ /dev/null
>@@ -1,127 +0,0 @@
>-/** @file
>- PAL Library implementation retrieving the PAL Entry Point from the SAL
>System Table
>- register in the EFI System Confguration Table.
>-
>- Copyright (c) 2007 - 2008, Intel Corporation. All rights reserved.<BR>
>- This program and the accompanying materials are
>- licensed and made available under the terms and conditions of
>- the BSD License which accompanies this distribution. The full
>- text of the license may be found at
>- http://opensource.org/licenses/bsd-license.php.
>-
>- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-
>-**/
>-
>-#include <PiDxe.h>
>-
>-#include <IndustryStandard/Sal.h>
>-#include <Library/UefiLib.h>
>-#include <Library/BaseLib.h>
>-#include <Library/DebugLib.h>
>-
>-#include <Guid/SalSystemTable.h>
>-
>-UINT64 mPalProcEntry;
>-
>-/**
>- Makes a PAL procedure call.
>-
>- This is a wrapper function to make a PAL procedure call. Based on the Index
>value,
>- this API will make static or stacked PAL call. Architected procedures may be
>designated
>- as required or optional. If a PAL procedure is specified as optional, a unique
>return
>- code of 0xFFFFFFFFFFFFFFFF is returned in the Status field of the
>PAL_CALL_RETURN structure.
>- This indicates that the procedure is not present in this PAL implementation.
>It is the
>- caller's responsibility to check for this return code after calling any optional
>PAL
>- procedure. No parameter checking is performed on the 4 input parameters,
>but there are
>- some common rules that the caller should follow when making a PAL call.
>Any address
>- passed to PAL as buffers for return parameters must be 8-byte aligned.
>Unaligned addresses
>- may cause undefined results. For those parameters defined as reserved or
>some fields
>- defined as reserved must be zero filled or the invalid argument return value
>may be
>- returned or undefined result may occur during the execution of the
>procedure.
>- This function is only available on IPF.
>-
>- @param Index The PAL procedure Index number.
>- @param Arg2 The 2nd parameter for PAL procedure calls.
>- @param Arg3 The 3rd parameter for PAL procedure calls.
>- @param Arg4 The 4th parameter for PAL procedure calls.
>-
>- @return Structure returned from the PAL Call procedure, including the
>status and return value.
>-
>-**/
>-PAL_CALL_RETURN
>-EFIAPI
>-PalCall (
>- IN UINT64 Index,
>- IN UINT64 Arg2,
>- IN UINT64 Arg3,
>- IN UINT64 Arg4
>- )
>-{
>- //
>- // mPalProcEntry is initialized in library constructor as PAL entry.
>- //
>- return AsmPalCall (
>- mPalProcEntry,
>- Index,
>- Arg2,
>- Arg3,
>- Arg4
>- );
>-
>-}
>-
>-/**
>- The constructor function of UEFI Pal Lib.
>-
>- The constructor function looks up the SAL System Table in the EFI System
>Configuration
>- Table. Once the SAL System Table is found, the PAL Entry Point in the SAL
>System Table
>- will be derived and stored into a global variable for library usage.
>- It will ASSERT() if the SAL System Table cannot be found or the data in the
>SAL System
>- Table is not the valid data.
>-
>- @param ImageHandle The firmware allocated handle for the EFI image.
>- @param SystemTable A pointer to the EFI System Table.
>-
>- @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.
>-
>-**/
>-EFI_STATUS
>-EFIAPI
>-UefiPalLibConstructor (
>- IN EFI_HANDLE ImageHandle,
>- IN EFI_SYSTEM_TABLE *SystemTable
>- )
>-{
>- EFI_STATUS Status;
>- SAL_ST_ENTRY_POINT_DESCRIPTOR *SalStEntryDes;
>- SAL_SYSTEM_TABLE_HEADER *SalSystemTable;
>-
>- Status = EfiGetSystemConfigurationTable (
>- &gEfiSalSystemTableGuid,
>- (VOID **) &SalSystemTable
>- );
>- ASSERT_EFI_ERROR (Status);
>- ASSERT (SalSystemTable != NULL);
>-
>- //
>- // Check the first entry of SAL System Table,
>- // because the SAL entry is in ascending order with the entry type,
>- // the type 0 entry should be the first if exist.
>- //
>- SalStEntryDes = (SAL_ST_ENTRY_POINT_DESCRIPTOR *)(SalSystemTable +
>1);
>-
>- //
>- // Assure the SAL ENTRY Type is 0
>- //
>- ASSERT (SalStEntryDes->Type == EFI_SAL_ST_ENTRY_POINT);
>-
>- mPalProcEntry = SalStEntryDes->PalProcEntry;
>- //
>- // Make sure the PalCallAddress has the valid value
>- //
>- ASSERT (mPalProcEntry != 0);
>-
>- return EFI_SUCCESS;
>-}
>diff --git a/MdePkg/Library/UefiPalLib/UefiPalLib.inf
>b/MdePkg/Library/UefiPalLib/UefiPalLib.inf
>deleted file mode 100644
>index 914c75128d..0000000000
>--- a/MdePkg/Library/UefiPalLib/UefiPalLib.inf
>+++ /dev/null
>@@ -1,49 +0,0 @@
>-## @file
>-# UEFI Instance of PAL Library Class.
>-#
>-# This instance of PAL library retrieves the PAL Entry Point from the SAL
>System Table
>-# register in the EFI System Confguration Table.
>-#
>-# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
>-#
>-# This program and the accompanying materials
>-# are licensed and made available under the terms and conditions of the BSD
>License
>-# which accompanies this distribution. The full text of the license may be
>found at
>-# http://opensource.org/licenses/bsd-license.php.
>-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-#
>-#
>-##
>-
>-[Defines]
>- INF_VERSION = 0x00010005
>- BASE_NAME = UefiPalLib
>- MODULE_UNI_FILE = UefiPalLib.uni
>- FILE_GUID = B7F30170-9E5F-482a-B553-A145A5787003
>- MODULE_TYPE = UEFI_DRIVER
>- VERSION_STRING = 1.0
>- LIBRARY_CLASS = PalLib|UEFI_DRIVER UEFI_APPLICATION
>-
>- CONSTRUCTOR = UefiPalLibConstructor
>-
>-#
>-# The following information is for reference only and not required by the
>build tools.
>-#
>-# VALID_ARCHITECTURES = IPF
>-#
>-
>-[Sources]
>- UefiPalLib.c
>-
>-[Packages]
>- MdePkg/MdePkg.dec
>-
>-[LibraryClasses]
>- UefiLib
>- BaseLib
>- DebugLib
>-
>-[Guids]
>- gEfiSalSystemTableGuid ## CONSUMES ## SystemTable
>-
>diff --git
>a/MdePkg/Library/UefiPciLibPciRootBridgeIo/UefiPciLibPciRootBridgeIo.inf
>b/MdePkg/Library/UefiPciLibPciRootBridgeIo/UefiPciLibPciRootBridgeIo.inf
>index b741d1b317..be917356a2 100644
>--- a/MdePkg/Library/UefiPciLibPciRootBridgeIo/UefiPciLibPciRootBridgeIo.inf
>+++
>b/MdePkg/Library/UefiPciLibPciRootBridgeIo/UefiPciLibPciRootBridgeIo.inf
>@@ -26,14 +26,14 @@
> FILE_GUID = 90EC42CB-B780-4eb8-8E99-C8E3E5F37530
> MODULE_TYPE = UEFI_DRIVER
> VERSION_STRING = 1.0
>- LIBRARY_CLASS = PciLib|DXE_DRIVER DXE_RUNTIME_DRIVER
>DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
>+ LIBRARY_CLASS = PciLib|DXE_DRIVER DXE_RUNTIME_DRIVER
>DXE_SMM_DRIVER UEFI_DRIVER UEFI_APPLICATION
>
> CONSTRUCTOR = PciLibConstructor
>
> #
> # The following information is for reference only and not required by the
>build tools.
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
>+# VALID_ARCHITECTURES = IA32 X64 EBC
> #
>
> [Sources]
>diff --git
>a/MdePkg/Library/UefiPciSegmentLibPciRootBridgeIo/UefiPciSegmentLibPciR
>ootBridgeIo.inf
>b/MdePkg/Library/UefiPciSegmentLibPciRootBridgeIo/UefiPciSegmentLibPciR
>ootBridgeIo.inf
>index 12f465ba9e..9a90476f07 100644
>---
>a/MdePkg/Library/UefiPciSegmentLibPciRootBridgeIo/UefiPciSegmentLibPciR
>ootBridgeIo.inf
>+++
>b/MdePkg/Library/UefiPciSegmentLibPciRootBridgeIo/UefiPciSegmentLibPciR
>ootBridgeIo.inf
>@@ -26,7 +26,7 @@
> FILE_GUID = C6068612-B6E0-48a3-BB92-60E4A4F89EDF
> MODULE_TYPE = UEFI_DRIVER
> VERSION_STRING = 1.0
>- LIBRARY_CLASS = PciSegmentLib|DXE_DRIVER
>DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER
>UEFI_APPLICATION
>+ LIBRARY_CLASS = PciSegmentLib|DXE_DRIVER
>DXE_RUNTIME_DRIVER DXE_SMM_DRIVER UEFI_DRIVER UEFI_APPLICATION
>
> CONSTRUCTOR = PciSegmentLibConstructor
> DESTRUCTOR = PciSegmentLibDestructor
>@@ -34,7 +34,7 @@
> #
> # The following information is for reference only and not required by the
>build tools.
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
>+# VALID_ARCHITECTURES = IA32 X64 EBC
> #
>
> [Sources]
>diff --git a/MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
>b/MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
>index 8f46495fc5..d9b51dad92 100644
>--- a/MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
>+++ b/MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
>@@ -24,13 +24,13 @@
> FILE_GUID = b1ee6c28-54aa-4d17-b705-3e28ccb27b2e
> MODULE_TYPE = DXE_RUNTIME_DRIVER
> VERSION_STRING = 1.0
>- LIBRARY_CLASS = UefiRuntimeLib|DXE_RUNTIME_DRIVER
>DXE_SAL_DRIVER
>+ LIBRARY_CLASS = UefiRuntimeLib|DXE_RUNTIME_DRIVER
>
> CONSTRUCTOR = RuntimeDriverLibConstruct
> DESTRUCTOR = RuntimeDriverLibDeconstruct
>
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
>+# VALID_ARCHITECTURES = IA32 X64 EBC
> #
>
>
>diff --git
>a/MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLi
>b.inf
>b/MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLi
>b.inf
>index a843436244..798a9e869c 100644
>---
>a/MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLi
>b.inf
>+++
>b/MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLi
>b.inf
>@@ -20,12 +20,12 @@
> FILE_GUID = 19cbbb97-ff61-45ff-8c3f-dfa66dd118c8
> MODULE_TYPE = UEFI_DRIVER
> VERSION_STRING = 1.0
>- LIBRARY_CLASS = UefiRuntimeServicesTableLib|DXE_CORE
>DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER DXE_SMM_DRIVER
>UEFI_APPLICATION UEFI_DRIVER SMM_CORE
>+ LIBRARY_CLASS = UefiRuntimeServicesTableLib|DXE_CORE
>DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION
>UEFI_DRIVER SMM_CORE
>
> CONSTRUCTOR = UefiRuntimeServicesTableLibConstructor
>
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
>+# VALID_ARCHITECTURES = IA32 X64 EBC
> #
>
> [Sources]
>diff --git a/MdePkg/Library/UefiSalLib/UefiSalLib.c
>b/MdePkg/Library/UefiSalLib/UefiSalLib.c
>deleted file mode 100644
>index e79c7ce8a9..0000000000
>--- a/MdePkg/Library/UefiSalLib/UefiSalLib.c
>+++ /dev/null
>@@ -1,139 +0,0 @@
>-/** @file
>- SAL Library implementation retrieving the SAL Entry Point from the SAL
>System Table
>- register in the EFI System Configuration Table.
>-
>- Copyright (c) 2007 - 2010, Intel Corporation. All rights reserved.<BR>
>- This program and the accompanying materials are
>- licensed and made available under the terms and conditions of
>- the BSD License which accompanies this distribution. The full
>- text of the license may be found at
>- http://opensource.org/licenses/bsd-license.php.
>-
>- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-
>-**/
>-
>-#include <PiDxe.h>
>-#include <IndustryStandard/Sal.h>
>-
>-#include <Library/SalLib.h>
>-#include <Library/UefiLib.h>
>-#include <Library/DebugLib.h>
>-
>-#include <Guid/SalSystemTable.h>
>-
>-EFI_PLABEL mPlabel;
>-SAL_PROC mSalProcEntry;
>-
>-/**
>- Makes a SAL procedure call.
>-
>- This is a wrapper function to make a SAL procedure call.
>- No parameter checking is performed on the 8 input parameters,
>- but there are some common rules that the caller should follow
>- when making a SAL call. Any address passed to SAL as buffers
>- for return parameters must be 8-byte aligned. Unaligned
>- addresses may cause undefined results. For those parameters
>- defined as reserved or some fields defined as reserved must be
>- zero filled or the invalid argument return value may be returned
>- or undefined result may occur during the execution of the procedure.
>- This function is only available on IPF.
>-
>- @param Index The SAL procedure Index number.
>- @param Arg2 The 2nd parameter for SAL procedure calls.
>- @param Arg3 The 3rd parameter for SAL procedure calls.
>- @param Arg4 The 4th parameter for SAL procedure calls.
>- @param Arg5 The 5th parameter for SAL procedure calls.
>- @param Arg6 The 6th parameter for SAL procedure calls.
>- @param Arg7 The 7th parameter for SAL procedure calls.
>- @param Arg8 The 8th parameter for SAL procedure calls.
>-
>- @return SAL returned registers.
>-
>-**/
>-SAL_RETURN_REGS
>-EFIAPI
>-SalCall (
>- IN UINT64 Index,
>- IN UINT64 Arg2,
>- IN UINT64 Arg3,
>- IN UINT64 Arg4,
>- IN UINT64 Arg5,
>- IN UINT64 Arg6,
>- IN UINT64 Arg7,
>- IN UINT64 Arg8
>- )
>-{
>- //
>- // mSalProcEntry is initialized in library constructor as SAL entry.
>- //
>- return mSalProcEntry(
>- Index,
>- Arg2,
>- Arg3,
>- Arg4,
>- Arg5,
>- Arg6,
>- Arg7,
>- Arg8
>- );
>-
>-}
>-
>-/**
>- The constructor function of UEFI SAL Lib.
>-
>- The constructor function looks up the SAL System Table in the EFI System
>Configuration
>- Table. Once the SAL System Table is found, the SAL Entry Point in the SAL
>System Table
>- will be derived and stored into a global variable for library usage.
>- It will ASSERT() if the SAL System Table cannot be found or the data in the
>SAL System
>- Table is not the valid data.
>-
>- @param ImageHandle The firmware allocated handle for the EFI image.
>- @param SystemTable A pointer to the EFI System Table.
>-
>- @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.
>-
>-**/
>-EFI_STATUS
>-EFIAPI
>-UefiSalLibConstructor (
>- IN EFI_HANDLE ImageHandle,
>- IN EFI_SYSTEM_TABLE *SystemTable
>- )
>-{
>- EFI_STATUS Status;
>- SAL_ST_ENTRY_POINT_DESCRIPTOR *SalStEntryDes;
>- SAL_SYSTEM_TABLE_HEADER *SalSystemTable;
>-
>- Status = EfiGetSystemConfigurationTable (
>- &gEfiSalSystemTableGuid,
>- (VOID **) &SalSystemTable
>- );
>- ASSERT_EFI_ERROR (Status);
>- ASSERT (SalSystemTable != NULL);
>-
>- //
>- // Check the first entry of SAL System Table,
>- // because the SAL entry is in ascending order with the entry type,
>- // the type 0 entry should be the first if exist.
>- //
>- SalStEntryDes = (SAL_ST_ENTRY_POINT_DESCRIPTOR *)(SalSystemTable +
>1);
>-
>- //
>- // Assure the SAL ENTRY Type is 0
>- //
>- ASSERT (SalStEntryDes->Type == EFI_SAL_ST_ENTRY_POINT);
>-
>- mPlabel.EntryPoint = SalStEntryDes->SalProcEntry;
>- mPlabel.GP = SalStEntryDes->SalGlobalDataPointer;
>- //
>- // Make sure the EntryPoint has the valid value
>- //
>- ASSERT ((mPlabel.EntryPoint != 0) && (mPlabel.GP != 0));
>-
>- mSalProcEntry = (SAL_PROC)((UINT64)&(mPlabel.EntryPoint));
>-
>- return EFI_SUCCESS;
>-}
>diff --git a/MdePkg/Library/UefiSalLib/UefiSalLib.inf
>b/MdePkg/Library/UefiSalLib/UefiSalLib.inf
>deleted file mode 100644
>index bc25c53b83..0000000000
>--- a/MdePkg/Library/UefiSalLib/UefiSalLib.inf
>+++ /dev/null
>@@ -1,47 +0,0 @@
>-## @file
>-# UEFI Instance of SAL Library Class.
>-#
>-# This instance of SAL library retrieves the SAL Entry Point from the SAL
>System Table
>-# register in the EFI System Confguration Table.
>-#
>-# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
>-#
>-# This program and the accompanying materials
>-# are licensed and made available under the terms and conditions of the BSD
>License
>-# which accompanies this distribution. The full text of the license may be
>found at
>-# http://opensource.org/licenses/bsd-license.php.
>-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS"
>BASIS,
>-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER
>EXPRESS OR IMPLIED.
>-#
>-#
>-##
>-
>-[Defines]
>- INF_VERSION = 0x00010005
>- BASE_NAME = UefiSalLib
>- MODULE_UNI_FILE = UefiSalLib.uni
>- FILE_GUID = 4ABCFD77-4A33-4089-B003-5F09BCA940A2
>- MODULE_TYPE = UEFI_DRIVER
>- VERSION_STRING = 1.0
>- LIBRARY_CLASS = SalLib|UEFI_DRIVER UEFI_APPLICATION
>-
>- CONSTRUCTOR = UefiSalLibConstructor
>-#
>-# The following information is for reference only and not required by the
>build tools.
>-#
>-# VALID_ARCHITECTURES = IPF
>-#
>-
>-[Sources]
>- UefiSalLib.c
>-
>-[Packages]
>- MdePkg/MdePkg.dec
>-
>-[LibraryClasses]
>- UefiLib
>- DebugLib
>-
>-[Guids]
>- gEfiSalSystemTableGuid ## CONSUMES ## SystemTable
>-
>diff --git a/MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
>b/MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
>index cd0c5c1ec8..0e00ab909e 100644
>--- a/MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
>+++ b/MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
>@@ -23,11 +23,11 @@
> FILE_GUID = 280E42C3-826E-4573-9772-B74EF1086D95
> MODULE_TYPE = UEFI_DRIVER
> VERSION_STRING = 1.0
>- LIBRARY_CLASS = UefiScsiLib|DXE_DRIVER DXE_RUNTIME_DRIVER
>DXE_SAL_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER
>+ LIBRARY_CLASS = UefiScsiLib|DXE_DRIVER DXE_RUNTIME_DRIVER
>DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER
>
>
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
>+# VALID_ARCHITECTURES = IA32 X64 EBC
> #
>
> [Sources]
>diff --git a/MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
>b/MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
>index 33062fd692..746daa79f8 100644
>--- a/MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
>+++ b/MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
>@@ -23,11 +23,11 @@
> FILE_GUID = 87eb5df9-722a-4241-ad7f-370d0b3a56d7
> MODULE_TYPE = UEFI_DRIVER
> VERSION_STRING = 1.0
>- LIBRARY_CLASS = UefiUsbLib|DXE_DRIVER DXE_RUNTIME_DRIVER
>DXE_SAL_DRIVER DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER
>+ LIBRARY_CLASS = UefiUsbLib|DXE_DRIVER DXE_RUNTIME_DRIVER
>DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER
>
>
> #
>-# VALID_ARCHITECTURES = IA32 X64 IPF EBC
>+# VALID_ARCHITECTURES = IA32 X64 EBC
> #
>
> [Sources]
>diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec
>index 0e64f22f4a..73923a04d2 100644
>--- a/MdePkg/MdePkg.dec
>+++ b/MdePkg/MdePkg.dec
>@@ -36,9 +36,6 @@
> [Includes.X64]
> Include/X64
>
>-[Includes.IPF]
>- Include/Ipf
>-
> [Includes.EBC]
> Include/Ebc
>
>@@ -274,16 +271,6 @@
> ## @libraryclass Provides services to log the SMI handler registration.
> SmiHandlerProfileLib|Include/Library/SmiHandlerProfileLib.h
>
>-[LibraryClasses.IPF]
>- ## @libraryclass The SAL Library provides a service to make a SAL CALL.
>- SalLib|Include/Library/SalLib.h
>-
>- ## @libraryclass Provides library services to make PAL Calls.
>- PalLib|Include/Library/PalLib.h
>-
>- ## @libraryclass Provides library services to make Extended SAL Calls.
>- ExtendedSalLib|Include/Library/ExtendedSalLib.h
>-
> [Guids]
> #
> # GUID defined in UEFI2.1/UEFI2.0/EFI1.1
>@@ -2212,11 +2199,6 @@
> # @Prompt Memory Address of GuidedExtractHandler Table.
>
>gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress|0x10000
>00|UINT64|0x30001015
>
>-[PcdsFixedAtBuild.IPF, PcdsPatchableInModule.IPF]
>- ## The base address of IO port space for IA64 arch.
>- # @Prompt IA64 IO Port Space Base Address.
>-
>gEfiMdePkgTokenSpaceGuid.PcdIoBlockBaseAddressForIpf|0x0ffffc000000|U
>INT64|0x0000000f
>-
> [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]
> ## This value is used to set the base address of PCI express hierarchy.
> # @Prompt PCI Express Base Address.
>diff --git a/MdePkg/MdePkg.dsc b/MdePkg/MdePkg.dsc
>index cf20bc3a1f..9ee84b2b50 100644
>--- a/MdePkg/MdePkg.dsc
>+++ b/MdePkg/MdePkg.dsc
>@@ -20,7 +20,7 @@
> PLATFORM_VERSION = 1.08
> DSC_SPECIFICATION = 0x00010005
> OUTPUT_DIRECTORY = Build/Mde
>- SUPPORTED_ARCHITECTURES = IA32|IPF|X64|EBC|ARM|AARCH64
>+ SUPPORTED_ARCHITECTURES = IA32|X64|EBC|ARM|AARCH64
> BUILD_TARGETS = DEBUG|RELEASE|NOOPT
> SKUID_IDENTIFIER = DEFAULT
>
>@@ -32,28 +32,6 @@
> gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000000
> gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000
>
>-[PcdsFixedAtBuild.IPF]
>- gEfiMdePkgTokenSpaceGuid.PcdIoBlockBaseAddressForIpf|0x0ffffc000000
>-
>-
>###########################################################
>########################################
>-#
>-# Components Section - list of the modules and components that will be
>processed by compilation
>-# tools and the EDK II tools to generate PE32/PE32+/Coff image
>files.
>-#
>-# Note: The EDK II DSC file is not used to specify how compiled binary images
>get placed
>-# into firmware volume images. This section is just a list of modules to
>compile from
>-# source into UEFI-compliant binaries.
>-# It is the FDF file that contains information on combining binary files into
>firmware
>-# volume images, whose concept is beyond UEFI and is described in PI
>specification.
>-# Binary modules do not need to be listed in this section, as they should
>be
>-# specified in the FDF file. For example: Shell binary (Shell_Full.efi), FAT
>binary (Fat.efi),
>-# Logo (Logo.bmp), and etc.
>-# There may also be modules listed in this section that are not required in
>the FDF file,
>-# When a module listed here is excluded from FDF file, then UEFI-
>compliant binary will be
>-# generated for it, but the binary will not be put into any firmware volume.
>-#
>-
>###########################################################
>########################################
>-
> [Components]
> MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
> MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
>@@ -164,23 +142,6 @@
> MdePkg/Library/SmmPciExpressLib/SmmPciExpressLib.inf
> MdePkg/Library/SmiHandlerProfileLibNull/SmiHandlerProfileLibNull.inf
>
>-[Components.IPF]
>- MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
>- MdePkg/Library/BasePalLibNull/BasePalLibNull.inf
>- MdePkg/Library/PeiPalLib/PeiPalLib.inf
>-
>MdePkg/Library/PeiServicesTablePointerLibKr7/PeiServicesTablePointerLibKr
>7.inf
>- MdePkg/Library/SecPeiDxeTimerLibCpu/SecPeiDxeTimerLibCpu.inf
>- MdePkg/Library/UefiPalLib/UefiPalLib.inf
>- MdePkg/Library/UefiSalLib/UefiSalLib.inf
>- MdePkg/Library/DxeExtendedSalLib/DxeExtendedSalLib.inf
>- MdePkg/Library/DxeIoLibEsal/DxeIoLibEsal.inf
>- MdePkg/Library/DxePalLibEsal/DxePalLibEsal.inf
>- MdePkg/Library/DxePciLibEsal/DxePciLibEsal.inf
>- MdePkg/Library/DxePciSegmentLibEsal/DxePciSegmentLibEsal.inf
>-
>MdePkg/Library/DxeRuntimeExtendedSalLib/DxeRuntimeExtendedSalLib.inf
>- MdePkg/Library/DxeSalLibEsal/DxeSalLibEsal.inf
>- MdePkg/Library/DxeTimerLibEsal/DxeTimerLibEsal.inf
>-
> [Components.EBC]
> MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
> MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
>--
>2.16.2.windows.1
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2018-06-13 3:44 [PATCH 21/37] MdePkg: Removing ipf which is no longer supported from edk2 chenc2
2018-06-13 5:48 ` Gao, Liming
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