From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.120; helo=mga04.intel.com; envelope-from=liming.gao@intel.com; receiver=edk2-devel@lists.01.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 92954211C3858 for ; Thu, 31 Jan 2019 00:06:56 -0800 (PST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 31 Jan 2019 00:06:56 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,543,1539673200"; d="scan'208";a="139439221" Received: from fmsmsx108.amr.corp.intel.com ([10.18.124.206]) by fmsmga002.fm.intel.com with ESMTP; 31 Jan 2019 00:06:56 -0800 Received: from fmsmsx154.amr.corp.intel.com (10.18.116.70) by FMSMSX108.amr.corp.intel.com (10.18.124.206) with Microsoft SMTP Server (TLS) id 14.3.408.0; Thu, 31 Jan 2019 00:06:55 -0800 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by FMSMSX154.amr.corp.intel.com (10.18.116.70) with Microsoft SMTP Server (TLS) id 14.3.408.0; Thu, 31 Jan 2019 00:06:55 -0800 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.102]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.109]) with mapi id 14.03.0415.000; Thu, 31 Jan 2019 16:06:53 +0800 From: "Gao, Liming" To: "Solanki, Digant H" , "edk2-devel@lists.01.org" Thread-Topic: [PATCH 5/5] IntelSiliconPkg\Include\IndustryStandard: Update IGD_OPREGION_MBOX3 Structure Thread-Index: AQHUuTspM//KwZ2W6021zaJ5oABcWqXJBPwA Date: Thu, 31 Jan 2019 08:06:53 +0000 Message-ID: <4A89E2EF3DFEDB4C8BFDE51014F606A14E3D4250@SHSMSX104.ccr.corp.intel.com> References: <20190131080109.13108-1-digant.h.solanki@intel.com> In-Reply-To: <20190131080109.13108-1-digant.h.solanki@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ctpclassification: CTP_NT x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiMjAzZGIxZjAtYWE0ZS00OGQ1LWFkZTYtYmViYmY2YmViN2E3IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiZEVhVFNmVUlJUUlaM21WOXR0eFcwMFY4Z3pJRFZcL3lmUlZLZ0crWjZYNCtKMTZBMzdvY1JnSnVCbG0waWpPUDkifQ== dlp-product: dlpe-windows dlp-version: 11.0.400.15 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH 5/5] IntelSiliconPkg\Include\IndustryStandard: Update IGD_OPREGION_MBOX3 Structure X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 31 Jan 2019 08:06:56 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable One comment on the title. This is Patch V5, not Patch 5/5. You don't need t= o send new patch.=20 Thanks Liming > -----Original Message----- > From: Solanki, Digant H > Sent: Thursday, January 31, 2019 4:01 PM > To: edk2-devel@lists.01.org > Cc: Ni, Ray ; Gao, Liming ; Chaga= nty, Rangasai V > Subject: [PATCH 5/5] IntelSiliconPkg\Include\IndustryStandard: Update IGD= _OPREGION_MBOX3 Structure >=20 > BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1454 > Based on latest IGD OpRegion Spec, IGD_OPREGION_MBOX3 needs to be updated= with two new members : Physical Address of Raw VBT > Data (RVDA) and Size of Raw VBT Data (RVDS) >=20 > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Digant H Solanki > Cc: Ray Ni > Cc: Liming Gao > Cc: Rangasai V Chaganty > --- > IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion.h | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) >=20 > diff --git a/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion.h b/Int= elSiliconPkg/Include/IndustryStandard/IgdOpRegion.h > index 5ce80a5be8..300a85a717 100644 > --- a/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion.h > +++ b/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion.h > @@ -4,9 +4,7 @@ >=20 > https://01.org/sites/default/files/documentation/skl_opregion_rev0p5.p= df >=20 > - @note Fixed bug in the spec Mailbox3 - RM31 size from 0x45(69) to 0x46= (70) > - > - Copyright (c) 2016, Intel Corporation. All rights reserved.
> + Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
> This program and the accompanying materials > are licensed and made available under the terms and conditions of the = BSD License > which accompanies this distribution. The full text of the license may= be found at > @@ -118,7 +116,9 @@ typedef struct { > UINT64 FDSS; ///< Offset 0x3AA DSS Buffer address allocated f= or IFFS feature > UINT32 FDSP; ///< Offset 0x3B2 Size of DSS buffer > UINT32 STAT; ///< Offset 0x3B6 State Indicator > - UINT8 RM31[0x46]; ///< Offset 0x3BA - 0x3FF Reserved Must be zero= . Bug in spec 0x45(69) > + UINT64 RVDA; ///< Offset 0x3BA Physical address of Raw VBT da= ta. Added from Spec Version 0.90 to support VBT greater > than 6KB. > + UINT32 RVDS; ///< Offset 0x3C2 Size of Raw VBT data. Added fr= om Spec Version 0.90 to support VBT greater than 6KB. > + UINT8 RM32[0x3A]; ///< Offset 0x3C6 - 0x3FF Reserved Must be zero= . > } IGD_OPREGION_MBOX3; >=20 > /// > -- > 2.18.0.windows.1