From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.65; helo=mga03.intel.com; envelope-from=liming.gao@intel.com; receiver=edk2-devel@lists.01.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 4B981211C6075 for ; Fri, 1 Feb 2019 04:18:51 -0800 (PST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 01 Feb 2019 04:18:51 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.56,548,1539673200"; d="scan'208";a="296472929" Received: from fmsmsx108.amr.corp.intel.com ([10.18.124.206]) by orsmga005.jf.intel.com with ESMTP; 01 Feb 2019 04:18:50 -0800 Received: from fmsmsx154.amr.corp.intel.com (10.18.116.70) by FMSMSX108.amr.corp.intel.com (10.18.124.206) with Microsoft SMTP Server (TLS) id 14.3.408.0; Fri, 1 Feb 2019 04:18:50 -0800 Received: from shsmsx102.ccr.corp.intel.com (10.239.4.154) by FMSMSX154.amr.corp.intel.com (10.18.116.70) with Microsoft SMTP Server (TLS) id 14.3.408.0; Fri, 1 Feb 2019 04:18:50 -0800 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.102]) by shsmsx102.ccr.corp.intel.com ([169.254.2.207]) with mapi id 14.03.0415.000; Fri, 1 Feb 2019 20:18:47 +0800 From: "Gao, Liming" To: "Kubacki, Michael A" , "edk2-devel@lists.01.org" Thread-Topic: [edk2] [edk2-platforms/devel-MinPlatform][PATCH v3 0/6] Add initial ClevoOpenBoardPkg Thread-Index: AQHUtRNdMo7sQZq7xUmno8lLvxCv3KXK5mEg Date: Fri, 1 Feb 2019 12:18:47 +0000 Message-ID: <4A89E2EF3DFEDB4C8BFDE51014F606A14E3D4CB1@SHSMSX104.ccr.corp.intel.com> References: <20190126010540.34444-1-michael.a.kubacki@intel.com> In-Reply-To: <20190126010540.34444-1-michael.a.kubacki@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ctpclassification: CTP_NT x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiMTE4YWI1MzEtM2M0OC00YjdhLTg1MzgtZjI0YzFjY2QyNmFmIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiUENFRWJMOWhldFEyYXNQNE1rWVVST29LTTFjdVF1TVBCMkRFSUh1ZWQ4YTdtbmxnZFNFb1pPU3gycnBOVUp4RSJ9 dlp-product: dlpe-windows dlp-version: 11.0.400.15 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [edk2-platforms/devel-MinPlatform][PATCH v3 0/6] Add initial ClevoOpenBoardPkg X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 01 Feb 2019 12:18:52 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Liming Gao > -----Original Message----- > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Mi= chael Kubacki > Sent: Saturday, January 26, 2019 9:06 AM > To: edk2-devel@lists.01.org > Subject: [edk2] [edk2-platforms/devel-MinPlatform][PATCH v3 0/6] Add init= ial ClevoOpenBoardPkg >=20 > This series adds a new board package in Platform/Intel for Clevo > boards. This provides a board implementation for use with the > MinPlatformPkg. Currently, this is largely a copy of > KabylakeOpenBoardPkg with the name refactored. It is intended to > serve as a base for future community development. >=20 > A board directory for the N1xxWU series of Clevo boards based on > Kaby Lake-R is provided as this is the first board planned to be > enabled. The next board instance expected to be supported is the > N1xxZU series based on Whiskey Lake. This directory will be a > peer to N1xxWU in ClevoOpenBoardPkg. Both boards share common > resources in the ClevoOpenBoardPkg root directory. >=20 > To minimize intial delta from the source KabylakeOpenBoardPkg, > changes required for boot have not yet been made. Therefore, > in this current state boot functionality should not be expected. >=20 > The build instructions are similar to the other boards already > present in Platform/Intel and can be found in ReadMe.md on > devel-MinPlatform. > https://github.com/tianocore/edk2-platforms/tree/devel-MinPlatform >=20 > Michael Kubacki (6): > ClevoOpenBoardPkg: Add package and headers > ClevoOpenBoardPkg/N1xxWU: Add headers > ClevoOpenBoardPkg: Add library instances > ClevoOpenBoardPkg/N1xxWU: Add library instances > ClevoOpenBoardPkg: Add modules > ClevoOpenBoardPkg/N1xxWU: Add DSC and build files >=20 > Platform/Intel/ClevoOpenBoardPkg/OpenBoardPkg.dec | 306 ++++ > .../ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc | 351 ++++ > .../N1xxWU/OpenBoardPkgBuildOption.dsc | 155 ++ > .../N1xxWU/OpenBoardPkgConfig.dsc | 139 ++ > .../ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgPcd.dsc | 268 +++ > .../N1xxWU/Include/Fdf/FlashMapInclude.fdf | 52 + > .../ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf | 716 ++++++++ > .../Acpi/BoardAcpiDxe/BoardAcpiDxe.inf | 75 + > .../Features/PciHotPlug/PciHotPlug.inf | 65 + > .../Library/DxeTbtPolicyLib/DxeTbtPolicyLib.inf | 73 + > .../Library/PeiDxeSmmTbtCommonLib/TbtCommonLib.inf | 68 + > .../Library/PeiTbtPolicyLib/PeiTbtPolicyLib.inf | 62 + > .../Private/PeiDTbtInitLib/PeiDTbtInitLib.inf | 47 + > .../Features/Tbt/TbtInit/Dxe/TbtDxe.inf | 55 + > .../Features/Tbt/TbtInit/Pei/PeiTbtInit.inf | 50 + > .../Features/Tbt/TbtInit/Smm/TbtSmm.inf | 83 + > .../BaseGpioExpanderLib/BaseGpioExpanderLib.inf | 39 + > .../Library/PeiI2cAccessLib/PeiI2cAccessLib.inf | 42 + > .../PeiSiliconPolicyUpdateLibFsp.inf | 149 ++ > .../BasePlatformHookLib/BasePlatformHookLib.inf | 57 + > .../Library/BoardAcpiLib/DxeBoardAcpiTableLib.inf | 53 + > .../BoardAcpiLib/DxeMultiBoardAcpiSupportLib.inf | 54 + > .../Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf | 53 + > .../BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf | 54 + > .../BoardInitLib/PeiBoardInitPostMemLib.inf | 59 + > .../Library/BoardInitLib/PeiBoardInitPreMemLib.inf | 138 ++ > .../BoardInitLib/PeiMultiBoardInitPostMemLib.inf | 61 + > .../BoardInitLib/PeiMultiBoardInitPreMemLib.inf | 140 ++ > .../DxeSiliconPolicyUpdateLib.inf | 55 + > .../Features/PciHotPlug/PciHotPlug.h | 136 ++ > .../Features/Tbt/Include/Acpi/TbtNvsAreaDef.h | 68 + > .../Features/Tbt/Include/Library/DxeTbtPolicyLib.h | 52 + > .../Features/Tbt/Include/Library/PeiTbtPolicyLib.h | 47 + > .../Features/Tbt/Include/Library/TbtCommonLib.h | 247 +++ > .../Features/Tbt/Include/Ppi/PeiTbtPolicy.h | 35 + > .../Tbt/Include/Private/Library/PeiDTbtInitLib.h | 114 ++ > .../Include/Private/Library/PeiTbtCommonInitLib.h | 47 + > .../Features/Tbt/Include/Protocol/DxeTbtPolicy.h | 116 ++ > .../Features/Tbt/Include/Protocol/TbtNvsArea.h | 48 + > .../Features/Tbt/Include/TbtBoardInfo.h | 28 + > .../Tbt/Include/TbtPolicyCommonDefinition.h | 83 + > .../Library/DxeTbtPolicyLib/DxeTbtPolicyLibrary.h | 28 + > .../Library/PeiTbtPolicyLib/PeiTbtPolicyLibrary.h | 23 + > .../Features/Tbt/TbtInit/Smm/TbtSmiHandler.h | 185 ++ > .../Include/Acpi/GlobalNvsAreaDef.h | 122 ++ > .../Intel/ClevoOpenBoardPkg/Include/IoExpander.h | 73 + > .../Include/Library/GpioExpanderLib.h | 128 ++ > .../Include/Library/I2cAccessLib.h | 39 + > .../ClevoOpenBoardPkg/Include/PchHsioPtssTables.h | 57 + > .../Include/Protocol/GlobalNvsArea.h | 53 + > Platform/Intel/ClevoOpenBoardPkg/Include/SioRegs.h | 163 ++ > .../PeiPchPolicyUpdate.h | 34 + > .../PeiSaPolicyUpdate.h | 36 + > .../ClevoOpenBoardPkg/N1xxWU/Include/N1xxWUId.h | 19 + > .../N1xxWU/Library/BoardInitLib/PeiN1xxWUInitLib.h | 48 + > .../DxeSiliconPolicyUpdateLib/DxeGopPolicyInit.h | 45 + > .../DxeSiliconPolicyUpdateLib/DxeSaPolicyInit.h | 70 + > .../Acpi/BoardAcpiDxe/AcpiGnvsInit.c | 101 ++ > .../Acpi/BoardAcpiDxe/BoardAcpiDxe.c | 313 ++++ > .../Acpi/BoardAcpiDxe/UpdateDsdt.c | 782 ++++++++ > .../Features/PciHotPlug/PciHotPlug.c | 357 ++++ > .../Tbt/Library/DxeTbtPolicyLib/DxeTbtPolicyLib.c | 166 ++ > .../Library/PeiDxeSmmTbtCommonLib/TbtCommonLib.c | 321 ++++ > .../Tbt/Library/PeiTbtPolicyLib/PeiTbtPolicyLib.c | 210 +++ > .../Private/PeiDTbtInitLib/PeiDTbtInitLib.c | 572 ++++++ > .../Features/Tbt/TbtInit/Dxe/TbtDxe.c | 234 +++ > .../Features/Tbt/TbtInit/Pei/PeiTbtInit.c | 199 ++ > .../Features/Tbt/TbtInit/Smm/TbtSmiHandler.c | 1616 ++++++++++++++= +++ > .../Features/Tbt/TbtInit/Smm/TbtSmm.c | 1770 ++++++++++++++= ++++ > .../BaseGpioExpanderLib/BaseGpioExpanderLib.c | 315 ++++ > .../Library/PeiI2cAccessLib/PeiI2cAccessLib.c | 121 ++ > .../PeiSiliconPolicyUpdateLibFsp/PcieDeviceTable.c | 121 ++ > .../PeiFspMiscUpdUpdateLib.c | 93 + > .../PeiFspPolicyUpdateLib.c | 192 ++ > .../PeiPchPolicyUpdate.c | 159 ++ > .../PeiPchPolicyUpdatePreMem.c | 254 +++ > .../PeiSaPolicyUpdate.c | 90 + > .../PeiSaPolicyUpdatePreMem.c | 74 + > .../BasePlatformHookLib/BasePlatformHookLib.c | 668 +++++++ > .../Library/BoardAcpiLib/DxeBoardAcpiTableLib.c | 42 + > .../BoardAcpiLib/DxeMultiBoardAcpiSupportLib.c | 49 + > .../Library/BoardAcpiLib/DxeN1xxWUAcpiTableLib.c | 80 + > .../Library/BoardAcpiLib/SmmBoardAcpiEnableLib.c | 68 + > .../BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c | 87 + > .../Library/BoardAcpiLib/SmmN1xxWUAcpiEnableLib.c | 45 + > .../Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c | 174 ++ > .../N1xxWU/Library/BoardInitLib/N1xxWUGpioTable.c | 375 ++++ > .../Library/BoardInitLib/N1xxWUHdaVerbTables.c | 238 +++ > .../Library/BoardInitLib/N1xxWUHsioPtssTables.c | 111 ++ > .../N1xxWU/Library/BoardInitLib/N1xxWUSpdTable.c | 432 +++++ > .../Library/BoardInitLib/PeiBoardInitPostMemLib.c | 45 + > .../Library/BoardInitLib/PeiBoardInitPreMemLib.c | 111 ++ > .../BoardInitLib/PeiMultiBoardInitPostMemLib.c | 46 + > .../BoardInitLib/PeiMultiBoardInitPreMemLib.c | 88 + > .../N1xxWU/Library/BoardInitLib/PeiN1xxWUDetect.c | 72 + > .../Library/BoardInitLib/PeiN1xxWUInitPostMemLib.c | 215 +++ > .../Library/BoardInitLib/PeiN1xxWUInitPreMemLib.c | 236 +++ > .../DxeSiliconPolicyUpdateLib/DxeGopPolicyInit.c | 181 ++ > .../DxeSiliconPolicyUpdateLib/DxeSaPolicyUpdate.c | 71 + > .../DxeSiliconPolicyUpdateLib.c | 60 + > .../Acpi/BoardAcpiDxe/Dsdt/ALS.ASL | 43 + > .../Acpi/BoardAcpiDxe/Dsdt/AMLUPD.asl | 27 + > .../Acpi/BoardAcpiDxe/Dsdt/CPU.asl | 252 +++ > .../Acpi/BoardAcpiDxe/Dsdt/DSDT.ASL | 127 ++ > .../Acpi/BoardAcpiDxe/Dsdt/Gpe.asl | 856 +++++++++ > .../Acpi/BoardAcpiDxe/Dsdt/Itss.asl | 39 + > .../Acpi/BoardAcpiDxe/Dsdt/LPC_DEV.ASL | 205 +++ > .../Acpi/BoardAcpiDxe/Dsdt/LpcB.asl | 94 + > .../Acpi/BoardAcpiDxe/Dsdt/PCI_DRC.ASL | 122 ++ > .../Acpi/BoardAcpiDxe/Dsdt/PciTree.asl | 312 ++++ > .../Acpi/BoardAcpiDxe/Dsdt/Platform.asl | 1135 ++++++++++++ > .../Acpi/BoardAcpiDxe/Dsdt/PlatformGnvs.asl | 14 + > .../Acpi/BoardAcpiDxe/Dsdt/Video.asl | 33 + > Platform/Intel/ClevoOpenBoardPkg/Contributions.txt | 218 +++ > .../Features/Tbt/AcpiTables/Rtd3SptPcieTbt.asl | 409 +++++ > .../Features/Tbt/AcpiTables/Tbt.asl | 1908 ++++++++++++++= ++++++ > .../Features/Tbt/Include/Acpi/TbtNvs.asl | 62 + > .../ClevoOpenBoardPkg/Include/Acpi/GlobalNvs.asl | 120 ++ > Platform/Intel/ClevoOpenBoardPkg/License.txt | 25 + > .../ClevoOpenBoardPkg/N1xxWU/GitEdk2Clevo.bat | 85 + > Platform/Intel/ClevoOpenBoardPkg/N1xxWU/bld.bat | 165 ++ > Platform/Intel/ClevoOpenBoardPkg/N1xxWU/cln.bat | 54 + > .../Intel/ClevoOpenBoardPkg/N1xxWU/postbuild.bat | 45 + > .../Intel/ClevoOpenBoardPkg/N1xxWU/prebuild.bat | 220 +++ > Platform/Intel/ClevoOpenBoardPkg/N1xxWU/prep.bat | 85 + > 125 files changed, 23872 insertions(+) > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/OpenBoardPkg.dec > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.= dsc > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgB= uildOption.dsc > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgC= onfig.dsc > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgP= cd.dsc > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Include/Fdf/F= lashMapInclude.fdf > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.= fdf > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Bo= ardAcpiDxe.inf > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Features/PciHotPlug/= PciHotPlug.inf > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library= /DxeTbtPolicyLib/DxeTbtPolicyLib.inf > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library= /PeiDxeSmmTbtCommonLib/TbtCommonLib.inf > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library= /PeiTbtPolicyLib/PeiTbtPolicyLib.inf > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library= /Private/PeiDTbtInitLib/PeiDTbtInitLib.inf > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit= /Dxe/TbtDxe.inf > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit= /Pei/PeiTbtInit.inf > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit= /Smm/TbtSmm.inf > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Library/BaseGpioExpa= nderLib/BaseGpioExpanderLib.inf > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Library/PeiI2cAccess= Lib/PeiI2cAccessLib.inf > create mode 100644 > Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPoli= cyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BaseP= latformHookLib/BasePlatformHookLib.inf > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/Board= AcpiLib/DxeBoardAcpiTableLib.inf > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/Board= AcpiLib/DxeMultiBoardAcpiSupportLib.inf > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/Board= AcpiLib/SmmBoardAcpiEnableLib.inf > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/Board= AcpiLib/SmmMultiBoardAcpiSupportLib.inf > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/Board= InitLib/PeiBoardInitPostMemLib.inf > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/Board= InitLib/PeiBoardInitPreMemLib.inf > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/Board= InitLib/PeiMultiBoardInitPostMemLib.inf > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/Board= InitLib/PeiMultiBoardInitPreMemLib.inf > create mode 100644 > Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Policy/Library/DxeSiliconPolicyUp= dateLib/DxeSiliconPolicyUpdateLib.inf > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Features/PciHotPlug/= PciHotPlug.h > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include= /Acpi/TbtNvsAreaDef.h > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include= /Library/DxeTbtPolicyLib.h > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include= /Library/PeiTbtPolicyLib.h > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include= /Library/TbtCommonLib.h > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include= /Ppi/PeiTbtPolicy.h > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include= /Private/Library/PeiDTbtInitLib.h > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include= /Private/Library/PeiTbtCommonInitLib.h > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include= /Protocol/DxeTbtPolicy.h > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include= /Protocol/TbtNvsArea.h > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include= /TbtBoardInfo.h > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include= /TbtPolicyCommonDefinition.h > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library= /DxeTbtPolicyLib/DxeTbtPolicyLibrary.h > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library= /PeiTbtPolicyLib/PeiTbtPolicyLibrary.h > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit= /Smm/TbtSmiHandler.h > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Include/Acpi/GlobalN= vsAreaDef.h > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Include/IoExpander.h > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Include/Library/Gpio= ExpanderLib.h > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Include/Library/I2cA= ccessLib.h > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Include/PchHsioPtssT= ables.h > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Include/Protocol/Glo= balNvsArea.h > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Include/SioRegs.h > create mode 100644 > Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPoli= cyUpdateLibFsp/PeiPchPolicyUpdate.h > create mode 100644 > Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPoli= cyUpdateLibFsp/PeiSaPolicyUpdate.h > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Include/N1xxW= UId.h > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/Board= InitLib/PeiN1xxWUInitLib.h > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Policy/Librar= y/DxeSiliconPolicyUpdateLib/DxeGopPolicyInit.h > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Policy/Librar= y/DxeSiliconPolicyUpdateLib/DxeSaPolicyInit.h > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Ac= piGnvsInit.c > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Bo= ardAcpiDxe.c > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Up= dateDsdt.c > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Features/PciHotPlug/= PciHotPlug.c > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library= /DxeTbtPolicyLib/DxeTbtPolicyLib.c > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library= /PeiDxeSmmTbtCommonLib/TbtCommonLib.c > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library= /PeiTbtPolicyLib/PeiTbtPolicyLib.c > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Library= /Private/PeiDTbtInitLib/PeiDTbtInitLib.c > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit= /Dxe/TbtDxe.c > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit= /Pei/PeiTbtInit.c > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit= /Smm/TbtSmiHandler.c > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit= /Smm/TbtSmm.c > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Library/BaseGpioExpa= nderLib/BaseGpioExpanderLib.c > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Library/PeiI2cAccess= Lib/PeiI2cAccessLib.c > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Li= brary/PeiSiliconPolicyUpdateLibFsp/PcieDeviceTable.c > create mode 100644 > Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPoli= cyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c > create mode 100644 > Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPoli= cyUpdateLibFsp/PeiFspPolicyUpdateLib.c > create mode 100644 > Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPoli= cyUpdateLibFsp/PeiPchPolicyUpdate.c > create mode 100644 > Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPoli= cyUpdateLibFsp/PeiPchPolicyUpdatePreMem.c > create mode 100644 > Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPoli= cyUpdateLibFsp/PeiSaPolicyUpdate.c > create mode 100644 > Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPoli= cyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BaseP= latformHookLib/BasePlatformHookLib.c > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/Board= AcpiLib/DxeBoardAcpiTableLib.c > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/Board= AcpiLib/DxeMultiBoardAcpiSupportLib.c > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/Board= AcpiLib/DxeN1xxWUAcpiTableLib.c > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/Board= AcpiLib/SmmBoardAcpiEnableLib.c > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/Board= AcpiLib/SmmMultiBoardAcpiSupportLib.c > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/Board= AcpiLib/SmmN1xxWUAcpiEnableLib.c > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/Board= AcpiLib/SmmSiliconAcpiEnableLib.c > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/Board= InitLib/N1xxWUGpioTable.c > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/Board= InitLib/N1xxWUHdaVerbTables.c > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/Board= InitLib/N1xxWUHsioPtssTables.c > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/Board= InitLib/N1xxWUSpdTable.c > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/Board= InitLib/PeiBoardInitPostMemLib.c > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/Board= InitLib/PeiBoardInitPreMemLib.c > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/Board= InitLib/PeiMultiBoardInitPostMemLib.c > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/Board= InitLib/PeiMultiBoardInitPreMemLib.c > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/Board= InitLib/PeiN1xxWUDetect.c > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/Board= InitLib/PeiN1xxWUInitPostMemLib.c > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/Board= InitLib/PeiN1xxWUInitPreMemLib.c > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Policy/Librar= y/DxeSiliconPolicyUpdateLib/DxeGopPolicyInit.c > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Policy/Librar= y/DxeSiliconPolicyUpdateLib/DxeSaPolicyUpdate.c > create mode 100644 > Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Policy/Library/DxeSiliconPolicyUp= dateLib/DxeSiliconPolicyUpdateLib.c > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Ds= dt/ALS.ASL > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Ds= dt/AMLUPD.asl > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Ds= dt/CPU.asl > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Ds= dt/DSDT.ASL > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Ds= dt/Gpe.asl > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Ds= dt/Itss.asl > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Ds= dt/LPC_DEV.ASL > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Ds= dt/LpcB.asl > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Ds= dt/PCI_DRC.ASL > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Ds= dt/PciTree.asl > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Ds= dt/Platform.asl > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Ds= dt/PlatformGnvs.asl > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Acpi/BoardAcpiDxe/Ds= dt/Video.asl > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Contributions.txt > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/AcpiTab= les/Rtd3SptPcieTbt.asl > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/AcpiTab= les/Tbt.asl > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/Include= /Acpi/TbtNvs.asl > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/Include/Acpi/GlobalN= vs.asl > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/License.txt > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/GitEdk2Clevo.= bat > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/bld.bat > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/cln.bat > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/postbuild.bat > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/prebuild.bat > create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/prep.bat >=20 > -- > 2.16.2.windows.1 >=20 > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel