From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.136, mailfrom: liming.gao@intel.com) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by groups.io with SMTP; Sun, 28 Apr 2019 01:28:36 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 28 Apr 2019 01:28:35 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,405,1549958400"; d="scan'208";a="341468197" Received: from fmsmsx104.amr.corp.intel.com ([10.18.124.202]) by fmsmga005.fm.intel.com with ESMTP; 28 Apr 2019 01:28:35 -0700 Received: from fmsmsx154.amr.corp.intel.com (10.18.116.70) by fmsmsx104.amr.corp.intel.com (10.18.124.202) with Microsoft SMTP Server (TLS) id 14.3.408.0; Sun, 28 Apr 2019 01:28:35 -0700 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by FMSMSX154.amr.corp.intel.com (10.18.116.70) with Microsoft SMTP Server (TLS) id 14.3.408.0; Sun, 28 Apr 2019 01:28:35 -0700 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.92]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.42]) with mapi id 14.03.0415.000; Sun, 28 Apr 2019 16:28:33 +0800 From: "Liming Gao" To: "Kinney, Michael D" , "devel@edk2.groups.io" Subject: Re: [Patch 1/4] MdePkg/BaseLib: Verify SSE2 support in IA32 AsmLfence() Thread-Topic: [Patch 1/4] MdePkg/BaseLib: Verify SSE2 support in IA32 AsmLfence() Thread-Index: AQHU+4/RbaIMiJkWFk2qZQ3JfsqslaZRQWHA Date: Sun, 28 Apr 2019 08:28:33 +0000 Message-ID: <4A89E2EF3DFEDB4C8BFDE51014F606A14E431CC3@SHSMSX104.ccr.corp.intel.com> References: <20190425175334.5944-1-michael.d.kinney@intel.com> <20190425175334.5944-2-michael.d.kinney@intel.com> In-Reply-To: <20190425175334.5944-2-michael.d.kinney@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Return-Path: liming.gao@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Mike: I think X64 implementation also needs to add this check.=20 Thanks Liming >-----Original Message----- >From: Kinney, Michael D >Sent: Friday, April 26, 2019 1:54 AM >To: devel@edk2.groups.io >Cc: Gao, Liming >Subject: [Patch 1/4] MdePkg/BaseLib: Verify SSE2 support in IA32 AsmLfence= () > >Use CPUID in IA32 implementation of AsmLfence() to verify >that SSE2 is supported before using the LFENCE instruction. > >Cc: Liming Gao >Signed-off-by: Michael D Kinney >--- > MdePkg/Library/BaseLib/Ia32/Lfence.nasm | 14 +++++++++++++- > 1 file changed, 13 insertions(+), 1 deletion(-) > >diff --git a/MdePkg/Library/BaseLib/Ia32/Lfence.nasm >b/MdePkg/Library/BaseLib/Ia32/Lfence.nasm >index 44478be35f..0a60ae1d57 100644 >--- a/MdePkg/Library/BaseLib/Ia32/Lfence.nasm >+++ b/MdePkg/Library/BaseLib/Ia32/Lfence.nasm >@@ -1,5 +1,5 @@ > ;------------------------------------------------------------------------= ------ ; >-; Copyright (c) 2018, Intel Corporation. All rights reserved.
>+; Copyright (c) 2018 - 2019, Intel Corporation. All rights reserved.
> ; SPDX-License-Identifier: BSD-2-Clause-Patent > ; > ; Module Name: >@@ -26,5 +26,17 @@ > ;------------------------------------------------------------------------= ------ > global ASM_PFX(AsmLfence) > ASM_PFX(AsmLfence): >+ ; >+ ; Use CPUID instruction (CPUID.01H:EDX.SSE2[bit 26] =3D 1) to test wh= ether >the >+ ; processor supports SSE2 instruction. Save/restore non-volatile reg= ister >+ ; EBX that is modified by CPUID >+ ; >+ push ebx >+ mov eax, 1 >+ cpuid >+ bt edx, 26 >+ jnc Done > lfence >+Done: >+ pop ebx > ret >-- >2.21.0.windows.1