* [PATCH] MdePkg/PciExpress21.h: Fix the PCIe industry standard registers
@ 2019-07-22 6:26 Javeed, Ashraf
2019-07-25 14:04 ` Liming Gao
0 siblings, 1 reply; 11+ messages in thread
From: Javeed, Ashraf @ 2019-07-22 6:26 UTC (permalink / raw)
To: devel; +Cc: Michael D Kinney, Liming Gao, Ray Ni, Hao A Wu
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2007
The PCIe Device capability register #2 (PCI_REG_PCIE_DEVICE_CAPABILITY2)
needs to be upgraded for the PCI features like - LN system CLS, 10b Tag
completer/requester register fields, emergency power reduction support
and initialization requirement, and FRS support.
The PCIe Device Control register #2 (PCI_REG_PCIE_DEVICE_CONTROL2) needs
to be upgraded for the - emergency power reduction request enabling and
also the 10b Extended Tag enabling.
Needs macro definitions for all the ranges of Maximum Payload Sizes and
Maximum Read Request Sizes defined
Needs macro definitions for all the ranges of Completion Timeout range
needs to be defined.
Signed-off-by: Ashraf Javeed <ashraf.javeed@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
---
MdePkg/Include/IndustryStandard/PciExpress21.h | 39 ++++++++++++++++++++++++++++++++++++---
1 file changed, 36 insertions(+), 3 deletions(-)
diff --git a/MdePkg/Include/IndustryStandard/PciExpress21.h b/MdePkg/Include/IndustryStandard/PciExpress21.h
index d4003de74c..e652e77a1e 100644
--- a/MdePkg/Include/IndustryStandard/PciExpress21.h
+++ b/MdePkg/Include/IndustryStandard/PciExpress21.h
@@ -91,6 +91,24 @@ typedef union {
UINT16 Uint16;
} PCI_REG_PCIE_DEVICE_CONTROL;
+#define PCIE_MAX_PAYLOAD_SIZE_128B 0
+#define PCIE_MAX_PAYLOAD_SIZE_256B 1
+#define PCIE_MAX_PAYLOAD_SIZE_512B 2
+#define PCIE_MAX_PAYLOAD_SIZE_1024B 3
+#define PCIE_MAX_PAYLOAD_SIZE_2048B 4
+#define PCIE_MAX_PAYLOAD_SIZE_4096B 5
+#define PCIE_MAX_PAYLOAD_SIZE_RVSD1 6
+#define PCIE_MAX_PAYLOAD_SIZE_RVSD2 7
+
+#define PCIE_MAX_READ_REQ_SIZE_128B 0
+#define PCIE_MAX_READ_REQ_SIZE_256B 1
+#define PCIE_MAX_READ_REQ_SIZE_512B 2
+#define PCIE_MAX_READ_REQ_SIZE_1024B 3
+#define PCIE_MAX_READ_REQ_SIZE_2048B 4
+#define PCIE_MAX_READ_REQ_SIZE_4096B 5
+#define PCIE_MAX_READ_REQ_SIZE_RVSD1 6
+#define PCIE_MAX_READ_REQ_SIZE_RVSD2 7
+
typedef union {
struct {
UINT16 CorrectableError : 1;
@@ -250,16 +268,30 @@ typedef union {
UINT32 NoRoEnabledPrPrPassing : 1;
UINT32 LtrMechanism : 1;
UINT32 TphCompleter : 2;
- UINT32 Reserved : 4;
+ UINT32 LnSystemCLS : 2;
+ UINT32 TenBitTagCompleterSupported : 1;
+ UINT32 TenBitTagRequesterSupported : 1;
UINT32 Obff : 2;
UINT32 ExtendedFmtField : 1;
UINT32 EndEndTlpPrefix : 1;
UINT32 MaxEndEndTlpPrefixes : 2;
- UINT32 Reserved2 : 8;
+ UINT32 EmergencyPowerReductionSupported : 2;
+ UINT32 EmergencyPowerReductionInitializationRequired : 1;
+ UINT32 Reserved : 4;
+ UINT32 FrsSupported : 1;
} Bits;
UINT32 Uint32;
} PCI_REG_PCIE_DEVICE_CAPABILITY2;
+#define PCIE_COMPLETION_TIMEOUT_NOT_SUPPORTED 0
+#define PCIE_COMPLETION_TIMEOUT_RANGE_A_SUPPORTED 1
+#define PCIE_COMPLETION_TIMEOUT_RANGE_B_SUPPORTED 2
+#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_SUPPORTED 3
+#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_SUPPORTED 6
+#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_SUPPORTED 7
+#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_D_SUPPORTED 14
+#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_D_SUPPORTED 15
+
#define PCIE_DEVICE_CAPABILITY_OBFF_MESSAGE BIT0
#define PCIE_DEVICE_CAPABILITY_OBFF_WAKE BIT1
@@ -273,7 +305,8 @@ typedef union {
UINT16 IdoRequest : 1;
UINT16 IdoCompletion : 1;
UINT16 LtrMechanism : 2;
- UINT16 Reserved : 2;
+ UINT16 EmergencyPowerReductionRequest : 1;
+ UINT16 TenBitTagRequesterEnable : 1;
UINT16 Obff : 2;
UINT16 EndEndTlpPrefixBlocking : 1;
} Bits;
--
2.21.0.windows.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH] MdePkg/PciExpress21.h: Fix the PCIe industry standard registers
2019-07-22 6:26 [PATCH] MdePkg/PciExpress21.h: Fix the PCIe industry standard registers Javeed, Ashraf
@ 2019-07-25 14:04 ` Liming Gao
2019-07-25 14:24 ` Javeed, Ashraf
0 siblings, 1 reply; 11+ messages in thread
From: Liming Gao @ 2019-07-25 14:04 UTC (permalink / raw)
To: Javeed, Ashraf, devel@edk2.groups.io
Cc: Kinney, Michael D, Ni, Ray, Wu, Hao A
Ashraf:
So, those update base on PCI Express Base Specification Revision 4.0. If new definitions are in version 4.0, they can be added into PciExpress40.h. If the existing structure is extended, they can be kept in PciExpress21.h.
Thanks
Liming
> -----Original Message-----
> From: Javeed, Ashraf
> Sent: Monday, July 22, 2019 2:26 PM
> To: devel@edk2.groups.io
> Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Gao, Liming <liming.gao@intel.com>; Ni, Ray <ray.ni@intel.com>; Wu, Hao A
> <hao.a.wu@intel.com>
> Subject: [PATCH] MdePkg/PciExpress21.h: Fix the PCIe industry standard registers
>
> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2007
> The PCIe Device capability register #2 (PCI_REG_PCIE_DEVICE_CAPABILITY2)
> needs to be upgraded for the PCI features like - LN system CLS, 10b Tag
> completer/requester register fields, emergency power reduction support
> and initialization requirement, and FRS support.
>
> The PCIe Device Control register #2 (PCI_REG_PCIE_DEVICE_CONTROL2) needs
> to be upgraded for the - emergency power reduction request enabling and
> also the 10b Extended Tag enabling.
>
> Needs macro definitions for all the ranges of Maximum Payload Sizes and
> Maximum Read Request Sizes defined
>
> Needs macro definitions for all the ranges of Completion Timeout range
> needs to be defined.
>
> Signed-off-by: Ashraf Javeed <ashraf.javeed@intel.com>
> Cc: Michael D Kinney <michael.d.kinney@intel.com>
> Cc: Liming Gao <liming.gao@intel.com>
> Cc: Ray Ni <ray.ni@intel.com>
> Cc: Hao A Wu <hao.a.wu@intel.com>
> ---
> MdePkg/Include/IndustryStandard/PciExpress21.h | 39 ++++++++++++++++++++++++++++++++++++---
> 1 file changed, 36 insertions(+), 3 deletions(-)
>
> diff --git a/MdePkg/Include/IndustryStandard/PciExpress21.h b/MdePkg/Include/IndustryStandard/PciExpress21.h
> index d4003de74c..e652e77a1e 100644
> --- a/MdePkg/Include/IndustryStandard/PciExpress21.h
> +++ b/MdePkg/Include/IndustryStandard/PciExpress21.h
> @@ -91,6 +91,24 @@ typedef union {
> UINT16 Uint16;
> } PCI_REG_PCIE_DEVICE_CONTROL;
>
> +#define PCIE_MAX_PAYLOAD_SIZE_128B 0
> +#define PCIE_MAX_PAYLOAD_SIZE_256B 1
> +#define PCIE_MAX_PAYLOAD_SIZE_512B 2
> +#define PCIE_MAX_PAYLOAD_SIZE_1024B 3
> +#define PCIE_MAX_PAYLOAD_SIZE_2048B 4
> +#define PCIE_MAX_PAYLOAD_SIZE_4096B 5
> +#define PCIE_MAX_PAYLOAD_SIZE_RVSD1 6
> +#define PCIE_MAX_PAYLOAD_SIZE_RVSD2 7
> +
> +#define PCIE_MAX_READ_REQ_SIZE_128B 0
> +#define PCIE_MAX_READ_REQ_SIZE_256B 1
> +#define PCIE_MAX_READ_REQ_SIZE_512B 2
> +#define PCIE_MAX_READ_REQ_SIZE_1024B 3
> +#define PCIE_MAX_READ_REQ_SIZE_2048B 4
> +#define PCIE_MAX_READ_REQ_SIZE_4096B 5
> +#define PCIE_MAX_READ_REQ_SIZE_RVSD1 6
> +#define PCIE_MAX_READ_REQ_SIZE_RVSD2 7
> +
> typedef union {
> struct {
> UINT16 CorrectableError : 1;
> @@ -250,16 +268,30 @@ typedef union {
> UINT32 NoRoEnabledPrPrPassing : 1;
> UINT32 LtrMechanism : 1;
> UINT32 TphCompleter : 2;
> - UINT32 Reserved : 4;
> + UINT32 LnSystemCLS : 2;
> + UINT32 TenBitTagCompleterSupported : 1;
> + UINT32 TenBitTagRequesterSupported : 1;
> UINT32 Obff : 2;
> UINT32 ExtendedFmtField : 1;
> UINT32 EndEndTlpPrefix : 1;
> UINT32 MaxEndEndTlpPrefixes : 2;
> - UINT32 Reserved2 : 8;
> + UINT32 EmergencyPowerReductionSupported : 2;
> + UINT32 EmergencyPowerReductionInitializationRequired : 1;
> + UINT32 Reserved : 4;
> + UINT32 FrsSupported : 1;
> } Bits;
> UINT32 Uint32;
> } PCI_REG_PCIE_DEVICE_CAPABILITY2;
>
> +#define PCIE_COMPLETION_TIMEOUT_NOT_SUPPORTED 0
> +#define PCIE_COMPLETION_TIMEOUT_RANGE_A_SUPPORTED 1
> +#define PCIE_COMPLETION_TIMEOUT_RANGE_B_SUPPORTED 2
> +#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_SUPPORTED 3
> +#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_SUPPORTED 6
> +#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_SUPPORTED 7
> +#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_D_SUPPORTED 14
> +#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_D_SUPPORTED 15
> +
> #define PCIE_DEVICE_CAPABILITY_OBFF_MESSAGE BIT0
> #define PCIE_DEVICE_CAPABILITY_OBFF_WAKE BIT1
>
> @@ -273,7 +305,8 @@ typedef union {
> UINT16 IdoRequest : 1;
> UINT16 IdoCompletion : 1;
> UINT16 LtrMechanism : 2;
> - UINT16 Reserved : 2;
> + UINT16 EmergencyPowerReductionRequest : 1;
> + UINT16 TenBitTagRequesterEnable : 1;
> UINT16 Obff : 2;
> UINT16 EndEndTlpPrefixBlocking : 1;
> } Bits;
> --
> 2.21.0.windows.1
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] MdePkg/PciExpress21.h: Fix the PCIe industry standard registers
2019-07-25 14:04 ` Liming Gao
@ 2019-07-25 14:24 ` Javeed, Ashraf
2019-07-25 14:35 ` Liming Gao
0 siblings, 1 reply; 11+ messages in thread
From: Javeed, Ashraf @ 2019-07-25 14:24 UTC (permalink / raw)
To: Gao, Liming, devel@edk2.groups.io; +Cc: Kinney, Michael D, Ni, Ray, Wu, Hao A
Liming,
The existing structure are extended in PCI Express Base Specification Revision 4; hence I have made the change in PciExpress21.h.
Thanks
Ashraf
> -----Original Message-----
> From: Gao, Liming
> Sent: Thursday, July 25, 2019 7:35 PM
> To: Javeed, Ashraf <ashraf.javeed@intel.com>; devel@edk2.groups.io
> Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Ni, Ray
> <ray.ni@intel.com>; Wu, Hao A <hao.a.wu@intel.com>
> Subject: RE: [PATCH] MdePkg/PciExpress21.h: Fix the PCIe industry standard
> registers
>
> Ashraf:
> So, those update base on PCI Express Base Specification Revision 4.0. If new
> definitions are in version 4.0, they can be added into PciExpress40.h. If the
> existing structure is extended, they can be kept in PciExpress21.h.
>
> Thanks
> Liming
> > -----Original Message-----
> > From: Javeed, Ashraf
> > Sent: Monday, July 22, 2019 2:26 PM
> > To: devel@edk2.groups.io
> > Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Gao, Liming
> > <liming.gao@intel.com>; Ni, Ray <ray.ni@intel.com>; Wu, Hao A
> > <hao.a.wu@intel.com>
> > Subject: [PATCH] MdePkg/PciExpress21.h: Fix the PCIe industry standard
> > registers
> >
> > BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2007
> > The PCIe Device capability register #2
> > (PCI_REG_PCIE_DEVICE_CAPABILITY2) needs to be upgraded for the PCI
> > features like - LN system CLS, 10b Tag completer/requester register
> > fields, emergency power reduction support and initialization requirement, and
> FRS support.
> >
> > The PCIe Device Control register #2 (PCI_REG_PCIE_DEVICE_CONTROL2)
> > needs to be upgraded for the - emergency power reduction request
> > enabling and also the 10b Extended Tag enabling.
> >
> > Needs macro definitions for all the ranges of Maximum Payload Sizes
> > and Maximum Read Request Sizes defined
> >
> > Needs macro definitions for all the ranges of Completion Timeout range
> > needs to be defined.
> >
> > Signed-off-by: Ashraf Javeed <ashraf.javeed@intel.com>
> > Cc: Michael D Kinney <michael.d.kinney@intel.com>
> > Cc: Liming Gao <liming.gao@intel.com>
> > Cc: Ray Ni <ray.ni@intel.com>
> > Cc: Hao A Wu <hao.a.wu@intel.com>
> > ---
> > MdePkg/Include/IndustryStandard/PciExpress21.h | 39
> > ++++++++++++++++++++++++++++++++++++---
> > 1 file changed, 36 insertions(+), 3 deletions(-)
> >
> > diff --git a/MdePkg/Include/IndustryStandard/PciExpress21.h
> > b/MdePkg/Include/IndustryStandard/PciExpress21.h
> > index d4003de74c..e652e77a1e 100644
> > --- a/MdePkg/Include/IndustryStandard/PciExpress21.h
> > +++ b/MdePkg/Include/IndustryStandard/PciExpress21.h
> > @@ -91,6 +91,24 @@ typedef union {
> > UINT16 Uint16;
> > } PCI_REG_PCIE_DEVICE_CONTROL;
> >
> > +#define PCIE_MAX_PAYLOAD_SIZE_128B 0
> > +#define PCIE_MAX_PAYLOAD_SIZE_256B 1
> > +#define PCIE_MAX_PAYLOAD_SIZE_512B 2
> > +#define PCIE_MAX_PAYLOAD_SIZE_1024B 3 #define
> > +PCIE_MAX_PAYLOAD_SIZE_2048B 4 #define
> PCIE_MAX_PAYLOAD_SIZE_4096B 5
> > +#define PCIE_MAX_PAYLOAD_SIZE_RVSD1 6 #define
> > +PCIE_MAX_PAYLOAD_SIZE_RVSD2 7
> > +
> > +#define PCIE_MAX_READ_REQ_SIZE_128B 0
> > +#define PCIE_MAX_READ_REQ_SIZE_256B 1
> > +#define PCIE_MAX_READ_REQ_SIZE_512B 2
> > +#define PCIE_MAX_READ_REQ_SIZE_1024B 3
> > +#define PCIE_MAX_READ_REQ_SIZE_2048B 4
> > +#define PCIE_MAX_READ_REQ_SIZE_4096B 5
> > +#define PCIE_MAX_READ_REQ_SIZE_RVSD1 6
> > +#define PCIE_MAX_READ_REQ_SIZE_RVSD2 7
> > +
> > typedef union {
> > struct {
> > UINT16 CorrectableError : 1;
> > @@ -250,16 +268,30 @@ typedef union {
> > UINT32 NoRoEnabledPrPrPassing : 1;
> > UINT32 LtrMechanism : 1;
> > UINT32 TphCompleter : 2;
> > - UINT32 Reserved : 4;
> > + UINT32 LnSystemCLS : 2;
> > + UINT32 TenBitTagCompleterSupported : 1;
> > + UINT32 TenBitTagRequesterSupported : 1;
> > UINT32 Obff : 2;
> > UINT32 ExtendedFmtField : 1;
> > UINT32 EndEndTlpPrefix : 1;
> > UINT32 MaxEndEndTlpPrefixes : 2;
> > - UINT32 Reserved2 : 8;
> > + UINT32 EmergencyPowerReductionSupported : 2;
> > + UINT32 EmergencyPowerReductionInitializationRequired : 1;
> > + UINT32 Reserved : 4;
> > + UINT32 FrsSupported : 1;
> > } Bits;
> > UINT32 Uint32;
> > } PCI_REG_PCIE_DEVICE_CAPABILITY2;
> >
> > +#define PCIE_COMPLETION_TIMEOUT_NOT_SUPPORTED 0
> > +#define PCIE_COMPLETION_TIMEOUT_RANGE_A_SUPPORTED 1
> > +#define PCIE_COMPLETION_TIMEOUT_RANGE_B_SUPPORTED 2
> > +#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_SUPPORTED 3
> > +#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_SUPPORTED 6
> > +#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_SUPPORTED 7
> > +#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_D_SUPPORTED 14
> > +#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_D_SUPPORTED 15
> > +
> > #define PCIE_DEVICE_CAPABILITY_OBFF_MESSAGE BIT0
> > #define PCIE_DEVICE_CAPABILITY_OBFF_WAKE BIT1
> >
> > @@ -273,7 +305,8 @@ typedef union {
> > UINT16 IdoRequest : 1;
> > UINT16 IdoCompletion : 1;
> > UINT16 LtrMechanism : 2;
> > - UINT16 Reserved : 2;
> > + UINT16 EmergencyPowerReductionRequest : 1;
> > + UINT16 TenBitTagRequesterEnable : 1;
> > UINT16 Obff : 2;
> > UINT16 EndEndTlpPrefixBlocking : 1;
> > } Bits;
> > --
> > 2.21.0.windows.1
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] MdePkg/PciExpress21.h: Fix the PCIe industry standard registers
2019-07-25 14:24 ` Javeed, Ashraf
@ 2019-07-25 14:35 ` Liming Gao
2019-07-25 15:29 ` Javeed, Ashraf
0 siblings, 1 reply; 11+ messages in thread
From: Liming Gao @ 2019-07-25 14:35 UTC (permalink / raw)
To: Javeed, Ashraf, devel@edk2.groups.io
Cc: Kinney, Michael D, Ni, Ray, Wu, Hao A
I agree the structure update in PciExpress21.h. I also see some new macro definitions. Can they be added to PciExpress40.h, for example:
#define PCIE_MAX_PAYLOAD_SIZE_128B 0
#define PCIE_MAX_PAYLOAD_SIZE_256B 1
#define PCIE_MAX_PAYLOAD_SIZE_512B 2
#define PCIE_MAX_PAYLOAD_SIZE_1024B 3
#define PCIE_MAX_PAYLOAD_SIZE_2048B 4
#define PCIE_MAX_PAYLOAD_SIZE_4096B 5
#define PCIE_MAX_PAYLOAD_SIZE_RVSD1 6
#define PCIE_MAX_PAYLOAD_SIZE_RVSD2 7
#define PCIE_MAX_READ_REQ_SIZE_128B 0
#define PCIE_MAX_READ_REQ_SIZE_256B 1
#define PCIE_MAX_READ_REQ_SIZE_512B 2
#define PCIE_MAX_READ_REQ_SIZE_1024B 3
#define PCIE_MAX_READ_REQ_SIZE_2048B 4
#define PCIE_MAX_READ_REQ_SIZE_4096B 5
#define PCIE_MAX_READ_REQ_SIZE_RVSD1 6
#define PCIE_MAX_READ_REQ_SIZE_RVSD2 7
Thanks
Liming
> -----Original Message-----
> From: Javeed, Ashraf
> Sent: Thursday, July 25, 2019 10:24 PM
> To: Gao, Liming <liming.gao@intel.com>; devel@edk2.groups.io
> Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Ni, Ray <ray.ni@intel.com>; Wu, Hao A <hao.a.wu@intel.com>
> Subject: RE: [PATCH] MdePkg/PciExpress21.h: Fix the PCIe industry standard registers
>
> Liming,
> The existing structure are extended in PCI Express Base Specification Revision 4; hence I have made the change in PciExpress21.h.
>
> Thanks
> Ashraf
>
> > -----Original Message-----
> > From: Gao, Liming
> > Sent: Thursday, July 25, 2019 7:35 PM
> > To: Javeed, Ashraf <ashraf.javeed@intel.com>; devel@edk2.groups.io
> > Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Ni, Ray
> > <ray.ni@intel.com>; Wu, Hao A <hao.a.wu@intel.com>
> > Subject: RE: [PATCH] MdePkg/PciExpress21.h: Fix the PCIe industry standard
> > registers
> >
> > Ashraf:
> > So, those update base on PCI Express Base Specification Revision 4.0. If new
> > definitions are in version 4.0, they can be added into PciExpress40.h. If the
> > existing structure is extended, they can be kept in PciExpress21.h.
> >
> > Thanks
> > Liming
> > > -----Original Message-----
> > > From: Javeed, Ashraf
> > > Sent: Monday, July 22, 2019 2:26 PM
> > > To: devel@edk2.groups.io
> > > Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Gao, Liming
> > > <liming.gao@intel.com>; Ni, Ray <ray.ni@intel.com>; Wu, Hao A
> > > <hao.a.wu@intel.com>
> > > Subject: [PATCH] MdePkg/PciExpress21.h: Fix the PCIe industry standard
> > > registers
> > >
> > > BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2007
> > > The PCIe Device capability register #2
> > > (PCI_REG_PCIE_DEVICE_CAPABILITY2) needs to be upgraded for the PCI
> > > features like - LN system CLS, 10b Tag completer/requester register
> > > fields, emergency power reduction support and initialization requirement, and
> > FRS support.
> > >
> > > The PCIe Device Control register #2 (PCI_REG_PCIE_DEVICE_CONTROL2)
> > > needs to be upgraded for the - emergency power reduction request
> > > enabling and also the 10b Extended Tag enabling.
> > >
> > > Needs macro definitions for all the ranges of Maximum Payload Sizes
> > > and Maximum Read Request Sizes defined
> > >
> > > Needs macro definitions for all the ranges of Completion Timeout range
> > > needs to be defined.
> > >
> > > Signed-off-by: Ashraf Javeed <ashraf.javeed@intel.com>
> > > Cc: Michael D Kinney <michael.d.kinney@intel.com>
> > > Cc: Liming Gao <liming.gao@intel.com>
> > > Cc: Ray Ni <ray.ni@intel.com>
> > > Cc: Hao A Wu <hao.a.wu@intel.com>
> > > ---
> > > MdePkg/Include/IndustryStandard/PciExpress21.h | 39
> > > ++++++++++++++++++++++++++++++++++++---
> > > 1 file changed, 36 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/MdePkg/Include/IndustryStandard/PciExpress21.h
> > > b/MdePkg/Include/IndustryStandard/PciExpress21.h
> > > index d4003de74c..e652e77a1e 100644
> > > --- a/MdePkg/Include/IndustryStandard/PciExpress21.h
> > > +++ b/MdePkg/Include/IndustryStandard/PciExpress21.h
> > > @@ -91,6 +91,24 @@ typedef union {
> > > UINT16 Uint16;
> > > } PCI_REG_PCIE_DEVICE_CONTROL;
> > >
> > > +#define PCIE_MAX_PAYLOAD_SIZE_128B 0
> > > +#define PCIE_MAX_PAYLOAD_SIZE_256B 1
> > > +#define PCIE_MAX_PAYLOAD_SIZE_512B 2
> > > +#define PCIE_MAX_PAYLOAD_SIZE_1024B 3 #define
> > > +PCIE_MAX_PAYLOAD_SIZE_2048B 4 #define
> > PCIE_MAX_PAYLOAD_SIZE_4096B 5
> > > +#define PCIE_MAX_PAYLOAD_SIZE_RVSD1 6 #define
> > > +PCIE_MAX_PAYLOAD_SIZE_RVSD2 7
> > > +
> > > +#define PCIE_MAX_READ_REQ_SIZE_128B 0
> > > +#define PCIE_MAX_READ_REQ_SIZE_256B 1
> > > +#define PCIE_MAX_READ_REQ_SIZE_512B 2
> > > +#define PCIE_MAX_READ_REQ_SIZE_1024B 3
> > > +#define PCIE_MAX_READ_REQ_SIZE_2048B 4
> > > +#define PCIE_MAX_READ_REQ_SIZE_4096B 5
> > > +#define PCIE_MAX_READ_REQ_SIZE_RVSD1 6
> > > +#define PCIE_MAX_READ_REQ_SIZE_RVSD2 7
> > > +
> > > typedef union {
> > > struct {
> > > UINT16 CorrectableError : 1;
> > > @@ -250,16 +268,30 @@ typedef union {
> > > UINT32 NoRoEnabledPrPrPassing : 1;
> > > UINT32 LtrMechanism : 1;
> > > UINT32 TphCompleter : 2;
> > > - UINT32 Reserved : 4;
> > > + UINT32 LnSystemCLS : 2;
> > > + UINT32 TenBitTagCompleterSupported : 1;
> > > + UINT32 TenBitTagRequesterSupported : 1;
> > > UINT32 Obff : 2;
> > > UINT32 ExtendedFmtField : 1;
> > > UINT32 EndEndTlpPrefix : 1;
> > > UINT32 MaxEndEndTlpPrefixes : 2;
> > > - UINT32 Reserved2 : 8;
> > > + UINT32 EmergencyPowerReductionSupported : 2;
> > > + UINT32 EmergencyPowerReductionInitializationRequired : 1;
> > > + UINT32 Reserved : 4;
> > > + UINT32 FrsSupported : 1;
> > > } Bits;
> > > UINT32 Uint32;
> > > } PCI_REG_PCIE_DEVICE_CAPABILITY2;
> > >
> > > +#define PCIE_COMPLETION_TIMEOUT_NOT_SUPPORTED 0
> > > +#define PCIE_COMPLETION_TIMEOUT_RANGE_A_SUPPORTED 1
> > > +#define PCIE_COMPLETION_TIMEOUT_RANGE_B_SUPPORTED 2
> > > +#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_SUPPORTED 3
> > > +#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_SUPPORTED 6
> > > +#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_SUPPORTED 7
> > > +#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_D_SUPPORTED 14
> > > +#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_D_SUPPORTED 15
> > > +
> > > #define PCIE_DEVICE_CAPABILITY_OBFF_MESSAGE BIT0
> > > #define PCIE_DEVICE_CAPABILITY_OBFF_WAKE BIT1
> > >
> > > @@ -273,7 +305,8 @@ typedef union {
> > > UINT16 IdoRequest : 1;
> > > UINT16 IdoCompletion : 1;
> > > UINT16 LtrMechanism : 2;
> > > - UINT16 Reserved : 2;
> > > + UINT16 EmergencyPowerReductionRequest : 1;
> > > + UINT16 TenBitTagRequesterEnable : 1;
> > > UINT16 Obff : 2;
> > > UINT16 EndEndTlpPrefixBlocking : 1;
> > > } Bits;
> > > --
> > > 2.21.0.windows.1
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] MdePkg/PciExpress21.h: Fix the PCIe industry standard registers
2019-07-25 14:35 ` Liming Gao
@ 2019-07-25 15:29 ` Javeed, Ashraf
2019-07-25 15:35 ` Liming Gao
0 siblings, 1 reply; 11+ messages in thread
From: Javeed, Ashraf @ 2019-07-25 15:29 UTC (permalink / raw)
To: Gao, Liming, devel@edk2.groups.io; +Cc: Kinney, Michael D, Ni, Ray, Wu, Hao A
These new macros definitions define PCI attributes which exist in the PCI Express Base Specification Revision 2.1; hence placing this in the PciExpress21.h align with the specification revision.
Thanks
Ashraf
> -----Original Message-----
> From: Gao, Liming
> Sent: Thursday, July 25, 2019 8:05 PM
> To: Javeed, Ashraf <ashraf.javeed@intel.com>; devel@edk2.groups.io
> Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Ni, Ray
> <ray.ni@intel.com>; Wu, Hao A <hao.a.wu@intel.com>
> Subject: RE: [PATCH] MdePkg/PciExpress21.h: Fix the PCIe industry standard
> registers
>
> I agree the structure update in PciExpress21.h. I also see some new macro
> definitions. Can they be added to PciExpress40.h, for example:
>
> #define PCIE_MAX_PAYLOAD_SIZE_128B 0
> #define PCIE_MAX_PAYLOAD_SIZE_256B 1
> #define PCIE_MAX_PAYLOAD_SIZE_512B 2
> #define PCIE_MAX_PAYLOAD_SIZE_1024B 3
> #define PCIE_MAX_PAYLOAD_SIZE_2048B 4
> #define PCIE_MAX_PAYLOAD_SIZE_4096B 5
> #define PCIE_MAX_PAYLOAD_SIZE_RVSD1 6
> #define PCIE_MAX_PAYLOAD_SIZE_RVSD2 7
>
> #define PCIE_MAX_READ_REQ_SIZE_128B 0
> #define PCIE_MAX_READ_REQ_SIZE_256B 1
> #define PCIE_MAX_READ_REQ_SIZE_512B 2
> #define PCIE_MAX_READ_REQ_SIZE_1024B 3
> #define PCIE_MAX_READ_REQ_SIZE_2048B 4
> #define PCIE_MAX_READ_REQ_SIZE_4096B 5
> #define PCIE_MAX_READ_REQ_SIZE_RVSD1 6
> #define PCIE_MAX_READ_REQ_SIZE_RVSD2 7
>
> Thanks
> Liming
> > -----Original Message-----
> > From: Javeed, Ashraf
> > Sent: Thursday, July 25, 2019 10:24 PM
> > To: Gao, Liming <liming.gao@intel.com>; devel@edk2.groups.io
> > Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Ni, Ray
> > <ray.ni@intel.com>; Wu, Hao A <hao.a.wu@intel.com>
> > Subject: RE: [PATCH] MdePkg/PciExpress21.h: Fix the PCIe industry
> > standard registers
> >
> > Liming,
> > The existing structure are extended in PCI Express Base Specification Revision
> 4; hence I have made the change in PciExpress21.h.
> >
> > Thanks
> > Ashraf
> >
> > > -----Original Message-----
> > > From: Gao, Liming
> > > Sent: Thursday, July 25, 2019 7:35 PM
> > > To: Javeed, Ashraf <ashraf.javeed@intel.com>; devel@edk2.groups.io
> > > Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Ni, Ray
> > > <ray.ni@intel.com>; Wu, Hao A <hao.a.wu@intel.com>
> > > Subject: RE: [PATCH] MdePkg/PciExpress21.h: Fix the PCIe industry
> > > standard registers
> > >
> > > Ashraf:
> > > So, those update base on PCI Express Base Specification Revision
> > > 4.0. If new definitions are in version 4.0, they can be added into
> > > PciExpress40.h. If the existing structure is extended, they can be kept in
> PciExpress21.h.
> > >
> > > Thanks
> > > Liming
> > > > -----Original Message-----
> > > > From: Javeed, Ashraf
> > > > Sent: Monday, July 22, 2019 2:26 PM
> > > > To: devel@edk2.groups.io
> > > > Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Gao, Liming
> > > > <liming.gao@intel.com>; Ni, Ray <ray.ni@intel.com>; Wu, Hao A
> > > > <hao.a.wu@intel.com>
> > > > Subject: [PATCH] MdePkg/PciExpress21.h: Fix the PCIe industry
> > > > standard registers
> > > >
> > > > BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2007
> > > > The PCIe Device capability register #2
> > > > (PCI_REG_PCIE_DEVICE_CAPABILITY2) needs to be upgraded for the
> > > > PCI features like - LN system CLS, 10b Tag completer/requester
> > > > register fields, emergency power reduction support and
> > > > initialization requirement, and
> > > FRS support.
> > > >
> > > > The PCIe Device Control register #2 (PCI_REG_PCIE_DEVICE_CONTROL2)
> > > > needs to be upgraded for the - emergency power reduction request
> > > > enabling and also the 10b Extended Tag enabling.
> > > >
> > > > Needs macro definitions for all the ranges of Maximum Payload
> > > > Sizes and Maximum Read Request Sizes defined
> > > >
> > > > Needs macro definitions for all the ranges of Completion Timeout
> > > > range needs to be defined.
> > > >
> > > > Signed-off-by: Ashraf Javeed <ashraf.javeed@intel.com>
> > > > Cc: Michael D Kinney <michael.d.kinney@intel.com>
> > > > Cc: Liming Gao <liming.gao@intel.com>
> > > > Cc: Ray Ni <ray.ni@intel.com>
> > > > Cc: Hao A Wu <hao.a.wu@intel.com>
> > > > ---
> > > > MdePkg/Include/IndustryStandard/PciExpress21.h | 39
> > > > ++++++++++++++++++++++++++++++++++++---
> > > > 1 file changed, 36 insertions(+), 3 deletions(-)
> > > >
> > > > diff --git a/MdePkg/Include/IndustryStandard/PciExpress21.h
> > > > b/MdePkg/Include/IndustryStandard/PciExpress21.h
> > > > index d4003de74c..e652e77a1e 100644
> > > > --- a/MdePkg/Include/IndustryStandard/PciExpress21.h
> > > > +++ b/MdePkg/Include/IndustryStandard/PciExpress21.h
> > > > @@ -91,6 +91,24 @@ typedef union {
> > > > UINT16 Uint16;
> > > > } PCI_REG_PCIE_DEVICE_CONTROL;
> > > >
> > > > +#define PCIE_MAX_PAYLOAD_SIZE_128B 0
> > > > +#define PCIE_MAX_PAYLOAD_SIZE_256B 1
> > > > +#define PCIE_MAX_PAYLOAD_SIZE_512B 2
> > > > +#define PCIE_MAX_PAYLOAD_SIZE_1024B 3 #define
> > > > +PCIE_MAX_PAYLOAD_SIZE_2048B 4 #define
> > > PCIE_MAX_PAYLOAD_SIZE_4096B 5
> > > > +#define PCIE_MAX_PAYLOAD_SIZE_RVSD1 6 #define
> > > > +PCIE_MAX_PAYLOAD_SIZE_RVSD2 7
> > > > +
> > > > +#define PCIE_MAX_READ_REQ_SIZE_128B 0
> > > > +#define PCIE_MAX_READ_REQ_SIZE_256B 1
> > > > +#define PCIE_MAX_READ_REQ_SIZE_512B 2
> > > > +#define PCIE_MAX_READ_REQ_SIZE_1024B 3
> > > > +#define PCIE_MAX_READ_REQ_SIZE_2048B 4
> > > > +#define PCIE_MAX_READ_REQ_SIZE_4096B 5
> > > > +#define PCIE_MAX_READ_REQ_SIZE_RVSD1 6
> > > > +#define PCIE_MAX_READ_REQ_SIZE_RVSD2 7
> > > > +
> > > > typedef union {
> > > > struct {
> > > > UINT16 CorrectableError : 1;
> > > > @@ -250,16 +268,30 @@ typedef union {
> > > > UINT32 NoRoEnabledPrPrPassing : 1;
> > > > UINT32 LtrMechanism : 1;
> > > > UINT32 TphCompleter : 2;
> > > > - UINT32 Reserved : 4;
> > > > + UINT32 LnSystemCLS : 2;
> > > > + UINT32 TenBitTagCompleterSupported : 1;
> > > > + UINT32 TenBitTagRequesterSupported : 1;
> > > > UINT32 Obff : 2;
> > > > UINT32 ExtendedFmtField : 1;
> > > > UINT32 EndEndTlpPrefix : 1;
> > > > UINT32 MaxEndEndTlpPrefixes : 2;
> > > > - UINT32 Reserved2 : 8;
> > > > + UINT32 EmergencyPowerReductionSupported : 2;
> > > > + UINT32 EmergencyPowerReductionInitializationRequired : 1;
> > > > + UINT32 Reserved : 4;
> > > > + UINT32 FrsSupported : 1;
> > > > } Bits;
> > > > UINT32 Uint32;
> > > > } PCI_REG_PCIE_DEVICE_CAPABILITY2;
> > > >
> > > > +#define PCIE_COMPLETION_TIMEOUT_NOT_SUPPORTED 0
> > > > +#define PCIE_COMPLETION_TIMEOUT_RANGE_A_SUPPORTED 1
> > > > +#define PCIE_COMPLETION_TIMEOUT_RANGE_B_SUPPORTED 2
> > > > +#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_SUPPORTED 3
> > > > +#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_SUPPORTED 6
> > > > +#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_SUPPORTED 7
> > > > +#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_D_SUPPORTED 14
> > > > +#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_D_SUPPORTED 15
> > > > +
> > > > #define PCIE_DEVICE_CAPABILITY_OBFF_MESSAGE BIT0
> > > > #define PCIE_DEVICE_CAPABILITY_OBFF_WAKE BIT1
> > > >
> > > > @@ -273,7 +305,8 @@ typedef union {
> > > > UINT16 IdoRequest : 1;
> > > > UINT16 IdoCompletion : 1;
> > > > UINT16 LtrMechanism : 2;
> > > > - UINT16 Reserved : 2;
> > > > + UINT16 EmergencyPowerReductionRequest : 1;
> > > > + UINT16 TenBitTagRequesterEnable : 1;
> > > > UINT16 Obff : 2;
> > > > UINT16 EndEndTlpPrefixBlocking : 1;
> > > > } Bits;
> > > > --
> > > > 2.21.0.windows.1
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] MdePkg/PciExpress21.h: Fix the PCIe industry standard registers
2019-07-25 15:29 ` Javeed, Ashraf
@ 2019-07-25 15:35 ` Liming Gao
2019-07-25 16:04 ` Javeed, Ashraf
0 siblings, 1 reply; 11+ messages in thread
From: Liming Gao @ 2019-07-25 15:35 UTC (permalink / raw)
To: Javeed, Ashraf, devel@edk2.groups.io
Cc: Kinney, Michael D, Ni, Ray, Wu, Hao A
That make sense. In the commit message, can you update the message to describe which change bases on PCI Express Base Specification Revision 4.0?
Thanks
Liming
> -----Original Message-----
> From: Javeed, Ashraf
> Sent: Thursday, July 25, 2019 11:30 PM
> To: Gao, Liming <liming.gao@intel.com>; devel@edk2.groups.io
> Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Ni, Ray <ray.ni@intel.com>; Wu, Hao A <hao.a.wu@intel.com>
> Subject: RE: [PATCH] MdePkg/PciExpress21.h: Fix the PCIe industry standard registers
>
> These new macros definitions define PCI attributes which exist in the PCI Express Base Specification Revision 2.1; hence placing this in the
> PciExpress21.h align with the specification revision.
>
> Thanks
> Ashraf
>
> > -----Original Message-----
> > From: Gao, Liming
> > Sent: Thursday, July 25, 2019 8:05 PM
> > To: Javeed, Ashraf <ashraf.javeed@intel.com>; devel@edk2.groups.io
> > Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Ni, Ray
> > <ray.ni@intel.com>; Wu, Hao A <hao.a.wu@intel.com>
> > Subject: RE: [PATCH] MdePkg/PciExpress21.h: Fix the PCIe industry standard
> > registers
> >
> > I agree the structure update in PciExpress21.h. I also see some new macro
> > definitions. Can they be added to PciExpress40.h, for example:
> >
> > #define PCIE_MAX_PAYLOAD_SIZE_128B 0
> > #define PCIE_MAX_PAYLOAD_SIZE_256B 1
> > #define PCIE_MAX_PAYLOAD_SIZE_512B 2
> > #define PCIE_MAX_PAYLOAD_SIZE_1024B 3
> > #define PCIE_MAX_PAYLOAD_SIZE_2048B 4
> > #define PCIE_MAX_PAYLOAD_SIZE_4096B 5
> > #define PCIE_MAX_PAYLOAD_SIZE_RVSD1 6
> > #define PCIE_MAX_PAYLOAD_SIZE_RVSD2 7
> >
> > #define PCIE_MAX_READ_REQ_SIZE_128B 0
> > #define PCIE_MAX_READ_REQ_SIZE_256B 1
> > #define PCIE_MAX_READ_REQ_SIZE_512B 2
> > #define PCIE_MAX_READ_REQ_SIZE_1024B 3
> > #define PCIE_MAX_READ_REQ_SIZE_2048B 4
> > #define PCIE_MAX_READ_REQ_SIZE_4096B 5
> > #define PCIE_MAX_READ_REQ_SIZE_RVSD1 6
> > #define PCIE_MAX_READ_REQ_SIZE_RVSD2 7
> >
> > Thanks
> > Liming
> > > -----Original Message-----
> > > From: Javeed, Ashraf
> > > Sent: Thursday, July 25, 2019 10:24 PM
> > > To: Gao, Liming <liming.gao@intel.com>; devel@edk2.groups.io
> > > Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Ni, Ray
> > > <ray.ni@intel.com>; Wu, Hao A <hao.a.wu@intel.com>
> > > Subject: RE: [PATCH] MdePkg/PciExpress21.h: Fix the PCIe industry
> > > standard registers
> > >
> > > Liming,
> > > The existing structure are extended in PCI Express Base Specification Revision
> > 4; hence I have made the change in PciExpress21.h.
> > >
> > > Thanks
> > > Ashraf
> > >
> > > > -----Original Message-----
> > > > From: Gao, Liming
> > > > Sent: Thursday, July 25, 2019 7:35 PM
> > > > To: Javeed, Ashraf <ashraf.javeed@intel.com>; devel@edk2.groups.io
> > > > Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Ni, Ray
> > > > <ray.ni@intel.com>; Wu, Hao A <hao.a.wu@intel.com>
> > > > Subject: RE: [PATCH] MdePkg/PciExpress21.h: Fix the PCIe industry
> > > > standard registers
> > > >
> > > > Ashraf:
> > > > So, those update base on PCI Express Base Specification Revision
> > > > 4.0. If new definitions are in version 4.0, they can be added into
> > > > PciExpress40.h. If the existing structure is extended, they can be kept in
> > PciExpress21.h.
> > > >
> > > > Thanks
> > > > Liming
> > > > > -----Original Message-----
> > > > > From: Javeed, Ashraf
> > > > > Sent: Monday, July 22, 2019 2:26 PM
> > > > > To: devel@edk2.groups.io
> > > > > Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Gao, Liming
> > > > > <liming.gao@intel.com>; Ni, Ray <ray.ni@intel.com>; Wu, Hao A
> > > > > <hao.a.wu@intel.com>
> > > > > Subject: [PATCH] MdePkg/PciExpress21.h: Fix the PCIe industry
> > > > > standard registers
> > > > >
> > > > > BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2007
> > > > > The PCIe Device capability register #2
> > > > > (PCI_REG_PCIE_DEVICE_CAPABILITY2) needs to be upgraded for the
> > > > > PCI features like - LN system CLS, 10b Tag completer/requester
> > > > > register fields, emergency power reduction support and
> > > > > initialization requirement, and
> > > > FRS support.
> > > > >
> > > > > The PCIe Device Control register #2 (PCI_REG_PCIE_DEVICE_CONTROL2)
> > > > > needs to be upgraded for the - emergency power reduction request
> > > > > enabling and also the 10b Extended Tag enabling.
> > > > >
> > > > > Needs macro definitions for all the ranges of Maximum Payload
> > > > > Sizes and Maximum Read Request Sizes defined
> > > > >
> > > > > Needs macro definitions for all the ranges of Completion Timeout
> > > > > range needs to be defined.
> > > > >
> > > > > Signed-off-by: Ashraf Javeed <ashraf.javeed@intel.com>
> > > > > Cc: Michael D Kinney <michael.d.kinney@intel.com>
> > > > > Cc: Liming Gao <liming.gao@intel.com>
> > > > > Cc: Ray Ni <ray.ni@intel.com>
> > > > > Cc: Hao A Wu <hao.a.wu@intel.com>
> > > > > ---
> > > > > MdePkg/Include/IndustryStandard/PciExpress21.h | 39
> > > > > ++++++++++++++++++++++++++++++++++++---
> > > > > 1 file changed, 36 insertions(+), 3 deletions(-)
> > > > >
> > > > > diff --git a/MdePkg/Include/IndustryStandard/PciExpress21.h
> > > > > b/MdePkg/Include/IndustryStandard/PciExpress21.h
> > > > > index d4003de74c..e652e77a1e 100644
> > > > > --- a/MdePkg/Include/IndustryStandard/PciExpress21.h
> > > > > +++ b/MdePkg/Include/IndustryStandard/PciExpress21.h
> > > > > @@ -91,6 +91,24 @@ typedef union {
> > > > > UINT16 Uint16;
> > > > > } PCI_REG_PCIE_DEVICE_CONTROL;
> > > > >
> > > > > +#define PCIE_MAX_PAYLOAD_SIZE_128B 0
> > > > > +#define PCIE_MAX_PAYLOAD_SIZE_256B 1
> > > > > +#define PCIE_MAX_PAYLOAD_SIZE_512B 2
> > > > > +#define PCIE_MAX_PAYLOAD_SIZE_1024B 3 #define
> > > > > +PCIE_MAX_PAYLOAD_SIZE_2048B 4 #define
> > > > PCIE_MAX_PAYLOAD_SIZE_4096B 5
> > > > > +#define PCIE_MAX_PAYLOAD_SIZE_RVSD1 6 #define
> > > > > +PCIE_MAX_PAYLOAD_SIZE_RVSD2 7
> > > > > +
> > > > > +#define PCIE_MAX_READ_REQ_SIZE_128B 0
> > > > > +#define PCIE_MAX_READ_REQ_SIZE_256B 1
> > > > > +#define PCIE_MAX_READ_REQ_SIZE_512B 2
> > > > > +#define PCIE_MAX_READ_REQ_SIZE_1024B 3
> > > > > +#define PCIE_MAX_READ_REQ_SIZE_2048B 4
> > > > > +#define PCIE_MAX_READ_REQ_SIZE_4096B 5
> > > > > +#define PCIE_MAX_READ_REQ_SIZE_RVSD1 6
> > > > > +#define PCIE_MAX_READ_REQ_SIZE_RVSD2 7
> > > > > +
> > > > > typedef union {
> > > > > struct {
> > > > > UINT16 CorrectableError : 1;
> > > > > @@ -250,16 +268,30 @@ typedef union {
> > > > > UINT32 NoRoEnabledPrPrPassing : 1;
> > > > > UINT32 LtrMechanism : 1;
> > > > > UINT32 TphCompleter : 2;
> > > > > - UINT32 Reserved : 4;
> > > > > + UINT32 LnSystemCLS : 2;
> > > > > + UINT32 TenBitTagCompleterSupported : 1;
> > > > > + UINT32 TenBitTagRequesterSupported : 1;
> > > > > UINT32 Obff : 2;
> > > > > UINT32 ExtendedFmtField : 1;
> > > > > UINT32 EndEndTlpPrefix : 1;
> > > > > UINT32 MaxEndEndTlpPrefixes : 2;
> > > > > - UINT32 Reserved2 : 8;
> > > > > + UINT32 EmergencyPowerReductionSupported : 2;
> > > > > + UINT32 EmergencyPowerReductionInitializationRequired : 1;
> > > > > + UINT32 Reserved : 4;
> > > > > + UINT32 FrsSupported : 1;
> > > > > } Bits;
> > > > > UINT32 Uint32;
> > > > > } PCI_REG_PCIE_DEVICE_CAPABILITY2;
> > > > >
> > > > > +#define PCIE_COMPLETION_TIMEOUT_NOT_SUPPORTED 0
> > > > > +#define PCIE_COMPLETION_TIMEOUT_RANGE_A_SUPPORTED 1
> > > > > +#define PCIE_COMPLETION_TIMEOUT_RANGE_B_SUPPORTED 2
> > > > > +#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_SUPPORTED 3
> > > > > +#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_SUPPORTED 6
> > > > > +#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_SUPPORTED 7
> > > > > +#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_D_SUPPORTED 14
> > > > > +#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_D_SUPPORTED 15
> > > > > +
> > > > > #define PCIE_DEVICE_CAPABILITY_OBFF_MESSAGE BIT0
> > > > > #define PCIE_DEVICE_CAPABILITY_OBFF_WAKE BIT1
> > > > >
> > > > > @@ -273,7 +305,8 @@ typedef union {
> > > > > UINT16 IdoRequest : 1;
> > > > > UINT16 IdoCompletion : 1;
> > > > > UINT16 LtrMechanism : 2;
> > > > > - UINT16 Reserved : 2;
> > > > > + UINT16 EmergencyPowerReductionRequest : 1;
> > > > > + UINT16 TenBitTagRequesterEnable : 1;
> > > > > UINT16 Obff : 2;
> > > > > UINT16 EndEndTlpPrefixBlocking : 1;
> > > > > } Bits;
> > > > > --
> > > > > 2.21.0.windows.1
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] MdePkg/PciExpress21.h: Fix the PCIe industry standard registers
2019-07-25 15:35 ` Liming Gao
@ 2019-07-25 16:04 ` Javeed, Ashraf
2019-07-25 16:22 ` Liming Gao
0 siblings, 1 reply; 11+ messages in thread
From: Javeed, Ashraf @ 2019-07-25 16:04 UTC (permalink / raw)
To: Gao, Liming, devel@edk2.groups.io; +Cc: Kinney, Michael D, Ni, Ray, Wu, Hao A
Liming,
The following are the 2 points summarizing the changes as per spec 4, and it is already part of commit message...
> > > > > The PCIe Device capability register #2
> > > > > (PCI_REG_PCIE_DEVICE_CAPABILITY2) needs to be upgraded for
> > > > > the PCI features like - LN system CLS, 10b Tag
> > > > > completer/requester register fields, emergency power reduction
> > > > > support and initialization requirement, and
> > > > FRS support.
> > > > >
> > > > > The PCIe Device Control register #2
> > > > > (PCI_REG_PCIE_DEVICE_CONTROL2) needs to be upgraded for the -
> > > > > emergency power reduction request enabling and also the 10b Extended Tag enabling.
Thanks
Ashraf
> -----Original Message-----
> From: Gao, Liming
> Sent: Thursday, July 25, 2019 9:06 PM
> To: Javeed, Ashraf <ashraf.javeed@intel.com>; devel@edk2.groups.io
> Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Ni, Ray
> <ray.ni@intel.com>; Wu, Hao A <hao.a.wu@intel.com>
> Subject: RE: [PATCH] MdePkg/PciExpress21.h: Fix the PCIe industry standard
> registers
>
> That make sense. In the commit message, can you update the message to
> describe which change bases on PCI Express Base Specification Revision 4.0?
>
> Thanks
> Liming
> > -----Original Message-----
> > From: Javeed, Ashraf
> > Sent: Thursday, July 25, 2019 11:30 PM
> > To: Gao, Liming <liming.gao@intel.com>; devel@edk2.groups.io
> > Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Ni, Ray
> > <ray.ni@intel.com>; Wu, Hao A <hao.a.wu@intel.com>
> > Subject: RE: [PATCH] MdePkg/PciExpress21.h: Fix the PCIe industry
> > standard registers
> >
> > These new macros definitions define PCI attributes which exist in the
> > PCI Express Base Specification Revision 2.1; hence placing this in the
> PciExpress21.h align with the specification revision.
> >
> > Thanks
> > Ashraf
> >
> > > -----Original Message-----
> > > From: Gao, Liming
> > > Sent: Thursday, July 25, 2019 8:05 PM
> > > To: Javeed, Ashraf <ashraf.javeed@intel.com>; devel@edk2.groups.io
> > > Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Ni, Ray
> > > <ray.ni@intel.com>; Wu, Hao A <hao.a.wu@intel.com>
> > > Subject: RE: [PATCH] MdePkg/PciExpress21.h: Fix the PCIe industry
> > > standard registers
> > >
> > > I agree the structure update in PciExpress21.h. I also see some new
> > > macro definitions. Can they be added to PciExpress40.h, for example:
> > >
> > > #define PCIE_MAX_PAYLOAD_SIZE_128B 0
> > > #define PCIE_MAX_PAYLOAD_SIZE_256B 1
> > > #define PCIE_MAX_PAYLOAD_SIZE_512B 2
> > > #define PCIE_MAX_PAYLOAD_SIZE_1024B 3 #define
> > > PCIE_MAX_PAYLOAD_SIZE_2048B 4 #define
> PCIE_MAX_PAYLOAD_SIZE_4096B
> > > 5 #define PCIE_MAX_PAYLOAD_SIZE_RVSD1 6 #define
> > > PCIE_MAX_PAYLOAD_SIZE_RVSD2 7
> > >
> > > #define PCIE_MAX_READ_REQ_SIZE_128B 0
> > > #define PCIE_MAX_READ_REQ_SIZE_256B 1
> > > #define PCIE_MAX_READ_REQ_SIZE_512B 2
> > > #define PCIE_MAX_READ_REQ_SIZE_1024B 3
> > > #define PCIE_MAX_READ_REQ_SIZE_2048B 4
> > > #define PCIE_MAX_READ_REQ_SIZE_4096B 5
> > > #define PCIE_MAX_READ_REQ_SIZE_RVSD1 6
> > > #define PCIE_MAX_READ_REQ_SIZE_RVSD2 7
> > >
> > > Thanks
> > > Liming
> > > > -----Original Message-----
> > > > From: Javeed, Ashraf
> > > > Sent: Thursday, July 25, 2019 10:24 PM
> > > > To: Gao, Liming <liming.gao@intel.com>; devel@edk2.groups.io
> > > > Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Ni, Ray
> > > > <ray.ni@intel.com>; Wu, Hao A <hao.a.wu@intel.com>
> > > > Subject: RE: [PATCH] MdePkg/PciExpress21.h: Fix the PCIe industry
> > > > standard registers
> > > >
> > > > Liming,
> > > > The existing structure are extended in PCI Express Base
> > > > Specification Revision
> > > 4; hence I have made the change in PciExpress21.h.
> > > >
> > > > Thanks
> > > > Ashraf
> > > >
> > > > > -----Original Message-----
> > > > > From: Gao, Liming
> > > > > Sent: Thursday, July 25, 2019 7:35 PM
> > > > > To: Javeed, Ashraf <ashraf.javeed@intel.com>;
> > > > > devel@edk2.groups.io
> > > > > Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Ni, Ray
> > > > > <ray.ni@intel.com>; Wu, Hao A <hao.a.wu@intel.com>
> > > > > Subject: RE: [PATCH] MdePkg/PciExpress21.h: Fix the PCIe
> > > > > industry standard registers
> > > > >
> > > > > Ashraf:
> > > > > So, those update base on PCI Express Base Specification
> > > > > Revision 4.0. If new definitions are in version 4.0, they can be
> > > > > added into PciExpress40.h. If the existing structure is
> > > > > extended, they can be kept in
> > > PciExpress21.h.
> > > > >
> > > > > Thanks
> > > > > Liming
> > > > > > -----Original Message-----
> > > > > > From: Javeed, Ashraf
> > > > > > Sent: Monday, July 22, 2019 2:26 PM
> > > > > > To: devel@edk2.groups.io
> > > > > > Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Gao,
> > > > > > Liming <liming.gao@intel.com>; Ni, Ray <ray.ni@intel.com>; Wu,
> > > > > > Hao A <hao.a.wu@intel.com>
> > > > > > Subject: [PATCH] MdePkg/PciExpress21.h: Fix the PCIe industry
> > > > > > standard registers
> > > > > >
> > > > > > BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2007
> > > > > > The PCIe Device capability register #2
> > > > > > (PCI_REG_PCIE_DEVICE_CAPABILITY2) needs to be upgraded for
> > > > > > the PCI features like - LN system CLS, 10b Tag
> > > > > > completer/requester register fields, emergency power reduction
> > > > > > support and initialization requirement, and
> > > > > FRS support.
> > > > > >
> > > > > > The PCIe Device Control register #2
> > > > > > (PCI_REG_PCIE_DEVICE_CONTROL2) needs to be upgraded for the -
> > > > > > emergency power reduction request enabling and also the 10b
> Extended Tag enabling.
> > > > > >
> > > > > > Needs macro definitions for all the ranges of Maximum Payload
> > > > > > Sizes and Maximum Read Request Sizes defined
> > > > > >
> > > > > > Needs macro definitions for all the ranges of Completion
> > > > > > Timeout range needs to be defined.
> > > > > >
> > > > > > Signed-off-by: Ashraf Javeed <ashraf.javeed@intel.com>
> > > > > > Cc: Michael D Kinney <michael.d.kinney@intel.com>
> > > > > > Cc: Liming Gao <liming.gao@intel.com>
> > > > > > Cc: Ray Ni <ray.ni@intel.com>
> > > > > > Cc: Hao A Wu <hao.a.wu@intel.com>
> > > > > > ---
> > > > > > MdePkg/Include/IndustryStandard/PciExpress21.h | 39
> > > > > > ++++++++++++++++++++++++++++++++++++---
> > > > > > 1 file changed, 36 insertions(+), 3 deletions(-)
> > > > > >
> > > > > > diff --git a/MdePkg/Include/IndustryStandard/PciExpress21.h
> > > > > > b/MdePkg/Include/IndustryStandard/PciExpress21.h
> > > > > > index d4003de74c..e652e77a1e 100644
> > > > > > --- a/MdePkg/Include/IndustryStandard/PciExpress21.h
> > > > > > +++ b/MdePkg/Include/IndustryStandard/PciExpress21.h
> > > > > > @@ -91,6 +91,24 @@ typedef union {
> > > > > > UINT16 Uint16;
> > > > > > } PCI_REG_PCIE_DEVICE_CONTROL;
> > > > > >
> > > > > > +#define PCIE_MAX_PAYLOAD_SIZE_128B 0
> > > > > > +#define PCIE_MAX_PAYLOAD_SIZE_256B 1
> > > > > > +#define PCIE_MAX_PAYLOAD_SIZE_512B 2
> > > > > > +#define PCIE_MAX_PAYLOAD_SIZE_1024B 3 #define
> > > > > > +PCIE_MAX_PAYLOAD_SIZE_2048B 4 #define
> > > > > PCIE_MAX_PAYLOAD_SIZE_4096B 5
> > > > > > +#define PCIE_MAX_PAYLOAD_SIZE_RVSD1 6 #define
> > > > > > +PCIE_MAX_PAYLOAD_SIZE_RVSD2 7
> > > > > > +
> > > > > > +#define PCIE_MAX_READ_REQ_SIZE_128B 0
> > > > > > +#define PCIE_MAX_READ_REQ_SIZE_256B 1
> > > > > > +#define PCIE_MAX_READ_REQ_SIZE_512B 2
> > > > > > +#define PCIE_MAX_READ_REQ_SIZE_1024B 3
> > > > > > +#define PCIE_MAX_READ_REQ_SIZE_2048B 4
> > > > > > +#define PCIE_MAX_READ_REQ_SIZE_4096B 5
> > > > > > +#define PCIE_MAX_READ_REQ_SIZE_RVSD1 6
> > > > > > +#define PCIE_MAX_READ_REQ_SIZE_RVSD2 7
> > > > > > +
> > > > > > typedef union {
> > > > > > struct {
> > > > > > UINT16 CorrectableError : 1; @@ -250,16 +268,30 @@
> > > > > > typedef union {
> > > > > > UINT32 NoRoEnabledPrPrPassing : 1;
> > > > > > UINT32 LtrMechanism : 1;
> > > > > > UINT32 TphCompleter : 2;
> > > > > > - UINT32 Reserved : 4;
> > > > > > + UINT32 LnSystemCLS : 2;
> > > > > > + UINT32 TenBitTagCompleterSupported : 1;
> > > > > > + UINT32 TenBitTagRequesterSupported : 1;
> > > > > > UINT32 Obff : 2;
> > > > > > UINT32 ExtendedFmtField : 1;
> > > > > > UINT32 EndEndTlpPrefix : 1;
> > > > > > UINT32 MaxEndEndTlpPrefixes : 2;
> > > > > > - UINT32 Reserved2 : 8;
> > > > > > + UINT32 EmergencyPowerReductionSupported : 2;
> > > > > > + UINT32 EmergencyPowerReductionInitializationRequired : 1;
> > > > > > + UINT32 Reserved : 4;
> > > > > > + UINT32 FrsSupported : 1;
> > > > > > } Bits;
> > > > > > UINT32 Uint32;
> > > > > > } PCI_REG_PCIE_DEVICE_CAPABILITY2;
> > > > > >
> > > > > > +#define PCIE_COMPLETION_TIMEOUT_NOT_SUPPORTED 0
> > > > > > +#define PCIE_COMPLETION_TIMEOUT_RANGE_A_SUPPORTED 1
> > > > > > +#define PCIE_COMPLETION_TIMEOUT_RANGE_B_SUPPORTED 2
> > > > > > +#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_SUPPORTED 3
> > > > > > +#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_SUPPORTED 6
> > > > > > +#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_SUPPORTED
> 7
> > > > > > +#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_D_SUPPORTED
> 14
> > > > > > +#define
> PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_D_SUPPORTED 15
> > > > > > +
> > > > > > #define PCIE_DEVICE_CAPABILITY_OBFF_MESSAGE BIT0
> > > > > > #define PCIE_DEVICE_CAPABILITY_OBFF_WAKE BIT1
> > > > > >
> > > > > > @@ -273,7 +305,8 @@ typedef union {
> > > > > > UINT16 IdoRequest : 1;
> > > > > > UINT16 IdoCompletion : 1;
> > > > > > UINT16 LtrMechanism : 2;
> > > > > > - UINT16 Reserved : 2;
> > > > > > + UINT16 EmergencyPowerReductionRequest : 1;
> > > > > > + UINT16 TenBitTagRequesterEnable : 1;
> > > > > > UINT16 Obff : 2;
> > > > > > UINT16 EndEndTlpPrefixBlocking : 1;
> > > > > > } Bits;
> > > > > > --
> > > > > > 2.21.0.windows.1
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] MdePkg/PciExpress21.h: Fix the PCIe industry standard registers
2019-07-25 16:04 ` Javeed, Ashraf
@ 2019-07-25 16:22 ` Liming Gao
0 siblings, 0 replies; 11+ messages in thread
From: Liming Gao @ 2019-07-25 16:22 UTC (permalink / raw)
To: Javeed, Ashraf, devel@edk2.groups.io
Cc: Kinney, Michael D, Ni, Ray, Wu, Hao A
Yes. I mean highlight those changes bases on PCI Express Base Specification Revision 4.0.
Otherwise, I don't know where are they from.
Thanks
Liming
> -----Original Message-----
> From: Javeed, Ashraf
> Sent: Friday, July 26, 2019 12:05 AM
> To: Gao, Liming <liming.gao@intel.com>; devel@edk2.groups.io
> Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Ni, Ray <ray.ni@intel.com>; Wu, Hao A <hao.a.wu@intel.com>
> Subject: RE: [PATCH] MdePkg/PciExpress21.h: Fix the PCIe industry standard registers
>
> Liming,
> The following are the 2 points summarizing the changes as per spec 4, and it is already part of commit message...
> > > > > > The PCIe Device capability register #2
> > > > > > (PCI_REG_PCIE_DEVICE_CAPABILITY2) needs to be upgraded for
> > > > > > the PCI features like - LN system CLS, 10b Tag
> > > > > > completer/requester register fields, emergency power reduction
> > > > > > support and initialization requirement, and
> > > > > FRS support.
> > > > > >
> > > > > > The PCIe Device Control register #2
> > > > > > (PCI_REG_PCIE_DEVICE_CONTROL2) needs to be upgraded for the -
> > > > > > emergency power reduction request enabling and also the 10b Extended Tag enabling.
>
> Thanks
> Ashraf
>
> > -----Original Message-----
> > From: Gao, Liming
> > Sent: Thursday, July 25, 2019 9:06 PM
> > To: Javeed, Ashraf <ashraf.javeed@intel.com>; devel@edk2.groups.io
> > Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Ni, Ray
> > <ray.ni@intel.com>; Wu, Hao A <hao.a.wu@intel.com>
> > Subject: RE: [PATCH] MdePkg/PciExpress21.h: Fix the PCIe industry standard
> > registers
> >
> > That make sense. In the commit message, can you update the message to
> > describe which change bases on PCI Express Base Specification Revision 4.0?
> >
> > Thanks
> > Liming
> > > -----Original Message-----
> > > From: Javeed, Ashraf
> > > Sent: Thursday, July 25, 2019 11:30 PM
> > > To: Gao, Liming <liming.gao@intel.com>; devel@edk2.groups.io
> > > Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Ni, Ray
> > > <ray.ni@intel.com>; Wu, Hao A <hao.a.wu@intel.com>
> > > Subject: RE: [PATCH] MdePkg/PciExpress21.h: Fix the PCIe industry
> > > standard registers
> > >
> > > These new macros definitions define PCI attributes which exist in the
> > > PCI Express Base Specification Revision 2.1; hence placing this in the
> > PciExpress21.h align with the specification revision.
> > >
> > > Thanks
> > > Ashraf
> > >
> > > > -----Original Message-----
> > > > From: Gao, Liming
> > > > Sent: Thursday, July 25, 2019 8:05 PM
> > > > To: Javeed, Ashraf <ashraf.javeed@intel.com>; devel@edk2.groups.io
> > > > Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Ni, Ray
> > > > <ray.ni@intel.com>; Wu, Hao A <hao.a.wu@intel.com>
> > > > Subject: RE: [PATCH] MdePkg/PciExpress21.h: Fix the PCIe industry
> > > > standard registers
> > > >
> > > > I agree the structure update in PciExpress21.h. I also see some new
> > > > macro definitions. Can they be added to PciExpress40.h, for example:
> > > >
> > > > #define PCIE_MAX_PAYLOAD_SIZE_128B 0
> > > > #define PCIE_MAX_PAYLOAD_SIZE_256B 1
> > > > #define PCIE_MAX_PAYLOAD_SIZE_512B 2
> > > > #define PCIE_MAX_PAYLOAD_SIZE_1024B 3 #define
> > > > PCIE_MAX_PAYLOAD_SIZE_2048B 4 #define
> > PCIE_MAX_PAYLOAD_SIZE_4096B
> > > > 5 #define PCIE_MAX_PAYLOAD_SIZE_RVSD1 6 #define
> > > > PCIE_MAX_PAYLOAD_SIZE_RVSD2 7
> > > >
> > > > #define PCIE_MAX_READ_REQ_SIZE_128B 0
> > > > #define PCIE_MAX_READ_REQ_SIZE_256B 1
> > > > #define PCIE_MAX_READ_REQ_SIZE_512B 2
> > > > #define PCIE_MAX_READ_REQ_SIZE_1024B 3
> > > > #define PCIE_MAX_READ_REQ_SIZE_2048B 4
> > > > #define PCIE_MAX_READ_REQ_SIZE_4096B 5
> > > > #define PCIE_MAX_READ_REQ_SIZE_RVSD1 6
> > > > #define PCIE_MAX_READ_REQ_SIZE_RVSD2 7
> > > >
> > > > Thanks
> > > > Liming
> > > > > -----Original Message-----
> > > > > From: Javeed, Ashraf
> > > > > Sent: Thursday, July 25, 2019 10:24 PM
> > > > > To: Gao, Liming <liming.gao@intel.com>; devel@edk2.groups.io
> > > > > Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Ni, Ray
> > > > > <ray.ni@intel.com>; Wu, Hao A <hao.a.wu@intel.com>
> > > > > Subject: RE: [PATCH] MdePkg/PciExpress21.h: Fix the PCIe industry
> > > > > standard registers
> > > > >
> > > > > Liming,
> > > > > The existing structure are extended in PCI Express Base
> > > > > Specification Revision
> > > > 4; hence I have made the change in PciExpress21.h.
> > > > >
> > > > > Thanks
> > > > > Ashraf
> > > > >
> > > > > > -----Original Message-----
> > > > > > From: Gao, Liming
> > > > > > Sent: Thursday, July 25, 2019 7:35 PM
> > > > > > To: Javeed, Ashraf <ashraf.javeed@intel.com>;
> > > > > > devel@edk2.groups.io
> > > > > > Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Ni, Ray
> > > > > > <ray.ni@intel.com>; Wu, Hao A <hao.a.wu@intel.com>
> > > > > > Subject: RE: [PATCH] MdePkg/PciExpress21.h: Fix the PCIe
> > > > > > industry standard registers
> > > > > >
> > > > > > Ashraf:
> > > > > > So, those update base on PCI Express Base Specification
> > > > > > Revision 4.0. If new definitions are in version 4.0, they can be
> > > > > > added into PciExpress40.h. If the existing structure is
> > > > > > extended, they can be kept in
> > > > PciExpress21.h.
> > > > > >
> > > > > > Thanks
> > > > > > Liming
> > > > > > > -----Original Message-----
> > > > > > > From: Javeed, Ashraf
> > > > > > > Sent: Monday, July 22, 2019 2:26 PM
> > > > > > > To: devel@edk2.groups.io
> > > > > > > Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Gao,
> > > > > > > Liming <liming.gao@intel.com>; Ni, Ray <ray.ni@intel.com>; Wu,
> > > > > > > Hao A <hao.a.wu@intel.com>
> > > > > > > Subject: [PATCH] MdePkg/PciExpress21.h: Fix the PCIe industry
> > > > > > > standard registers
> > > > > > >
> > > > > > > BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2007
> > > > > > > The PCIe Device capability register #2
> > > > > > > (PCI_REG_PCIE_DEVICE_CAPABILITY2) needs to be upgraded for
> > > > > > > the PCI features like - LN system CLS, 10b Tag
> > > > > > > completer/requester register fields, emergency power reduction
> > > > > > > support and initialization requirement, and
> > > > > > FRS support.
> > > > > > >
> > > > > > > The PCIe Device Control register #2
> > > > > > > (PCI_REG_PCIE_DEVICE_CONTROL2) needs to be upgraded for the -
> > > > > > > emergency power reduction request enabling and also the 10b
> > Extended Tag enabling.
> > > > > > >
> > > > > > > Needs macro definitions for all the ranges of Maximum Payload
> > > > > > > Sizes and Maximum Read Request Sizes defined
> > > > > > >
> > > > > > > Needs macro definitions for all the ranges of Completion
> > > > > > > Timeout range needs to be defined.
> > > > > > >
> > > > > > > Signed-off-by: Ashraf Javeed <ashraf.javeed@intel.com>
> > > > > > > Cc: Michael D Kinney <michael.d.kinney@intel.com>
> > > > > > > Cc: Liming Gao <liming.gao@intel.com>
> > > > > > > Cc: Ray Ni <ray.ni@intel.com>
> > > > > > > Cc: Hao A Wu <hao.a.wu@intel.com>
> > > > > > > ---
> > > > > > > MdePkg/Include/IndustryStandard/PciExpress21.h | 39
> > > > > > > ++++++++++++++++++++++++++++++++++++---
> > > > > > > 1 file changed, 36 insertions(+), 3 deletions(-)
> > > > > > >
> > > > > > > diff --git a/MdePkg/Include/IndustryStandard/PciExpress21.h
> > > > > > > b/MdePkg/Include/IndustryStandard/PciExpress21.h
> > > > > > > index d4003de74c..e652e77a1e 100644
> > > > > > > --- a/MdePkg/Include/IndustryStandard/PciExpress21.h
> > > > > > > +++ b/MdePkg/Include/IndustryStandard/PciExpress21.h
> > > > > > > @@ -91,6 +91,24 @@ typedef union {
> > > > > > > UINT16 Uint16;
> > > > > > > } PCI_REG_PCIE_DEVICE_CONTROL;
> > > > > > >
> > > > > > > +#define PCIE_MAX_PAYLOAD_SIZE_128B 0
> > > > > > > +#define PCIE_MAX_PAYLOAD_SIZE_256B 1
> > > > > > > +#define PCIE_MAX_PAYLOAD_SIZE_512B 2
> > > > > > > +#define PCIE_MAX_PAYLOAD_SIZE_1024B 3 #define
> > > > > > > +PCIE_MAX_PAYLOAD_SIZE_2048B 4 #define
> > > > > > PCIE_MAX_PAYLOAD_SIZE_4096B 5
> > > > > > > +#define PCIE_MAX_PAYLOAD_SIZE_RVSD1 6 #define
> > > > > > > +PCIE_MAX_PAYLOAD_SIZE_RVSD2 7
> > > > > > > +
> > > > > > > +#define PCIE_MAX_READ_REQ_SIZE_128B 0
> > > > > > > +#define PCIE_MAX_READ_REQ_SIZE_256B 1
> > > > > > > +#define PCIE_MAX_READ_REQ_SIZE_512B 2
> > > > > > > +#define PCIE_MAX_READ_REQ_SIZE_1024B 3
> > > > > > > +#define PCIE_MAX_READ_REQ_SIZE_2048B 4
> > > > > > > +#define PCIE_MAX_READ_REQ_SIZE_4096B 5
> > > > > > > +#define PCIE_MAX_READ_REQ_SIZE_RVSD1 6
> > > > > > > +#define PCIE_MAX_READ_REQ_SIZE_RVSD2 7
> > > > > > > +
> > > > > > > typedef union {
> > > > > > > struct {
> > > > > > > UINT16 CorrectableError : 1; @@ -250,16 +268,30 @@
> > > > > > > typedef union {
> > > > > > > UINT32 NoRoEnabledPrPrPassing : 1;
> > > > > > > UINT32 LtrMechanism : 1;
> > > > > > > UINT32 TphCompleter : 2;
> > > > > > > - UINT32 Reserved : 4;
> > > > > > > + UINT32 LnSystemCLS : 2;
> > > > > > > + UINT32 TenBitTagCompleterSupported : 1;
> > > > > > > + UINT32 TenBitTagRequesterSupported : 1;
> > > > > > > UINT32 Obff : 2;
> > > > > > > UINT32 ExtendedFmtField : 1;
> > > > > > > UINT32 EndEndTlpPrefix : 1;
> > > > > > > UINT32 MaxEndEndTlpPrefixes : 2;
> > > > > > > - UINT32 Reserved2 : 8;
> > > > > > > + UINT32 EmergencyPowerReductionSupported : 2;
> > > > > > > + UINT32 EmergencyPowerReductionInitializationRequired : 1;
> > > > > > > + UINT32 Reserved : 4;
> > > > > > > + UINT32 FrsSupported : 1;
> > > > > > > } Bits;
> > > > > > > UINT32 Uint32;
> > > > > > > } PCI_REG_PCIE_DEVICE_CAPABILITY2;
> > > > > > >
> > > > > > > +#define PCIE_COMPLETION_TIMEOUT_NOT_SUPPORTED 0
> > > > > > > +#define PCIE_COMPLETION_TIMEOUT_RANGE_A_SUPPORTED 1
> > > > > > > +#define PCIE_COMPLETION_TIMEOUT_RANGE_B_SUPPORTED 2
> > > > > > > +#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_SUPPORTED 3
> > > > > > > +#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_SUPPORTED 6
> > > > > > > +#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_SUPPORTED
> > 7
> > > > > > > +#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_D_SUPPORTED
> > 14
> > > > > > > +#define
> > PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_D_SUPPORTED 15
> > > > > > > +
> > > > > > > #define PCIE_DEVICE_CAPABILITY_OBFF_MESSAGE BIT0
> > > > > > > #define PCIE_DEVICE_CAPABILITY_OBFF_WAKE BIT1
> > > > > > >
> > > > > > > @@ -273,7 +305,8 @@ typedef union {
> > > > > > > UINT16 IdoRequest : 1;
> > > > > > > UINT16 IdoCompletion : 1;
> > > > > > > UINT16 LtrMechanism : 2;
> > > > > > > - UINT16 Reserved : 2;
> > > > > > > + UINT16 EmergencyPowerReductionRequest : 1;
> > > > > > > + UINT16 TenBitTagRequesterEnable : 1;
> > > > > > > UINT16 Obff : 2;
> > > > > > > UINT16 EndEndTlpPrefixBlocking : 1;
> > > > > > > } Bits;
> > > > > > > --
> > > > > > > 2.21.0.windows.1
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH] MdePkg/PciExpress21.h: Fix the PCIe industry standard registers
@ 2019-07-25 17:57 Javeed, Ashraf
0 siblings, 0 replies; 11+ messages in thread
From: Javeed, Ashraf @ 2019-07-25 17:57 UTC (permalink / raw)
To: devel; +Cc: Michael D Kinney, Liming Gao, Ray Ni, Hao A Wu
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2007
The following two PCI Capability Structure registers are updated as per
the PCI Base Specification Revision 4:-
(1) The PCI Device capability register 2(PCI_REG_PCIE_DEVICE_CAPABILITY2)
needs to be upgraded for the PCI features like -
LN system CLS (LnSystemCLS),
10b Tag completer/requester register fields
(TenBitTagCompleterSupported, TenBitTagRequesterSupported),
Emergency power reduction support and initialization requirement
(EmergencyPowerReductionSupported,
EmergencyPowerReductionInitializationRequired),
and FRS support (FrsSupported ).
(2) The PCI Device Control register 2(PCI_REG_PCIE_DEVICE_CONTROL2) needs
to be upgraded for the -
Emergency power reduction request enabling
(EmergencyPowerReductionRequest), and also the 10b Extended Tag
enabling (TenBitTagRequesterEnable).
The following two are defined as per the PCI Express Base Specification
Revision 2.1:-
(1) Defined macro definitions for all the ranges of Maximum Payload Sizes
and Maximum Read Request Sizes defined
(2) Defined macro definitions for all the ranges of Completion Timeout
value.
Signed-off-by: Ashraf Javeed <ashraf.javeed@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
---
MdePkg/Include/IndustryStandard/PciExpress21.h | 39 ++++++++++++++++++++++++++++++++++++---
1 file changed, 36 insertions(+), 3 deletions(-)
diff --git a/MdePkg/Include/IndustryStandard/PciExpress21.h b/MdePkg/Include/IndustryStandard/PciExpress21.h
index d4003de74c..e652e77a1e 100644
--- a/MdePkg/Include/IndustryStandard/PciExpress21.h
+++ b/MdePkg/Include/IndustryStandard/PciExpress21.h
@@ -91,6 +91,24 @@ typedef union {
UINT16 Uint16;
} PCI_REG_PCIE_DEVICE_CONTROL;
+#define PCIE_MAX_PAYLOAD_SIZE_128B 0
+#define PCIE_MAX_PAYLOAD_SIZE_256B 1
+#define PCIE_MAX_PAYLOAD_SIZE_512B 2
+#define PCIE_MAX_PAYLOAD_SIZE_1024B 3
+#define PCIE_MAX_PAYLOAD_SIZE_2048B 4
+#define PCIE_MAX_PAYLOAD_SIZE_4096B 5
+#define PCIE_MAX_PAYLOAD_SIZE_RVSD1 6
+#define PCIE_MAX_PAYLOAD_SIZE_RVSD2 7
+
+#define PCIE_MAX_READ_REQ_SIZE_128B 0
+#define PCIE_MAX_READ_REQ_SIZE_256B 1
+#define PCIE_MAX_READ_REQ_SIZE_512B 2
+#define PCIE_MAX_READ_REQ_SIZE_1024B 3
+#define PCIE_MAX_READ_REQ_SIZE_2048B 4
+#define PCIE_MAX_READ_REQ_SIZE_4096B 5
+#define PCIE_MAX_READ_REQ_SIZE_RVSD1 6
+#define PCIE_MAX_READ_REQ_SIZE_RVSD2 7
+
typedef union {
struct {
UINT16 CorrectableError : 1;
@@ -250,16 +268,30 @@ typedef union {
UINT32 NoRoEnabledPrPrPassing : 1;
UINT32 LtrMechanism : 1;
UINT32 TphCompleter : 2;
- UINT32 Reserved : 4;
+ UINT32 LnSystemCLS : 2;
+ UINT32 TenBitTagCompleterSupported : 1;
+ UINT32 TenBitTagRequesterSupported : 1;
UINT32 Obff : 2;
UINT32 ExtendedFmtField : 1;
UINT32 EndEndTlpPrefix : 1;
UINT32 MaxEndEndTlpPrefixes : 2;
- UINT32 Reserved2 : 8;
+ UINT32 EmergencyPowerReductionSupported : 2;
+ UINT32 EmergencyPowerReductionInitializationRequired : 1;
+ UINT32 Reserved : 4;
+ UINT32 FrsSupported : 1;
} Bits;
UINT32 Uint32;
} PCI_REG_PCIE_DEVICE_CAPABILITY2;
+#define PCIE_COMPLETION_TIMEOUT_NOT_SUPPORTED 0
+#define PCIE_COMPLETION_TIMEOUT_RANGE_A_SUPPORTED 1
+#define PCIE_COMPLETION_TIMEOUT_RANGE_B_SUPPORTED 2
+#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_SUPPORTED 3
+#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_SUPPORTED 6
+#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_SUPPORTED 7
+#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_D_SUPPORTED 14
+#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_D_SUPPORTED 15
+
#define PCIE_DEVICE_CAPABILITY_OBFF_MESSAGE BIT0
#define PCIE_DEVICE_CAPABILITY_OBFF_WAKE BIT1
@@ -273,7 +305,8 @@ typedef union {
UINT16 IdoRequest : 1;
UINT16 IdoCompletion : 1;
UINT16 LtrMechanism : 2;
- UINT16 Reserved : 2;
+ UINT16 EmergencyPowerReductionRequest : 1;
+ UINT16 TenBitTagRequesterEnable : 1;
UINT16 Obff : 2;
UINT16 EndEndTlpPrefixBlocking : 1;
} Bits;
--
2.21.0.windows.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH] MdePkg/PciExpress21.h: Fix the PCIe industry standard registers
@ 2019-07-25 18:16 Javeed, Ashraf
0 siblings, 0 replies; 11+ messages in thread
From: Javeed, Ashraf @ 2019-07-25 18:16 UTC (permalink / raw)
To: devel; +Cc: Michael D Kinney, Liming Gao, Ray Ni, Hao A Wu
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2007
The PCIe Device capability register #2 (PCI_REG_PCIE_DEVICE_CAPABILITY2)
needs to be upgraded for the PCI features like - LN system CLS, 10b Tag
completer/requester register fields, emergency power reduction support
and initialization requirement, and FRS support.
The PCIe Device Control register #2 (PCI_REG_PCIE_DEVICE_CONTROL2) needs
to be upgraded for the - emergency power reduction request enabling and
also the 10b Extended Tag enabling.
Needs macro definitions for all the ranges of Maximum Payload Sizes and
Maximum Read Request Sizes defined
Needs macro definitions for all the ranges of Completion Timeout range
needs to be defined.
Signed-off-by: Ashraf Javeed <ashraf.javeed@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
---
MdePkg/Include/IndustryStandard/PciExpress21.h | 39 ++++++++++++++++++++++++++++++++++++---
1 file changed, 36 insertions(+), 3 deletions(-)
diff --git a/MdePkg/Include/IndustryStandard/PciExpress21.h b/MdePkg/Include/IndustryStandard/PciExpress21.h
index d4003de74c..e652e77a1e 100644
--- a/MdePkg/Include/IndustryStandard/PciExpress21.h
+++ b/MdePkg/Include/IndustryStandard/PciExpress21.h
@@ -91,6 +91,24 @@ typedef union {
UINT16 Uint16;
} PCI_REG_PCIE_DEVICE_CONTROL;
+#define PCIE_MAX_PAYLOAD_SIZE_128B 0
+#define PCIE_MAX_PAYLOAD_SIZE_256B 1
+#define PCIE_MAX_PAYLOAD_SIZE_512B 2
+#define PCIE_MAX_PAYLOAD_SIZE_1024B 3
+#define PCIE_MAX_PAYLOAD_SIZE_2048B 4
+#define PCIE_MAX_PAYLOAD_SIZE_4096B 5
+#define PCIE_MAX_PAYLOAD_SIZE_RVSD1 6
+#define PCIE_MAX_PAYLOAD_SIZE_RVSD2 7
+
+#define PCIE_MAX_READ_REQ_SIZE_128B 0
+#define PCIE_MAX_READ_REQ_SIZE_256B 1
+#define PCIE_MAX_READ_REQ_SIZE_512B 2
+#define PCIE_MAX_READ_REQ_SIZE_1024B 3
+#define PCIE_MAX_READ_REQ_SIZE_2048B 4
+#define PCIE_MAX_READ_REQ_SIZE_4096B 5
+#define PCIE_MAX_READ_REQ_SIZE_RVSD1 6
+#define PCIE_MAX_READ_REQ_SIZE_RVSD2 7
+
typedef union {
struct {
UINT16 CorrectableError : 1;
@@ -250,16 +268,30 @@ typedef union {
UINT32 NoRoEnabledPrPrPassing : 1;
UINT32 LtrMechanism : 1;
UINT32 TphCompleter : 2;
- UINT32 Reserved : 4;
+ UINT32 LnSystemCLS : 2;
+ UINT32 TenBitTagCompleterSupported : 1;
+ UINT32 TenBitTagRequesterSupported : 1;
UINT32 Obff : 2;
UINT32 ExtendedFmtField : 1;
UINT32 EndEndTlpPrefix : 1;
UINT32 MaxEndEndTlpPrefixes : 2;
- UINT32 Reserved2 : 8;
+ UINT32 EmergencyPowerReductionSupported : 2;
+ UINT32 EmergencyPowerReductionInitializationRequired : 1;
+ UINT32 Reserved : 4;
+ UINT32 FrsSupported : 1;
} Bits;
UINT32 Uint32;
} PCI_REG_PCIE_DEVICE_CAPABILITY2;
+#define PCIE_COMPLETION_TIMEOUT_NOT_SUPPORTED 0
+#define PCIE_COMPLETION_TIMEOUT_RANGE_A_SUPPORTED 1
+#define PCIE_COMPLETION_TIMEOUT_RANGE_B_SUPPORTED 2
+#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_SUPPORTED 3
+#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_SUPPORTED 6
+#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_SUPPORTED 7
+#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_D_SUPPORTED 14
+#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_D_SUPPORTED 15
+
#define PCIE_DEVICE_CAPABILITY_OBFF_MESSAGE BIT0
#define PCIE_DEVICE_CAPABILITY_OBFF_WAKE BIT1
@@ -273,7 +305,8 @@ typedef union {
UINT16 IdoRequest : 1;
UINT16 IdoCompletion : 1;
UINT16 LtrMechanism : 2;
- UINT16 Reserved : 2;
+ UINT16 EmergencyPowerReductionRequest : 1;
+ UINT16 TenBitTagRequesterEnable : 1;
UINT16 Obff : 2;
UINT16 EndEndTlpPrefixBlocking : 1;
} Bits;
--
2.21.0.windows.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH] MdePkg/PciExpress21.h: Fix the PCIe industry standard registers
@ 2019-07-25 18:23 Javeed, Ashraf
0 siblings, 0 replies; 11+ messages in thread
From: Javeed, Ashraf @ 2019-07-25 18:23 UTC (permalink / raw)
To: devel; +Cc: Michael D Kinney, Liming Gao, Ray Ni, Hao A Wu
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2007
The following two PCI Capability Structure registers are updated as per
the PCI Base Specification Revision 4:-
(1) The PCI Device capability register 2(PCI_REG_PCIE_DEVICE_CAPABILITY2)
needs to be upgraded for the PCI features like -
LN system CLS (LnSystemCLS),
10b Tag completer/requester register fields
(TenBitTagCompleterSupported, TenBitTagRequesterSupported),
Emergency power reduction support and initialization requirement
(EmergencyPowerReductionSupported,
EmergencyPowerReductionInitializationRequired),
and FRS support (FrsSupported ).
(2) The PCI Device Control register 2(PCI_REG_PCIE_DEVICE_CONTROL2) needs
to be upgraded for the -
Emergency power reduction request enabling
(EmergencyPowerReductionRequest), and also the 10b Extended Tag
enabling (TenBitTagRequesterEnable).
The following two are defined as per the PCI Express Base Specification
Revision 2.1:-
(1) Defined macro definitions for all the ranges of Maximum Payload Sizes
and Maximum Read Request Sizes defined
(2) Defined macro definitions for all the ranges of Completion Timeout
value.
Signed-off-by: Ashraf Javeed <ashraf.javeed@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
---
MdePkg/Include/IndustryStandard/PciExpress21.h | 39 ++++++++++++++++++++++++++++++++++++---
1 file changed, 36 insertions(+), 3 deletions(-)
diff --git a/MdePkg/Include/IndustryStandard/PciExpress21.h b/MdePkg/Include/IndustryStandard/PciExpress21.h
index d4003de74c..e652e77a1e 100644
--- a/MdePkg/Include/IndustryStandard/PciExpress21.h
+++ b/MdePkg/Include/IndustryStandard/PciExpress21.h
@@ -91,6 +91,24 @@ typedef union {
UINT16 Uint16;
} PCI_REG_PCIE_DEVICE_CONTROL;
+#define PCIE_MAX_PAYLOAD_SIZE_128B 0
+#define PCIE_MAX_PAYLOAD_SIZE_256B 1
+#define PCIE_MAX_PAYLOAD_SIZE_512B 2
+#define PCIE_MAX_PAYLOAD_SIZE_1024B 3
+#define PCIE_MAX_PAYLOAD_SIZE_2048B 4
+#define PCIE_MAX_PAYLOAD_SIZE_4096B 5
+#define PCIE_MAX_PAYLOAD_SIZE_RVSD1 6
+#define PCIE_MAX_PAYLOAD_SIZE_RVSD2 7
+
+#define PCIE_MAX_READ_REQ_SIZE_128B 0
+#define PCIE_MAX_READ_REQ_SIZE_256B 1
+#define PCIE_MAX_READ_REQ_SIZE_512B 2
+#define PCIE_MAX_READ_REQ_SIZE_1024B 3
+#define PCIE_MAX_READ_REQ_SIZE_2048B 4
+#define PCIE_MAX_READ_REQ_SIZE_4096B 5
+#define PCIE_MAX_READ_REQ_SIZE_RVSD1 6
+#define PCIE_MAX_READ_REQ_SIZE_RVSD2 7
+
typedef union {
struct {
UINT16 CorrectableError : 1;
@@ -250,16 +268,30 @@ typedef union {
UINT32 NoRoEnabledPrPrPassing : 1;
UINT32 LtrMechanism : 1;
UINT32 TphCompleter : 2;
- UINT32 Reserved : 4;
+ UINT32 LnSystemCLS : 2;
+ UINT32 TenBitTagCompleterSupported : 1;
+ UINT32 TenBitTagRequesterSupported : 1;
UINT32 Obff : 2;
UINT32 ExtendedFmtField : 1;
UINT32 EndEndTlpPrefix : 1;
UINT32 MaxEndEndTlpPrefixes : 2;
- UINT32 Reserved2 : 8;
+ UINT32 EmergencyPowerReductionSupported : 2;
+ UINT32 EmergencyPowerReductionInitializationRequired : 1;
+ UINT32 Reserved : 4;
+ UINT32 FrsSupported : 1;
} Bits;
UINT32 Uint32;
} PCI_REG_PCIE_DEVICE_CAPABILITY2;
+#define PCIE_COMPLETION_TIMEOUT_NOT_SUPPORTED 0
+#define PCIE_COMPLETION_TIMEOUT_RANGE_A_SUPPORTED 1
+#define PCIE_COMPLETION_TIMEOUT_RANGE_B_SUPPORTED 2
+#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_SUPPORTED 3
+#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_SUPPORTED 6
+#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_SUPPORTED 7
+#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_D_SUPPORTED 14
+#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_D_SUPPORTED 15
+
#define PCIE_DEVICE_CAPABILITY_OBFF_MESSAGE BIT0
#define PCIE_DEVICE_CAPABILITY_OBFF_WAKE BIT1
@@ -273,7 +305,8 @@ typedef union {
UINT16 IdoRequest : 1;
UINT16 IdoCompletion : 1;
UINT16 LtrMechanism : 2;
- UINT16 Reserved : 2;
+ UINT16 EmergencyPowerReductionRequest : 1;
+ UINT16 TenBitTagRequesterEnable : 1;
UINT16 Obff : 2;
UINT16 EndEndTlpPrefixBlocking : 1;
} Bits;
--
2.21.0.windows.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
end of thread, other threads:[~2019-07-25 18:23 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz follow: Atom feed
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2019-07-22 6:26 [PATCH] MdePkg/PciExpress21.h: Fix the PCIe industry standard registers Javeed, Ashraf
2019-07-25 14:04 ` Liming Gao
2019-07-25 14:24 ` Javeed, Ashraf
2019-07-25 14:35 ` Liming Gao
2019-07-25 15:29 ` Javeed, Ashraf
2019-07-25 15:35 ` Liming Gao
2019-07-25 16:04 ` Javeed, Ashraf
2019-07-25 16:22 ` Liming Gao
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