From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.24, mailfrom: liming.gao@intel.com) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by groups.io with SMTP; Thu, 25 Jul 2019 07:04:59 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 25 Jul 2019 07:04:58 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,306,1559545200"; d="scan'208";a="170255921" Received: from fmsmsx106.amr.corp.intel.com ([10.18.124.204]) by fmsmga008.fm.intel.com with ESMTP; 25 Jul 2019 07:04:58 -0700 Received: from fmsmsx112.amr.corp.intel.com (10.18.116.6) by FMSMSX106.amr.corp.intel.com (10.18.124.204) with Microsoft SMTP Server (TLS) id 14.3.439.0; Thu, 25 Jul 2019 07:04:58 -0700 Received: from shsmsx105.ccr.corp.intel.com (10.239.4.158) by FMSMSX112.amr.corp.intel.com (10.18.116.6) with Microsoft SMTP Server (TLS) id 14.3.439.0; Thu, 25 Jul 2019 07:04:57 -0700 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.112]) by SHSMSX105.ccr.corp.intel.com ([169.254.11.15]) with mapi id 14.03.0439.000; Thu, 25 Jul 2019 22:04:56 +0800 From: "Liming Gao" To: "Javeed, Ashraf" , "devel@edk2.groups.io" CC: "Kinney, Michael D" , "Ni, Ray" , "Wu, Hao A" Subject: Re: [PATCH] MdePkg/PciExpress21.h: Fix the PCIe industry standard registers Thread-Topic: [PATCH] MdePkg/PciExpress21.h: Fix the PCIe industry standard registers Thread-Index: AQHVQFZ3lxBHivQTJkmq0JjMFqXL76bbXjEQ Date: Thu, 25 Jul 2019 14:04:55 +0000 Message-ID: <4A89E2EF3DFEDB4C8BFDE51014F606A14E4BE088@SHSMSX104.ccr.corp.intel.com> References: <20190722062627.12276-1-ashraf.javeed@intel.com> In-Reply-To: <20190722062627.12276-1-ashraf.javeed@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ctpclassification: CTP_NT x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiZTBiYmQ4MGQtZmYxMC00YTllLWFiYjctZjFjZjI1YjFlMGZiIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiT0tMY3JycW03YVhSVnY4UXRGeFdmVTNMYjdFUnF1cnZQOHpWbTlRaXF0TkVEbFoyWkdwQXh1SHVWZHQyTlFRQSJ9 dlp-product: dlpe-windows dlp-version: 11.0.600.7 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Return-Path: liming.gao@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Ashraf: So, those update base on PCI Express Base Specification Revision 4.0. If = new definitions are in version 4.0, they can be added into PciExpress40.h. = If the existing structure is extended, they can be kept in PciExpress21.h. Thanks Liming > -----Original Message----- > From: Javeed, Ashraf > Sent: Monday, July 22, 2019 2:26 PM > To: devel@edk2.groups.io > Cc: Kinney, Michael D ; Gao, Liming ; Ni, Ray ; Wu, Hao A > > Subject: [PATCH] MdePkg/PciExpress21.h: Fix the PCIe industry standard re= gisters >=20 > BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2007 > The PCIe Device capability register #2 (PCI_REG_PCIE_DEVICE_CAPABILITY2) > needs to be upgraded for the PCI features like - LN system CLS, 10b Tag > completer/requester register fields, emergency power reduction support > and initialization requirement, and FRS support. >=20 > The PCIe Device Control register #2 (PCI_REG_PCIE_DEVICE_CONTROL2) needs > to be upgraded for the - emergency power reduction request enabling and > also the 10b Extended Tag enabling. >=20 > Needs macro definitions for all the ranges of Maximum Payload Sizes and > Maximum Read Request Sizes defined >=20 > Needs macro definitions for all the ranges of Completion Timeout range > needs to be defined. >=20 > Signed-off-by: Ashraf Javeed > Cc: Michael D Kinney > Cc: Liming Gao > Cc: Ray Ni > Cc: Hao A Wu > --- > MdePkg/Include/IndustryStandard/PciExpress21.h | 39 ++++++++++++++++++++= ++++++++++++++++--- > 1 file changed, 36 insertions(+), 3 deletions(-) >=20 > diff --git a/MdePkg/Include/IndustryStandard/PciExpress21.h b/MdePkg/Incl= ude/IndustryStandard/PciExpress21.h > index d4003de74c..e652e77a1e 100644 > --- a/MdePkg/Include/IndustryStandard/PciExpress21.h > +++ b/MdePkg/Include/IndustryStandard/PciExpress21.h > @@ -91,6 +91,24 @@ typedef union { > UINT16 Uint16; > } PCI_REG_PCIE_DEVICE_CONTROL; >=20 > +#define PCIE_MAX_PAYLOAD_SIZE_128B 0 > +#define PCIE_MAX_PAYLOAD_SIZE_256B 1 > +#define PCIE_MAX_PAYLOAD_SIZE_512B 2 > +#define PCIE_MAX_PAYLOAD_SIZE_1024B 3 > +#define PCIE_MAX_PAYLOAD_SIZE_2048B 4 > +#define PCIE_MAX_PAYLOAD_SIZE_4096B 5 > +#define PCIE_MAX_PAYLOAD_SIZE_RVSD1 6 > +#define PCIE_MAX_PAYLOAD_SIZE_RVSD2 7 > + > +#define PCIE_MAX_READ_REQ_SIZE_128B 0 > +#define PCIE_MAX_READ_REQ_SIZE_256B 1 > +#define PCIE_MAX_READ_REQ_SIZE_512B 2 > +#define PCIE_MAX_READ_REQ_SIZE_1024B 3 > +#define PCIE_MAX_READ_REQ_SIZE_2048B 4 > +#define PCIE_MAX_READ_REQ_SIZE_4096B 5 > +#define PCIE_MAX_READ_REQ_SIZE_RVSD1 6 > +#define PCIE_MAX_READ_REQ_SIZE_RVSD2 7 > + > typedef union { > struct { > UINT16 CorrectableError : 1; > @@ -250,16 +268,30 @@ typedef union { > UINT32 NoRoEnabledPrPrPassing : 1; > UINT32 LtrMechanism : 1; > UINT32 TphCompleter : 2; > - UINT32 Reserved : 4; > + UINT32 LnSystemCLS : 2; > + UINT32 TenBitTagCompleterSupported : 1; > + UINT32 TenBitTagRequesterSupported : 1; > UINT32 Obff : 2; > UINT32 ExtendedFmtField : 1; > UINT32 EndEndTlpPrefix : 1; > UINT32 MaxEndEndTlpPrefixes : 2; > - UINT32 Reserved2 : 8; > + UINT32 EmergencyPowerReductionSupported : 2; > + UINT32 EmergencyPowerReductionInitializationRequired : 1; > + UINT32 Reserved : 4; > + UINT32 FrsSupported : 1; > } Bits; > UINT32 Uint32; > } PCI_REG_PCIE_DEVICE_CAPABILITY2; >=20 > +#define PCIE_COMPLETION_TIMEOUT_NOT_SUPPORTED 0 > +#define PCIE_COMPLETION_TIMEOUT_RANGE_A_SUPPORTED 1 > +#define PCIE_COMPLETION_TIMEOUT_RANGE_B_SUPPORTED 2 > +#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_SUPPORTED 3 > +#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_SUPPORTED 6 > +#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_SUPPORTED 7 > +#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_D_SUPPORTED 14 > +#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_D_SUPPORTED 15 > + > #define PCIE_DEVICE_CAPABILITY_OBFF_MESSAGE BIT0 > #define PCIE_DEVICE_CAPABILITY_OBFF_WAKE BIT1 >=20 > @@ -273,7 +305,8 @@ typedef union { > UINT16 IdoRequest : 1; > UINT16 IdoCompletion : 1; > UINT16 LtrMechanism : 2; > - UINT16 Reserved : 2; > + UINT16 EmergencyPowerReductionRequest : 1; > + UINT16 TenBitTagRequesterEnable : 1; > UINT16 Obff : 2; > UINT16 EndEndTlpPrefixBlocking : 1; > } Bits; > -- > 2.21.0.windows.1