From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.136, mailfrom: liming.gao@intel.com) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by groups.io with SMTP; Mon, 29 Jul 2019 00:54:20 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 Jul 2019 00:54:19 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,321,1559545200"; d="scan'208";a="322775406" Received: from fmsmsx103.amr.corp.intel.com ([10.18.124.201]) by orsmga004.jf.intel.com with ESMTP; 29 Jul 2019 00:54:19 -0700 Received: from fmsmsx118.amr.corp.intel.com (10.18.116.18) by FMSMSX103.amr.corp.intel.com (10.18.124.201) with Microsoft SMTP Server (TLS) id 14.3.439.0; Mon, 29 Jul 2019 00:54:18 -0700 Received: from shsmsx106.ccr.corp.intel.com (10.239.4.159) by fmsmsx118.amr.corp.intel.com (10.18.116.18) with Microsoft SMTP Server (TLS) id 14.3.439.0; Mon, 29 Jul 2019 00:54:18 -0700 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.112]) by SHSMSX106.ccr.corp.intel.com ([169.254.10.204]) with mapi id 14.03.0439.000; Mon, 29 Jul 2019 15:54:16 +0800 From: "Liming Gao" To: "Javeed, Ashraf" , "devel@edk2.groups.io" CC: "Kinney, Michael D" , "Ni, Ray" , "Wu, Hao A" Subject: Re: [Patch V2] MdePkg/PciExpress21.h: Fix the PCI industry standard register defines Thread-Topic: [Patch V2] MdePkg/PciExpress21.h: Fix the PCI industry standard register defines Thread-Index: AQHVRcDpNp5wzPpgpEatR813tgqWJqbhOhUw Date: Mon, 29 Jul 2019 07:54:15 +0000 Message-ID: <4A89E2EF3DFEDB4C8BFDE51014F606A14E4C44D9@SHSMSX104.ccr.corp.intel.com> References: <20190729035123.12444-1-ashraf.javeed@intel.com> In-Reply-To: <20190729035123.12444-1-ashraf.javeed@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Return-Path: liming.gao@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable The patch is good. Reviewed-by: Liming Gao >-----Original Message----- >From: Javeed, Ashraf >Sent: Monday, July 29, 2019 11:51 AM >To: devel@edk2.groups.io >Cc: Kinney, Michael D ; Gao, Liming >; Ni, Ray ; Wu, Hao A > >Subject: [Patch V2] MdePkg/PciExpress21.h: Fix the PCI industry standard >register defines > >BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2007 >The following two PCI Capability Structure registers are updated as per >the PCI Base Specification Revision 4:- >(1) The PCI Device capability register 2(PCI_REG_PCIE_DEVICE_CAPABILITY2) > needs to be upgraded for the PCI features like - > LN system CLS (LnSystemCLS), > 10b Tag completer/requester register fields > (TenBitTagCompleterSupported, TenBitTagRequesterSupported), > Emergency power reduction support and initialization requirement > (EmergencyPowerReductionSupported, > EmergencyPowerReductionInitializationRequired), > and FRS support (FrsSupported ). > >(2) The PCI Device Control register 2(PCI_REG_PCIE_DEVICE_CONTROL2) >needs > to be upgraded for the - > Emergency power reduction request enabling > (EmergencyPowerReductionRequest), and also the 10b Extended Tag > enabling (TenBitTagRequesterEnable). > >The following two are defined as per the PCI Express Base Specification >Revision 2.1:- >(1) Defined macro definitions for all the ranges of Maximum Payload Sizes > and Maximum Read Request Sizes register fields > >(2) Defined macro definitions for all the ranges of Completion Timeout > value. > > >Signed-off-by: Ashraf Javeed >Cc: Michael D Kinney >Cc: Liming Gao >Cc: Ray Ni >Cc: Hao A Wu >--- > >In V2: Reserved field name change in PCI_REG_PCIE_DEVICE_CAPABILITY2 >--- > MdePkg/Include/IndustryStandard/PciExpress21.h | 39 >++++++++++++++++++++++++++++++++++++--- > 1 file changed, 36 insertions(+), 3 deletions(-) > >diff --git a/MdePkg/Include/IndustryStandard/PciExpress21.h >b/MdePkg/Include/IndustryStandard/PciExpress21.h >index d4003de74c..f17f570775 100644 >--- a/MdePkg/Include/IndustryStandard/PciExpress21.h >+++ b/MdePkg/Include/IndustryStandard/PciExpress21.h >@@ -91,6 +91,24 @@ typedef union { > UINT16 Uint16; > } PCI_REG_PCIE_DEVICE_CONTROL; > >+#define PCIE_MAX_PAYLOAD_SIZE_128B 0 >+#define PCIE_MAX_PAYLOAD_SIZE_256B 1 >+#define PCIE_MAX_PAYLOAD_SIZE_512B 2 >+#define PCIE_MAX_PAYLOAD_SIZE_1024B 3 >+#define PCIE_MAX_PAYLOAD_SIZE_2048B 4 >+#define PCIE_MAX_PAYLOAD_SIZE_4096B 5 >+#define PCIE_MAX_PAYLOAD_SIZE_RVSD1 6 >+#define PCIE_MAX_PAYLOAD_SIZE_RVSD2 7 >+ >+#define PCIE_MAX_READ_REQ_SIZE_128B 0 >+#define PCIE_MAX_READ_REQ_SIZE_256B 1 >+#define PCIE_MAX_READ_REQ_SIZE_512B 2 >+#define PCIE_MAX_READ_REQ_SIZE_1024B 3 >+#define PCIE_MAX_READ_REQ_SIZE_2048B 4 >+#define PCIE_MAX_READ_REQ_SIZE_4096B 5 >+#define PCIE_MAX_READ_REQ_SIZE_RVSD1 6 >+#define PCIE_MAX_READ_REQ_SIZE_RVSD2 7 >+ > typedef union { > struct { > UINT16 CorrectableError : 1; >@@ -250,16 +268,30 @@ typedef union { > UINT32 NoRoEnabledPrPrPassing : 1; > UINT32 LtrMechanism : 1; > UINT32 TphCompleter : 2; >- UINT32 Reserved : 4; >+ UINT32 LnSystemCLS : 2; >+ UINT32 TenBitTagCompleterSupported : 1; >+ UINT32 TenBitTagRequesterSupported : 1; > UINT32 Obff : 2; > UINT32 ExtendedFmtField : 1; > UINT32 EndEndTlpPrefix : 1; > UINT32 MaxEndEndTlpPrefixes : 2; >- UINT32 Reserved2 : 8; >+ UINT32 EmergencyPowerReductionSupported : 2; >+ UINT32 EmergencyPowerReductionInitializationRequired : 1; >+ UINT32 Reserved3 : 4; >+ UINT32 FrsSupported : 1; > } Bits; > UINT32 Uint32; > } PCI_REG_PCIE_DEVICE_CAPABILITY2; > >+#define PCIE_COMPLETION_TIMEOUT_NOT_SUPPORTED 0 >+#define PCIE_COMPLETION_TIMEOUT_RANGE_A_SUPPORTED 1 >+#define PCIE_COMPLETION_TIMEOUT_RANGE_B_SUPPORTED 2 >+#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_SUPPORTED 3 >+#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_SUPPORTED 6 >+#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_SUPPORTED 7 >+#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_D_SUPPORTED 14 >+#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_D_SUPPORTED 15 >+ > #define PCIE_DEVICE_CAPABILITY_OBFF_MESSAGE BIT0 > #define PCIE_DEVICE_CAPABILITY_OBFF_WAKE BIT1 > >@@ -273,7 +305,8 @@ typedef union { > UINT16 IdoRequest : 1; > UINT16 IdoCompletion : 1; > UINT16 LtrMechanism : 2; >- UINT16 Reserved : 2; >+ UINT16 EmergencyPowerReductionRequest : 1; >+ UINT16 TenBitTagRequesterEnable : 1; > UINT16 Obff : 2; > UINT16 EndEndTlpPrefixBlocking : 1; > } Bits; >-- >2.21.0.windows.1