Re: [PATCH v3 1/1] ShellPkg/Pci.c: Update supported link speed to PCI5.0

["Liming Gao" <liming.gao@intel.com>]

push@adb59b633c12eae334540295092da94736bffa33

>-----Original Message-----
>From: Ni, Ray
>Sent: Wednesday, September 04, 2019 12:10 PM
>To: Gao, Zhichao <zhichao.gao@intel.com>; devel@edk2.groups.io
>Cc: Oleksiy <oleksiyy@ami.com>; Gao, Liming <liming.gao@intel.com>
>Subject: RE: [PATCH v3 1/1] ShellPkg/Pci.c: Update supported link speed to
>PCI5.0
>
>Reviewed-by: Ray Ni <ray.ni@intel.com>
>
>> -----Original Message-----
>> From: Gao, Zhichao
>> Sent: Sunday, September 1, 2019 8:15 AM
>> To: devel@edk2.groups.io
>> Cc: Gao, Zhichao <zhichao.gao@intel.com>; Ni, Ray <ray.ni@intel.com>;
>Oleksiy <oleksiyy@ami.com>; Gao, Liming
>> <liming.gao@intel.com>
>> Subject: [PATCH v3 1/1] ShellPkg/Pci.c: Update supported link speed to
>PCI5.0
>>
>> From: "Gao, Zhichao" <zhichao.gao@intel.com>
>>
>> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1955
>>
>> Refer to PCI express base specification Reversion 5.0, Version
>> 1.0, Table 7-33, Supported Link Speeds Vector bit 3 indicate
>> the speed 16 GT/s and bit 4 indicate the speed 32 GT/s.
>> Add the support to shell command 'pci ...'.
>>
>> Change the MaxLinkSpeed other values' result from 'Unknown'
>> to 'Reserved' to make the result align.
>>
>> Cc: Ray Ni <ray.ni@intel.com>
>> Cc: Oleksiy <oleksiyy@ami.com>
>> Cc: Liming Gao <liming.gao@intel.com>
>> Signed-off-by: Zhichao Gao <zhichao.gao@intel.com>
>> ---
>> V2:
>> Update the copyright.
>>
>> V3:
>> Update the link speed to support PCI 5.0.
>>
>>   Update the support
>>  .../Library/UefiShellDebug1CommandsLib/Pci.c     | 16 ++++++++++++++--
>>  1 file changed, 14 insertions(+), 2 deletions(-)
>>
>> diff --git a/ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.c
>b/ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.c
>> index ba9caa774398..3e138188cec3 100644
>> --- a/ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.c
>> +++ b/ShellPkg/Library/UefiShellDebug1CommandsLib/Pci.c
>> @@ -1,7 +1,7 @@
>>  /** @file
>>    Main file for Pci shell Debug1 function.
>>
>> -  Copyright (c) 2005 - 2018, Intel Corporation. All rights reserved.<BR>
>> +  Copyright (c) 2005 - 2019, Intel Corporation. All rights reserved.<BR>
>>    (C) Copyright 2013-2015 Hewlett-Packard Development Company, L.P.<BR>
>>    (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
>>    SPDX-License-Identifier: BSD-2-Clause-Patent
>> @@ -4515,8 +4515,14 @@ ExplainPcieLinkCap (
>>      case 3:
>>        MaxLinkSpeed = L"8.0 GT/s";
>>        break;
>> +    case 4:
>> +      MaxLinkSpeed = L"16.0 GT/s";
>> +      break;
>> +    case 5:
>> +      MaxLinkSpeed = L"32.0 GT/s";
>> +      break;
>>      default:
>> -      MaxLinkSpeed = L"Unknown";
>> +      MaxLinkSpeed = L"Reserved";
>>        break;
>>    }
>>    ShellPrintEx (-1, -1,
>> @@ -4672,6 +4678,12 @@ ExplainPcieLinkStatus (
>>      case 3:
>>        CurLinkSpeed = L"8.0 GT/s";
>>        break;
>> +    case 4:
>> +      CurLinkSpeed = L"16.0 GT/s";
>> +      break;
>> +    case 5:
>> +      CurLinkSpeed = L"32.0 GT/s";
>> +      break;
>>      default:
>>        CurLinkSpeed = L"Reserved";
>>        break;
>> --
>> 2.21.0.windows.1