From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mx.groups.io with SMTP id smtpd.web11.3311.1573173600033660547 for ; Thu, 07 Nov 2019 16:40:00 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.24, mailfrom: liming.gao@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Nov 2019 16:39:59 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,279,1569308400"; d="scan'208";a="286153903" Received: from fmsmsx104.amr.corp.intel.com ([10.18.124.202]) by orsmga001.jf.intel.com with ESMTP; 07 Nov 2019 16:39:58 -0800 Received: from fmsmsx117.amr.corp.intel.com (10.18.116.17) by fmsmsx104.amr.corp.intel.com (10.18.124.202) with Microsoft SMTP Server (TLS) id 14.3.439.0; Thu, 7 Nov 2019 16:39:58 -0800 Received: from shsmsx106.ccr.corp.intel.com (10.239.4.159) by fmsmsx117.amr.corp.intel.com (10.18.116.17) with Microsoft SMTP Server (TLS) id 14.3.439.0; Thu, 7 Nov 2019 16:39:58 -0800 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.127]) by SHSMSX106.ccr.corp.intel.com ([169.254.10.248]) with mapi id 14.03.0439.000; Fri, 8 Nov 2019 08:39:56 +0800 From: "Liming Gao" To: "devel@edk2.groups.io" , "ard.biesheuvel@linaro.org" CC: "eugene@hp.com" Subject: Re: [edk2-devel] [PATCH 1/1] BaseTools/GenFw AARCH64: disregard ADRP instructions that are patched already Thread-Topic: [edk2-devel] [PATCH 1/1] BaseTools/GenFw AARCH64: disregard ADRP instructions that are patched already Thread-Index: AQHVlUqwm/OMwjsibECZyq14NeZY/aeAb3ug Date: Fri, 8 Nov 2019 00:39:55 +0000 Message-ID: <4A89E2EF3DFEDB4C8BFDE51014F606A14E539892@SHSMSX104.ccr.corp.intel.com> References: <20191107090618.15813-1-ard.biesheuvel@linaro.org> In-Reply-To: <20191107090618.15813-1-ard.biesheuvel@linaro.org> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Return-Path: liming.gao@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Acked-by: Liming Gao >-----Original Message----- >From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of Ard >Biesheuvel >Sent: Thursday, November 07, 2019 5:06 PM >To: devel@edk2.groups.io >Cc: eugene@hp.com; Ard Biesheuvel >Subject: [edk2-devel] [PATCH 1/1] BaseTools/GenFw AARCH64: disregard >ADRP instructions that are patched already > >In order to permit the use of compilers that only implement the small >code model [which involves the use of ADRP instructions that require >4 KB segment alignment] for generating PE/COFF binaries with a small >footprint, we patch ADRP instructions into ADR instructions while doing >the ELF to PE/COFF conversion. > >As it turns out, the linker may be doing the same, but for different >reasons: there is a silicon erratum #843419 for ARM Cortex-A53 which >affects ADRP instructions appearing at a certain offset in memory, and >one of the mitigations for this erratum is to patch them into ADR >instructions at link time if the symbol reference is within -/+ 1 MB. >However, the LD linker fails to update the static relocation tables, and >so we end up with an ADR instruction in the fully linked binary, but >with a relocation entry in the RELA section identifying it as an ADRP >instruction. > >Since the linker has already updated the symbol reference, there is no >handling needed in GenFw for such instructions, and we can simply treat >it as an ordinary ADR. However, since it is guaranteed to be accompanied >by an add or load instruction with a LO12 relocation referencing the same >symbol, the section offset check we apply to ADR instructions is going to >take place anyway, so we can just disregard the ADR instruction entirely. > >Reported-by: Eugene Cohen >Suggested-by: Eugene Cohen >Signed-off-by: Ard Biesheuvel >--- > BaseTools/Source/C/GenFw/Elf64Convert.c | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > >diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c >b/BaseTools/Source/C/GenFw/Elf64Convert.c >index d574300ac4fe..d623dce1f9da 100644 >--- a/BaseTools/Source/C/GenFw/Elf64Convert.c >+++ b/BaseTools/Source/C/GenFw/Elf64Convert.c >@@ -1044,6 +1044,19 @@ WriteSections64 ( > /* fall through */ > > case R_AARCH64_ADR_PREL_PG_HI21: >+ // >+ // In order to handle Cortex-A53 erratum #843419, the LD lin= ker may >+ // convert ADRP instructions into ADR instructions, but with= out >+ // updating the static relocation type, and so we may end up= here >+ // while the instruction in question is actually ADR. So let= 's >+ // just disregard it: the section offset check we apply belo= w to >+ // ADR instructions will trigger for its R_AARCH64_xxx_ABS_L= O12_NC >+ // companion instruction as well, so it is safe to omit it h= ere. >+ // >+ if ((*(UINT32 *)Targ & BIT31) =3D=3D 0) { >+ break; >+ } >+ > // > // AArch64 PG_H21 relocations are typically paired with ABS_= LO12 > // relocations, where a PC-relative reference with +/- 4 GB = range is >-- >2.17.1 > > >