From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mx.groups.io with SMTP id smtpd.web11.6235.1575381920422994880 for ; Tue, 03 Dec 2019 06:05:20 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.115, mailfrom: liming.gao@intel.com) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 03 Dec 2019 06:05:20 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,273,1571727600"; d="scan'208";a="218638459" Received: from fmsmsx103.amr.corp.intel.com ([10.18.124.201]) by fmsmga001.fm.intel.com with ESMTP; 03 Dec 2019 06:05:19 -0800 Received: from fmsmsx162.amr.corp.intel.com (10.18.125.71) by FMSMSX103.amr.corp.intel.com (10.18.124.201) with Microsoft SMTP Server (TLS) id 14.3.439.0; Tue, 3 Dec 2019 06:05:19 -0800 Received: from shsmsx108.ccr.corp.intel.com (10.239.4.97) by fmsmsx162.amr.corp.intel.com (10.18.125.71) with Microsoft SMTP Server (TLS) id 14.3.439.0; Tue, 3 Dec 2019 06:05:19 -0800 Received: from shsmsx104.ccr.corp.intel.com ([169.254.5.90]) by SHSMSX108.ccr.corp.intel.com ([169.254.8.46]) with mapi id 14.03.0439.000; Tue, 3 Dec 2019 22:05:18 +0800 From: "Liming Gao" To: "devel@edk2.groups.io" , "Chen, Chen A" Subject: Re: [edk2-devel] [[edk2-platform][PATCH v2]] Platform/FitGen: Add FitGen feature to support uCode Capsule Update Thread-Topic: [edk2-devel] [[edk2-platform][PATCH v2]] Platform/FitGen: Add FitGen feature to support uCode Capsule Update Thread-Index: AQHVqbxjMmO7QC3BNUmRbQ+DsV/atKeoca8Q Date: Tue, 3 Dec 2019 14:05:17 +0000 Message-ID: <4A89E2EF3DFEDB4C8BFDE51014F606A14E55B31F@SHSMSX104.ccr.corp.intel.com> References: <20191203075634.28308-1-chen.a.chen@intel.com> In-Reply-To: <20191203075634.28308-1-chen.a.chen@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ctpclassification: CTP_NT x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiMjFmNWNjNWItZjQyNC00NjgwLWEyYmItMWIwN2ZjYzg5Y2QyIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjEwLjE4MDQuNDkiLCJUcnVzdGVkTGFiZWxIYXNoIjoiMUg2Yjk5Z3IxQXUrUTkrOTZIU3Z2UzlDUGdicFVZdUxWMjRabjBWOXRSRkFuM20yR1pRU0NoeDRsWWpNVE52NyJ9 dlp-product: dlpe-windows dlp-version: 11.2.0.6 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Return-Path: liming.gao@intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Liming Gao > -----Original Message----- > From: devel@edk2.groups.io On Behalf Of Chen A Ch= en > Sent: Tuesday, December 3, 2019 3:57 PM > To: devel@edk2.groups.io > Subject: [edk2-devel] [[edk2-platform][PATCH v2]] Platform/FitGen: Add F= itGen feature to support uCode Capsule Update >=20 > Add slot mode handling with a header array. > BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2321 >=20 > Signed-off-by: Chen A Chen > --- > Silicon/Intel/Tools/FitGen/FitGen.c | 79 ++++++++++++++++++++++++++++++= ++++++- > 1 file changed, 77 insertions(+), 2 deletions(-) >=20 > diff --git a/Silicon/Intel/Tools/FitGen/FitGen.c b/Silicon/Intel/Tools/F= itGen/FitGen.c > index faf9880060..833610f2a0 100644 > --- a/Silicon/Intel/Tools/FitGen/FitGen.c > +++ b/Silicon/Intel/Tools/FitGen/FitGen.c > @@ -315,6 +315,7 @@ Returns: > "\t[-F ] [-F ] = [-V ]\n" > "\t[-NA]\n" > "\t[-CLEAR]\n" > + "\t[-L ]\n" > "\t[-I ]\n" > "\t[-S |] [= -V ]\n" > "\t[-B ] [-B ...] [-V ]\n" > @@ -340,6 +341,8 @@ Returns: > printf ("\tMicrocodeRegionOffset - Offset of Microcode region in inp= ut FD image.\n"); > printf ("\tMicrocodeRegionSize - Size of Microcode region in input= FD image.\n"); > printf ("\tMicrocodeGuid - Guid of Microcode Module.\n"); > + printf ("\tMicrocodeSlotSize - Occupied region size of each Micr= ocode binary.\n"); > + printf ("\tMicrocodeFfsGuid - Guid of FFS which is used to save= Microcode binary"); > printf ("\t-NA - No 0x800 aligned Microcode requir= ement. No -NA means Microcode is 0x800 aligned.\n"); > printf ("\tRecordType - FIT entry record type. User shoul= d ensure it is ordered.\n"); > printf ("\tRecordDataAddress - FIT entry record data address.\n"= ); > @@ -764,6 +767,7 @@ Returns: > */ > { > EFI_GUID Guid; > + EFI_GUID MicrocodeFfsGuid; > INTN Index; > UINT8 *FileBuffer; > UINT32 FileSize; > @@ -774,16 +778,22 @@ Returns: > UINT32 MicrocodeBase; > UINT32 MicrocodeSize; > UINT8 *MicrocodeBuffer; > + UINT32 MicrocodeBufferSize; > + UINT8 *Walker; > UINT32 MicrocodeRegionOffset; > UINT32 MicrocodeRegionSize; > + UINT32 SlotSize; > STATUS Status; > EFI_FIRMWARE_VOLUME_HEADER *FvHeader; > UINTN FitEntryNumber; > BOOLEAN BiosInfoExist; > + BOOLEAN SlotMode; > BIOS_INFO_HEADER *BiosInfo; > BIOS_INFO_STRUCT *BiosInfoStruct; > UINTN BiosInfoIndex; >=20 > + SlotMode =3D FALSE; > + > // > // Init index > // > @@ -900,7 +910,34 @@ Returns: > } >=20 > // > - // 0.5 BiosInfo > + // 0.5 SlotSize > + // > + if ((Index + 1 >=3D argc) || > + ((strcmp (argv[Index], "-L") !=3D 0) && > + (strcmp (argv[Index], "-l") !=3D 0)) ) { > + // > + // Bypass > + // > + SlotSize =3D 0; > + } else { > + SlotSize =3D xtoi (argv[Index + 1]); > + > + if (SlotSize =3D=3D 0) { > + printf ("Invalid slotsize =3D %d\n", SlotSize); > + return 0; > + } > + > + SlotMode =3D IsGuidData(argv[Index + 2], &MicrocodeFfsGuid); > + if (!SlotMode) { > + printf ("Need a ffs GUID for search uCode ffs\n"); > + return 0; > + } > + > + Index +=3D 3; > + } > + > + // > + // 0.6 BiosInfo > // > if ((Index + 1 >=3D argc) || > ((strcmp (argv[Index], "-I") !=3D 0) && > @@ -1007,6 +1044,16 @@ Returns: > } else { > MicrocodeBuffer =3D MicrocodeFileBuffer; > } > + > + if (SlotMode) { > + MicrocodeBuffer =3D FindFileFromFvByGuid(MicrocodeFileBuf= fer, MicrocodeFileSize, &MicrocodeFfsGuid, > &MicrocodeBufferSize); > + if (MicrocodeBuffer =3D=3D NULL) { > + printf ("-L Parameter incorrect, GUID not found\n"); > + // not found > + return 0; > + } > + } > + > while ((UINT32)(MicrocodeBuffer - MicrocodeFileBuffer) < Mi= crocodeFileSize) { > if (*(UINT32 *)(MicrocodeBuffer) !=3D 0x1) { // HeaderVer= sion > break; > @@ -1040,7 +1087,35 @@ Returns: > gFitTableContext.MicrocodeNumber++; > gFitTableContext.FitEntryNumber++; >=20 > - MicrocodeBuffer +=3D MicrocodeSize; > + if (SlotSize !=3D 0) { > + MicrocodeBuffer +=3D SlotSize; > + } else { > + MicrocodeBuffer +=3D MicrocodeSize; > + } > + } > + > + /// > + /// Check the remaining buffer > + /// > + if (((UINT32)(MicrocodeBuffer - MicrocodeFileBuffer) < Micr= ocodeFileSize) && SlotMode !=3D 0) { > + for (Walker =3D MicrocodeBuffer; Walker < MicrocodeFileBu= ffer + MicrocodeFileSize; Walker++) { > + if (*Walker !=3D 0xFF) { > + printf ("Error: detect non-spare space after uCode ar= ray, please check uCode array!\n"); > + return 0; > + } > + } > + > + /// > + /// Split the spare space as empty buffer for save uCode = patch. > + /// > + while (MicrocodeBuffer + SlotSize <=3D MicrocodeFileBuffe= r + MicrocodeFileSize) { > + gFitTableContext.Microcode[gFitTableContext.MicrocodeNu= mber].Type =3D FIT_TABLE_TYPE_MICROCODE; > + gFitTableContext.Microcode[gFitTableContext.MicrocodeNu= mber].Address =3D MicrocodeBase + ((UINT32) (UINTN) > MicrocodeBuffer - (UINT32) (UINTN) MicrocodeFileBuffer); > + gFitTableContext.MicrocodeNumber++; > + gFitTableContext.FitEntryNumber++; > + > + MicrocodeBuffer +=3D SlotSize; > + } > } > } > break; > -- > 2.16.2.windows.1 >=20 >=20 >=20