From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from loongson.cn (loongson.cn [114.242.206.163]) by mx.groups.io with SMTP id smtpd.web09.4220.1663908333930024373 for ; Thu, 22 Sep 2022 21:45:34 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: loongson.cn, ip: 114.242.206.163, mailfrom: lichao@loongson.cn) Received: from lichao-PC (unknown [10.40.24.149]) by localhost.localdomain (Coremail) with SMTP id AQAAf8DxReLqOS1jinwgAA--.56901S2; Fri, 23 Sep 2022 12:45:30 +0800 (CST) Date: Fri, 23 Sep 2022 12:45:30 +0800 From: "Chao Li" To: Michael D Kinney Cc: Liming Gao , Zhiguang Liu , "=?utf-8?Q?devel=40edk2.groups.io?=" Message-ID: <4F1D80C1-B531-422B-9A8A-8EEACB41C09D@getmailspring.com> In-Reply-To: <20220914094118.3696973-1-lichao@loongson.cn> References: <20220914094118.3696973-1-lichao@loongson.cn> Subject: Re: [PATCH v2 24/34] MdePkg/BaseCacheMaintenanceLib: LoongArch cache maintenance implementation. X-Mailer: Mailspring MIME-Version: 1.0 X-CM-TRANSID: AQAAf8DxReLqOS1jinwgAA--.56901S2 X-Coremail-Antispam: 1UD129KBjvJXoW3KrWkCrykCFyxAw1fZF1kXwb_yoWDCrW5pr WfGr47trW8XrWxG3yvqw48GFn5ua95Ja42y3s8C34Syrn5tF97Ca4jyr1Ygayjkr1xAw1I qw47tanrXFs8ZaDanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUBlb7Iv0xC_KF4lb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I2 0VC2zVCF04k26cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28lY4IEw2IIxxk0rw A2F7IY1VAKz4vEj48ve4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_JFI_Gr1l84ACjcxK6xII jxv20xvEc7CjxVAFwI0_Cr0_Gr1UM28EF7xvwVC2z280aVAFwI0_Cr1j6rxdM28EF7xvwV C2z280aVCY1x0267AKxVW0oVCq3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40Eb7x2 x7xS6r1j6r4UMc02F40EFcxC0VAKzVAqx4xG6I80ewAqx4xG64kEw2xG04xIwI0_Xr0_Wr 1lYx0E2Ix0cI8IcVAFwI0_JrI_JrylYx0Ex4A2jsIE14v26r4j6F4UMcvjeVCFs4IE7xkE bVWUJVW8JwACjcxG0xvY0x0EwIxGrwCjr7xvwVCIw2I0I7xG6c02F41lc2xSY4AK6svPMx AIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_JrI_ JrWlx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUAVWUtwCIc40Y0x0EwI xGrwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVWUJVW8 JwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Gr0_Cr1lIxAIcV C2z280aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7IU8pOJUUUUUU== X-CM-SenderInfo: xolfxt3r6o00pqjv00gofq/1tbiAQASCGMsUF0RiAABsB Content-Type: multipart/alternative; boundary="632d39ea_df1e6fc_dbe1" --632d39ea_df1e6fc_dbe1 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Content-Disposition: inline Hi Mike, I have converted the cache opeartion to .S, the implementation please ref= er to the patch 0023, can you review it again=3F Thanks, Chao -------- On 9=E6=9C=88 14 2022, at 5:41 =E4=B8=8B=E5=8D=88, Chao Li wrote: > RE=46: https://bugzilla.tianocore.org/show=5Fbug.cgi=3Fid=3D4053 > > Implement LoongArch cache maintenance functions in > BaseCacheMaintenanceLib. > > Cc: Michael D Kinney > Cc: Liming Gao > Cc: Zhiguang Liu > > Signed-off-by: Chao Li > --- > .../BaseCacheMaintenanceLib.inf =7C 6 +- > .../BaseCacheMaintenanceLib/LoongArchCache.c =7C 254 ++++++++++++++++++= > 2 files changed, 259 insertions(+), 1 deletion(-) > create mode 100644 MdePkg/Library/BaseCacheMaintenanceLib/LoongArchCach= e.c > > diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanc= eLib.inf b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib= .inf > index 33114243d5..6fd9cbe5f6 100644 > --- a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.in= f > +++ b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.in= f > =40=40 -7,6 +7,7 =40=40 > =23 Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<= BR> > > =23 Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.=
> =23 Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All = rights reserved.
> +=23 Copyright (c) 2022, Loongson Technology Corporation Limited. All r= ights reserved.
> =23 > =23 SPDX-License-Identifier: BSD-2-Clause-Patent > =23 > =40=40 -24,7 +25,7 =40=40 > > > > =23 > -=23 VALID=5FARCHITECTURES =3D IA32 X64 EBC ARM AARCH64 > +=23 VALID=5FARCHITECTURES =3D IA32 X64 EBC ARM AARCH64 RISCV64 LOONGAR= CH64 > =23 > > > =5BSources.IA32=5D > =40=40 -45,6 +46,9 =40=40 > =5BSources.RISCV64=5D > > RiscVCache.c > > > +=5BSources.LOONGARCH64=5D > + LoongArchCache.c > + > =5BPackages=5D > MdePkg/MdePkg.dec > > > diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/LoongArchCache.c b/= MdePkg/Library/BaseCacheMaintenanceLib/LoongArchCache.c > new file mode 100644 > index 0000000000..4c8773278c > --- /dev/null > +++ b/MdePkg/Library/BaseCacheMaintenanceLib/LoongArchCache.c > =40=40 -0,0 +1,254 =40=40 > +/** =40file > > + Cache Maintenance =46unctions for LoongArch. > + LoongArch cache maintenance functions has not yet been completed, and= will added in later. > + =46unctions are null functions now. > + > + Copyright (c) 2022, Loongson Technology Corporation Limited. All righ= ts reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +// > +// Include common header file for this module. > +// > +=23include > +=23include > +=23include > + > +/** > + LoongArch data barrier operation. > +**/ > +VOID > +E=46IAPI > +AsmDataBarrierLoongArch ( > + VOID > + ); > + > +/** > + LoongArch instruction barrier operation. > +**/ > +VOID > +E=46IAPI > +AsmInstructionBarrierLoongArch ( > + VOID > + ); > + > +/** > + Invalidates the entire instruction cache in cache coherency domain of= the > + calling CPU. > + > +**/ > +VOID > +E=46IAPI > +InvalidateInstructionCache ( > + VOID > + ) > +=7B > + AsmInstructionBarrierLoongArch (); > +=7D > + > +/** > + Invalidates a range of instruction cache lines in the cache coherency= domain > + of the calling CPU. > + > + Invalidates the instruction cache lines specified by Address and Leng= th. If > + Address is not aligned on a cache line boundary, then entire instruct= ion > + cache line containing Address is invalidated. If Address + Length is = not > + aligned on a cache line boundary, then the entire instruction cache l= ine > + containing Address + Length -1 is invalidated. This function may choo= se to > + invalidate the entire instruction cache if that is more efficient tha= n > + invalidating the specified range. If Length is 0, the no instruction = cache > + lines are invalidated. Address is returned. > + > + If Length is greater than (MAX=5FADDRESS - Address + 1), then ASSERT(= ). > + > + =40param=5Bin=5D Address The base address of the instruction cache li= nes to > + invalidate. If the CPU is in a physical addressing mode, then > + Address is a physical address. If the CPU is in a virtual > + addressing mode, then Address is a virtual address. > + > + =40param=5Bin=5D Length The number of bytes to invalidate from the in= struction cache. > + > + =40return Address. > + > +**/ > +VOID * > +E=46IAPI > +InvalidateInstructionCacheRange ( > + IN VOID *Address, > + IN UINTN Length > + ) > +=7B > + AsmInstructionBarrierLoongArch (); > + return Address; > +=7D > + > +/** > + Writes Back and Invalidates the entire data cache in cache coherency = domain > + of the calling CPU. > + > + Writes Back and Invalidates the entire data cache in cache coherency = domain > + of the calling CPU. This function guarantees that all dirty cache lin= es are > + written back to system memory, and also invalidates all the data cach= e lines > + in the cache coherency domain of the calling CPU. > + > +**/ > +VOID > +E=46IAPI > +WriteBackInvalidateDataCache ( > + VOID > + ) > +=7B > + DEBUG ((DEBUG=5FERROR, =22%a: Not currently implemented on LoongArch.= =5Cn=22, =5F=5F=46UNCTION=5F=5F)); > +=7D > + > +/** > + Writes Back and Invalidates a range of data cache lines in the cache > + coherency domain of the calling CPU. > + > + Writes Back and Invalidate the data cache lines specified by Address = and > + Length. If Address is not aligned on a cache line boundary, then enti= re data > + cache line containing Address is written back and invalidated. If Add= ress + > + Length is not aligned on a cache line boundary, then the entire data = cache > + line containing Address + Length -1 is written back and invalidated. = This > + function may choose to write back and invalidate the entire data cach= e if > + that is more efficient than writing back and invalidating the specifi= ed > + range. If Length is 0, the no data cache lines are written back and > + invalidated. Address is returned. > + > + If Length is greater than (MAX=5FADDRESS - Address + 1), then ASSERT(= ). > + > + =40param=5Bin=5D Address The base address of the data cache lines to = write back and > + invalidate. If the CPU is in a physical addressing mode, then > + Address is a physical address. If the CPU is in a virtual > + addressing mode, then Address is a virtual address. > + =40param=5Bin=5D Length The number of bytes to write back and invalid= ate from the > + data cache. > + > + =40return Address of cache invalidation. > + > +**/ > +VOID * > +E=46IAPI > +WriteBackInvalidateDataCacheRange ( > + IN VOID *Address, > + IN UINTN Length > + ) > +=7B > + DEBUG ((DEBUG=5FERROR, =22%a: Not currently implemented on LoongArch.= =5Cn=22, =5F=5F=46UNCTION=5F=5F)); > + return Address; > +=7D > + > +/** > + Writes Back the entire data cache in cache coherency domain of the ca= lling > + CPU. > + > + Writes Back the entire data cache in cache coherency domain of the ca= lling > + CPU. This function guarantees that all dirty cache lines are written = back to > + system memory. This function may also invalidate all the data cache l= ines in > + the cache coherency domain of the calling CPU. > + > +**/ > +VOID > +E=46IAPI > +WriteBackDataCache ( > + VOID > + ) > +=7B > + WriteBackInvalidateDataCache (); > +=7D > + > +/** > + Writes Back a range of data cache lines in the cache coherency domain= of the > + calling CPU. > + > + Writes Back the data cache lines specified by Address and Length. If = Address > + is not aligned on a cache line boundary, then entire data cache line > + containing Address is written back. If Address + Length is not aligne= d on a > + cache line boundary, then the entire data cache line containing Addre= ss + > + Length -1 is written back. This function may choose to write back the= entire > + data cache if that is more efficient than writing back the specified = range. > + If Length is 0, the no data cache lines are written back. This functi= on may > + also invalidate all the data cache lines in the specified range of th= e cache > + coherency domain of the calling CPU. Address is returned. > + > + If Length is greater than (MAX=5FADDRESS - Address + 1), then ASSERT(= ). > + > + =40param=5Bin=5D Address The base address of the data cache lines to = write back. If > + the CPU is in a physical addressing mode, then Address is a > + physical address. If the CPU is in a virtual addressing > + mode, then Address is a virtual address. > + =40param=5Bin=5D Length The number of bytes to write back from the da= ta cache. > + > + =40return Address of cache written in main memory. > + > +**/ > +VOID * > +E=46IAPI > +WriteBackDataCacheRange ( > + IN VOID *Address, > + IN UINTN Length > + ) > +=7B > + DEBUG ((DEBUG=5FERROR, =22%a: Not currently implemented on LoongArch.= =5Cn=22, =5F=5F=46UNCTION=5F=5F)); > + return Address; > +=7D > + > +/** > + Invalidates the entire data cache in cache coherency domain of the ca= lling > + CPU. > + > + Invalidates the entire data cache in cache coherency domain of the ca= lling > + CPU. This function must be used with care because dirty cache lines a= re not > + written back to system memory. It is typically used for cache diagnos= tics. If > + the CPU does not support invalidation of the entire data cache, then = a write > + back and invalidate operation should be performed on the entire data = cache. > + > +**/ > +VOID > +E=46IAPI > +InvalidateDataCache ( > + VOID > + ) > +=7B > + AsmDataBarrierLoongArch (); > +=7D > + > +/** > + Invalidates a range of data cache lines in the cache coherency domain= of the > + calling CPU. > + > + Invalidates the data cache lines specified by Address and Length. If = Address > + is not aligned on a cache line boundary, then entire data cache line > + containing Address is invalidated. If Address + Length is not aligned= on a > + cache line boundary, then the entire data cache line containing Addre= ss + > + Length -1 is invalidated. This function must never invalidate any cac= he lines > + outside the specified range. If Length is 0, the no data cache lines = are > + invalidated. Address is returned. This function must be used with car= e > + because dirty cache lines are not written back to system memory. It i= s > + typically used for cache diagnostics. If the CPU does not support > + invalidation of a data cache range, then a write back and invalidate > + operation should be performed on the data cache range. > + > + If Length is greater than (MAX=5FADDRESS - Address + 1), then ASSERT(= ). > + > + =40param=5Bin=5D Address The base address of the data cache lines to = invalidate. If > + the CPU is in a physical addressing mode, then Address is a > + physical address. If the CPU is in a virtual addressing mode, > + then Address is a virtual address. > + =40param=5Bin=5D Length The number of bytes to invalidate from the da= ta cache. > + > + =40return Address. > + > +**/ > +VOID * > +E=46IAPI > +InvalidateDataCacheRange ( > + IN VOID *Address, > + IN UINTN Length > + ) > +=7B > + AsmDataBarrierLoongArch (); > + return Address; > +=7D > -- > 2.27.0 > --632d39ea_df1e6fc_dbe1 Content-Type: text/html; charset="utf-8" Content-Transfer-Encoding: quoted-printable Content-Disposition: inline
Hi Mike,
I have converted the cache opeartion to .S, the i= mplementation please refer to the patch 0023, can you review it again=3F<= /div>


Thanks,
Chao
--------

On 9=E6=9C=88= 14 2022, at 5:41 =E4=B8=8B=E5=8D=88, Chao Li <lichao=40loongson.cn>= ; wrote:
RE=46: https://bugzilla.tianocore.org= /show=5Fbug.cgi=3Fid=3D4053

Implement LoongArch cache maint= enance functions in
BaseCacheMaintenanceLib.

Cc: = Michael D Kinney <michael.d.kinney=40intel.com>
Cc: Limin= g Gao <gaoliming=40byosoft.com.cn>
Cc: Zhiguang Liu <z= higuang.liu=40intel.com>

Signed-off-by: Chao Li <lich= ao=40loongson.cn>
---
.../BaseCacheMaintenanceLib.= inf =7C 6 +-
.../BaseCacheMaintenanceLib/LoongArchCache.c =7C 2= 54 ++++++++++++++++++
2 files changed, 259 insertions(+), 1 del= etion(-)
create mode 100644 MdePkg/Library/BaseCacheMaintenance= Lib/LoongArchCache.c

diff --git a/MdePkg/Library/BaseCacheM= aintenanceLib/BaseCacheMaintenanceLib.inf b/MdePkg/Library/BaseCacheMaint= enanceLib/BaseCacheMaintenanceLib.inf
index 33114243d5..6fd9cbe= 5f6 100644
--- a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCac= heMaintenanceLib.inf
+++ b/MdePkg/Library/BaseCacheMaintenanceL= ib/BaseCacheMaintenanceLib.inf
=40=40 -7,6 +7,7 =40=40
=23 Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.&= lt;BR>

=23 Portions copyright (c) 2008 - 2009, Apple Inc= . All rights reserved.<BR>

=23 Copyright (c) 2020, He= wlett Packard Enterprise Development LP. All rights reserved.<BR>
+=23 Copyright (c) 2022, Loongson Technology Corporation Lim= ited. All rights reserved.<BR>

=23

=23 = SPDX-License-Identifier: BSD-2-Clause-Patent

=23

<= div>=40=40 -24,7 +25,7 =40=40




=23

-=23 VALID=5FARCHITECTURES =3D IA32 X64 EBC ARM AARCH64

+=23= VALID=5FARCHITECTURES =3D IA32 X64 EBC ARM AARCH64 RISCV64 LOONGARCH64
=23



=5BSources.IA32=5D

=40= =40 -45,6 +46,9 =40=40
=5BSources.RISCV64=5D

Risc= VCache.c



+=5BSources.LOONGARCH64=5D

+= LoongArchCache.c

+

=5BPackages=5D

<= div>MdePkg/MdePkg.dec



diff --git a/MdePkg/Library/B= aseCacheMaintenanceLib/LoongArchCache.c b/MdePkg/Library/BaseCacheMainten= anceLib/LoongArchCache.c
new file mode 100644
index 0= 000000000..4c8773278c
--- /dev/null
+++ b/MdePkg/Libr= ary/BaseCacheMaintenanceLib/LoongArchCache.c
=40=40 -0,0 +1,254= =40=40
+/** =40file

+ Cache Maintenance =46uncti= ons for LoongArch.

+ LoongArch cache maintenance functions = has not yet been completed, and will added in later.

+ =46u= nctions are null functions now.

+

+ Copyright= (c) 2022, Loongson Technology Corporation Limited. All rights reserved.&= lt;BR>

+

+ SPDX-License-Identifier: BSD-2-= Clause-Patent

+

+**/

+
+//

+// Include common header file for this module.
+//

+=23include <Base.h>

+= =23include <Library/BaseLib.h>

+=23include <Librar= y/DebugLib.h>

+

+/**

+ Loong= Arch data barrier operation.

+**/

+VOID
=
+E=46IAPI

+AsmDataBarrierLoongArch (

+ VOID

+ );

+

+/**

+ LoongArch instruction barrier operation.
+**/
+VOID

+E=46IAPI

+AsmInstructionBarrierL= oongArch (

+ VOID

+ );

+
<= br>
+/**

+ Invalidates the entire instruction cache in = cache coherency domain of the

+ calling CPU.

= +

+**/

+VOID

+E=46IAPI
+InvalidateInstructionCache (

+ VOID

+ = )

+=7B

+ AsmInstructionBarrierLoongArch ();
+=7D

+

+/**

+ Inva= lidates a range of instruction cache lines in the cache coherency domain<= /div>
+ of the calling CPU.

+

+ Inval= idates the instruction cache lines specified by Address and Length. If
+ Address is not aligned on a cache line boundary, then entir= e instruction

+ cache line containing Address is invalidate= d. If Address + Length is not

+ aligned on a cache line bou= ndary, then the entire instruction cache line

+ containing = Address + Length -1 is invalidated. This function may choose to

=
+ invalidate the entire instruction cache if that is more efficient = than

+ invalidating the specified range. If Length is 0, th= e no instruction cache

+ lines are invalidated. Address is = returned.

+

+ If Length is greater than (MAX=5F= ADDRESS - Address + 1), then ASSERT().

+

+ =40= param=5Bin=5D Address The base address of the instruction cache lines to<= /div>
+ invalidate. If the CPU is in a physical addressing mode, = then

+ Address is a physical address. If the CPU is in a vi= rtual

+ addressing mode, then Address is a virtual address.=

+

+ =40param=5Bin=5D Length The number of by= tes to invalidate from the instruction cache.

+

+ =40return Address.

+

+**/

= +VOID *

+E=46IAPI

+InvalidateInstructionCache= Range (

+ IN VOID *Address,

+ IN UINTN Length=

+ )

+=7B

+ AsmInstructionBarri= erLoongArch ();

+ return Address;

+=7D
<= br>
+

+/**

+ Writes Back and Invalidates = the entire data cache in cache coherency domain

+ of the ca= lling CPU.

+

+ Writes Back and Invalidates th= e entire data cache in cache coherency domain

+ of the call= ing CPU. This function guarantees that all dirty cache lines are
+ written back to system memory, and also invalidates all the data = cache lines

+ in the cache coherency domain of the calling = CPU.

+

+**/

+VOID

+E=46IAPI

+WriteBackInvalidateDataCache (

+ = VOID

+ )

+=7B

+ DEBUG ((DEBUG=5F= ERROR, =22%a: Not currently implemented on LoongArch.=5Cn=22, =5F=5F=46UN= CTION=5F=5F));

+=7D

+

+/**
+ Writes Back and Invalidates a range of data cache lines in th= e cache

+ coherency domain of the calling CPU.

+

+ Writes Back and Invalidate the data cache lines speci= fied by Address and

+ Length. If Address is not aligned on = a cache line boundary, then entire data

+ cache line contai= ning Address is written back and invalidated. If Address +

= + Length is not aligned on a cache line boundary, then the entire data ca= che

+ line containing Address + Length -1 is written back a= nd invalidated. This

+ function may choose to write back an= d invalidate the entire data cache if

+ that is more effici= ent than writing back and invalidating the specified

+ rang= e. If Length is 0, the no data cache lines are written back and

=
+ invalidated. Address is returned.

+

+ = If Length is greater than (MAX=5FADDRESS - Address + 1), then ASSERT().
+

+ =40param=5Bin=5D Address The base address = of the data cache lines to write back and

+ invalidate. If = the CPU is in a physical addressing mode, then

+ Address is= a physical address. If the CPU is in a virtual

+ addressin= g mode, then Address is a virtual address.

+ =40param=5Bin=5D= Length The number of bytes to write back and invalidate from the
+ data cache.

+

+ =40return Address of= cache invalidation.

+

+**/

+VO= ID *

+E=46IAPI

+WriteBackInvalidateDataCacheR= ange (

+ IN VOID *Address,

+ IN UINTN Length<= /div>
+ )

+=7B

+ DEBUG ((DEBUG=5FERRO= R, =22%a: Not currently implemented on LoongArch.=5Cn=22, =5F=5F=46UNCTIO= N=5F=5F));

+ return Address;

+=7D

+

+/**

+ Writes Back the entire data cache= in cache coherency domain of the calling

+ CPU.

<= div>+

+ Writes Back the entire data cache in cache coherenc= y domain of the calling

+ CPU. This function guarantees tha= t all dirty cache lines are written back to

+ system memory= . This function may also invalidate all the data cache lines in

=
+ the cache coherency domain of the calling CPU.

+
+**/

+VOID

+E=46IAPI

+WriteBackDataCache (

+ VOID

+ )

+=7B

+ WriteBackInvalidateDataCache ();

+=7D=

+

+/**

+ Writes Back a range o= f data cache lines in the cache coherency domain of the

+ c= alling CPU.

+

+ Writes Back the data cache li= nes specified by Address and Length. If Address

+ is not al= igned on a cache line boundary, then entire data cache line

+ containing Address is written back. If Address + Length is not aligned= on a

+ cache line boundary, then the entire data cache lin= e containing Address +

+ Length -1 is written back. This fu= nction may choose to write back the entire

+ data cache if = that is more efficient than writing back the specified range.

+ If Length is 0, the no data cache lines are written back. This funct= ion may
+ also invalidate all the data cache lines in the s= pecified range of the cache

+ coherency domain of the calli= ng CPU. Address is returned.

+

+ If Length is= greater than (MAX=5FADDRESS - Address + 1), then ASSERT().

+
+ =40param=5Bin=5D Address The base address of the data = cache lines to write back. If

+ the CPU is in a physical ad= dressing mode, then Address is a

+ physical address. If the= CPU is in a virtual addressing

+ mode, then Address is a v= irtual address.

+ =40param=5Bin=5D Length The number of byt= es to write back from the data cache.

+

+ =40= return Address of cache written in main memory.

+

=
+**/

+VOID *

+E=46IAPI

+Wr= iteBackDataCacheRange (

+ IN VOID *Address,

+= IN UINTN Length

+ )

+=7B

+ DEB= UG ((DEBUG=5FERROR, =22%a: Not currently implemented on LoongArch.=5Cn=22= , =5F=5F=46UNCTION=5F=5F));

+ return Address;

+=7D
+

+/**

+ Invalidates the = entire data cache in cache coherency domain of the calling

= + CPU.

+

+ Invalidates the entire data cache = in cache coherency domain of the calling

+ CPU. This functi= on must be used with care because dirty cache lines are not

+ written back to system memory. It is typically used for cache diagnost= ics. If
+ the CPU does not support invalidation of the enti= re data cache, then a write

+ back and invalidate operation= should be performed on the entire data cache.

+

<= div>+**/
+VOID

+E=46IAPI

+Inval= idateDataCache (

+ VOID

+ )

+=7B=

+ AsmDataBarrierLoongArch ();

+=7D

=
+

+/**

+ Invalidates a range of data cac= he lines in the cache coherency domain of the

+ calling CPU= .

+

+ Invalidates the data cache lines specif= ied by Address and Length. If Address

+ is not aligned on a= cache line boundary, then entire data cache line

+ contain= ing Address is invalidated. If Address + Length is not aligned on a
=
+ cache line boundary, then the entire data cache line containin= g Address +

+ Length -1 is invalidated. This function must = never invalidate any cache lines

+ outside the specified ra= nge. If Length is 0, the no data cache lines are

+ invalida= ted. Address is returned. This function must be used with care

<= div>+ because dirty cache lines are not written back to system memory. It= is
+ typically used for cache diagnostics. If the CPU does= not support

+ invalidation of a data cache range, then a w= rite back and invalidate

+ operation should be performed on= the data cache range.

+

+ If Length is great= er than (MAX=5FADDRESS - Address + 1), then ASSERT().

+
+ =40param=5Bin=5D Address The base address of the data cache = lines to invalidate. If

+ the CPU is in a physical addressi= ng mode, then Address is a

+ physical address. If the CPU i= s in a virtual addressing mode,

+ then Address is a virtual= address.

+ =40param=5Bin=5D Length The number of bytes to = invalidate from the data cache.

+

+ =40return= Address.

+

+**/

+VOID *
<= br>
+E=46IAPI

+InvalidateDataCacheRange (

+ IN VOID *Address,

+ IN UINTN Length

+ )
+=7B

+ AsmDataBarrierLoongArch ();

+ return Address;

+=7D

--
2.27.0<= /div>
--632d39ea_df1e6fc_dbe1--