From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web10.8928.1586174147832800377 for ; Mon, 06 Apr 2020 04:55:48 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: ard.biesheuvel@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 53BFA30E; Mon, 6 Apr 2020 04:55:47 -0700 (PDT) Received: from [10.37.8.45] (unknown [10.37.8.45]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B87DC3F52E; Mon, 6 Apr 2020 04:55:46 -0700 (PDT) Subject: Re: [PATCH 1/1] ArmPkg: rename misleading local #define in CpuDxe To: Leif Lindholm , devel@edk2.groups.io References: <20200403114847.15760-1-leif@nuviainc.com> From: "Ard Biesheuvel" Message-ID: <4ac2f00a-f51c-073d-de13-86e9d4cee565@arm.com> Date: Mon, 6 Apr 2020 13:55:44 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 MIME-Version: 1.0 In-Reply-To: <20200403114847.15760-1-leif@nuviainc.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit On 4/3/20 1:48 PM, Leif Lindholm wrote: > The local #define TT_ATTR_INDX_INVALID is used as a local error code > in the AArch64 implementation, but is misleadingly named to match the > definitions in ArmPkg/Include/Chipset/AArch64Mmu.h. > > Rename it INVALID_ENTRY to reduce confusion and improve readability. > > Signed-off-by: Leif Lindholm Reviewed-by: Ard Biesheuvel > --- > ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c | 14 +++++++------- > 1 file changed, 7 insertions(+), 7 deletions(-) > > diff --git a/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c b/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c > index 29fa08f9e07c..fca2d4f7638a 100644 > --- a/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c > +++ b/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c > @@ -13,7 +13,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent > #include > #include "CpuDxe.h" > > -#define TT_ATTR_INDX_INVALID ((UINT32)~0) > +#define INVALID_ENTRY ((UINT32)~0) > > #define MIN_T0SZ 16 > #define BITS_PER_LEVEL 9 > @@ -98,7 +98,7 @@ GetFirstPageAttribute ( > { > return FirstEntry & TT_ATTR_INDX_MASK; > } else { > - return TT_ATTR_INDX_INVALID; > + return INVALID_ENTRY; > } > } > > @@ -139,8 +139,8 @@ GetNextEntryAttribute ( > // If Entry is a Table Descriptor type entry then go through the sub-level table > if ((EntryType == TT_TYPE_BLOCK_ENTRY) || > ((TableLevel == 3) && (EntryType == TT_TYPE_BLOCK_ENTRY_LEVEL3))) { > - if ((*PrevEntryAttribute == TT_ATTR_INDX_INVALID) || (EntryAttribute != *PrevEntryAttribute)) { > - if (*PrevEntryAttribute != TT_ATTR_INDX_INVALID) { > + if ((*PrevEntryAttribute == INVALID_ENTRY) || (EntryAttribute != *PrevEntryAttribute)) { > + if (*PrevEntryAttribute != INVALID_ENTRY) { > // Update GCD with the last region > SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, > *StartGcdRegion, > @@ -164,7 +164,7 @@ GetNextEntryAttribute ( > (BaseAddress + (Index * TT_ADDRESS_AT_LEVEL(TableLevel))), > PrevEntryAttribute, StartGcdRegion); > } else { > - if (*PrevEntryAttribute != TT_ATTR_INDX_INVALID) { > + if (*PrevEntryAttribute != INVALID_ENTRY) { > // Update GCD with the last region > SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, > *StartGcdRegion, > @@ -173,7 +173,7 @@ GetNextEntryAttribute ( > > // Start of the new region > *StartGcdRegion = BaseAddress + (Index * TT_ADDRESS_AT_LEVEL(TableLevel)); > - *PrevEntryAttribute = TT_ATTR_INDX_INVALID; > + *PrevEntryAttribute = INVALID_ENTRY; > } > } > } > @@ -238,7 +238,7 @@ SyncCacheConfig ( > &PageAttribute, &BaseAddressGcdRegion); > > // Update GCD with the last region if valid > - if (PageAttribute != TT_ATTR_INDX_INVALID) { > + if (PageAttribute != INVALID_ENTRY) { > SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, > BaseAddressGcdRegion, > EndAddressGcdRegion - BaseAddressGcdRegion, >