From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=65.50.211.136; helo=mail.zytor.com; envelope-from=pcacjr@zytor.com; receiver=edk2-devel@lists.01.org Received: from mail.zytor.com (terminus.zytor.com [65.50.211.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id D3FA221B00DC4 for ; Wed, 15 Nov 2017 17:44:51 -0800 (PST) Received: from [192.168.15.5] (187.113.193.87.static.host.gvt.net.br [187.113.193.87] (may be forged)) (authenticated bits=0) by mail.zytor.com (8.15.2/8.15.2) with ESMTPSA id vAG1kSrg005486 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NO); Wed, 15 Nov 2017 17:46:29 -0800 To: edk2-devel@lists.01.org Cc: Rick Bramley , Andrew Fish , Eric Dong , Laszlo Ersek , "Brian J. Johnson" , Jeff Fan References: From: Paulo Alcantara Message-ID: <4c77020a-e01e-f048-9410-f474c6128601@zytor.com> Date: Wed, 15 Nov 2017 23:46:22 -0200 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.4.0 MIME-Version: 1.0 In-Reply-To: Subject: Re: [RFC v2 0/3] Stack trace support in X64 exception handling X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 16 Nov 2017 01:44:52 -0000 X-Groupsio-MsgNum: 17515 Content-Type: multipart/mixed; boundary="------------44CE604379D1399E3F4921ED" Content-Language: en-US --------------44CE604379D1399E3F4921ED Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Hi, On 11/15/2017 11:18 PM, Paulo Alcantara wrote: > Hi, > > This series adds stack trace support during a X64 CPU exception. > > Informations like back trace, stack contents and image module names > (that were part of the call stack) will be dumped out. > > We already have such support in ARM/AArch64 (IIRC) exception handling > (thanks to Ard), and then I thought we'd also deserve it in X64 and > IA-32 platforms. > > What do you think guys? > > BTW, I've tested this only with OVMF (X64 only), using: > - gcc-6.3.0, GCC5, NOOPT > > Any other tests would be really appreciable. > > Thanks! > Paulo > > Repo: https://github.com/pcacjr/edk2.git > Branch: stacktrace_v2 > > Cc: Rick Bramley > Cc: Andrew Fish > Cc: Eric Dong > Cc: Laszlo Ersek > Cc: "Brian J. Johnson" > Cc: Jeff Fan > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Paulo Alcantara > --- > > v1 -> v2: > * Add IA32 arch support (GCC toolchain only) > * Replace hard-coded stack alignment value (16) with > CPU_STACK_ALIGNMENT. > * Check for proper stack and frame pointer alignments. > * Fix initialization of UnwoundStacksCount to 1. > * Move GetPdbFileName() to common code since it will be used by both > IA32 and X64 implementations. Sorry for the delay in sending v2. It's holiday here :-) FWIW, I've attached two files which contain stack trace dumps of IA32 and X64 exceptions. The new IA32 arch support is still limited to GCC only (that is, relying on frame pointers), but I'll start investing in a new solution that would work on both MSVC and GCC toolchains -- probably this weekend. If I come up with something, I'll let you know. On IA32, I performed the same test as in X64 to trigger an NMI interrupt manually with: asm ("int $0x2") in PartitionDxe driver and watched out the call stack. The difference between the two dumps, regardless the CPU context, etc. is that we don't see the calls from PeiCore.dll. Then I figured out that the EIP gets a value of 0 before jumping to PartitionDxe's entry point. I guess that's related to the "push $0" that Andrew mentioned earlier so the debugger knows when to stop unwinding. Although I can't see a "push 0" equivalent neither in SwitchStack.nasm nor in SwitchStack.asm for X64 -- so we're able to see the calls within PeiCore.dll. Thanks! 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