From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=216.228.121.64; helo=hqemgate15.nvidia.com; envelope-from=ashishsingha@nvidia.com; receiver=edk2-devel@lists.01.org Received: from hqemgate15.nvidia.com (hqemgate15.nvidia.com [216.228.121.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 68AC821A07A80 for ; Thu, 8 Nov 2018 10:58:31 -0800 (PST) Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 08 Nov 2018 10:58:27 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 08 Nov 2018 10:58:30 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 08 Nov 2018 10:58:30 -0800 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 8 Nov 2018 18:58:30 +0000 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 8 Nov 2018 18:58:29 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Thu, 8 Nov 2018 18:58:30 +0000 Received: from ashishsingha-lnx.nvidia.com (Not Verified[10.28.48.147]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Thu, 08 Nov 2018 10:58:29 -0800 From: Ashish Singhal To: CC: Ashish Singhal Date: Thu, 8 Nov 2018 11:58:26 -0700 Message-ID: <4d91387d2b96ec0b20b2aa78aaacc921ae258d0f.1541703096.git.ashishsingha@nvidia.com> X-Mailer: git-send-email 2.7.4 X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1541703507; bh=nWhg5oJwRLB2QrYup/TT0kbsceBQegKGhPfv5Ou6tD0=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: X-NVConfidentiality:MIME-Version:Content-Type; b=dfRGMr3umnMjyB+0FZy/TyeMkFSPt/yoZwCn2Oh+1G+aAxsbCegeKtVVDpHc7JhZM 1bvDwi2WkxJMxOzQT+fhDodVL2+OxcRSO7LYrgGVGdxcM5V4R/YtfBe2TieBuiQtjz x/PKUVl3/Wmr6gKbn9fDNEdlE1k5p8O3IVc/oXja1SMjZAFYcXp7OOgzPBU85K0U+z XGPDSZ+dd6rlhQPcaL4NpuhhlOAEfV70T7iRsnKLZE6t+1sIjqi6ZqSLDb9xmKEbvm 2K2gFx0dyWIoecEkVZGT6y9DMRkh8I0RjEOHCDWPg4UV8lCdBjB0AEbu91OtaDPd55 /V/CMPtOra0Ww== Subject: [PATCH 1/2] MdeModulePkg/SdMmcPciHcDxe: Declare V4 64 bit address capability X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 08 Nov 2018 18:58:31 -0000 Content-Type: text/plain Add capability declaration for V4.x 64 bit system address support. This would be used for host controllers working in version 4. Enable 64 bit DMA support in PCI layer if V3 or V4 64 bit support is enabled in host capability register. The usage of this new field does not need a guard for version check as spec for previous SDMMC versions defines this field as reserved with default value of 0. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ashish Singhal --- MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c | 4 ++-- MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 3 ++- MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h | 10 +++++----- 3 files changed, 9 insertions(+), 8 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c index bf9869d..1c18ea4 100644 --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c @@ -617,7 +617,6 @@ SdMmcPciHcDriverBindingStart ( } } - Support64BitDma = TRUE; for (Slot = FirstBar; Slot < (FirstBar + SlotNum); Slot++) { Private->Slot[Slot].Enable = TRUE; @@ -638,7 +637,8 @@ SdMmcPciHcDriverBindingStart ( } DumpCapabilityReg (Slot, &Private->Capability[Slot]); - Support64BitDma &= Private->Capability[Slot].SysBus64; + Support64BitDma = (Private->Capability[Slot].SysBus64V3 | + Private->Capability[Slot].SysBus64V4); Status = SdMmcHcGetMaxCurrent (PciIo, Slot, &Private->MaxCurrent[Slot]); if (EFI_ERROR (Status)) { diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c index bedc968..e506875 100644 --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c @@ -45,7 +45,8 @@ DumpCapabilityReg ( DEBUG ((DEBUG_INFO, " Voltage 3.3 %a\n", Capability->Voltage33 ? "TRUE" : "FALSE")); DEBUG ((DEBUG_INFO, " Voltage 3.0 %a\n", Capability->Voltage30 ? "TRUE" : "FALSE")); DEBUG ((DEBUG_INFO, " Voltage 1.8 %a\n", Capability->Voltage18 ? "TRUE" : "FALSE")); - DEBUG ((DEBUG_INFO, " 64-bit Sys Bus %a\n", Capability->SysBus64 ? "TRUE" : "FALSE")); + DEBUG ((DEBUG_INFO, " V4 64-bit Sys Bus %a\n", Capability->SysBus64V4 ? "TRUE" : "FALSE")); + DEBUG ((DEBUG_INFO, " V3 64-bit Sys Bus %a\n", Capability->SysBus64V3 ? "TRUE" : "FALSE")); DEBUG ((DEBUG_INFO, " Async Interrupt %a\n", Capability->AsyncInt ? "TRUE" : "FALSE")); DEBUG ((DEBUG_INFO, " SlotType ")); if (Capability->SlotType == 0x00) { diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h index 7e3f588..cc138fc 100644 --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h @@ -114,24 +114,24 @@ typedef struct { UINT32 Voltage33:1; // bit 24 UINT32 Voltage30:1; // bit 25 UINT32 Voltage18:1; // bit 26 - UINT32 Reserved3:1; // bit 27 - UINT32 SysBus64:1; // bit 28 + UINT32 SysBus64V4:1; // bit 27 + UINT32 SysBus64V3:1; // bit 28 UINT32 AsyncInt:1; // bit 29 UINT32 SlotType:2; // bit 30:31 UINT32 Sdr50:1; // bit 32 UINT32 Sdr104:1; // bit 33 UINT32 Ddr50:1; // bit 34 - UINT32 Reserved4:1; // bit 35 + UINT32 Reserved3:1; // bit 35 UINT32 DriverTypeA:1; // bit 36 UINT32 DriverTypeC:1; // bit 37 UINT32 DriverTypeD:1; // bit 38 UINT32 DriverType4:1; // bit 39 UINT32 TimerCount:4; // bit 40:43 - UINT32 Reserved5:1; // bit 44 + UINT32 Reserved4:1; // bit 44 UINT32 TuningSDR50:1; // bit 45 UINT32 RetuningMod:2; // bit 46:47 UINT32 ClkMultiplier:8; // bit 48:55 - UINT32 Reserved6:7; // bit 56:62 + UINT32 Reserved5:7; // bit 56:62 UINT32 Hs400:1; // bit 63 } SD_MMC_HC_SLOT_CAP; -- 2.7.4