From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by mx.groups.io with SMTP id smtpd.web12.8480.1648454962517853012 for ; Mon, 28 Mar 2022 01:09:52 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=CiDM2zy1; spf=pass (domain: intel.com, ip: 192.55.52.120, mailfrom: min.m.xu@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1648454992; x=1679990992; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=PwAVat4wn+/FHcP/Ajyw9tD4CvQ3XQSO/p8apvU2jIk=; b=CiDM2zy1zQ+zF/cnvk+XBVTZN98xG79sANSAZ4PsvMpDj4pGwxVcmn8m iUfzS0wwmda6w2002d+c4RfALJ1uZP39LAj/3gQJSmzl+5FCebwekP8FI tIH4Fb6VWohRjFt4ZhC54im5HnsV5BwVPvmvry6v7Zjq+cwCjFowQsYHq cVxfM+bbNzK9OkT+cCyUkC2jyJLYnvbxH15MKKdWcT8LXTXAkdgcom2HK XXl54Kg515jpoUQB3ruTXUmMhIQJ1aCdzcUYahAzWTALXm0PxTYw2aJun cXLSMwauop6Js0MTDpe89cxuBvhSlD7xqKy9GKh6nBtQkOojPNQ9OD1gQ g==; X-IronPort-AV: E=McAfee;i="6200,9189,10299"; a="257771024" X-IronPort-AV: E=Sophos;i="5.90,216,1643702400"; d="scan'208";a="257771024" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Mar 2022 01:09:51 -0700 X-IronPort-AV: E=Sophos;i="5.90,216,1643702400"; d="scan'208";a="563427537" Received: from mxu9-mobl1.ccr.corp.intel.com ([10.249.175.167]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Mar 2022 01:09:48 -0700 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Ard Biesheuvel , Jordan Justen , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky , Gerd Hoffmann , Sebastien Boeuf Subject: [PATCH V11 22/47] OvmfPkg/PlatformPei: Refactor AddressWidthInitialization Date: Mon, 28 Mar 2022 16:08:01 +0800 Message-Id: <4fcf2fdf74b0c474341b22ca113544dabb284314.1648454441.git.min.m.xu@intel.com> X-Mailer: git-send-email 2.29.2.windows.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3863 >>From this patch we start to restruct the functions which set PCDs into two, one for PlatformInitLib, one for PlatformPei. AddressWidthInitialization is the first one. It is splitted into two: - PlatformAddressWidthInitialization is for PlatformInitLib - AddressWidthInitialization is for PlatformPei. It calls PlatformAddressWidthInitialization then set PCDs. Below functions are also refined for PlatformInitLib: - PlatformScanOrAdd64BitE820Ram - PlatformGetSystemMemorySizeAbove4gb - PlatformGetFirstNonAddress All the SetPcd codes are removed from above functions. Cc: Ard Biesheuvel Cc: Jordan Justen Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Cc: Gerd Hoffmann Cc: Sebastien Boeuf Acked-by: Gerd Hoffmann Signed-off-by: Min Xu --- OvmfPkg/PlatformPei/MemDetect.c | 117 ++++++++++++++++++++------------ OvmfPkg/PlatformPei/Platform.c | 6 +- 2 files changed, 78 insertions(+), 45 deletions(-) diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetect.c index f3819b997b3b..5507d9585bab 100644 --- a/OvmfPkg/PlatformPei/MemDetect.c +++ b/OvmfPkg/PlatformPei/MemDetect.c @@ -189,7 +189,7 @@ QemuUc32BaseInitialization ( Find the highest exclusive >=4GB RAM address, or produce memory resource descriptor HOBs for RAM entries that start at or above 4GB. - @param[out] MaxAddress If MaxAddress is NULL, then ScanOrAdd64BitE820Ram() + @param[out] MaxAddress If MaxAddress is NULL, then PlatformScanOrAdd64BitE820Ram() produces memory resource descriptor HOBs for RAM entries that start at or above 4GB. @@ -210,7 +210,7 @@ QemuUc32BaseInitialization ( **/ STATIC EFI_STATUS -ScanOrAdd64BitE820Ram ( +PlatformScanOrAdd64BitE820Ram ( IN BOOLEAN AddHighHob, OUT UINT64 *LowMemory OPTIONAL, OUT UINT64 *MaxAddress OPTIONAL @@ -385,7 +385,7 @@ GetSystemMemorySizeBelow4gb ( return (UINT32)GetHighestSystemMemoryAddressFromPvhMemmap (TRUE); } - Status = ScanOrAdd64BitE820Ram (FALSE, &LowerMemorySize, NULL); + Status = PlatformScanOrAdd64BitE820Ram (FALSE, &LowerMemorySize, NULL); if ((Status == EFI_SUCCESS) && (LowerMemorySize > 0)) { return (UINT32)LowerMemorySize; } @@ -407,7 +407,7 @@ GetSystemMemorySizeBelow4gb ( STATIC UINT64 -GetSystemMemorySizeAbove4gb ( +PlatformGetSystemMemorySizeAbove4gb ( ) { UINT32 Size; @@ -434,7 +434,7 @@ GetSystemMemorySizeAbove4gb ( **/ STATIC UINT64 -GetFirstNonAddress ( +PlatformGetFirstNonAddress ( IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob ) { @@ -444,7 +444,6 @@ GetFirstNonAddress ( FIRMWARE_CONFIG_ITEM FwCfgItem; UINTN FwCfgSize; UINT64 HotPlugMemoryEnd; - RETURN_STATUS PcdStatus; // // set FirstNonAddress to suppress incorrect compiler/analyzer warnings @@ -458,9 +457,9 @@ GetFirstNonAddress ( // Otherwise, get the flat size of the memory above 4GB from the CMOS (which // can only express a size smaller than 1TB), and add it to 4GB. // - Status = ScanOrAdd64BitE820Ram (FALSE, NULL, &FirstNonAddress); + Status = PlatformScanOrAdd64BitE820Ram (FALSE, NULL, &FirstNonAddress); if (EFI_ERROR (Status)) { - FirstNonAddress = BASE_4GB + GetSystemMemorySizeAbove4gb (); + FirstNonAddress = BASE_4GB + PlatformGetSystemMemorySizeAbove4gb (); } // @@ -475,12 +474,6 @@ GetFirstNonAddress ( #endif - // - // Otherwise, in order to calculate the highest address plus one, we must - // consider the 64-bit PCI host aperture too. Fetch the default size. - // - PlatformInfoHob->PcdPciMmio64Size = PcdGet64 (PcdPciMmio64Size); - // // See if the user specified the number of megabytes for the 64-bit PCI host // aperture. Accept an aperture size up to 16TB. @@ -522,8 +515,6 @@ GetFirstNonAddress ( "%a: disabling 64-bit PCI host aperture\n", __FUNCTION__ )); - PcdStatus = PcdSet64S (PcdPciMmio64Size, 0); - ASSERT_RETURN_ERROR (PcdStatus); } // @@ -574,26 +565,6 @@ GetFirstNonAddress ( // PlatformInfoHob->PcdPciMmio64Base = ALIGN_VALUE (PlatformInfoHob->PcdPciMmio64Base, GetPowerOfTwo64 (PlatformInfoHob->PcdPciMmio64Size)); - if (PlatformInfoHob->BootMode != BOOT_ON_S3_RESUME) { - // - // The core PciHostBridgeDxe driver will automatically add this range to - // the GCD memory space map through our PciHostBridgeLib instance; here we - // only need to set the PCDs. - // - PcdStatus = PcdSet64S (PcdPciMmio64Base, PlatformInfoHob->PcdPciMmio64Base); - ASSERT_RETURN_ERROR (PcdStatus); - PcdStatus = PcdSet64S (PcdPciMmio64Size, PlatformInfoHob->PcdPciMmio64Size); - ASSERT_RETURN_ERROR (PcdStatus); - - DEBUG (( - DEBUG_INFO, - "%a: Pci64Base=0x%Lx Pci64Size=0x%Lx\n", - __FUNCTION__, - PlatformInfoHob->PcdPciMmio64Base, - PlatformInfoHob->PcdPciMmio64Size - )); - } - // // The useful address space ends with the 64-bit PCI host aperture. // @@ -602,10 +573,11 @@ GetFirstNonAddress ( } /** - Initialize the mPhysMemAddressWidth variable, based on guest RAM size. + Initialize the PhysMemAddressWidth field in PlatformInfoHob based on guest RAM size. **/ VOID -AddressWidthInitialization ( +EFIAPI +PlatformAddressWidthInitialization ( IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob ) { @@ -618,7 +590,7 @@ AddressWidthInitialization ( // The DXL IPL keys off of the physical address bits advertized in the CPU // HOB. To conserve memory, we calculate the minimum address width here. // - FirstNonAddress = GetFirstNonAddress (PlatformInfoHob); + FirstNonAddress = PlatformGetFirstNonAddress (PlatformInfoHob); PhysMemAddressWidth = (UINT8)HighBitSet64 (FirstNonAddress); // @@ -645,6 +617,65 @@ AddressWidthInitialization ( PlatformInfoHob->PhysMemAddressWidth = PhysMemAddressWidth; } +/** + Initialize the PhysMemAddressWidth field in PlatformInfoHob based on guest RAM size. +**/ +VOID +AddressWidthInitialization ( + IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob + ) +{ + RETURN_STATUS PcdStatus; + + PlatformAddressWidthInitialization (PlatformInfoHob); + + // + // If DXE is 32-bit, then we're done; PciBusDxe will degrade 64-bit MMIO + // resources to 32-bit anyway. See DegradeResource() in + // "PciResourceSupport.c". + // + #ifdef MDE_CPU_IA32 + if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode)) { + return; + } + + #endif + + if (PlatformInfoHob->PcdPciMmio64Size == 0) { + if (PlatformInfoHob->BootMode != BOOT_ON_S3_RESUME) { + DEBUG (( + DEBUG_INFO, + "%a: disabling 64-bit PCI host aperture\n", + __FUNCTION__ + )); + PcdStatus = PcdSet64S (PcdPciMmio64Size, 0); + ASSERT_RETURN_ERROR (PcdStatus); + } + + return; + } + + if (PlatformInfoHob->BootMode != BOOT_ON_S3_RESUME) { + // + // The core PciHostBridgeDxe driver will automatically add this range to + // the GCD memory space map through our PciHostBridgeLib instance; here we + // only need to set the PCDs. + // + PcdStatus = PcdSet64S (PcdPciMmio64Base, PlatformInfoHob->PcdPciMmio64Base); + ASSERT_RETURN_ERROR (PcdStatus); + PcdStatus = PcdSet64S (PcdPciMmio64Size, PlatformInfoHob->PcdPciMmio64Size); + ASSERT_RETURN_ERROR (PcdStatus); + + DEBUG (( + DEBUG_INFO, + "%a: Pci64Base=0x%Lx Pci64Size=0x%Lx\n", + __FUNCTION__, + PlatformInfoHob->PcdPciMmio64Base, + PlatformInfoHob->PcdPciMmio64Size + )); + } +} + /** Calculate the cap for the permanent PEI memory. **/ @@ -704,7 +735,7 @@ GetPeiMemoryCap ( // // Add 64 MB for miscellaneous allocations. Note that for - // mPhysMemAddressWidth values close to 36, the cap will actually be + // PhysMemAddressWidth values close to 36, the cap will actually be // dominated by this increment. // return (UINT32)(EFI_PAGES_TO_SIZE (TotalPages) + SIZE_64MB); @@ -763,7 +794,7 @@ PublishPeiMemory ( PeiMemoryCap = GetPeiMemoryCap (); DEBUG (( DEBUG_INFO, - "%a: mPhysMemAddressWidth=%d PeiMemoryCap=%u KB\n", + "%a: PhysMemAddressWidth=%d PeiMemoryCap=%u KB\n", __FUNCTION__, mPlatformInfoHob.PhysMemAddressWidth, PeiMemoryCap >> 10 @@ -902,9 +933,9 @@ QemuInitializeRam ( // entries. Otherwise, create a single memory HOB with the flat >=4GB // memory size read from the CMOS. // - Status = ScanOrAdd64BitE820Ram (TRUE, NULL, NULL); + Status = PlatformScanOrAdd64BitE820Ram (TRUE, NULL, NULL); if (EFI_ERROR (Status)) { - UpperMemorySize = GetSystemMemorySizeAbove4gb (); + UpperMemorySize = PlatformGetSystemMemorySizeAbove4gb (); if (UpperMemorySize != 0) { PlatformAddMemoryBaseSizeHob (BASE_4GB, UpperMemorySize); } diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c index 3e0c56db57ed..7d370c9b8fa8 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -734,8 +734,10 @@ InitializePlatform ( DEBUG ((DEBUG_INFO, "Platform PEIM Loaded\n")); - mPlatformInfoHob.SmmSmramRequire = FeaturePcdGet (PcdSmmSmramRequire); - mPlatformInfoHob.SevEsIsEnabled = MemEncryptSevEsIsEnabled (); + mPlatformInfoHob.SmmSmramRequire = FeaturePcdGet (PcdSmmSmramRequire); + mPlatformInfoHob.SevEsIsEnabled = MemEncryptSevEsIsEnabled (); + mPlatformInfoHob.PcdPciMmio64Size = PcdGet64 (PcdPciMmio64Size); + mPlatformInfoHob.DefaultMaxCpuNumber = PcdGet32 (PcdCpuMaxLogicalProcessorNumber); PlatformDebugDumpCmos (); -- 2.29.2.windows.2