From: "Laszlo Ersek" <lersek@redhat.com>
To: devel@edk2.groups.io, kraxel@redhat.com
Cc: Erdem Aktas <erdemaktas@google.com>,
Oliver Steffen <osteffen@redhat.com>,
Jiewen Yao <jiewen.yao@intel.com>,
Ard Biesheuvel <ardb+tianocore@kernel.org>,
Min Xu <min.m.xu@intel.com>,
Tom Lendacky <thomas.lendacky@amd.com>,
Michael Roth <michael.roth@amd.com>,
Liming Gao <gaoliming@byosoft.com.cn>
Subject: Re: [edk2-devel] [PATCH v2 2/5] MdeModulePkg/DxeIplPeim: rename variable
Date: Tue, 30 Jan 2024 19:58:50 +0100 [thread overview]
Message-ID: <4fd25d70-4d95-3c4d-63aa-102be04e3c84@redhat.com> (raw)
In-Reply-To: <20240130123204.764453-3-kraxel@redhat.com>
On 1/30/24 13:32, Gerd Hoffmann wrote:
> Rename Page5LevelSupported to Page5LevelEnabled.
>
> The variable is set to true in case 5-paging level is enabled (64-bit
> PEI) or will be enabled (32-bit PEI), it does *not* tell whenever the
> 5-level paging is supported by the CPU.
>
> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
> ---
> .../Core/DxeIplPeim/X64/VirtualMemory.c | 22 +++++++++----------
> 1 file changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
> index 1d240e95966e..df6196a41cd5 100644
> --- a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
> +++ b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
> @@ -696,7 +696,7 @@ CreateIdentityMappingPageTables (
> UINTN TotalPagesNum;
> UINTN BigPageAddress;
> VOID *Hob;
> - BOOLEAN Page5LevelSupport;
> + BOOLEAN Page5LevelEnabled;
> BOOLEAN Page1GSupport;
> PAGE_TABLE_1G_ENTRY *PageDirectory1GEntry;
> UINT64 AddressEncMask;
> @@ -744,15 +744,15 @@ CreateIdentityMappingPageTables (
> // If cpu has already run in 64bit long mode PEI, Page table Level in DXE must align with previous level.
> //
> Cr4.UintN = AsmReadCr4 ();
> - Page5LevelSupport = (Cr4.Bits.LA57 != 0);
> - if (Page5LevelSupport) {
> + Page5LevelEnabled = (Cr4.Bits.LA57 != 0);
> + if (Page5LevelEnabled) {
> ASSERT (PcdGetBool (PcdUse5LevelPageTable));
> }
> } else {
> //
> // If cpu runs in 32bit protected mode PEI, Page table Level in DXE is decided by PCD and feature capability.
> //
> - Page5LevelSupport = FALSE;
> + Page5LevelEnabled = FALSE;
> if (PcdGetBool (PcdUse5LevelPageTable)) {
> AsmCpuidEx (
> CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,
> @@ -763,12 +763,12 @@ CreateIdentityMappingPageTables (
> NULL
> );
> if (EcxFlags.Bits.FiveLevelPage != 0) {
> - Page5LevelSupport = TRUE;
> + Page5LevelEnabled = TRUE;
> }
> }
> }
>
> - DEBUG ((DEBUG_INFO, "AddressBits=%u 5LevelPaging=%u 1GPage=%u\n", PhysicalAddressBits, Page5LevelSupport, Page1GSupport));
> + DEBUG ((DEBUG_INFO, "AddressBits=%u 5LevelPaging=%u 1GPage=%u\n", PhysicalAddressBits, Page5LevelEnabled, Page1GSupport));
>
> //
> // IA-32e paging translates 48-bit linear addresses to 52-bit physical addresses
> @@ -776,7 +776,7 @@ CreateIdentityMappingPageTables (
> // due to either unsupported by HW, or disabled by PCD.
> //
> ASSERT (PhysicalAddressBits <= 52);
> - if (!Page5LevelSupport && (PhysicalAddressBits > 48)) {
> + if (!Page5LevelEnabled && (PhysicalAddressBits > 48)) {
> PhysicalAddressBits = 48;
> }
>
> @@ -811,7 +811,7 @@ CreateIdentityMappingPageTables (
> //
> // Substract the one page occupied by PML5 entries if 5-Level Paging is disabled.
> //
> - if (!Page5LevelSupport) {
> + if (!Page5LevelEnabled) {
> TotalPagesNum--;
> }
>
> @@ -831,7 +831,7 @@ CreateIdentityMappingPageTables (
> // By architecture only one PageMapLevel4 exists - so lets allocate storage for it.
> //
> PageMap = (VOID *)BigPageAddress;
> - if (Page5LevelSupport) {
> + if (Page5LevelEnabled) {
> //
> // By architecture only one PageMapLevel5 exists - so lets allocate storage for it.
> //
> @@ -853,7 +853,7 @@ CreateIdentityMappingPageTables (
> PageMapLevel4Entry = (VOID *)BigPageAddress;
> BigPageAddress += SIZE_4KB;
>
> - if (Page5LevelSupport) {
> + if (Page5LevelEnabled) {
> //
> // Make a PML5 Entry
> //
> @@ -947,7 +947,7 @@ CreateIdentityMappingPageTables (
> ZeroMem (PageMapLevel4Entry, (512 - IndexOfPml4Entries) * sizeof (PAGE_MAP_AND_DIRECTORY_POINTER));
> }
>
> - if (Page5LevelSupport) {
> + if (Page5LevelEnabled) {
> Cr4.UintN = AsmReadCr4 ();
> Cr4.Bits.LA57 = 1;
> AsmWriteCr4 (Cr4.UintN);
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Thanks!
Laszlo
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next prev parent reply other threads:[~2024-01-30 18:59 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-30 12:31 [edk2-devel] [PATCH v2 0/5] OvmfPkg: Add support for 5-level paging Gerd Hoffmann
2024-01-30 12:32 ` [edk2-devel] [PATCH v2 1/5] MdeModulePkg/DxeIplPeim: fix PcdUse5LevelPageTable assert Gerd Hoffmann
2024-01-30 12:32 ` [edk2-devel] [PATCH v2 2/5] MdeModulePkg/DxeIplPeim: rename variable Gerd Hoffmann
2024-01-30 18:58 ` Laszlo Ersek [this message]
2024-01-30 12:32 ` [edk2-devel] [PATCH v2 3/5] OvmfPkg/ResetVector: improve page table flag names Gerd Hoffmann
2024-01-30 19:04 ` Laszlo Ersek
2024-01-30 19:46 ` Pedro Falcato
2024-01-30 22:28 ` Laszlo Ersek
2024-01-31 8:14 ` Gerd Hoffmann
2024-01-31 11:22 ` Laszlo Ersek
2024-01-31 17:50 ` Pedro Falcato
2024-01-30 12:32 ` [edk2-devel] [PATCH v2 4/5] OvmfPkg/ResetVector: add 5-level paging support Gerd Hoffmann
2024-01-30 19:13 ` Laszlo Ersek
2024-02-01 15:44 ` Lendacky, Thomas via groups.io
2024-02-01 16:33 ` Gerd Hoffmann
2024-02-01 23:31 ` Laszlo Ersek
2024-01-30 12:32 ` [edk2-devel] [PATCH v2 5/5] OvmfPkg/PlatformInitLib: " Gerd Hoffmann
2024-01-30 19:15 ` [edk2-devel] [PATCH v2 0/5] OvmfPkg: Add support for 5-level paging Laszlo Ersek
2024-02-01 16:01 ` Lendacky, Thomas via groups.io
2024-01-31 6:19 ` Min Xu
2024-01-31 8:24 ` Gerd Hoffmann
2024-02-01 5:44 ` Min Xu
2024-02-01 8:45 ` Gerd Hoffmann
2024-02-01 14:14 ` Gerd Hoffmann
2024-02-02 8:30 ` Min Xu
2024-02-02 8:44 ` Gerd Hoffmann
2024-02-02 19:28 ` Lendacky, Thomas via groups.io
2024-02-12 15:13 ` Gerd Hoffmann
2024-01-31 12:02 ` Laszlo Ersek
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