From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 0CA8478003C for ; Tue, 30 Jan 2024 18:59:00 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=V+7wnVj/6j+Yxlcngjtu7LpOMspb19wHJP0ShuiuzpQ=; c=relaxed/simple; d=groups.io; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From:In-Reply-To:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Language:Content-Type:Content-Transfer-Encoding; s=20140610; t=1706641139; v=1; b=VmC+Fg9lEQZ70yCsS6Lv/4v3cZwd5on4EfEOdVxCkK067TIta+U6OyRe1uDJNE+Bft1ZOLaV Pkfu0SrTmg0h+9g/B4mt32UNOyk1tP68UzrvK6RDWObSX7Ct9Zkno/t5paFYGevQ117uX3+pTiI lQZ+KO2W62rrdaZdkLbMNP5Q= X-Received: by 127.0.0.2 with SMTP id xJzmYY7687511xNSpI6U8J6l; Tue, 30 Jan 2024 10:58:59 -0800 X-Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) by mx.groups.io with SMTP id smtpd.web10.4806.1706641138857747091 for ; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,lersek@redhat.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: haGRvLi2To80w3hMlnSWiPdQx7686176AA= Content-Language: en-US Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=VmC+Fg9l; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=redhat.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io On 1/30/24 13:32, Gerd Hoffmann wrote: > Rename Page5LevelSupported to Page5LevelEnabled. >=20 > The variable is set to true in case 5-paging level is enabled (64-bit > PEI) or will be enabled (32-bit PEI), it does *not* tell whenever the > 5-level paging is supported by the CPU. >=20 > Signed-off-by: Gerd Hoffmann > --- > .../Core/DxeIplPeim/X64/VirtualMemory.c | 22 +++++++++---------- > 1 file changed, 11 insertions(+), 11 deletions(-) >=20 > diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c b/MdeModule= Pkg/Core/DxeIplPeim/X64/VirtualMemory.c > index 1d240e95966e..df6196a41cd5 100644 > --- a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c > +++ b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c > @@ -696,7 +696,7 @@ CreateIdentityMappingPageTables ( > UINTN TotalPagesNum; > UINTN BigPageAddress; > VOID *Hob; > - BOOLEAN Page5LevelSupport; > + BOOLEAN Page5LevelEnabled; > BOOLEAN Page1GSupport; > PAGE_TABLE_1G_ENTRY *PageDirectory1GEntry; > UINT64 AddressEncMask; > @@ -744,15 +744,15 @@ CreateIdentityMappingPageTables ( > // If cpu has already run in 64bit long mode PEI, Page table Level i= n DXE must align with previous level. > // > Cr4.UintN =3D AsmReadCr4 (); > - Page5LevelSupport =3D (Cr4.Bits.LA57 !=3D 0); > - if (Page5LevelSupport) { > + Page5LevelEnabled =3D (Cr4.Bits.LA57 !=3D 0); > + if (Page5LevelEnabled) { > ASSERT (PcdGetBool (PcdUse5LevelPageTable)); > } > } else { > // > // If cpu runs in 32bit protected mode PEI, Page table Level in DXE = is decided by PCD and feature capability. > // > - Page5LevelSupport =3D FALSE; > + Page5LevelEnabled =3D FALSE; > if (PcdGetBool (PcdUse5LevelPageTable)) { > AsmCpuidEx ( > CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, > @@ -763,12 +763,12 @@ CreateIdentityMappingPageTables ( > NULL > ); > if (EcxFlags.Bits.FiveLevelPage !=3D 0) { > - Page5LevelSupport =3D TRUE; > + Page5LevelEnabled =3D TRUE; > } > } > } > =20 > - DEBUG ((DEBUG_INFO, "AddressBits=3D%u 5LevelPaging=3D%u 1GPage=3D%u\n"= , PhysicalAddressBits, Page5LevelSupport, Page1GSupport)); > + DEBUG ((DEBUG_INFO, "AddressBits=3D%u 5LevelPaging=3D%u 1GPage=3D%u\n"= , PhysicalAddressBits, Page5LevelEnabled, Page1GSupport)); > =20 > // > // IA-32e paging translates 48-bit linear addresses to 52-bit physical= addresses > @@ -776,7 +776,7 @@ CreateIdentityMappingPageTables ( > // due to either unsupported by HW, or disabled by PCD. > // > ASSERT (PhysicalAddressBits <=3D 52); > - if (!Page5LevelSupport && (PhysicalAddressBits > 48)) { > + if (!Page5LevelEnabled && (PhysicalAddressBits > 48)) { > PhysicalAddressBits =3D 48; > } > =20 > @@ -811,7 +811,7 @@ CreateIdentityMappingPageTables ( > // > // Substract the one page occupied by PML5 entries if 5-Level Paging i= s disabled. > // > - if (!Page5LevelSupport) { > + if (!Page5LevelEnabled) { > TotalPagesNum--; > } > =20 > @@ -831,7 +831,7 @@ CreateIdentityMappingPageTables ( > // By architecture only one PageMapLevel4 exists - so lets allocate st= orage for it. > // > PageMap =3D (VOID *)BigPageAddress; > - if (Page5LevelSupport) { > + if (Page5LevelEnabled) { > // > // By architecture only one PageMapLevel5 exists - so lets allocate = storage for it. > // > @@ -853,7 +853,7 @@ CreateIdentityMappingPageTables ( > PageMapLevel4Entry =3D (VOID *)BigPageAddress; > BigPageAddress +=3D SIZE_4KB; > =20 > - if (Page5LevelSupport) { > + if (Page5LevelEnabled) { > // > // Make a PML5 Entry > // > @@ -947,7 +947,7 @@ CreateIdentityMappingPageTables ( > ZeroMem (PageMapLevel4Entry, (512 - IndexOfPml4Entries) * sizeof (PA= GE_MAP_AND_DIRECTORY_POINTER)); > } > =20 > - if (Page5LevelSupport) { > + if (Page5LevelEnabled) { > Cr4.UintN =3D AsmReadCr4 (); > Cr4.Bits.LA57 =3D 1; > AsmWriteCr4 (Cr4.UintN); Reviewed-by: Laszlo Ersek Thanks! Laszlo -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#114814): https://edk2.groups.io/g/devel/message/114814 Mute This Topic: https://groups.io/mt/104052211/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/leave/12367111/7686176/19134562= 12/xyzzy [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-