From: "Min Xu" <min.m.xu@intel.com>
To: devel@edk2.groups.io
Cc: Min Xu <min.m.xu@intel.com>, Eric Dong <eric.dong@intel.com>,
Ray Ni <ray.ni@intel.com>, Rahul Kumar <rahul1.kumar@intel.com>,
Brijesh Singh <brijesh.singh@amd.com>,
Erdem Aktas <erdemaktas@google.com>,
James Bottomley <jejb@linux.ibm.com>,
Jiewen Yao <jiewen.yao@intel.com>,
Tom Lendacky <thomas.lendacky@amd.com>,
Gerd Hoffmann <kraxel@redhat.com>
Subject: [PATCH V12 12/47] UefiCpuPkg: Support TDX in BaseXApicX2ApicLib
Date: Wed, 30 Mar 2022 07:46:05 +0800 [thread overview]
Message-ID: <509734c09ed1b345bc0ac016bf7c8c02ee0fae28.1648555175.git.min.m.xu@intel.com> (raw)
In-Reply-To: <cover.1648555175.git.min.m.xu@intel.com>
RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3429
MSR is accessed in BaseXApicX2ApicLib. In TDX some MSRs are accessed
directly from/to CPU. Some should be accessed via explicit requests
from the host VMM using TDCALL(TDG.VP.VMCALL). This is done by the
help of TdxLib.
Please refer to [TDX] Section 18.1
TDX: https://software.intel.com/content/dam/develop/external/us/en/
documents/tdx-module-1.0-public-spec-v0.931.pdf
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Signed-off-by: Min Xu <min.m.xu@intel.com>
---
.../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c | 160 +++++++++++++++++-
1 file changed, 152 insertions(+), 8 deletions(-)
diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
index aaa42ff8450b..2d17177df12b 100644
--- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
+++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
@@ -23,11 +23,155 @@
#include <Library/TimerLib.h>
#include <Library/PcdLib.h>
#include <Library/UefiCpuLib.h>
+#include <IndustryStandard/Tdx.h>
//
// Library internal functions
//
+/**
+ Some MSRs in TDX are accessed via TdCall.
+ Some are directly read/write from/to CPU.
+
+ @param MsrIndex Index of the MSR
+ @retval TRUE MSR accessed via TdCall.
+ @retval FALSE MSR accessed not via TdCall.
+
+**/
+BOOLEAN
+AccessMsrTdxCall (
+ IN UINT32 MsrIndex
+ )
+{
+ if (!TdIsEnabled ()) {
+ return FALSE;
+ }
+
+ switch (MsrIndex) {
+ case MSR_IA32_X2APIC_TPR:
+ case MSR_IA32_X2APIC_PPR:
+ case MSR_IA32_X2APIC_EOI:
+ case MSR_IA32_X2APIC_ISR0:
+ case MSR_IA32_X2APIC_ISR1:
+ case MSR_IA32_X2APIC_ISR2:
+ case MSR_IA32_X2APIC_ISR3:
+ case MSR_IA32_X2APIC_ISR4:
+ case MSR_IA32_X2APIC_ISR5:
+ case MSR_IA32_X2APIC_ISR6:
+ case MSR_IA32_X2APIC_ISR7:
+ case MSR_IA32_X2APIC_TMR0:
+ case MSR_IA32_X2APIC_TMR1:
+ case MSR_IA32_X2APIC_TMR2:
+ case MSR_IA32_X2APIC_TMR3:
+ case MSR_IA32_X2APIC_TMR4:
+ case MSR_IA32_X2APIC_TMR5:
+ case MSR_IA32_X2APIC_TMR6:
+ case MSR_IA32_X2APIC_TMR7:
+ case MSR_IA32_X2APIC_IRR0:
+ case MSR_IA32_X2APIC_IRR1:
+ case MSR_IA32_X2APIC_IRR2:
+ case MSR_IA32_X2APIC_IRR3:
+ case MSR_IA32_X2APIC_IRR4:
+ case MSR_IA32_X2APIC_IRR5:
+ case MSR_IA32_X2APIC_IRR6:
+ case MSR_IA32_X2APIC_IRR7:
+ return FALSE;
+ default:
+ break;
+ }
+
+ return TRUE;
+}
+
+/**
+ Read MSR value.
+
+ @param MsrIndex Index of the MSR to read
+ @retval 64-bit Value of MSR.
+
+**/
+UINT64
+LocalApicReadMsrReg64 (
+ IN UINT32 MsrIndex
+ )
+{
+ UINT64 Val;
+ UINT64 Status;
+
+ if (AccessMsrTdxCall (MsrIndex)) {
+ Status = TdVmCall (TDVMCALL_RDMSR, (UINT64)MsrIndex, 0, 0, 0, &Val);
+ if (Status != 0) {
+ TdVmCall (TDVMCALL_HALT, 0, 0, 0, 0, 0);
+ }
+ } else {
+ Val = AsmReadMsr64 (MsrIndex);
+ }
+
+ return Val;
+}
+
+/**
+ Write to MSR.
+
+ @param MsrIndex Index of the MSR to write to
+ @param Value Value to be written to the MSR
+
+ @return Value
+
+**/
+UINT64
+LocalApicWriteMsrReg64 (
+ IN UINT32 MsrIndex,
+ IN UINT64 Value
+ )
+{
+ UINT64 Status;
+
+ if (AccessMsrTdxCall (MsrIndex)) {
+ Status = TdVmCall (TDVMCALL_WRMSR, (UINT64)MsrIndex, Value, 0, 0, 0);
+ if (Status != 0) {
+ TdVmCall (TDVMCALL_HALT, 0, 0, 0, 0, 0);
+ }
+ } else {
+ AsmWriteMsr64 (MsrIndex, Value);
+ }
+
+ return Value;
+}
+
+/**
+ Read MSR value.
+
+ @param MsrIndex Index of the MSR to read
+ @retval 32-bit Value of MSR.
+
+**/
+UINT32
+LocalApicReadMsrReg32 (
+ IN UINT32 MsrIndex
+ )
+{
+ return (UINT32)LocalApicReadMsrReg64 (MsrIndex);
+}
+
+/**
+ Write to MSR.
+
+ @param MsrIndex Index of the MSR to write to
+ @param Value Value to be written to the MSR
+
+ @return Value
+
+**/
+UINT32
+LocalApicWriteMsrReg32 (
+ IN UINT32 MsrIndex,
+ IN UINT32 Value
+ )
+{
+ return (UINT32)LocalApicWriteMsrReg64 (MsrIndex, Value);
+}
+
/**
Determine if the CPU supports the Local APIC Base Address MSR.
@@ -78,7 +222,7 @@ GetLocalApicBaseAddress (
return PcdGet32 (PcdCpuLocalApicBaseAddress);
}
- ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
+ ApicBaseMsr.Uint64 = LocalApicReadMsrReg64 (MSR_IA32_APIC_BASE);
return (UINTN)(LShiftU64 ((UINT64)ApicBaseMsr.Bits.ApicBaseHi, 32)) +
(((UINTN)ApicBaseMsr.Bits.ApicBase) << 12);
@@ -109,12 +253,12 @@ SetLocalApicBaseAddress (
return;
}
- ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
+ ApicBaseMsr.Uint64 = LocalApicReadMsrReg64 (MSR_IA32_APIC_BASE);
ApicBaseMsr.Bits.ApicBase = (UINT32)(BaseAddress >> 12);
ApicBaseMsr.Bits.ApicBaseHi = (UINT32)(RShiftU64 ((UINT64)BaseAddress, 32));
- AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);
+ LocalApicWriteMsrReg64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);
}
/**
@@ -154,7 +298,7 @@ ReadLocalApicReg (
ASSERT (MmioOffset != XAPIC_ICR_HIGH_OFFSET);
MsrIndex = (UINT32)(MmioOffset >> 4) + X2APIC_MSR_BASE_ADDRESS;
- return AsmReadMsr32 (MsrIndex);
+ return LocalApicReadMsrReg32 (MsrIndex);
}
}
@@ -203,7 +347,7 @@ WriteLocalApicReg (
// Use memory fence here to force the serializing semantics to be consisent with xAPIC mode.
//
MemoryFence ();
- AsmWriteMsr32 (MsrIndex, Value);
+ LocalApicWriteMsrReg32 (MsrIndex, Value);
}
}
@@ -309,7 +453,7 @@ GetApicMode (
return LOCAL_APIC_MODE_XAPIC;
}
- ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
+ ApicBaseMsr.Uint64 = LocalApicReadMsrReg64 (MSR_IA32_APIC_BASE);
//
// Local APIC should have been enabled
//
@@ -354,9 +498,9 @@ SetApicMode (
case LOCAL_APIC_MODE_XAPIC:
break;
case LOCAL_APIC_MODE_X2APIC:
- ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
+ ApicBaseMsr.Uint64 = LocalApicReadMsrReg64 (MSR_IA32_APIC_BASE);
ApicBaseMsr.Bits.EXTD = 1;
- AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);
+ LocalApicWriteMsrReg64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);
break;
default:
ASSERT (FALSE);
--
2.29.2.windows.2
next prev parent reply other threads:[~2022-03-29 23:47 UTC|newest]
Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-29 23:45 [PATCH V12 00/47] Enable Intel TDX in OvmfPkg (Config-A) Min Xu
2022-03-29 23:45 ` [PATCH V12 01/47] MdePkg: Add Tdx.h Min Xu
2022-03-29 23:45 ` [PATCH V12 02/47] MdePkg: Update Cpuid.h for Tdx Min Xu
2022-03-29 23:45 ` [PATCH V12 03/47] MdePkg: Introduce basic Tdx functions in BaseLib Min Xu
2022-03-29 23:45 ` [PATCH V12 04/47] MdePkg: Add TdxLib to wrap Tdx operations Min Xu
2022-03-29 23:45 ` [PATCH V12 05/47] UefiCpuPkg: Extend VmgExitLibNull to handle #VE exception Min Xu
2022-03-29 23:45 ` [PATCH V12 06/47] OvmfPkg: Extend VmgExitLib " Min Xu
2022-03-29 23:46 ` [PATCH V12 07/47] UefiCpuPkg/CpuExceptionHandler: Add base support for the " Min Xu
2022-03-29 23:46 ` [PATCH V12 08/47] MdePkg: Add helper functions for Tdx guest in BaseIoLibIntrinsic Min Xu
2022-03-29 23:46 ` [PATCH V12 09/47] MdePkg: Support mmio " Min Xu
2022-03-29 23:46 ` [PATCH V12 10/47] MdePkg: Support IoFifo " Min Xu
2022-03-29 23:46 ` [PATCH V12 11/47] MdePkg: Support IoRead/IoWrite " Min Xu
2022-03-29 23:46 ` Min Xu [this message]
2022-03-29 23:46 ` [PATCH V12 13/47] MdePkg: Add macro to check SEV / TDX guest Min Xu
2022-03-29 23:46 ` [PATCH V12 14/47] UefiCpuPkg: Enable Tdx support in MpInitLib Min Xu
2022-03-30 7:53 ` [edk2-devel] " Ni, Ray
2022-04-28 13:15 ` Lendacky, Thomas
2022-04-29 2:12 ` Min Xu
2022-03-29 23:46 ` [PATCH V12 15/47] OvmfPkg: Add IntelTdx.h in OvmfPkg/Include/IndustryStandard Min Xu
2022-03-29 23:46 ` [PATCH V12 16/47] OvmfPkg: Add TdxMailboxLib Min Xu
2022-03-29 23:46 ` [PATCH V12 17/47] OvmfPkg: Create initial version of PlatformInitLib Min Xu
2022-03-29 23:46 ` [PATCH V12 18/47] OvmfPkg/PlatformInitLib: Add hob functions Min Xu
2022-03-29 23:46 ` [PATCH V12 19/47] OvmfPkg/PlatformPei: Move global variables to PlatformInfoHob Min Xu
2022-03-29 23:46 ` [PATCH V12 20/47] OvmfPkg/PlatformPei: Refactor MiscInitialization Min Xu
2022-03-29 23:46 ` [PATCH V12 21/47] OvmfPkg/PlatformPei: Refactor MiscInitialization for CloudHV Min Xu
2022-03-29 23:46 ` [PATCH V12 22/47] OvmfPkg/PlatformPei: Refactor AddressWidthInitialization Min Xu
2022-03-29 23:46 ` [PATCH V12 23/47] OvmfPkg/PlatformPei: Refactor MaxCpuCountInitialization Min Xu
2022-03-29 23:46 ` [PATCH V12 24/47] OvmfPkg/PlatformPei: Refactor QemuUc32BaseInitialization Min Xu
2022-03-29 23:46 ` [PATCH V12 25/47] OvmfPkg/PlatformPei: Refactor InitializeRamRegions Min Xu
2022-03-29 23:46 ` [PATCH V12 26/47] OvmfPkg/PlatformPei: Refactor MemMapInitialization Min Xu
2022-03-29 23:46 ` [PATCH V12 27/47] OvmfPkg/PlatformPei: Refactor NoexecDxeInitialization Min Xu
2022-03-29 23:46 ` [PATCH V12 28/47] OvmfPkg/PlatformPei: Refactor MiscInitialization Min Xu
2022-03-29 23:46 ` [PATCH V12 29/47] OvmfPkg/PlatformInitLib: Create MemDetect.c Min Xu
2022-03-29 23:46 ` [PATCH V12 30/47] OvmfPkg/PlatformInitLib: Move functions to Platform.c Min Xu
2022-03-29 23:46 ` [PATCH V12 31/47] OvmfPkg: Update PlatformInitLib to process Tdx hoblist Min Xu
2022-03-29 23:46 ` [PATCH V12 32/47] OvmfPkg/Sec: Declare local variable as volatile in SecCoreStartupWithStack Min Xu
2022-03-29 23:46 ` [PATCH V12 33/47] OvmfPkg: Update Sec to support Tdx Min Xu
2022-04-15 20:05 ` Lendacky, Thomas
2022-04-16 0:13 ` Min Xu
2022-04-16 14:52 ` Lendacky, Thomas
2022-04-17 3:03 ` Min Xu
2022-03-29 23:46 ` [PATCH V12 34/47] OvmfPkg: Check Tdx in QemuFwCfgPei to avoid DMA operation Min Xu
2022-03-29 23:46 ` [PATCH V12 35/47] MdeModulePkg: Skip setting IA32_ERER.NXE if it has already been set Min Xu
2022-03-29 23:46 ` [PATCH V12 36/47] MdeModulePkg: Add PcdTdxSharedBitMask Min Xu
2022-03-29 23:46 ` [PATCH V12 37/47] UefiCpuPkg: Update AddressEncMask in CpuPageTable Min Xu
2022-03-29 23:46 ` [PATCH V12 38/47] OvmfPkg: Update PlatformInitLib for Tdx guest Min Xu
2022-03-29 23:46 ` [PATCH V12 39/47] OvmfPkg: Update PlatformPei to support " Min Xu
2022-03-31 2:47 ` [PATCH V12 00/47] Enable Intel TDX in OvmfPkg (Config-A) Yao, Jiewen
[not found] ` <4c3aa6915fe7aac06940bea0f9bc5fdd3c539121.1648555175.git.min.m.xu@intel.com>
2022-04-15 20:51 ` [PATCH V12 42/47] OvmfPkg: Add TdxDxe driver Lendacky, Thomas
2022-04-16 1:57 ` [edk2-devel] " Min Xu
2022-04-16 15:08 ` Lendacky, Thomas
2022-04-17 0:56 ` Min Xu
2022-04-18 13:36 ` Lendacky, Thomas
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