From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from hqnvemgate25.nvidia.com (hqnvemgate25.nvidia.com [216.228.121.64]) by mx.groups.io with SMTP id smtpd.web11.1790.1584557153889623637 for ; Wed, 18 Mar 2020 11:45:54 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@nvidia.com header.s=n1 header.b=JV8DLnCe; spf=pass (domain: nvidia.com, ip: 216.228.121.64, mailfrom: username@nvidia.com) Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Wed, 18 Mar 2020 11:45:04 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Wed, 18 Mar 2020 11:45:53 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Wed, 18 Mar 2020 11:45:53 -0700 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 18 Mar 2020 18:45:53 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 18 Mar 2020 18:45:53 +0000 Received: from ashishsingha-lnx.nvidia.com (Not Verified[10.28.48.147]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Wed, 18 Mar 2020 11:45:53 -0700 From: Name To: , , CC: Ashish Singhal Subject: [PATCH] ArmPkg/ArmLib: Fix cache-invalidate initial page tables Date: Wed, 18 Mar 2020 12:45:39 -0600 Message-ID: <512a7c3c31e649633c3fab14d57dbb01f0e37291.1584555937.git.ashishsingha@nvidia.com> X-Mailer: git-send-email 2.7.4 Return-Path: username@nvidia.com MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1584557104; bh=XCcZVpf4OFGeLb1txA+DjRsTcotRI7Tivcng6P7pRHM=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: MIME-Version:Content-Type; b=JV8DLnCezXjTmMzBbMNDUUsWGn4rorfz6EWUYQqa+XpsKsIVBidEOQdbMKonW9eId Y/2lNOnGG+zsckEtGHoFrRib9vjA+qMbxchmNUPjE2rBrTTANBCetEkMNzvzhktleo Mq94+96JctL47kn/6ENW49svuKNZcdFlA7boaMviOrtnWFyVQNklKP+V/NIiEWdb+6 vgD0yvLc3er2yKdFWd77sQ6jGm3JY+Td3ZGLkfA58iuHBZv58V3PF89xhUl7/hCasS j0KAC+ccTHaHlEtHdogf+wm+kjYzc6LW9Md+QNA0mrwYaktXCACnp7XmciHyq671dy JLFQP/L4mVp3w== Content-Type: text/plain From: Ashish Singhal Because of a bug, current EL gets passed to DC IVAC instruction instead of the VA entry that needs to be invalidated. Signed-off-by: Ashish Singhal --- ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S index f744cd6..ba0ec56 100644 --- a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S +++ b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupport.S @@ -122,7 +122,7 @@ ASM_FUNC(ArmSetMAIR) ASM_FUNC(ArmUpdateTranslationTableEntry) dsb nshst lsr x1, x1, #12 - EL1_OR_EL2_OR_EL3(x0) + EL1_OR_EL2_OR_EL3(x2) 1: tlbi vaae1, x1 // TLB Invalidate VA , EL1 mrs x2, sctlr_el1 b 4f -- 2.7.4 ----------------------------------------------------------------------------------- This email message is for the sole use of the intended recipient(s) and may contain confidential information. Any unauthorized review, use, disclosure or distribution is prohibited. If you are not the intended recipient, please contact the sender by reply email and destroy all copies of the original message. -----------------------------------------------------------------------------------