From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=216.228.121.64; helo=hqemgate15.nvidia.com; envelope-from=jbrasen@nvidia.com; receiver=edk2-devel@lists.01.org Received: from hqemgate15.nvidia.com (hqemgate15.nvidia.com [216.228.121.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9FEE42119377E for ; Wed, 28 Nov 2018 12:36:37 -0800 (PST) Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Wed, 28 Nov 2018 12:35:55 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Wed, 28 Nov 2018 12:36:37 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Wed, 28 Nov 2018 12:36:37 -0800 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 28 Nov 2018 20:36:36 +0000 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 28 Nov 2018 20:36:36 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Wed, 28 Nov 2018 20:36:36 +0000 Received: from jbrasen-ux.nvidia.com (Not Verified[10.28.48.113]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Wed, 28 Nov 2018 12:36:36 -0800 From: Jeff Brasen To: CC: Jeff Brasen , Ard Biesheuvel , Leif Lindholm , "Grish Pathak" Date: Wed, 28 Nov 2018 13:36:16 -0700 Message-ID: <51b70aa08f34e31ac4e19bebdc96d5298691e9ba.1543437347.git.jbrasen@nvidia.com> X-Mailer: git-send-email 2.7.4 X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1543437355; bh=91Myn1uEZMvOFdxdv4oxK5FWZ1sNTPZRd9tU2A+fvu0=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: X-NVConfidentiality:MIME-Version:Content-Type; b=BmaVse6i+b/fVEgt6wO2y5ikDbUucxLaIgUVgNuHFZVwK4Z3Dh86vEZc7/MyQs//I PMmK1o4ZU+DOpbjzjk+57oEG4KBtpejSEK/tv9hKizBKqDGLIcj9kmxLLV8Q1bKL5y 6XMst6p/nmkEErhFpti6xlTwTDdenR/ph+nwqymIAH+AqjL+12nqCu4TBLOdq5Sj79 4gCJF4YIrqkETpADkoG+zr9kKFohQioZ2PWOigPNgZKnLG0sRCh0KcnLFNQgSmd3/Q wbPRHzG2aGcqcFUx0OtRy7jHAwv72zbpIGLZ95ycbgg9mubZvIi5gTCgGlea6JIDvc VvHc163w31N2Q== Subject: [PATCH v2] ArmPkg/ArmScmiDxe: Add clock enable function X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 28 Nov 2018 20:36:37 -0000 Content-Type: text/plain Add function to allow enabling and disabling of the clock using the SCMI interface. Add gArmScmiClock2ProtocolGuid to distinguish platforms that support new API from those that just have the older protocol. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jeff Brasen Cc: Ard Biesheuvel Cc: Leif Lindholm Cc: Grish Pathak --- ArmPkg/ArmPkg.dec | 1 + .../ArmScmiDxe/ArmScmiClockProtocolPrivate.h | 7 +++ ArmPkg/Drivers/ArmScmiDxe/ArmScmiDxe.inf | 1 + ArmPkg/Drivers/ArmScmiDxe/ScmiClockProtocol.c | 52 +++++++++++++++++++++- ArmPkg/Include/Protocol/ArmScmiClockProtocol.h | 27 +++++++++++ 5 files changed, 87 insertions(+), 1 deletion(-) diff --git a/ArmPkg/ArmPkg.dec b/ArmPkg/ArmPkg.dec index d99eb67..2f5e5b3 100644 --- a/ArmPkg/ArmPkg.dec +++ b/ArmPkg/ArmPkg.dec @@ -59,6 +59,7 @@ ## Arm System Control and Management Interface(SCMI) Clock management protocol ## ArmPkg/Include/Protocol/ArmScmiClockProtocol.h gArmScmiClockProtocolGuid = { 0x91ce67a8, 0xe0aa, 0x4012, { 0xb9, 0x9f, 0xb6, 0xfc, 0xf3, 0x4, 0x8e, 0xaa } } + gArmScmiClock2ProtocolGuid = { 0xb8d8caf2, 0x9e94, 0x462c, { 0xa8, 0x34, 0x6c, 0x99, 0xfc, 0x05, 0xef, 0xcf } } ## Arm System Control and Management Interface(SCMI) Clock management protocol ## ArmPkg/Include/Protocol/ArmScmiPerformanceProtocol.h diff --git a/ArmPkg/Drivers/ArmScmiDxe/ArmScmiClockProtocolPrivate.h b/ArmPkg/Drivers/ArmScmiDxe/ArmScmiClockProtocolPrivate.h index 0d1ec6f..c135bac 100644 --- a/ArmPkg/Drivers/ArmScmiDxe/ArmScmiClockProtocolPrivate.h +++ b/ArmPkg/Drivers/ArmScmiDxe/ArmScmiClockProtocolPrivate.h @@ -59,6 +59,13 @@ typedef struct { CLOCK_RATE_DWORD Rate; } CLOCK_RATE_SET_ATTRIBUTES; + +// Message parameters for CLOCK_CONFIG_SET command. +typedef struct { + UINT32 ClockId; + UINT32 Attributes; +} CLOCK_CONFIG_SET_ATTRIBUTES; + // if ClockAttr Bit[0] is set then clock device is enabled. #define CLOCK_ENABLE_MASK 0x1 #define CLOCK_ENABLED(ClockAttr) ((ClockAttr & CLOCK_ENABLE_MASK) == 1) diff --git a/ArmPkg/Drivers/ArmScmiDxe/ArmScmiDxe.inf b/ArmPkg/Drivers/ArmScmiDxe/ArmScmiDxe.inf index 05ce9c0..9b29b9f 100644 --- a/ArmPkg/Drivers/ArmScmiDxe/ArmScmiDxe.inf +++ b/ArmPkg/Drivers/ArmScmiDxe/ArmScmiDxe.inf @@ -46,6 +46,7 @@ [Protocols] gArmScmiBaseProtocolGuid gArmScmiClockProtocolGuid + gArmScmiClock2ProtocolGuid gArmScmiPerformanceProtocolGuid [Depex] diff --git a/ArmPkg/Drivers/ArmScmiDxe/ScmiClockProtocol.c b/ArmPkg/Drivers/ArmScmiDxe/ScmiClockProtocol.c index 64d2afa..27b53d3 100644 --- a/ArmPkg/Drivers/ArmScmiDxe/ScmiClockProtocol.c +++ b/ArmPkg/Drivers/ArmScmiDxe/ScmiClockProtocol.c @@ -388,6 +388,53 @@ ClockRateSet ( return Status; } +/** Enable/Disable specified clock. + + @param[in] This A Pointer to SCMI_CLOCK_PROTOCOL Instance. + @param[in] ClockId Identifier for the clock device. + @param[in] Enable TRUE to enable, FALSE to disable. + + @retval EFI_SUCCESS Clock enable/disable successful. + @retval EFI_DEVICE_ERROR SCP returns an SCMI error. + @retval !(EFI_SUCCESS) Other errors. +**/ +STATIC +EFI_STATUS +ClockEnable ( + IN SCMI_CLOCK2_PROTOCOL *This, + IN UINT32 ClockId, + IN BOOLEAN Enable + ) +{ + EFI_STATUS Status; + CLOCK_CONFIG_SET_ATTRIBUTES *ClockConfigSetAttributes; + SCMI_COMMAND Cmd; + UINT32 PayloadLength; + + Status = ScmiCommandGetPayload ((UINT32**)&ClockConfigSetAttributes); + if (EFI_ERROR (Status)) { + return Status; + } + + // Fill arguments for clock protocol command. + ClockConfigSetAttributes->ClockId = ClockId; + ClockConfigSetAttributes->Attributes = Enable ? BIT0 : 0; + + Cmd.ProtocolId = SCMI_PROTOCOL_ID_CLOCK; + Cmd.MessageId = SCMI_MESSAGE_ID_CLOCK_CONFIG_SET; + + PayloadLength = sizeof (CLOCK_CONFIG_SET_ATTRIBUTES); + + // Execute and wait for response on a SCMI channel. + Status = ScmiCommandExecute ( + &Cmd, + &PayloadLength, + NULL + ); + + return Status; +} + // Instance of the SCMI clock management protocol. STATIC CONST SCMI_CLOCK_PROTOCOL ScmiClockProtocol = { ClockGetVersion, @@ -395,7 +442,8 @@ STATIC CONST SCMI_CLOCK_PROTOCOL ScmiClockProtocol = { ClockGetClockAttributes, ClockDescribeRates, ClockRateGet, - ClockRateSet + ClockRateSet, + ClockEnable }; /** Initialize clock management protocol and install protocol on a given handle. @@ -413,6 +461,8 @@ ScmiClockProtocolInit ( Handle, &gArmScmiClockProtocolGuid, &ScmiClockProtocol, + &gArmScmiClock2ProtocolGuid, + &ScmiClockProtocol, NULL ); } diff --git a/ArmPkg/Include/Protocol/ArmScmiClockProtocol.h b/ArmPkg/Include/Protocol/ArmScmiClockProtocol.h index 3db26cb..28d3d59 100644 --- a/ArmPkg/Include/Protocol/ArmScmiClockProtocol.h +++ b/ArmPkg/Include/Protocol/ArmScmiClockProtocol.h @@ -24,7 +24,12 @@ 0x91ce67a8, 0xe0aa, 0x4012, {0xb9, 0x9f, 0xb6, 0xfc, 0xf3, 0x4, 0x8e, 0xaa} \ } +#define ARM_SCMI_CLOCK2_PROTOCOL_GUID { \ + 0xb8d8caf2, 0x9e94, 0x462c, { 0xa8, 0x34, 0x6c, 0x99, 0xfc, 0x05, 0xef, 0xcf } \ + } + extern EFI_GUID gArmScmiClockProtocolGuid; +extern EFI_GUID gArmScmiClock2ProtocolGuid; // Message Type for clock management protocol. typedef enum { @@ -74,6 +79,7 @@ typedef struct { #pragma pack() typedef struct _SCMI_CLOCK_PROTOCOL SCMI_CLOCK_PROTOCOL; +typedef SCMI_CLOCK_PROTOCOL SCMI_CLOCK2_PROTOCOL; // Protocol Interface functions. @@ -205,6 +211,25 @@ EFI_STATUS IN UINT64 Rate ); +/** Enable/Disable specified clock. + Function is only available under gArmScmiClock2ProtocolGuid + + @param[in] This A Pointer to SCMI_CLOCK_PROTOCOL Instance. + @param[in] ClockId Identifier for the clock device. + @param[in] Enable TRUE to enable, FALSE to disable. + + @retval EFI_SUCCESS Clock enable/disable successful. + @retval EFI_DEVICE_ERROR SCP returns an SCMI error. + @retval !(EFI_SUCCESS) Other errors. +**/ +typedef +EFI_STATUS +(EFIAPI *SCMI_CLOCK_ENABLE) ( + IN SCMI_CLOCK2_PROTOCOL *This, + IN UINT32 ClockId, + IN BOOLEAN Enable + ); + typedef struct _SCMI_CLOCK_PROTOCOL { SCMI_CLOCK_GET_VERSION GetVersion; SCMI_CLOCK_GET_TOTAL_CLOCKS GetTotalClocks; @@ -212,6 +237,8 @@ typedef struct _SCMI_CLOCK_PROTOCOL { SCMI_CLOCK_DESCRIBE_RATES DescribeRates; SCMI_CLOCK_RATE_GET RateGet; SCMI_CLOCK_RATE_SET RateSet; + //Only available under gArmScmiClock2ProtocolGuid + SCMI_CLOCK_ENABLE Enable; } SCMI_CLOCK_PROTOCOL; #endif /* ARM_SCMI_CLOCK_PROTOCOL_H_ */ -- 2.7.4