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rv:102.0) Gecko/20100101 Thunderbird/102.5.0 Subject: Re: [edk2-devel] [PATCH 1/1] ArmPlatformPkg: Remove AP support from PrePi/PrePeiCore To: Rebecca Cran , Leif Lindholm , Ard Biesheuvel , Thomas Abraham CC: devel@edk2.groups.io, quic_rcran@quicinc.com, Ard Biesheuvel , "nd@arm.com" References: <20221027173121.754041-1-rebecca@quicinc.com> <1a0045d6-d826-ab1d-4297-cac91ca7cac9@quicinc.com> From: "Sami Mujawar" In-Reply-To: <1a0045d6-d826-ab1d-4297-cac91ca7cac9@quicinc.com> X-ClientProxiedBy: LO4P123CA0458.GBRP123.PROD.OUTLOOK.COM (2603:10a6:600:1aa::13) To AS8PR08MB6806.eurprd08.prod.outlook.com (2603:10a6:20b:39b::12) MIME-Version: 1.0 X-MS-TrafficTypeDiagnostic: AS8PR08MB6806:EE_|AM0PR08MB5475:EE_|DBAEUR03FT016:EE_|PAXPR08MB7525:EE_ X-MS-Office365-Filtering-Correlation-Id: e632b72e-76de-4fa8-bdf4-08dace2b67f8 x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: lw2I4hnDP8mC19GE/PTCfig/faftufAkyxbgnpMUqgpfwDpY4I5Hf4qHl81rQXPpQjv3hZxaGtWJFCJtcNiWq/yFQLBJpFI4naeZeG5aO39lEcw7VWIqZuAG1iVZPjUzAcHyyca6NDGABxzIjbNjxg7qfVHb5AwfFE/VwRTmbzqwzfWyrSj3B+9k0hsBaZ6E6dkQPChOW9aUtczWtWrR3RTwrV6E6ECWHzOeCFjx1cQb0xIHHMKbwsGwbkYNN9hy3+G/mNxrxePz5LNlAFfZCImtl11OBmV0m2PoAvNER/oARBPVe9B9iUOYbvYelbViftrUoydamvOPYQB3jRSRV93qPA3aGIPadAUwcovu9q9n0pykLMBnqirWh5i6qTz/tQmX22AyWbvRbb4QtAGxkcwhGUcbEIUQUuwvM93RcFPzZiAXpVzV95hBHN+UnySPSWB3e8J8LYosse/+3vl3Qw/5fkfi0t9GTzaHv01f+TxmU2qihjODcK0JAD6sasDILjHNh8NOaKm6/+uZ8/VXxqi33sKGwSNin9FHNwUNIoWKKofgD8JE5KGzY1vuXGHXQSNQC0lcSCpr0OmfaICXyQJ5oulv1PoS0O4jwOBlZuhiuA44PDKZriu88Fh+z0fk5Sauvyc3gMTJzvHS8uzHxSyniv0wPxAwWQnWEErjDnyrOVoP1D8p0hBoPQYdqGgMoUEK0ri4g7ziyUA12yOYjCaEQ9F3Nchw8GWclGQXpj7gOC4/DvgCVt8ZMTnhVIokZTj6wbYf+LmQXW3tBXco55yzBY443FWPUKYEa9DqLw0= X-Forefront-Antispam-Report-Untrusted: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:AS8PR08MB6806.eurprd08.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230022)(4636009)(39860400002)(346002)(396003)(136003)(376002)(366004)(451199015)(4326008)(8676002)(66946007)(66476007)(66556008)(8936002)(44832011)(30864003)(5660300002)(83380400001)(41300700001)(36756003)(31696002)(86362001)(26005)(6512007)(6506007)(478600001)(6486002)(53546011)(966005)(186003)(2616005)(6636002)(316002)(110136005)(2906002)(54906003)(31686004)(66899015)(38100700002)(45980500001)(43740500002);DIR:OUT;SFP:1101; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Nov 2022 14:51:44.9616 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e632b72e-76de-4fa8-bdf4-08dace2b67f8 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DBAEUR03FT016.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAXPR08MB7525 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: quoted-printable Hi Leif, Rebecca, Apologies for the delay in getting back. We can drop the TC2 support in edk2-platforms. Regards, Sami Mujawar On 18/11/2022 02:09 pm, Rebecca Cran wrote: > Hi Sami, > > I was wondering if you could answer Leif's question? > > Thanks. > Rebecca Cran > > On 10/28/22 03:17, Leif Lindholm wrote: >> On Thu, Oct 27, 2022 at 20:10:33 +0200, Ard Biesheuvel wrote: >>> On Thu, 27 Oct 2022 at 19:31, Rebecca Cran =20 >>> wrote: >>>> >>>> Modern platforms use TF-A, so there's no need for support of >>>> secondary cores in EDK2 since TF-A will keep them in a holding >>>> pen until the PSCI_CPU_ON SMC call is received. >>>> >>>> Therefore, remove the code that handles secondary CPUs from >>>> PrePeiCore and PrePi and add ASSERTs if a secondary core >>>> reaches the functions. >>>> >>>> Signed-off-by: Rebecca Cran >>> >>> No objections to this patch, but this change will break the old SMP >>> 32-bit ARM platforms in edk2-platforms so you will need to propose a >>> solution for those as well. >> >> I think TC2 is the last one of those standing. And I don't see much >> value in keeping all of this around for such a niche (and old) >> platform. If someone ports TF-A to it, we could always add it back in >> later. >> >> Single-core non-PSCI platforms (i.e. beagleboard) aren't affected. >> >> Sami: would you be OK with deleting the TC2 support in edk2-platforms? >> >> / >> =C2=A0=C2=A0=C2=A0=C2=A0 Leif >> >>>> --- >>>> =C2=A0 ArmPlatformPkg/PrePeiCore/MainMPCore.c=C2=A0 | 92 -------------= ------- >>>> =C2=A0 ArmPlatformPkg/PrePeiCore/MainUniCore.c |=C2=A0 9 -- >>>> =C2=A0 ArmPlatformPkg/PrePeiCore/PrePeiCore.c=C2=A0 | 37 ++++---- >>>> =C2=A0 ArmPlatformPkg/PrePi/MainMPCore.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 | 69 --------------- >>>> =C2=A0 ArmPlatformPkg/PrePi/MainUniCore.c=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 |=C2=A0 9 -- >>>> =C2=A0 ArmPlatformPkg/PrePi/PrePi.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 | 36 ++++---- >>>> =C2=A0 6 files changed, 34 insertions(+), 218 deletions(-) >>>> >>>> diff --git a/ArmPlatformPkg/PrePeiCore/MainMPCore.c=20 >>>> b/ArmPlatformPkg/PrePeiCore/MainMPCore.c >>>> index b5d0d3a6442f..44850a4f3946 100644 >>>> --- a/ArmPlatformPkg/PrePeiCore/MainMPCore.c >>>> +++ b/ArmPlatformPkg/PrePeiCore/MainMPCore.c >>>> @@ -12,98 +12,6 @@ >>>> >>>> =C2=A0 #include "PrePeiCore.h" >>>> >>>> -/* >>>> - * This is the main function for secondary cores. They loop around=20 >>>> until a non Null value is written to >>>> - * SYS_FLAGS register.The SYS_FLAGS register is platform specific. >>>> - * Note:The secondary cores, while executing secondary_main,=20 >>>> assumes that: >>>> - *=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 : SGI 0 is configured as Non-secure = interrupt >>>> - *=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 : Priority Mask is configured to all= ow SGI 0 >>>> - *=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 : Interrupt Distributor and CPU inte= rfaces are enabled >>>> - * >>>> - */ >>>> -VOID >>>> -EFIAPI >>>> -SecondaryMain ( >>>> -=C2=A0 IN UINTN=C2=A0 MpId >>>> -=C2=A0 ) >>>> -{ >>>> -=C2=A0 EFI_STATUS=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0 Status; >>>> -=C2=A0 UINTN=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 PpiListSize; >>>> -=C2=A0 UINTN=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 PpiListCount; >>>> -=C2=A0 EFI_PEI_PPI_DESCRIPTOR=C2=A0 *PpiList; >>>> -=C2=A0 ARM_MP_CORE_INFO_PPI=C2=A0=C2=A0=C2=A0 *ArmMpCoreInfoPpi; >>>> -=C2=A0 UINTN=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 Index; >>>> -=C2=A0 UINTN=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ArmCoreCount; >>>> -=C2=A0 ARM_CORE_INFO=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0 *ArmCoreInfoTable; >>>> -=C2=A0 UINT32=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ClusterId; >>>> -=C2=A0 UINT32=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 CoreId; >>>> - >>>> -=C2=A0 VOID=C2=A0 (*SecondaryStart)( >>>> -=C2=A0=C2=A0=C2=A0 VOID >>>> -=C2=A0=C2=A0=C2=A0 ); >>>> -=C2=A0 UINTN=C2=A0 SecondaryEntryAddr; >>>> -=C2=A0 UINTN=C2=A0 AcknowledgeInterrupt; >>>> -=C2=A0 UINTN=C2=A0 InterruptId; >>>> - >>>> -=C2=A0 ClusterId =3D GET_CLUSTER_ID (MpId); >>>> -=C2=A0 CoreId=C2=A0=C2=A0=C2=A0 =3D GET_CORE_ID (MpId); >>>> - >>>> -=C2=A0 // Get the gArmMpCoreInfoPpiGuid >>>> -=C2=A0 PpiListSize =3D 0; >>>> -=C2=A0 ArmPlatformGetPlatformPpiList (&PpiListSize, &PpiList); >>>> -=C2=A0 PpiListCount =3D PpiListSize / sizeof (EFI_PEI_PPI_DESCRIPTOR)= ; >>>> -=C2=A0 for (Index =3D 0; Index < PpiListCount; Index++, PpiList++) { >>>> -=C2=A0=C2=A0=C2=A0 if (CompareGuid (PpiList->Guid, &gArmMpCoreInfoPpi= Guid) =3D=3D=20 >>>> TRUE) { >>>> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 break; >>>> -=C2=A0=C2=A0=C2=A0 } >>>> -=C2=A0 } >>>> - >>>> -=C2=A0 // On MP Core Platform we must implement the ARM MP Core Info = PPI >>>> -=C2=A0 ASSERT (Index !=3D PpiListCount); >>>> - >>>> -=C2=A0 ArmMpCoreInfoPpi =3D PpiList->Ppi; >>>> -=C2=A0 ArmCoreCount=C2=A0=C2=A0=C2=A0=C2=A0 =3D 0; >>>> -=C2=A0 Status=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 =3D ArmMpCoreInfoPpi->GetMpCoreInfo=20 >>>> (&ArmCoreCount, &ArmCoreInfoTable); >>>> -=C2=A0 ASSERT_EFI_ERROR (Status); >>>> - >>>> -=C2=A0 // Find the core in the ArmCoreTable >>>> -=C2=A0 for (Index =3D 0; Index < ArmCoreCount; Index++) { >>>> -=C2=A0=C2=A0=C2=A0 if ((GET_MPIDR_AFF1 (ArmCoreInfoTable[Index].Mpidr= ) =3D=3D=20 >>>> ClusterId) && >>>> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (GET_MPIDR_AFF0 (ArmCoreIn= foTable[Index].Mpidr) =3D=3D CoreId)) >>>> -=C2=A0=C2=A0=C2=A0 { >>>> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 break; >>>> -=C2=A0=C2=A0=C2=A0 } >>>> -=C2=A0 } >>>> - >>>> -=C2=A0 // The ARM Core Info Table must define every core >>>> -=C2=A0 ASSERT (Index !=3D ArmCoreCount); >>>> - >>>> -=C2=A0 // Clear Secondary cores MailBox >>>> -=C2=A0 MmioWrite32 (ArmCoreInfoTable[Index].MailboxClearAddress,=20 >>>> ArmCoreInfoTable[Index].MailboxClearValue); >>>> - >>>> -=C2=A0 do { >>>> -=C2=A0=C2=A0=C2=A0 ArmCallWFI (); >>>> - >>>> -=C2=A0=C2=A0=C2=A0 // Read the Mailbox >>>> -=C2=A0=C2=A0=C2=A0 SecondaryEntryAddr =3D MmioRead32=20 >>>> (ArmCoreInfoTable[Index].MailboxGetAddress); >>>> - >>>> -=C2=A0=C2=A0=C2=A0 // Acknowledge the interrupt and send End of Inter= rupt signal. >>>> -=C2=A0=C2=A0=C2=A0 AcknowledgeInterrupt =3D ArmGicAcknowledgeInterrup= t (PcdGet64=20 >>>> (PcdGicInterruptInterfaceBase), &InterruptId); >>>> -=C2=A0=C2=A0=C2=A0 // Check if it is a valid interrupt ID >>>> -=C2=A0=C2=A0=C2=A0 if (InterruptId < ArmGicGetMaxNumInterrupts (PcdGe= t64=20 >>>> (PcdGicDistributorBase))) { >>>> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 // Got a valid SGI number hence signal= End of Interrupt >>>> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ArmGicEndOfInterrupt (PcdGet64=20 >>>> (PcdGicInterruptInterfaceBase), AcknowledgeInterrupt); >>>> -=C2=A0=C2=A0=C2=A0 } >>>> -=C2=A0 } while (SecondaryEntryAddr =3D=3D 0); >>>> - >>>> -=C2=A0 // Jump to secondary core entry point. >>>> -=C2=A0 SecondaryStart =3D (VOID (*)()) SecondaryEntryAddr; >>>> -=C2=A0 SecondaryStart (); >>>> - >>>> -=C2=A0 // The secondaries shouldn't reach here >>>> -=C2=A0 ASSERT (FALSE); >>>> -} >>>> - >>>> =C2=A0 VOID >>>> =C2=A0 EFIAPI >>>> =C2=A0 PrimaryMain ( >>>> diff --git a/ArmPlatformPkg/PrePeiCore/MainUniCore.c=20 >>>> b/ArmPlatformPkg/PrePeiCore/MainUniCore.c >>>> index 1c2580eb923b..3d3c6caaa32a 100644 >>>> --- a/ArmPlatformPkg/PrePeiCore/MainUniCore.c >>>> +++ b/ArmPlatformPkg/PrePeiCore/MainUniCore.c >>>> @@ -8,15 +8,6 @@ >>>> >>>> =C2=A0 #include "PrePeiCore.h" >>>> >>>> -VOID >>>> -EFIAPI >>>> -SecondaryMain ( >>>> -=C2=A0 IN UINTN=C2=A0 MpId >>>> -=C2=A0 ) >>>> -{ >>>> -=C2=A0 ASSERT (FALSE); >>>> -} >>>> - >>>> =C2=A0 VOID >>>> =C2=A0 EFIAPI >>>> =C2=A0 PrimaryMain ( >>>> diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c=20 >>>> b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c >>>> index 42a7ccc9c6a0..64d1ef601ea3 100644 >>>> --- a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c >>>> +++ b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c >>>> @@ -117,27 +117,26 @@ CEntryPoint ( >>>> >>>> =C2=A0=C2=A0=C2=A0 // Note: The MMU will be enabled by MemoryPeim. Onl= y the=20 >>>> primary core will have the MMU on. >>>> >>>> -=C2=A0 // If not primary Jump to Secondary Main >>>> -=C2=A0 if (ArmPlatformIsPrimaryCore (MpId)) { >>>> -=C2=A0=C2=A0=C2=A0 // Invoke "ProcessLibraryConstructorList" to have = all library=20 >>>> constructors >>>> -=C2=A0=C2=A0=C2=A0 // called. >>>> -=C2=A0=C2=A0=C2=A0 ProcessLibraryConstructorList (); >>>> - >>>> -=C2=A0=C2=A0=C2=A0 PrintFirmwareVersion (); >>>> - >>>> -=C2=A0=C2=A0=C2=A0 // Initialize the Debug Agent for Source Level Deb= ugging >>>> -=C2=A0=C2=A0=C2=A0 InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC= , NULL, NULL); >>>> -=C2=A0=C2=A0=C2=A0 SaveAndSetDebugTimerInterrupt (TRUE); >>>> - >>>> -=C2=A0=C2=A0=C2=A0 // Initialize the platform specific controllers >>>> -=C2=A0=C2=A0=C2=A0 ArmPlatformInitialize (MpId); >>>> - >>>> -=C2=A0=C2=A0=C2=A0 // Goto primary Main. >>>> -=C2=A0=C2=A0=C2=A0 PrimaryMain (PeiCoreEntryPoint); >>>> -=C2=A0 } else { >>>> -=C2=A0=C2=A0=C2=A0 SecondaryMain (MpId); >>>> +=C2=A0 if (!ArmPlatformIsPrimaryCore (MpId)) { >>>> +=C2=A0=C2=A0=C2=A0 ASSERT (FALSE); >>>> =C2=A0=C2=A0=C2=A0 } >>>> >>>> +=C2=A0 // Invoke "ProcessLibraryConstructorList" to have all library= =20 >>>> constructors >>>> +=C2=A0 // called. >>>> +=C2=A0 ProcessLibraryConstructorList (); >>>> + >>>> +=C2=A0 PrintFirmwareVersion (); >>>> + >>>> +=C2=A0 // Initialize the Debug Agent for Source Level Debugging >>>> +=C2=A0 InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, NULL, NULL= ); >>>> +=C2=A0 SaveAndSetDebugTimerInterrupt (TRUE); >>>> + >>>> +=C2=A0 // Initialize the platform specific controllers >>>> +=C2=A0 ArmPlatformInitialize (MpId); >>>> + >>>> +=C2=A0 // Goto primary Main. >>>> +=C2=A0 PrimaryMain (PeiCoreEntryPoint); >>>> + >>>> =C2=A0=C2=A0=C2=A0 // PEI Core should always load and never return >>>> =C2=A0=C2=A0=C2=A0 ASSERT (FALSE); >>>> =C2=A0 } >>>> diff --git a/ArmPlatformPkg/PrePi/MainMPCore.c=20 >>>> b/ArmPlatformPkg/PrePi/MainMPCore.c >>>> index 68a7c13298d0..ce7058a2846f 100644 >>>> --- a/ArmPlatformPkg/PrePi/MainMPCore.c >>>> +++ b/ArmPlatformPkg/PrePi/MainMPCore.c >>>> @@ -33,72 +33,3 @@ PrimaryMain ( >>>> =C2=A0=C2=A0=C2=A0 // We must never return >>>> =C2=A0=C2=A0=C2=A0 ASSERT (FALSE); >>>> =C2=A0 } >>>> - >>>> -VOID >>>> -SecondaryMain ( >>>> -=C2=A0 IN=C2=A0 UINTN=C2=A0 MpId >>>> -=C2=A0 ) >>>> -{ >>>> -=C2=A0 EFI_STATUS=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0 Status; >>>> -=C2=A0 ARM_MP_CORE_INFO_PPI=C2=A0 *ArmMpCoreInfoPpi; >>>> -=C2=A0 UINTN=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 Index; >>>> -=C2=A0 UINTN=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ArmCoreCount; >>>> -=C2=A0 ARM_CORE_INFO=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 = *ArmCoreInfoTable; >>>> -=C2=A0 UINT32=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ClusterId; >>>> -=C2=A0 UINT32=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 CoreId; >>>> - >>>> -=C2=A0 VOID=C2=A0 (*SecondaryStart)( >>>> -=C2=A0=C2=A0=C2=A0 VOID >>>> -=C2=A0=C2=A0=C2=A0 ); >>>> -=C2=A0 UINTN=C2=A0 SecondaryEntryAddr; >>>> -=C2=A0 UINTN=C2=A0 AcknowledgeInterrupt; >>>> -=C2=A0 UINTN=C2=A0 InterruptId; >>>> - >>>> -=C2=A0 ClusterId =3D GET_CLUSTER_ID (MpId); >>>> -=C2=A0 CoreId=C2=A0=C2=A0=C2=A0 =3D GET_CORE_ID (MpId); >>>> - >>>> -=C2=A0 // On MP Core Platform we must implement the ARM MP Core Info= =20 >>>> PPI (gArmMpCoreInfoPpiGuid) >>>> -=C2=A0 Status =3D GetPlatformPpi (&gArmMpCoreInfoPpiGuid, (VOID=20 >>>> **)&ArmMpCoreInfoPpi); >>>> -=C2=A0 ASSERT_EFI_ERROR (Status); >>>> - >>>> -=C2=A0 ArmCoreCount =3D 0; >>>> -=C2=A0 Status=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 =3D ArmMpCoreInfoPp= i->GetMpCoreInfo (&ArmCoreCount,=20 >>>> &ArmCoreInfoTable); >>>> -=C2=A0 ASSERT_EFI_ERROR (Status); >>>> - >>>> -=C2=A0 // Find the core in the ArmCoreTable >>>> -=C2=A0 for (Index =3D 0; Index < ArmCoreCount; Index++) { >>>> -=C2=A0=C2=A0=C2=A0 if ((GET_MPIDR_AFF1 (ArmCoreInfoTable[Index].Mpidr= ) =3D=3D=20 >>>> ClusterId) && >>>> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (GET_MPIDR_AFF0 (ArmCoreIn= foTable[Index].Mpidr) =3D=3D CoreId)) >>>> -=C2=A0=C2=A0=C2=A0 { >>>> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 break; >>>> -=C2=A0=C2=A0=C2=A0 } >>>> -=C2=A0 } >>>> - >>>> -=C2=A0 // The ARM Core Info Table must define every core >>>> -=C2=A0 ASSERT (Index !=3D ArmCoreCount); >>>> - >>>> -=C2=A0 // Clear Secondary cores MailBox >>>> -=C2=A0 MmioWrite32 (ArmCoreInfoTable[Index].MailboxClearAddress,=20 >>>> ArmCoreInfoTable[Index].MailboxClearValue); >>>> - >>>> -=C2=A0 do { >>>> -=C2=A0=C2=A0=C2=A0 ArmCallWFI (); >>>> - >>>> -=C2=A0=C2=A0=C2=A0 // Read the Mailbox >>>> -=C2=A0=C2=A0=C2=A0 SecondaryEntryAddr =3D MmioRead32=20 >>>> (ArmCoreInfoTable[Index].MailboxGetAddress); >>>> - >>>> -=C2=A0=C2=A0=C2=A0 // Acknowledge the interrupt and send End of Inter= rupt signal. >>>> -=C2=A0=C2=A0=C2=A0 AcknowledgeInterrupt =3D ArmGicAcknowledgeInterrup= t (PcdGet64=20 >>>> (PcdGicInterruptInterfaceBase), &InterruptId); >>>> -=C2=A0=C2=A0=C2=A0 // Check if it is a valid interrupt ID >>>> -=C2=A0=C2=A0=C2=A0 if (InterruptId < ArmGicGetMaxNumInterrupts (PcdGe= t64=20 >>>> (PcdGicDistributorBase))) { >>>> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 // Got a valid SGI number hence signal= End of Interrupt >>>> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ArmGicEndOfInterrupt (PcdGet64=20 >>>> (PcdGicInterruptInterfaceBase), AcknowledgeInterrupt); >>>> -=C2=A0=C2=A0=C2=A0 } >>>> -=C2=A0 } while (SecondaryEntryAddr =3D=3D 0); >>>> - >>>> -=C2=A0 // Jump to secondary core entry point. >>>> -=C2=A0 SecondaryStart =3D (VOID (*)()) SecondaryEntryAddr; >>>> -=C2=A0 SecondaryStart (); >>>> - >>>> -=C2=A0 // The secondaries shouldn't reach here >>>> -=C2=A0 ASSERT (FALSE); >>>> -} >>>> diff --git a/ArmPlatformPkg/PrePi/MainUniCore.c=20 >>>> b/ArmPlatformPkg/PrePi/MainUniCore.c >>>> index 6162d1241f84..7449facacd51 100644 >>>> --- a/ArmPlatformPkg/PrePi/MainUniCore.c >>>> +++ b/ArmPlatformPkg/PrePi/MainUniCore.c >>>> @@ -20,12 +20,3 @@ PrimaryMain ( >>>> =C2=A0=C2=A0=C2=A0 // We must never return >>>> =C2=A0=C2=A0=C2=A0 ASSERT (FALSE); >>>> =C2=A0 } >>>> - >>>> -VOID >>>> -SecondaryMain ( >>>> -=C2=A0 IN=C2=A0 UINTN=C2=A0 MpId >>>> -=C2=A0 ) >>>> -{ >>>> -=C2=A0 // We must never get into this function on UniCore system >>>> -=C2=A0 ASSERT (FALSE); >>>> -} >>>> diff --git a/ArmPlatformPkg/PrePi/PrePi.c=20 >>>> b/ArmPlatformPkg/PrePi/PrePi.c >>>> index 9b127b94a67c..60061b8b6963 100644 >>>> --- a/ArmPlatformPkg/PrePi/PrePi.c >>>> +++ b/ArmPlatformPkg/PrePi/PrePi.c >>>> @@ -177,7 +177,11 @@ CEntryPoint ( >>>> =C2=A0=C2=A0=C2=A0 // Initialize the platform specific controllers >>>> =C2=A0=C2=A0=C2=A0 ArmPlatformInitialize (MpId); >>>> >>>> -=C2=A0 if (ArmPlatformIsPrimaryCore (MpId) &&=20 >>>> PerformanceMeasurementEnabled ()) { >>>> +=C2=A0 if (!ArmPlatformIsPrimaryCore (MpId)) { >>>> +=C2=A0=C2=A0=C2=A0 ASSERT (FALSE); >>>> +=C2=A0 } >>>> + >>>> +=C2=A0 if (PerformanceMeasurementEnabled ()) { >>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 // Initialize the Timer Library to setu= p the Timer HW controller >>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 TimerConstructor (); >>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 // We cannot call yet the PerformanceLi= b because the HOB List=20 >>>> has not been initialized >>>> @@ -195,29 +199,21 @@ CEntryPoint ( >>>> >>>> =C2=A0=C2=A0=C2=A0 // Define the Global Variable region when we are no= t running in=20 >>>> XIP >>>> =C2=A0=C2=A0=C2=A0 if (!IS_XIP ()) { >>>> -=C2=A0=C2=A0=C2=A0 if (ArmPlatformIsPrimaryCore (MpId)) { >>>> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 if (ArmIsMpCore ()) { >>>> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 // Signal the Global Varia= ble Region is defined (event:=20 >>>> ARM_CPU_EVENT_DEFAULT) >>>> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ArmCallSEV (); >>>> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 } >>>> -=C2=A0=C2=A0=C2=A0 } else { >>>> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 // Wait the Primary core has defined t= he address of the=20 >>>> Global Variable region (event: ARM_CPU_EVENT_DEFAULT) >>>> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ArmCallWFE (); >>>> +=C2=A0=C2=A0=C2=A0 if (ArmIsMpCore ()) { >>>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 // Signal the Global Variable Region i= s defined (event:=20 >>>> ARM_CPU_EVENT_DEFAULT) >>>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ArmCallSEV (); >>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 } >>>> =C2=A0=C2=A0=C2=A0 } >>>> >>>> -=C2=A0 // If not primary Jump to Secondary Main >>>> -=C2=A0 if (ArmPlatformIsPrimaryCore (MpId)) { >>>> -=C2=A0=C2=A0=C2=A0 InvalidateDataCacheRange ( >>>> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (VOID *)UefiMemoryBase, >>>> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 FixedPcdGet32 (PcdSystemMemoryUefiRegi= onSize) >>>> -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ); >>>> +=C2=A0 InvalidateDataCacheRange ( >>>> +=C2=A0=C2=A0=C2=A0 (VOID *)UefiMemoryBase, >>>> +=C2=A0=C2=A0=C2=A0 FixedPcdGet32 (PcdSystemMemoryUefiRegionSize) >>>> +=C2=A0=C2=A0=C2=A0 ); >>>> >>>> -=C2=A0=C2=A0=C2=A0 // Goto primary Main. >>>> -=C2=A0=C2=A0=C2=A0 PrimaryMain (UefiMemoryBase, StacksBase, StartTime= Stamp); >>>> -=C2=A0 } else { >>>> -=C2=A0=C2=A0=C2=A0 SecondaryMain (MpId); >>>> -=C2=A0 } >>>> +=C2=A0 PrePiMain (UefiMemoryBase, StacksBase, StartTimeStamp); >>>> + >>>> +=C2=A0 // We must never return >>>> +=C2=A0 ASSERT (FALSE); >>>> >>>> =C2=A0=C2=A0=C2=A0 // DXE Core should always load and never return >>>> =C2=A0=C2=A0=C2=A0 ASSERT (FALSE); >>>> --=20 >>>> 2.30.2 >>>> >>>> >>>> >>>>=20 >>>> >>>>