* Re: [edk2-platforms] [PATCH v3 3/4] WhiskeylakeOpenBoardPkg/UpXtreme: Add Includes and Libraries
2020-02-21 0:49 ` [edk2-platforms] [PATCH v3 3/4] WhiskeylakeOpenBoardPkg/UpXtreme: Add Includes and Libraries Agyeman, Prince
@ 2020-02-21 2:00 ` Chiu, Chasel
2020-02-21 2:26 ` Nate DeSimone
1 sibling, 0 replies; 7+ messages in thread
From: Chiu, Chasel @ 2020-02-21 2:00 UTC (permalink / raw)
To: Agyeman, Prince, devel@edk2.groups.io; +Cc: Desimone, Nathaniel L
Hi Prince,
Please see my comments below inline.
> -----Original Message-----
> From: Agyeman, Prince <prince.agyeman@intel.com>
> Sent: Friday, February 21, 2020 8:49 AM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel <chasel.chiu@intel.com>; Desimone, Nathaniel L
> <nathaniel.l.desimone@intel.com>
> Subject: [edk2-platforms] [PATCH v3 3/4]
> WhiskeylakeOpenBoardPkg/UpXtreme: Add Includes and Libraries
>
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2191
>
> Adds the Include directory and UpXtreme board-specific library
> class instances.
>
> Co-authored-by: Michael Kubacki <michael.a.kubacki@intel.com>
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
> Signed-off-by: Prince Agyeman <prince.agyeman@intel.com>
> ---
> .../PeiFspMiscUpdUpdateLib.c | 110 +
> .../PeiFspPolicyUpdateLib.c | 126 +
> .../PeiMiscPolicyUpdate.h | 25 +
> .../PeiPchPolicyUpdate.c | 300 ++
> .../PeiPchPolicyUpdate.h | 28 +
> .../PeiPchPolicyUpdatePreMem.c | 39 +
> .../PeiSaPolicyUpdate.c | 158 +
> .../PeiSaPolicyUpdate.h | 45 +
> .../PeiSaPolicyUpdatePreMem.c | 124 +
> .../PeiSiliconPolicyUpdateLibFsp.inf | 144 +
> .../FspWrapperPlatformSecLib.c | 186 +
> .../SecFspWrapperPlatformSecLib/FsptCoreUpd.h | 40 +
> .../SecFspWrapperPlatformSecLib/Ia32/Fsp.h | 42 +
> .../Ia32/PeiCoreEntry.nasm | 130 +
> .../Ia32/SecEntry.nasm | 361 ++
> .../Ia32/Stack.nasm | 72 +
> .../PlatformInit.c | 47 +
> .../SecFspWrapperPlatformSecLib.inf | 105 +
> .../SecGetPerformance.c | 89 +
> .../SecPlatformInformation.c | 78 +
> .../SecRamInitData.c | 55 +
> .../SecTempRamDone.c | 93 +
> .../UpXtreme/Include/Fdf/FlashMapInclude.fdf | 51 +
> .../Include/Library/PeiPlatformHookLib.h | 131 +
> .../UpXtreme/Include/Library/PeiPlatformLib.h | 38 +
> .../UpXtreme/Include/PlatformBoardConfig.h | 103 +
> .../UpXtreme/Include/PlatformInfo.h | 42 +
> .../Library/BaseFuncLib/BaseFuncLib.inf | 33 +
> .../UpXtreme/Library/BaseFuncLib/Gop.c | 38 +
> .../BaseGpioCheckConflictLib.c | 137 +
> .../BaseGpioCheckConflictLib.inf | 35 +
> .../BaseGpioCheckConflictLibNull.c | 37 +
> .../BaseGpioCheckConflictLibNull.inf | 32 +
> .../BasePlatformHookLib/BasePlatformHookLib.c | 143 +
> .../BasePlatformHookLib.inf | 45 +
> .../BoardAcpiLib/SmmBoardAcpiEnableLib.c | 63 +
> .../BoardAcpiLib/SmmBoardAcpiEnableLib.inf | 50 +
> .../SmmMultiBoardAcpiSupportLib.c | 82 +
> .../SmmMultiBoardAcpiSupportLib.inf | 50 +
> .../BoardAcpiLib/SmmSiliconAcpiEnableLib.c | 170 +
> .../BoardAcpiLib/SmmUpXtremeAcpiEnableLib.c | 40 +
> .../BoardInitLib/BoardFuncInitPreMem.c | 25 +
> .../Library/BoardInitLib/BoardInitLib.h | 20 +
> .../BoardInitLib/BoardPchInitPreMemLib.c | 375 ++
> .../BoardInitLib/BoardSaConfigPreMem.h | 79 +
> .../BoardInitLib/BoardSaInitPreMemLib.c | 298 ++
> .../Library/BoardInitLib/GpioTableDefault.c | 213 ++
> .../Library/BoardInitLib/GpioTableUpXtreme.c | 217 ++
> .../Library/BoardInitLib/PchHdaVerbTables.h | 3014 +++++++++++++++++
> .../BoardInitLib/PeiBoardInitPostMemLib.c | 40 +
> .../BoardInitLib/PeiBoardInitPostMemLib.inf | 57 +
> .../BoardInitLib/PeiBoardInitPreMemLib.c | 106 +
> .../BoardInitLib/PeiBoardInitPreMemLib.inf | 124 +
> .../PeiMultiBoardInitPostMemLib.c | 41 +
> .../PeiMultiBoardInitPostMemLib.inf | 202 ++
> .../BoardInitLib/PeiMultiBoardInitPreMemLib.c | 83 +
> .../PeiMultiBoardInitPreMemLib.inf | 308 ++
> .../Library/BoardInitLib/PeiUpXtremeDetect.c | 192 ++
> .../BoardInitLib/PeiUpXtremeInitPostMemLib.c | 416 +++
> .../BoardInitLib/PeiUpXtremeInitPreMemLib.c | 659 ++++
> .../BoardInitLib/UpXtremeHsioPtssTables.c | 32 +
> .../Library/BoardInitLib/UpXtremeInit.h | 44 +
> .../Library/BoardInitLib/UpXtremeSpdTable.c | 86 +
> .../DxePolicyBoardConfig.h | 19 +
> .../DxePolicyBoardConfigLib.inf | 45 +
> .../DxeSaPolicyBoardConfig.c | 36 +
> .../PeiPlatformHookLib/PeiPlatformHookLib.c | 298 ++
> .../PeiPlatformHookLib/PeiPlatformHookLib.inf | 95 +
> .../PeiCpuPolicyBoardConfig.c | 49 +
> .../PeiCpuPolicyBoardConfigPreMem.c | 29 +
> .../PeiMePolicyBoardConfig.c | 36 +
> .../PeiMePolicyBoardConfigPreMem.c | 37 +
> .../PeiPchPolicyBoardConfig.c | 36 +
> .../PeiPchPolicyBoardConfigPreMem.c | 37 +
> .../PeiPolicyBoardConfig.h | 22 +
> .../PeiPolicyBoardConfigLib.inf | 71 +
> .../PeiSaPolicyBoardConfig.c | 36 +
> .../PeiSaPolicyBoardConfigPreMem.c | 30 +
> .../PeiSiPolicyBoardConfig.c | 27 +
> 79 files changed, 11251 insertions(+)
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/Pei
> SiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/Pei
> SiliconPolicyUpdateLibFsp/PeiFspPolicyUpdateLib.c
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/Pei
> SiliconPolicyUpdateLibFsp/PeiMiscPolicyUpdate.h
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/Pei
> SiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.c
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/Pei
> SiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.h
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/Pei
> SiliconPolicyUpdateLibFsp/PeiPchPolicyUpdatePreMem.c
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/Pei
> SiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/Pei
> SiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.h
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/Pei
> SiliconPolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/Pei
> SiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/Se
> cFspWrapperPlatformSecLib/FspWrapperPlatformSecLib.c
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/Se
> cFspWrapperPlatformSecLib/FsptCoreUpd.h
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/Se
> cFspWrapperPlatformSecLib/Ia32/Fsp.h
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/Se
> cFspWrapperPlatformSecLib/Ia32/PeiCoreEntry.nasm
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/Se
> cFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/Se
> cFspWrapperPlatformSecLib/Ia32/Stack.nasm
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/Se
> cFspWrapperPlatformSecLib/PlatformInit.c
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/Se
> cFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/Se
> cFspWrapperPlatformSecLib/SecGetPerformance.c
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/Se
> cFspWrapperPlatformSecLib/SecPlatformInformation.c
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/Se
> cFspWrapperPlatformSecLib/SecRamInitData.c
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/Se
> cFspWrapperPlatformSecLib/SecTempRamDone.c
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Include/Fdf/FlashMapI
> nclude.fdf
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Include/Library/PeiPlatf
> ormHookLib.h
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Include/Library/PeiPlatf
> ormLib.h
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Include/PlatformBoard
> Config.h
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Include/PlatformInfo.h
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BaseFuncLib/Ba
> seFuncLib.inf
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BaseFuncLib/Go
> p.c
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BaseGpioCheck
> ConflictLib/BaseGpioCheckConflictLib.c
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BaseGpioCheck
> ConflictLib/BaseGpioCheckConflictLib.inf
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BaseGpioCheck
> ConflictLibNull/BaseGpioCheckConflictLibNull.c
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BaseGpioCheck
> ConflictLibNull/BaseGpioCheckConflictLibNull.inf
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BasePlatformHo
> okLib/BasePlatformHookLib.c
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BasePlatformHo
> okLib/BasePlatformHookLib.inf
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardAcpiLib/S
> mmBoardAcpiEnableLib.c
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardAcpiLib/S
> mmBoardAcpiEnableLib.inf
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardAcpiLib/S
> mmMultiBoardAcpiSupportLib.c
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardAcpiLib/S
> mmMultiBoardAcpiSupportLib.inf
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardAcpiLib/S
> mmSiliconAcpiEnableLib.c
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardAcpiLib/S
> mmUpXtremeAcpiEnableLib.c
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/Bo
> ardFuncInitPreMem.c
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/Bo
> ardInitLib.h
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/Bo
> ardPchInitPreMemLib.c
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/Bo
> ardSaConfigPreMem.h
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/Bo
> ardSaInitPreMemLib.c
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/Gp
> ioTableDefault.c
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/Gp
> ioTableUpXtreme.c
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/Pc
> hHdaVerbTables.h
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/Pei
> BoardInitPostMemLib.c
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/Pei
> BoardInitPostMemLib.inf
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/Pei
> BoardInitPreMemLib.c
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/Pei
> BoardInitPreMemLib.inf
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/Pei
> MultiBoardInitPostMemLib.c
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/Pei
> MultiBoardInitPostMemLib.inf
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/Pei
> MultiBoardInitPreMemLib.c
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/Pei
> MultiBoardInitPreMemLib.inf
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/Pei
> UpXtremeDetect.c
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/Pei
> UpXtremeInitPostMemLib.c
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/Pei
> UpXtremeInitPreMemLib.c
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/Up
> XtremeHsioPtssTables.c
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/Up
> XtremeInit.h
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/Up
> XtremeSpdTable.c
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/DxePolicyBoard
> ConfigLib/DxePolicyBoardConfig.h
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/DxePolicyBoard
> ConfigLib/DxePolicyBoardConfigLib.inf
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/DxePolicyBoard
> ConfigLib/DxeSaPolicyBoardConfig.c
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPlatformHoo
> kLib/PeiPlatformHookLib.c
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPlatformHoo
> kLib/PeiPlatformHookLib.inf
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoardC
> onfigLib/PeiCpuPolicyBoardConfig.c
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoardC
> onfigLib/PeiCpuPolicyBoardConfigPreMem.c
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoardC
> onfigLib/PeiMePolicyBoardConfig.c
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoardC
> onfigLib/PeiMePolicyBoardConfigPreMem.c
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoardC
> onfigLib/PeiPchPolicyBoardConfig.c
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoardC
> onfigLib/PeiPchPolicyBoardConfigPreMem.c
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoardC
> onfigLib/PeiPolicyBoardConfig.h
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoardC
> onfigLib/PeiPolicyBoardConfigLib.inf
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoardC
> onfigLib/PeiSaPolicyBoardConfig.c
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoardC
> onfigLib/PeiSaPolicyBoardConfigPreMem.c
> create mode 100644
> Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoardC
> onfigLib/PeiSiPolicyBoardConfig.c
>
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/
> PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/
> PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
> new file mode 100644
> index 0000000000..145deb5de3
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/
> PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
> @@ -0,0 +1,110 @@
> +/** @file
> + Implementation of Fsp Misc UPD Initialization.
> +
> +
> + Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include <PiPei.h>
> +
> +#include <Library/DebugLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/PeiLib.h>
> +#include <Library/ConfigBlockLib.h>
> +#include <Library/PeiServicesLib.h>
> +
> +#include <FspEas.h>
> +#include <FspmUpd.h>
> +#include <FspsUpd.h>
> +
> +#include <Library/MemoryAllocationLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/DebugPrintErrorLevelLib.h>
> +#include <Library/PciLib.h>
> +#include <Ppi/ReadOnlyVariable2.h>
> +#include <Guid/MemoryOverwriteControl.h>
> +#include <PchAccess.h>
> +#include <Platform.h>
> +
> +#include "PeiMiscPolicyUpdate.h"
> +
> +/**
> + Performs FSP Misc UPD initialization.
> +
> + @param[in,out] FspmUpd Pointer to FSPM_UPD
> Data.
> +
> + @retval EFI_SUCCESS FSP UPD Data is
> updated.
> + @retval EFI_NOT_FOUND An instance of
> gEfiPeiReadOnlyVariable2PpiGuid
> + could not be located.
> + @retval EFI_OUT_OF_RESOURCES Insufficent resources
> to allocate a memory buffer.
> +**/
> +EFI_STATUS
> +EFIAPI
> +PeiFspMiscUpdUpdatePreMem (
> + IN OUT FSPM_UPD *FspmUpd
> + )
> +{
> + EFI_STATUS Status;
> + EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices;
> + UINTN VariableSize;
> + VOID *MemorySavedData;
> +
> + Status = PeiServicesLocatePpi (
> + &gEfiPeiReadOnlyVariable2PpiGuid,
> + 0,
> + NULL,
> + (VOID **) &VariableServices
> + );
> + if (EFI_ERROR (Status)) {
> + ASSERT_EFI_ERROR (Status);
> + return Status;
> + }
> +
> + VariableSize = 0;
> + MemorySavedData = NULL;
> + Status = VariableServices->GetVariable (
> + VariableServices,
> + L"MemoryConfig",
> + &gFspNonVolatileStorageHobGuid,
> + NULL,
> + &VariableSize,
> + MemorySavedData
> + );
> + if (Status == EFI_BUFFER_TOO_SMALL) {
> + MemorySavedData = AllocatePool (VariableSize);
> + if (MemorySavedData == NULL) {
> + ASSERT (MemorySavedData != NULL);
> + return EFI_OUT_OF_RESOURCES;
> + }
> +
> + DEBUG ((DEBUG_INFO, "VariableSize is 0x%x\n", VariableSize));
> + Status = VariableServices->GetVariable (
> + VariableServices,
> + L"MemoryConfig",
> + &gFspNonVolatileStorageHobGuid,
> + NULL,
> + &VariableSize,
> + MemorySavedData
> + );
> + if (Status == EFI_SUCCESS) {
> + FspmUpd->FspmArchUpd.NvsBufferPtr = MemorySavedData;
> + } else {
> + FspmUpd->FspmArchUpd.NvsBufferPtr = NULL;
> + DEBUG ((DEBUG_ERROR, "Fail to retrieve Variable:\"MemoryConfig\"
> gMemoryConfigVariableGuid, Status = %r\n", Status));
> + ASSERT_EFI_ERROR (Status);
> + }
> + }
> +
> + FspmUpd->FspmConfig.TsegSize = FixedPcdGet32
> (PcdTsegSize);
> + FspmUpd->FspmConfig.CpuRatio = 0;
> + FspmUpd->FspmConfig.CaVrefConfig = PcdGet8
> (PcdMrcCaVrefConfig);
> + FspmUpd->FspmConfig.PlatformMemorySize =
> PEI_MIN_MEMORY_SIZE;
> + FspmUpd->FspmConfig.PcdSerialDebugLevel = 3;
> + FspmUpd->FspmConfig.SafeMode = 0;
> + FspmUpd->FspmConfig.PeciC10Reset = 0;
> +
> + return EFI_SUCCESS;
> +}
> +
> +
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/
> PeiSiliconPolicyUpdateLibFsp/PeiFspPolicyUpdateLib.c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/
> PeiSiliconPolicyUpdateLibFsp/PeiFspPolicyUpdateLib.c
> new file mode 100644
> index 0000000000..1381c426ca
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/
> PeiSiliconPolicyUpdateLibFsp/PeiFspPolicyUpdateLib.c
> @@ -0,0 +1,126 @@
> +/** @file
> + Provide FSP wrapper platform related function.
> +
> + Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include <PiPei.h>
> +#include <Library/PcdLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +#include <Library/FspWrapperApiLib.h>
> +#include <Library/SiliconPolicyUpdateLib.h>
> +
> +#include <FspEas.h>
> +#include <FspmUpd.h>
> +#include <FspsUpd.h>
> +
> +#include "PeiSaPolicyUpdate.h"
> +#include "PeiMiscPolicyUpdate.h"
> +
> +/**
> + Performs FSP PCH PEI Policy initialization.
> +
> + @param[in][out] FspsUpd Pointer to FSP UPD Data.
> +
> + @retval EFI_SUCCESS FSP UPD Data is updated.
> + @retval EFI_NOT_FOUND Fail to locate required PPI.
> + @retval Other FSP UPD Data update process
> fail.
> +**/
> +EFI_STATUS
> +EFIAPI
> +PeiFspPchPolicyUpdate (
> + IN OUT FSPS_UPD *FspsUpd
> + );
> +
> +VOID
> +InternalPrintVariableData (
> + IN UINT8 *Data8,
> + IN UINTN DataSize
> + )
> +{
> + UINTN Index;
> +
> + for (Index = 0; Index < DataSize; Index++) {
> + if (Index % 0x10 == 0) {
> + DEBUG ((DEBUG_INFO, "\n%08X:", Index));
> + }
> + DEBUG ((DEBUG_INFO, " %02X", *Data8++));
> + }
> + DEBUG ((DEBUG_INFO, "\n"));
> +}
> +
> +/**
> + Performs silicon pre-mem policy update.
> +
> + The meaning of Policy is defined by silicon code.
> + It could be the raw data, a handle, a PPI, etc.
> +
> + The input Policy must be returned by SiliconPolicyDonePreMem().
> +
> + 1) In FSP path, the input Policy should be FspmUpd.
> + A platform may use this API to update the FSPM UPD policy initialized
> + by the silicon module or the default UPD data.
> + The output of FSPM UPD data from this API is the final UPD data.
> +
> + 2) In non-FSP path, the board may use additional way to get
> + the silicon policy data field based upon the input Policy.
> +
> + @param[in, out] Policy Pointer to policy.
> +
> + @return the updated policy.
> +**/
> +VOID *
> +EFIAPI
> +SiliconPolicyUpdatePreMem (
> + IN OUT VOID *FspmUpd
> + )
> +{
> + FSPM_UPD *FspmUpdDataPtr;
> +
> + FspmUpdDataPtr = FspmUpd;
> +
> + PeiFspSaPolicyUpdatePreMem (FspmUpdDataPtr);
> + PeiFspMiscUpdUpdatePreMem (FspmUpdDataPtr);
> + InternalPrintVariableData ((VOID *) FspmUpdDataPtr, sizeof (FSPM_UPD));
> +
> + return FspmUpd;
> +}
> +
> +/**
> + Performs silicon post-mem policy update.
> +
> + The meaning of Policy is defined by silicon code.
> + It could be the raw data, a handle, a PPI, etc.
> +
> + The input Policy must be returned by SiliconPolicyDonePostMem().
> +
> + 1) In FSP path, the input Policy should be FspsUpd.
> + A platform may use this API to update the FSPS UPD policy initialized
> + by the silicon module or the default UPD data.
> + The output of FSPS UPD data from this API is the final UPD data.
> +
> + 2) In non-FSP path, the board may use additional way to get
> + the silicon policy data field based upon the input Policy.
> +
> + @param[in, out] Policy Pointer to policy.
> +
> + @return the updated policy.
> +**/
> +VOID *
> +EFIAPI
> +SiliconPolicyUpdatePostMem (
> + IN OUT VOID *FspsUpd
> + )
> +{
> + FSPS_UPD *FspsUpdDataPtr;
> +
> + FspsUpdDataPtr = FspsUpd;
> +
> + PeiFspPchPolicyUpdate (FspsUpd);
> + InternalPrintVariableData ((VOID * ) FspsUpdDataPtr, sizeof (FSPS_UPD));
> +
> + return FspsUpd;
> +}
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/
> PeiSiliconPolicyUpdateLibFsp/PeiMiscPolicyUpdate.h
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/
> PeiSiliconPolicyUpdateLibFsp/PeiMiscPolicyUpdate.h
> new file mode 100644
> index 0000000000..1f2e82cf43
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/
> PeiSiliconPolicyUpdateLibFsp/PeiMiscPolicyUpdate.h
> @@ -0,0 +1,25 @@
> +/** @file
> +
> + Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PEI_MISC_POLICY_UPDATE_H_
> +#define _PEI_MISC_POLICY_UPDATE_H_
> +
> +#include <FspmUpd.h>
> +
> +/**
> + Performs FSP Misc UPD initialization.
> +
> + @param[in][out] FspmUpd Pointer to FSPM_UPD Data.
> +
> + @retval EFI_SUCCESS FSP UPD Data is updated.
> +**/
> +EFI_STATUS
> +EFIAPI
> +PeiFspMiscUpdUpdatePreMem (
> + IN OUT FSPM_UPD *FspmUpd
> + );
> +
> +#endif
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/
> PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/
> PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.c
> new file mode 100644
> index 0000000000..a089fecd3c
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/
> PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.c
> @@ -0,0 +1,300 @@
> +/** @file
> + This file is SampleCode of the library for Intel PCH PEI Policy initialization.
> +
> +
> + Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include "PeiPchPolicyUpdate.h"
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/HdaVerbTableLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +#include <Library/HobLib.h>
> +#include <Guid/GlobalVariable.h>
> +#include <Library/PchGbeLib.h>
> +#include <Library/PchInfoLib.h>
> +#include <Library/PchPcrLib.h>
> +#include <Library/PchHsioLib.h>
> +#include <Library/PchSerialIoLib.h>
> +#include <Library/PchPcieRpLib.h>
> +#include <GpioConfig.h>
> +#include <GpioPinsSklH.h>
> +#include <Library/DebugLib.h>
> +#include <Library/PchGbeLib.h>
> +#include <PcieDeviceOverrideTable.h>
> +
> +CONST UINT8 mPchSerialIoDevMode[PCH_MAX_SERIALIO_CONTROLLERS] =
> {
> + 1 /* I2C0 */, 1 /* I2C1 */, 0 /* I2C2 */, 0 /* I2C3 */, 0 /* I2C4 */, 0
> /* I2C5 */,
> + 0 /* SPI0 */, 0 /* SPI1 */, 0 /* SPI2 */, 1 /* UART0 */, 0 /* UART1 */, 3
> /* UART2 */
> +};
> +
> +CONST UINT8 mPchLpSerialIoDevMode[PCH_MAX_SERIALIO_CONTROLLERS]
> = {
> + 1 /* I2C0 */, 1 /* I2C1 */, 0 /* I2C2 */, 0 /* I2C3 */, 0 /* I2C4 */, 0
> /* I2C5 */,
> + 0 /* SPI0 */, 0 /* SPI1 */, 0 /* SPI2 */, 0 /* UART0 */, 0 /* UART1 */, 0
> /* UART2 */
> +};
> +
> +/**
> + Performs FSP PCH PEI Policy initialization.
> +
> + @param[in][out] FspsUpd Pointer to FSP UPD Data.
> +
> + @retval EFI_SUCCESS FSP UPD Data is updated.
> + @retval EFI_NOT_FOUND Fail to locate required PPI.
> + @retval Other FSP UPD Data update process
> fail.
> +**/
> +EFI_STATUS
> +EFIAPI
> +PeiFspPchPolicyUpdate (
> + IN OUT FSPS_UPD *FspsUpd
> + )
> +{
> + UINT32 Index;
> + UINT32 Length;
> +
> + FspsUpd->FspsConfig.PchPcieDeviceOverrideTablePtr = (UINT32)
> mPcieDeviceTable;
> +
> + FspsUpd->FspsConfig.PchPmSlpS3MinAssert = 0;
> + FspsUpd->FspsConfig.PchPmSlpS4MinAssert = 0;
> + FspsUpd->FspsConfig.PchPmSlpSusMinAssert = 0;
> + FspsUpd->FspsConfig.PchPmSlpAMinAssert = 0;
> + FspsUpd->FspsConfig.PchPmLpcClockRun = 1;
> + FspsUpd->FspsConfig.EnableTcoTimer = 0;
> + FspsUpd->FspsConfig.Enable8254ClockGating = 0;
> + FspsUpd->FspsConfig.Enable8254ClockGatingOnS3 = 0;
> +
> + FspsUpd->FspsConfig.ScsEmmcEnabled = 1;
> + FspsUpd->FspsConfig.ScsEmmcHs400Enabled = 1;
> + FspsUpd->FspsConfig.ScsSdCardEnabled = 0;
> + FspsUpd->FspsConfig.ScsUfsEnabled = 0;
> +
> + FspsUpd->FspsConfig.SataPwrOptEnable = 1;
> +
> + FspsUpd->FspsConfig.GpioIrqRoute = 14;
> + FspsUpd->FspsConfig.SciIrqSelect = 9;
> + FspsUpd->FspsConfig.TcoIrqEnable = 0;
> + FspsUpd->FspsConfig.TcoIrqSelect = 9;
> +
> + AddPlatformVerbTables (
> + PchHdaCodecPlatformOnboard,
> + &(FspsUpd->FspsConfig.PchHdaVerbTableEntryNum),
> + &(FspsUpd->FspsConfig.PchHdaVerbTablePtr)
> + );
> +
> +DEBUG_CODE_BEGIN();
> + if (
> + (FixedPcdGet8 (PcdSerialIoUartDebugEnable) == 1) &&
> + FspsUpd->FspsConfig.SerialIoDevMode[PchSerialIoIndexUart0 +
> PcdGet8 (PcdSerialIoUartNumber)] == PchSerialIoDisabled
> + ) {
> + FspsUpd->FspsConfig.SerialIoDevMode[PchSerialIoIndexUart0 +
> PcdGet8 (PcdSerialIoUartNumber)] = PchSerialIoHidden;
> + }
> + FspsUpd->FspsConfig.SerialIoDebugUartNumber = PcdGet8
> (PcdSerialIoUartNumber);
> + FspsUpd->FspsConfig.SerialIoEnableDebugUartAfterPost = TRUE;
> + FspsUpd->FspsConfig.SerialIoUartHwFlowCtrl[PcdGet8
> (PcdSerialIoUartNumber)] = 0;
> +DEBUG_CODE_END();
> +
> + //
> + // SerialIo config
> + //
> + if (IsPchLp()) {
> + CopyMem (&FspsUpd->FspsConfig.SerialIoDevMode,
> mPchLpSerialIoDevMode, PCH_MAX_SERIALIO_CONTROLLERS);
> + } else {
> + CopyMem (&FspsUpd->FspsConfig.SerialIoDevMode,
> mPchSerialIoDevMode, PCH_MAX_SERIALIO_CONTROLLERS);
> + }
> +
> + // Set debug UART in PCI mode
> +
> FspsUpd->FspsConfig.SerialIoDevMode[PCH_MAX_SERIALIO_I2C_CONTROLLE
> RS + PCH_MAX_SERIALIO_SPI_CONTROLLERS + 2] = 1;
> +
> + FspsUpd->FspsConfig.SerialIoSpiCsPolarity[0] = 1;
> + FspsUpd->FspsConfig.SerialIoSpiCsPolarity[1] = 0;
> + FspsUpd->FspsConfig.SerialIoSpiCsPolarity[2] = 0;
> + FspsUpd->FspsConfig.SerialIoUartHwFlowCtrl[0] = 1;
> + FspsUpd->FspsConfig.SerialIoUartHwFlowCtrl[1] = 1;
> + FspsUpd->FspsConfig.SerialIoUartHwFlowCtrl[2] = 1;
> + FspsUpd->FspsConfig.PchSerialIoI2cPadsTermination[0] = 1;
> + FspsUpd->FspsConfig.PchSerialIoI2cPadsTermination[1] = 1;
> + FspsUpd->FspsConfig.PchSerialIoI2cPadsTermination[2] = 1;
> + FspsUpd->FspsConfig.PchSerialIoI2cPadsTermination[3] = 1;
> + FspsUpd->FspsConfig.PchSerialIoI2cPadsTermination[4] = 1;
> + FspsUpd->FspsConfig.PchSerialIoI2cPadsTermination[5] = 1;
> +
> + //
> + // USB config
> + //
> + FspsUpd->FspsConfig.XdciEnable =
> FALSE;
> + FspsUpd->FspsConfig.PchEnableComplianceMode =
> FALSE;
> + FspsUpd->FspsConfig.UsbPdoProgramming =
> TRUE;
> + FspsUpd->FspsConfig.PchUsbOverCurrentEnable =
> TRUE;
> + FspsUpd->FspsConfig.PchUsb2PhySusPgEnable =
> TRUE;
> + FspsUpd->FspsTestConfig.PchXhciOcLock = TRUE;
> +
> + Length = GetPchXhciMaxUsb2PortNum ();
> + for (Index = 0; Index < Length; Index++) {
> + FspsUpd->FspsConfig.PortUsb20Enable[Index] = TRUE;
> + FspsUpd->FspsConfig.Usb2OverCurrentPin[Index] =
> UsbOverCurrentPinMax;
> + FspsUpd->FspsConfig.Usb2AfePetxiset[Index] = 7;
> + FspsUpd->FspsConfig.Usb2AfeTxiset[Index] = 5;
> + FspsUpd->FspsConfig.Usb2AfePredeemp[Index] = 3;
> + FspsUpd->FspsConfig.Usb2AfePehalfbit[Index] = 0;
> + }
> +
> + Length = GetPchXhciMaxUsb3PortNum ();
> + for (Index = 0; Index < Length; Index++) {
> + FspsUpd->FspsConfig.PortUsb30Enable[Index] = TRUE;
> + FspsUpd->FspsConfig.Usb3OverCurrentPin[Index] =
> UsbOverCurrentPinMax;
> + FspsUpd->FspsConfig.Usb3HsioTxDeEmphEnable[Index] = 0;
> + FspsUpd->FspsConfig.Usb3HsioTxDeEmph[Index] = 0;
> + FspsUpd->FspsConfig.Usb3HsioTxDownscaleAmpEnable[Index] = 0;
> + FspsUpd->FspsConfig.Usb3HsioTxDownscaleAmp[Index] = 0;
> + FspsUpd->FspsConfig.PchUsbHsioRxTuningEnable[Index] = 0;
> + FspsUpd->FspsConfig.PchUsbHsioRxTuningParameters[Index] = 3;
> + FspsUpd->FspsConfig.PchUsbHsioFilterSel[Index] = 0;
> + }
> +
> + if (IsPchLp()) {
> + FspsUpd->FspsConfig.Usb2OverCurrentPin[0] =
> UsbOverCurrentPin2;
> + FspsUpd->FspsConfig.Usb2OverCurrentPin[1] =
> UsbOverCurrentPinSkip;
> + FspsUpd->FspsConfig.Usb2OverCurrentPin[2] =
> UsbOverCurrentPin2;
> + FspsUpd->FspsConfig.Usb2OverCurrentPin[3] =
> UsbOverCurrentPin2;
> + FspsUpd->FspsConfig.Usb2OverCurrentPin[4] =
> UsbOverCurrentPin3;
> + FspsUpd->FspsConfig.Usb2OverCurrentPin[5] =
> UsbOverCurrentPin3;
> + FspsUpd->FspsConfig.Usb2OverCurrentPin[6] =
> UsbOverCurrentPin3;
> + FspsUpd->FspsConfig.Usb2OverCurrentPin[7] =
> UsbOverCurrentPin3;
> + FspsUpd->FspsConfig.Usb2OverCurrentPin[8] =
> UsbOverCurrentPinSkip;
> + FspsUpd->FspsConfig.Usb2OverCurrentPin[9] =
> UsbOverCurrentPinSkip;
> + FspsUpd->FspsConfig.Usb2OverCurrentPin[10] =
> UsbOverCurrentPinSkip;
> + FspsUpd->FspsConfig.Usb2OverCurrentPin[11] =
> UsbOverCurrentPinSkip;
> + FspsUpd->FspsConfig.Usb2OverCurrentPin[12] =
> UsbOverCurrentPinSkip;
> + FspsUpd->FspsConfig.Usb2OverCurrentPin[13] =
> UsbOverCurrentPinSkip;
> + FspsUpd->FspsConfig.Usb2OverCurrentPin[14] =
> UsbOverCurrentPinSkip;
> + FspsUpd->FspsConfig.Usb2OverCurrentPin[15] =
> UsbOverCurrentPinSkip;
> +
> + FspsUpd->FspsConfig.Usb3OverCurrentPin[0] =
> UsbOverCurrentPin2;
> + FspsUpd->FspsConfig.Usb3OverCurrentPin[1] =
> UsbOverCurrentPinSkip;
> + FspsUpd->FspsConfig.Usb3OverCurrentPin[2] =
> UsbOverCurrentPin2;
> + FspsUpd->FspsConfig.Usb3OverCurrentPin[3] =
> UsbOverCurrentPin2;
> + FspsUpd->FspsConfig.Usb3OverCurrentPin[4] =
> UsbOverCurrentPinSkip;
> + FspsUpd->FspsConfig.Usb3OverCurrentPin[5] =
> UsbOverCurrentPinSkip;
> + FspsUpd->FspsConfig.Usb3OverCurrentPin[6] =
> UsbOverCurrentPinSkip;
> + FspsUpd->FspsConfig.Usb3OverCurrentPin[7] =
> UsbOverCurrentPinSkip;
> + FspsUpd->FspsConfig.Usb3OverCurrentPin[8] =
> UsbOverCurrentPinSkip;
> + FspsUpd->FspsConfig.Usb3OverCurrentPin[9] =
> UsbOverCurrentPinSkip;
> +
> + Length = GetPchUsb2MaxPhysicalPortNum ();
> + for (Index = 0; Index < Length; Index++) {
> + FspsUpd->FspsConfig.Usb2AfePetxiset[Index] = 6;
> + FspsUpd->FspsConfig.Usb2AfeTxiset[Index] = 0;
> + FspsUpd->FspsConfig.Usb2AfePredeemp[Index] = 3;
> + FspsUpd->FspsConfig.Usb2AfePehalfbit[Index] = 0;
> + }
> + } else {
> + FspsUpd->FspsConfig.Usb2OverCurrentPin[0] =
> UsbOverCurrentPin4;
> + FspsUpd->FspsConfig.Usb2OverCurrentPin[1] =
> UsbOverCurrentPin0;
> + FspsUpd->FspsConfig.Usb2OverCurrentPin[2] =
> UsbOverCurrentPin2;
> + FspsUpd->FspsConfig.Usb2OverCurrentPin[3] =
> UsbOverCurrentPin5;
> + FspsUpd->FspsConfig.Usb2OverCurrentPin[4] =
> UsbOverCurrentPin5;
> + FspsUpd->FspsConfig.Usb2OverCurrentPin[5] =
> UsbOverCurrentPin0;
> + FspsUpd->FspsConfig.Usb2OverCurrentPin[6] =
> UsbOverCurrentPin1;
> + FspsUpd->FspsConfig.Usb2OverCurrentPin[7] =
> UsbOverCurrentPin1;
> + FspsUpd->FspsConfig.Usb2OverCurrentPin[8] =
> UsbOverCurrentPinSkip;
> + FspsUpd->FspsConfig.Usb2OverCurrentPin[9] =
> UsbOverCurrentPin3;
> + FspsUpd->FspsConfig.Usb2OverCurrentPin[10] =
> UsbOverCurrentPin3;
> + FspsUpd->FspsConfig.Usb2OverCurrentPin[11] =
> UsbOverCurrentPin6;
> + FspsUpd->FspsConfig.Usb2OverCurrentPin[12] =
> UsbOverCurrentPin6;
> + FspsUpd->FspsConfig.Usb2OverCurrentPin[13] =
> UsbOverCurrentPin0;
> +
> + FspsUpd->FspsConfig.Usb3OverCurrentPin[0] =
> UsbOverCurrentPin4;
> + FspsUpd->FspsConfig.Usb3OverCurrentPin[1] =
> UsbOverCurrentPin0;
> + FspsUpd->FspsConfig.Usb3OverCurrentPin[2] =
> UsbOverCurrentPin2;
> + FspsUpd->FspsConfig.Usb3OverCurrentPin[3] =
> UsbOverCurrentPin5;
> + FspsUpd->FspsConfig.Usb3OverCurrentPin[4] =
> UsbOverCurrentPin5;
> + FspsUpd->FspsConfig.Usb3OverCurrentPin[5] =
> UsbOverCurrentPin0;
> + FspsUpd->FspsConfig.Usb3OverCurrentPin[6] =
> UsbOverCurrentPin1;
> + FspsUpd->FspsConfig.Usb3OverCurrentPin[7] =
> UsbOverCurrentPin1;
> + FspsUpd->FspsConfig.Usb3OverCurrentPin[8] =
> UsbOverCurrentPinSkip;
> + FspsUpd->FspsConfig.Usb3OverCurrentPin[9] =
> UsbOverCurrentPin3;
> +
> + FspsUpd->FspsConfig.Usb2AfePetxiset[0] = 7;
> + FspsUpd->FspsConfig.Usb2AfeTxiset[0] = 0;
> + FspsUpd->FspsConfig.Usb2AfePredeemp[0] = 3;
> + FspsUpd->FspsConfig.Usb2AfePehalfbit[0] = 0;
> +
> + FspsUpd->FspsConfig.Usb2AfePetxiset[1] = 6;
> + FspsUpd->FspsConfig.Usb2AfeTxiset[1] = 0;
> + FspsUpd->FspsConfig.Usb2AfePredeemp[1] = 3;
> + FspsUpd->FspsConfig.Usb2AfePehalfbit[1] = 0;
> +
> + FspsUpd->FspsConfig.Usb2AfePetxiset[2] = 6;
> + FspsUpd->FspsConfig.Usb2AfeTxiset[2] = 0;
> + FspsUpd->FspsConfig.Usb2AfePredeemp[2] = 3;
> + FspsUpd->FspsConfig.Usb2AfePehalfbit[2] = 0;
> +
> + FspsUpd->FspsConfig.Usb2AfePetxiset[3] = 6;
> + FspsUpd->FspsConfig.Usb2AfeTxiset[3] = 0;
> + FspsUpd->FspsConfig.Usb2AfePredeemp[3] = 3;
> + FspsUpd->FspsConfig.Usb2AfePehalfbit[3] = 0;
> +
> + FspsUpd->FspsConfig.Usb2AfePetxiset[4] = 6;
> + FspsUpd->FspsConfig.Usb2AfeTxiset[4] = 0;
> + FspsUpd->FspsConfig.Usb2AfePredeemp[4] = 3;
> + FspsUpd->FspsConfig.Usb2AfePehalfbit[4] = 0;
> +
> + FspsUpd->FspsConfig.Usb2AfePetxiset[5] = 6;
> + FspsUpd->FspsConfig.Usb2AfeTxiset[5] = 0;
> + FspsUpd->FspsConfig.Usb2AfePredeemp[5] = 3;
> + FspsUpd->FspsConfig.Usb2AfePehalfbit[5] = 0;
> +
> + FspsUpd->FspsConfig.Usb2AfePetxiset[6] = 7;
> + FspsUpd->FspsConfig.Usb2AfeTxiset[6] = 0;
> + FspsUpd->FspsConfig.Usb2AfePredeemp[6] = 3;
> + FspsUpd->FspsConfig.Usb2AfePehalfbit[6] = 0;
> +
> + FspsUpd->FspsConfig.Usb2AfePetxiset[7] = 7;
> + FspsUpd->FspsConfig.Usb2AfeTxiset[7] = 0;
> + FspsUpd->FspsConfig.Usb2AfePredeemp[7] = 3;
> + FspsUpd->FspsConfig.Usb2AfePehalfbit[7] = 0;
> +
> + FspsUpd->FspsConfig.Usb2AfePetxiset[8] = 6;
> + FspsUpd->FspsConfig.Usb2AfeTxiset[8] = 0;
> + FspsUpd->FspsConfig.Usb2AfePredeemp[8] = 3;
> + FspsUpd->FspsConfig.Usb2AfePehalfbit[8] = 0;
> +
> + FspsUpd->FspsConfig.Usb2AfePetxiset[9] = 6;
> + FspsUpd->FspsConfig.Usb2AfeTxiset[9] = 0;
> + FspsUpd->FspsConfig.Usb2AfePredeemp[9] = 3;
> + FspsUpd->FspsConfig.Usb2AfePehalfbit[9] = 0;
> +
> + FspsUpd->FspsConfig.Usb2AfePetxiset[10] = 6;
> + FspsUpd->FspsConfig.Usb2AfeTxiset[10] = 0;
> + FspsUpd->FspsConfig.Usb2AfePredeemp[10] = 3;
> + FspsUpd->FspsConfig.Usb2AfePehalfbit[10] = 0;
> +
> + FspsUpd->FspsConfig.Usb2AfePetxiset[11] = 7;
> + FspsUpd->FspsConfig.Usb2AfeTxiset[11] = 0;
> + FspsUpd->FspsConfig.Usb2AfePredeemp[11] = 3;
> + FspsUpd->FspsConfig.Usb2AfePehalfbit[11] = 0;
> +
> + FspsUpd->FspsConfig.Usb2AfePetxiset[12] = 7;
> + FspsUpd->FspsConfig.Usb2AfeTxiset[12] = 0;
> + FspsUpd->FspsConfig.Usb2AfePredeemp[12] = 3;
> + FspsUpd->FspsConfig.Usb2AfePehalfbit[12] = 0;
> +
> + FspsUpd->FspsConfig.Usb2AfePetxiset[13] = 7;
> + FspsUpd->FspsConfig.Usb2AfeTxiset[13] = 0;
> + FspsUpd->FspsConfig.Usb2AfePredeemp[13] = 3;
> + FspsUpd->FspsConfig.Usb2AfePehalfbit[13] = 0;
> + }
> +
> + FspsUpd->FspsConfig.PcieSwEqCoeffListCm[0] = 4;
> + FspsUpd->FspsConfig.PcieSwEqCoeffListCp[0] = 8;
> + FspsUpd->FspsConfig.PcieSwEqCoeffListCm[1] = 6;
> + FspsUpd->FspsConfig.PcieSwEqCoeffListCp[1] = 2;
> + FspsUpd->FspsConfig.PcieSwEqCoeffListCm[2] = 8;
> + FspsUpd->FspsConfig.PcieSwEqCoeffListCp[2] = 6;
> + FspsUpd->FspsConfig.PcieSwEqCoeffListCm[3] = 10;
> + FspsUpd->FspsConfig.PcieSwEqCoeffListCp[3] = 8;
> + FspsUpd->FspsConfig.PcieSwEqCoeffListCm[4] = 12;
> + FspsUpd->FspsConfig.PcieSwEqCoeffListCp[4] = 2;
> +
> + return EFI_SUCCESS;
> +}
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/
> PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.h
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/
> PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.h
> new file mode 100644
> index 0000000000..3d8dfa4c08
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/
> PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.h
> @@ -0,0 +1,28 @@
> +/** @file
> +
> + Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PEI_PCH_POLICY_UPDATE_H_
> +#define _PEI_PCH_POLICY_UPDATE_H_
> +
> +//
> +// External include files do NOT need to be explicitly specified in real EDKII
> +// environment
> +//
> +#include <PiPei.h>
> +
> +#include <Library/DebugLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/PciLib.h>
> +#include <Ppi/SiPolicy.h>
> +#include <Library/MmPciLib.h>
> +#include <Library/ConfigBlockLib.h>
> +
> +#include <FspEas.h>
> +#include <FspmUpd.h>
> +#include <FspsUpd.h>
> +
> +#endif
> +
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/
> PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdatePreMem.c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/
> PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdatePreMem.c
> new file mode 100644
> index 0000000000..cbe9bf8fbb
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/
> PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdatePreMem.c
> @@ -0,0 +1,39 @@
> +/** @file
> + This file is SampleCode of the library for Intel PCH PEI Policy initialization.
> +
> +
> + Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include "PeiPchPolicyUpdate.h"
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +#include <Library/HobLib.h>
> +#include <Guid/GlobalVariable.h>
> +#include <Library/PchInfoLib.h>
> +#include <Library/PchPcrLib.h>
> +#include <Library/PchHsioLib.h>
> +#include <Library/PchPcieRpLib.h>
> +#include <PchHsioPtssTables.h>
> +#include <Library/DebugLib.h>
> +
> +/**
> + Performs FSP PCH PEI Policy pre mem initialization.
> +
> + @param[in][out] FspmUpd Pointer to FSP UPD Data.
> +
> + @retval EFI_SUCCESS FSP UPD Data is updated.
> + @retval EFI_NOT_FOUND Fail to locate required PPI.
> + @retval Other FSP UPD Data update process
> fail.
> +**/
> +EFI_STATUS
> +EFIAPI
> +PeiFspPchPolicyUpdatePreMem (
> + IN OUT FSPM_UPD *FspmUpd
> + )
> +{
> + return EFI_SUCCESS;
> +}
> +
> +
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/
> PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/
> PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c
> new file mode 100644
> index 0000000000..f051a5bca5
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/
> PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c
> @@ -0,0 +1,158 @@
> +/** @file
> +Do Platform Stage System Agent initialization.
> +
> +
> + Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include "PeiSaPolicyUpdate.h"
> +#include <Guid/MemoryTypeInformation.h>
> +#include <Library/HobLib.h>
> +#include <PchAccess.h>
> +#include <SaAccess.h>
> +#include <Pi/PiFirmwareFile.h>
> +#include <Pi/PiPeiCis.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +#include <Library/PeiSaPolicyLib.h>
> +#include <Library/PeiLib.h>
> +
> +CONST UINT8 mPxRcConfig[8] = { 11, 10, 11, 11, 11, 11, 11, 11 };
> +
> +/**
> + Performs FSP SA PEI Policy initialization.
> +
> + @param[in][out] FspsUpd Pointer to FSP UPD Data.
> +
> + @retval EFI_SUCCESS FSP UPD Data is updated.
> + @retval EFI_NOT_FOUND Fail to locate required PPI.
> + @retval Other FSP UPD Data update process
> fail.
> +**/
> +EFI_STATUS
> +EFIAPI
> +PeiFspSaPolicyUpdate (
> + IN OUT FSPS_UPD *FspsUpd
> + )
> +{
> + VOID *Buffer;
> + VOID *MemBuffer;
> + UINT32 Size;
> +
> + DEBUG((DEBUG_INFO, "\nUpdating SA Policy in Post Mem\n"));
> +
> + FspsUpd->FspsConfig.PeiGraphicsPeimInit = 1;
> +
> + Size = 0;
> + Buffer = NULL;
> + PeiGetSectionFromAnyFv (PcdGetPtr (PcdGraphicsVbtGuid),
> EFI_SECTION_RAW, 0, &Buffer, &Size);
> + if (Buffer == NULL) {
> + DEBUG((DEBUG_WARN, "Could not locate VBT\n"));
> + } else {
> + MemBuffer = (VOID *)AllocatePages (EFI_SIZE_TO_PAGES
> ((UINTN)Size));
> + if ((MemBuffer != NULL) && (Buffer != NULL)) {
> + CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size);
> + FspsUpd->FspsConfig.GraphicsConfigPtr =
> (UINT32)(UINTN)MemBuffer;
> + } else {
> + DEBUG((DEBUG_WARN, "Error in locating / copying VBT.\n"));
> + FspsUpd->FspsConfig.GraphicsConfigPtr = 0;
> + }
> + }
> + DEBUG((DEBUG_INFO, "Vbt Pointer from PeiGetSectionFromFv is 0x%x\n",
> FspsUpd->FspsConfig.GraphicsConfigPtr));
> + DEBUG((DEBUG_INFO, "Vbt Size from PeiGetSectionFromFv is 0x%x\n",
> Size));
> +
> + Size = 0;
> + Buffer = NULL;
> + PeiGetSectionFromAnyFv (&gTianoLogoGuid, EFI_SECTION_RAW, 0,
> &Buffer, &Size);
> + if (Buffer == NULL) {
> + DEBUG((DEBUG_WARN, "Could not locate Logo\n"));
> + } else {
> + MemBuffer = (VOID *)AllocatePages (EFI_SIZE_TO_PAGES
> ((UINTN)Size));
> + if ((MemBuffer != NULL) && (Buffer != NULL)) {
> + CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size);
> + FspsUpd->FspsConfig.LogoPtr = (UINT32)(UINTN)MemBuffer;
> + FspsUpd->FspsConfig.LogoSize = Size;
> + } else {
> + DEBUG((DEBUG_WARN, "Error in locating / copying LogoPtr.\n"));
> + FspsUpd->FspsConfig.LogoPtr = 0;
> + FspsUpd->FspsConfig.LogoSize = 0;
> + }
> + }
> + DEBUG((DEBUG_INFO, "LogoPtr from PeiGetSectionFromFv is 0x%x\n",
> FspsUpd->FspsConfig.LogoPtr));
> + DEBUG((DEBUG_INFO, "LogoSize from PeiGetSectionFromFv is 0x%x\n",
> FspsUpd->FspsConfig.LogoSize));
> +
> + CopyMem (&FspsUpd->FspsConfig.PxRcConfig, mPxRcConfig,
> sizeof(mPxRcConfig));
> +
> + //
> + // CPU power management config
> + //
> + FspsUpd->FspsConfig.TdcEnable[0] = 0x1;
> + FspsUpd->FspsConfig.TdcEnable[1] = 0x1;
> + FspsUpd->FspsConfig.TdcEnable[3] = 0x1;
> + FspsUpd->FspsConfig.TdcPowerLimit[1] = 0x2b0;
> + FspsUpd->FspsConfig.TdcPowerLimit[3] = 0xc8;
> + FspsUpd->FspsConfig.AcLoadline[0] = 0x406;
> + FspsUpd->FspsConfig.AcLoadline[1] = 0xb4;
> + FspsUpd->FspsConfig.AcLoadline[3] = 0x10e;
> + FspsUpd->FspsConfig.DcLoadline[0] = 0x406;
> + FspsUpd->FspsConfig.DcLoadline[1] = 0xb4;
> + FspsUpd->FspsConfig.DcLoadline[3] = 0x10e;
> + FspsUpd->FspsConfig.Psi1Threshold[0] = 0x50;
> + FspsUpd->FspsConfig.Psi1Threshold[1] = 0x50;
> + FspsUpd->FspsConfig.Psi1Threshold[2] = 0x50;
> + FspsUpd->FspsConfig.Psi1Threshold[3] = 0x50;
> + FspsUpd->FspsConfig.Psi1Threshold[4] = 0x50;
> + FspsUpd->FspsConfig.Psi2Threshold[0] = 0x14;
> + FspsUpd->FspsConfig.Psi2Threshold[1] = 0x14;
> + FspsUpd->FspsConfig.Psi2Threshold[2] = 0x14;
> + FspsUpd->FspsConfig.Psi2Threshold[3] = 0x14;
> + FspsUpd->FspsConfig.Psi2Threshold[4] = 0x14;
> + FspsUpd->FspsConfig.Psi3Threshold[0] = 0x4;
> + FspsUpd->FspsConfig.Psi3Threshold[1] = 0x4;
> + FspsUpd->FspsConfig.Psi3Threshold[2] = 0x4;
> + FspsUpd->FspsConfig.Psi3Threshold[3] = 0x4;
> + FspsUpd->FspsConfig.Psi3Threshold[4] = 0x4;
> + FspsUpd->FspsConfig.IccMax[0] = 0x2c;
> + FspsUpd->FspsConfig.IccMax[1] = 0x230;
> + FspsUpd->FspsConfig.IccMax[3] = 0x80;
> + FspsUpd->FspsConfig.McivrSpreadSpectrum = 0x3;
> +
> + FspsUpd->FspsTestConfig.OneCoreRatioLimit = 0x29;
> + FspsUpd->FspsTestConfig.TwoCoreRatioLimit = 0x28;
> + FspsUpd->FspsTestConfig.ThreeCoreRatioLimit = 0x27;
> + FspsUpd->FspsTestConfig.FourCoreRatioLimit = 0x26;
> + FspsUpd->FspsTestConfig.FiveCoreRatioLimit = 0x25;
> + FspsUpd->FspsTestConfig.SixCoreRatioLimit = 0x24;
> + FspsUpd->FspsTestConfig.TccActivationOffset = 0x0;
> + FspsUpd->FspsTestConfig.TccOffsetClamp = 0x0;
> +
> + FspsUpd->FspsTestConfig.PowerLimit1 = 0x0;
> + FspsUpd->FspsTestConfig.PowerLimit2Power = 0x0;
> + FspsUpd->FspsTestConfig.PowerLimit3 = 0x0;
> + FspsUpd->FspsTestConfig.PowerLimit4 = 0x0;
> + FspsUpd->FspsTestConfig.Custom1PowerLimit1 = 0x0;
> + FspsUpd->FspsTestConfig.Custom1PowerLimit2 = 0x0;
> + FspsUpd->FspsTestConfig.Custom2PowerLimit1 = 0x0;
> + FspsUpd->FspsTestConfig.Custom2PowerLimit2 = 0x0;
> + FspsUpd->FspsTestConfig.Custom3PowerLimit1 = 0x0;
> + FspsUpd->FspsTestConfig.Custom3PowerLimit2 = 0x0;
> + FspsUpd->FspsTestConfig.Custom1PowerLimit1Time = 0x0;
> + FspsUpd->FspsTestConfig.Custom1TurboActivationRatio = 0x0;
> + FspsUpd->FspsTestConfig.Custom2PowerLimit1Time = 0x0;
> + FspsUpd->FspsTestConfig.Custom2TurboActivationRatio = 0x0;
> + FspsUpd->FspsTestConfig.Custom3PowerLimit1Time = 0x0;
> + FspsUpd->FspsTestConfig.Custom3TurboActivationRatio = 0x0;
> +
> + FspsUpd->FspsTestConfig.VoltageOptimization = 0x0;
> + FspsUpd->FspsTestConfig.TStates = 0x0;
> + FspsUpd->FspsTestConfig.ProcHotResponse = 0x0;
> + FspsUpd->FspsTestConfig.Cx = 0x1;
> + FspsUpd->FspsTestConfig.PkgCStateLimit = 0xff;
> + FspsUpd->FspsTestConfig.MaxRatio = 0x8;
> + FspsUpd->FspsTestConfig.PsysPmax = 0x0;
> + FspsUpd->FspsTestConfig.CstateLatencyControl0Irtl = 0x4e;
> +
> + return EFI_SUCCESS;
> +}
> +
> +
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/
> PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.h
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/
> PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.h
> new file mode 100644
> index 0000000000..1728d3e123
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/
> PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.h
> @@ -0,0 +1,45 @@
> +/** @file
> +
> + Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PEI_SA_POLICY_UPDATE_H_
> +#define _PEI_SA_POLICY_UPDATE_H_
> +
> +//
> +// External include files do NOT need to be explicitly specified in real EDKII
> +// environment
> +//
> +#include <SaPolicyCommon.h>
> +#include <Library/DebugPrintErrorLevelLib.h>
> +#include <CpuRegs.h>
> +#include <Library/CpuPlatformLib.h>
> +#include "PeiPchPolicyUpdate.h"
> +#include <Library/PcdLib.h>
> +#include <CpuAccess.h>
> +
> +#include <FspEas.h>
> +#include <FspmUpd.h>
> +#include <FspsUpd.h>
> +
> +extern EFI_GUID gTianoLogoGuid;
> +
> +/**
> + Performs FSP SA PEI Policy initialization in pre-memory.
> +
> + @param[in][out] FspmUpd Pointer to FSP UPD Data.
> +
> + @retval EFI_SUCCESS FSP UPD Data is updated.
> + @retval EFI_NOT_FOUND Fail to locate required PPI.
> + @retval Other FSP UPD Data update process
> fail.
> +**/
> +EFI_STATUS
> +EFIAPI
> +PeiFspSaPolicyUpdatePreMem (
> + IN OUT FSPM_UPD *FspmUpd
> + );
> +
> +#endif
> +
> +
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/
> PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/
> PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c
> new file mode 100644
> index 0000000000..3fb74c8838
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/
> PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c
> @@ -0,0 +1,124 @@
> +/** @file
> + System Agent policy update.
> +
> +
> + Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include "PeiSaPolicyUpdate.h"
> +#include <CpuRegs.h>
> +#include <Library/CpuPlatformLib.h>
> +#include <Guid/MemoryTypeInformation.h>
> +#include <Guid/MemoryOverwriteControl.h>
> +#include <Library/HobLib.h>
> +#include <PchAccess.h>
> +#include <SaAccess.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +#include <Library/PeiSaPolicyLib.h>
> +#include <Library/GpioLib.h>
> +#include <GpioPinsSklH.h>
> +
> +
> +/**
> + Performs FSP SA PEI Policy initialization in pre-memory.
> +
> + @param[in][out] FspmUpd Pointer to FSP UPD Data.
> +
> + @retval EFI_SUCCESS FSP UPD Data is updated.
> + @retval EFI_NOT_FOUND Fail to locate required PPI.
> + @retval Other FSP UPD Data update process
> fail.
> +**/
> +EFI_STATUS
> +EFIAPI
> +PeiFspSaPolicyUpdatePreMem (
> + IN OUT FSPM_UPD *FspmUpd
> + )
> +{
> + VOID *Buffer;
> + UINT8 BomId;
> +
> + FspmUpd->FspmConfig.SpdAddressTable[0] = PcdGet8
> (PcdMrcSpdAddressTable0);
> + FspmUpd->FspmConfig.SpdAddressTable[1] = PcdGet8
> (PcdMrcSpdAddressTable1);
> + FspmUpd->FspmConfig.SpdAddressTable[2] = PcdGet8
> (PcdMrcSpdAddressTable2);
> + FspmUpd->FspmConfig.SpdAddressTable[3] = PcdGet8
> (PcdMrcSpdAddressTable3);
> + FspmUpd->FspmConfig.MemorySpdDataLen = PcdGet16
> (PcdMrcSpdDataSize);
> +
> + //
> + // If SpdAddressTable are not all 0, it means DIMM slots implemented and
> + // MemorySpdPtr* already updated by reading SPD from DIMM in
> SiliconPolicyInitPreMem.
> + //
> + // If SpdAddressTable all 0, this is memory down design and hardcoded
> SpdData
> + // should be applied to MemorySpdPtr*.
> + //
> + if ((PcdGet8 (PcdMrcSpdAddressTable0) == 0) && (PcdGet8
> (PcdMrcSpdAddressTable1) == 0)
> + && (PcdGet8 (PcdMrcSpdAddressTable2) == 0) && (PcdGet8
> (PcdMrcSpdAddressTable3) == 0)) {
> + DEBUG ((DEBUG_INFO, "Using static SPD data for down memory.\n"));
> +
> + // BOMID [1:0]
> + // 0: 16G A & B CH
> + // 1: 8G A CH
> + // 2: 8G A & B CH
> + // 3: 4G A CH
> + BomId = PcdGet8(PcdBoardBomId);
> +
> + if ((BomId & BIT0) == BIT0) {
> + // Single Channel
> + FspmUpd->FspmConfig.MemorySpdPtr00 = PcdGet32
> (PcdMrcSpdData);
> + FspmUpd->FspmConfig.MemorySpdPtr01 = 0;
> + FspmUpd->FspmConfig.MemorySpdPtr10 = 0;
> + FspmUpd->FspmConfig.MemorySpdPtr11 = 0;
> + }else{
> + // Dual Channel
> + FspmUpd->FspmConfig.MemorySpdPtr00 = PcdGet32
> (PcdMrcSpdData);
> + FspmUpd->FspmConfig.MemorySpdPtr01 = 0;
> + FspmUpd->FspmConfig.MemorySpdPtr10 = PcdGet32
> (PcdMrcSpdData);
> + FspmUpd->FspmConfig.MemorySpdPtr11 = 0;
> + }
> + // CopyMem (
> + // (VOID *) (UINTN) FspmUpd->FspmConfig.MemorySpdPtr00,
> + // (VOID *) (UINTN) PcdGet32 (PcdMrcSpdData),
> + // PcdGet16 (PcdMrcSpdDataSize)
> + // );
> + // CopyMem (
> + // (VOID *) (UINTN) FspmUpd->FspmConfig.MemorySpdPtr10,
> + // (VOID *) (UINTN) PcdGet32 (PcdMrcSpdData),
> + // PcdGet16 (PcdMrcSpdDataSize)
> + // );
> + }
> +
> + DEBUG((DEBUG_INFO, "Updating Dq Byte Map and DQS Byte Swizzling
> Settings...\n"));
> + Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcDqByteMap);
> + if (Buffer) {
> + CopyMem ((VOID *) FspmUpd->FspmConfig.DqByteMapCh0, Buffer,
> sizeof (FspmUpd->FspmConfig.DqByteMapCh0));
> + CopyMem (
> + (VOID *) FspmUpd->FspmConfig.DqByteMapCh1,
> + (UINT8 *) Buffer + sizeof (FspmUpd->FspmConfig.DqByteMapCh0),
> + sizeof (FspmUpd->FspmConfig.DqByteMapCh1)
> + );
> + }
> + Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcDqsMapCpu2Dram);
> + if (Buffer) {
> + CopyMem ((VOID *) FspmUpd->FspmConfig.DqsMapCpu2DramCh0,
> Buffer, sizeof (FspmUpd->FspmConfig.DqsMapCpu2DramCh0));
> + CopyMem (
> + (VOID *) FspmUpd->FspmConfig.DqsMapCpu2DramCh1,
> + (UINT8 *) Buffer + sizeof
> (FspmUpd->FspmConfig.DqsMapCpu2DramCh0),
> + sizeof (FspmUpd->FspmConfig.DqsMapCpu2DramCh1)
> + );
> + }
> +
> + DEBUG((DEBUG_INFO, "Updating Dq Pins Interleaved,Rcomp Resistor &
> Rcomp Target Settings...\n"));
> + FspmUpd->FspmConfig.DqPinsInterleaved = (PcdGetBool
> (PcdMrcDqPinsInterleaved) ? 1 : 0);
> + Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcRcompResistor);
> + if (Buffer) {
> + CopyMem ((VOID *) FspmUpd->FspmConfig.RcompResistor, Buffer,
> sizeof (FspmUpd->FspmConfig.RcompResistor));
> + }
> + Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcRcompTarget);
> + if (Buffer) {
> + CopyMem ((VOID *) FspmUpd->FspmConfig.RcompTarget, Buffer, sizeof
> (FspmUpd->FspmConfig.RcompTarget));
> + }
> + return EFI_SUCCESS;
> +}
> +
> +
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/
> PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/
> PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf
> new file mode 100644
> index 0000000000..529c2f1253
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/
> PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf
> @@ -0,0 +1,144 @@
> +## @file
> +# FSP silicon policy updates for the Up Xtreme board.
> +#
> +#
> +# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +##
> +
> +###############################################################
> #################
> +#
> +# Defines Section - statements that will be processed to create a Makefile.
> +#
> +###############################################################
> #################
> +[Defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = SiliconPolicyUpdateLibFsp
> + FILE_GUID =
> 392554A5-CC26-4941-B536-6A71BEE4EE49
> + MODULE_TYPE = PEIM
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = SiliconPolicyUpdateLib
> +
> +
> +#
> +# The following information is for reference only and not required by the
> build tools.
> +#
> +# VALID_ARCHITECTURES = IA32 X64
> +#
> +
> +###############################################################
> #################
> +#
> +# Sources Section - list of files that are required for the build to succeed.
> +#
> +###############################################################
> #################
> +
> +[Sources]
> + PeiFspPolicyUpdateLib.c
> + PeiPchPolicyUpdatePreMem.c
> + PeiPchPolicyUpdate.c
> + PeiSaPolicyUpdatePreMem.c
> + PeiSaPolicyUpdate.c
> + PeiFspMiscUpdUpdateLib.c
> +
> +###############################################################
> #################
> +#
> +# Package Dependency Section - list of Package files that are required for
> +# this module.
> +#
> +###############################################################
> #################
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + IntelFsp2Pkg/IntelFsp2Pkg.dec
> + IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
> + IntelSiliconPkg/IntelSiliconPkg.dec
> + CoffeelakeSiliconPkg/SiPkg.dec
> + CoffeeLakeFspBinPkg/CoffeeLakeFspBinPkg.dec
> + MinPlatformPkg/MinPlatformPkg.dec
> + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec
> +
> +[LibraryClasses.IA32]
> + FspWrapperApiLib
> + OcWdtLib
> + PchResetLib
> + FspWrapperPlatformLib
> + BaseMemoryLib
> + CpuPlatformLib
> + DebugLib
> + HdaVerbTableLib
> + HobLib
> + IoLib
> + PcdLib
> + PostCodeLib
> + SmbusLib
> + ConfigBlockLib
> + PeiSaPolicyLib
> + PchGbeLib
> + PchInfoLib
> + PchHsioLib
> + PchPcieRpLib
> + MemoryAllocationLib
> + DebugPrintErrorLevelLib
> + SiPolicyLib
> + PchGbeLib
> + TimerLib
> + GpioLib
> + PeiLib
> +
> +[FixedPcd]
> + gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable
> ## CONSUMES
> + gSiPkgTokenSpaceGuid.PcdTsegSize
> ## CONSUMES
> +
> +[Pcd]
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor
> ## CONSUMES
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget
> ## CONSUMES
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMap
> ## CONSUMES
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2Dram
> ## CONSUMES
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqPinsInterleaved
> ## CONSUMES
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdData
> ## CONSUMES
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdDataSize
> ## CONSUMES
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcCaVrefConfig
> ## CONSUMES
> +
> + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
> ## CONSUMES
> + gSiPkgTokenSpaceGuid.PcdSerialIoUartNumber
> ## CONSUMES
> + gSiPkgTokenSpaceGuid.PcdSmmbaseSwSmi
> ## CONSUMES
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSaDdrFreqLimit
> ## CONSUMES
> +
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable1
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable2
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable1Siz
> e
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable2Siz
> e
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size
> +
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable1
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable2
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable1Size
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable2Size
> +
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGraphicsVbtGuid
> +
> + # SPD Address Table
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable0
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable1
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable2
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable3
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardBomId
> +
> +[Guids]
> + gFspNonVolatileStorageHobGuid ## CONSUMES
> + gTianoLogoGuid ## CONSUMES
> + gEfiMemoryOverwriteControlDataGuid
> +
> +[Depex]
> + gEdkiiVTdInfoPpiGuid
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/
> SecFspWrapperPlatformSecLib/FspWrapperPlatformSecLib.c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/
> SecFspWrapperPlatformSecLib/FspWrapperPlatformSecLib.c
> new file mode 100644
> index 0000000000..91ca226092
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/
> SecFspWrapperPlatformSecLib/FspWrapperPlatformSecLib.c
> @@ -0,0 +1,186 @@
> +/** @file
> + Provide FSP wrapper platform sec related function.
> +
> +Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> +SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include <PiPei.h>
> +
> +#include <Ppi/SecPlatformInformation.h>
> +#include <Ppi/SecPerformance.h>
> +#include <Ppi/FirmwareVolumeInfo.h>
> +#include <Ppi/TopOfTemporaryRam.h>
> +#include <Ppi/PeiCoreFvLocation.h>
> +#include <Guid/FirmwareFileSystem2.h>
> +
> +#include <Library/LocalApicLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/IoLib.h>
> +
> +/**
> + This interface conveys state information out of the Security (SEC) phase
> into PEI.
> +
> + @param[in] PeiServices Pointer to the PEI Services
> Table.
> + @param[in,out] StructureSize Pointer to the variable
> describing size of the input buffer.
> + @param[out] PlatformInformationRecord Pointer to the
> EFI_SEC_PLATFORM_INFORMATION_RECORD.
> +
> + @retval EFI_SUCCESS The data was successfully returned.
> + @retval EFI_BUFFER_TOO_SMALL The buffer was too small.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +SecPlatformInformation (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN OUT UINT64 *StructureSize,
> + OUT EFI_SEC_PLATFORM_INFORMATION_RECORD
> *PlatformInformationRecord
> + );
> +
> +/**
> + This interface conveys performance information out of the Security (SEC)
> phase into PEI.
> +
> + This service is published by the SEC phase. The SEC phase handoff has an
> optional
> + EFI_PEI_PPI_DESCRIPTOR list as its final argument when control is passed
> from SEC into the
> + PEI Foundation. As such, if the platform supports collecting performance
> data in SEC,
> + this information is encapsulated into the data structure abstracted by this
> service.
> + This information is collected for the boot-strap processor (BSP) on IA-32.
> +
> + @param[in] PeiServices The pointer to the PEI Services Table.
> + @param[in] This The pointer to this instance of the
> PEI_SEC_PERFORMANCE_PPI.
> + @param[out] Performance The pointer to performance data collected
> in SEC phase.
> +
> + @retval EFI_SUCCESS The data was successfully returned.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +SecGetPerformance (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN PEI_SEC_PERFORMANCE_PPI *This,
> + OUT FIRMWARE_SEC_PERFORMANCE *Performance
> + );
> +
> +PEI_SEC_PERFORMANCE_PPI mSecPerformancePpi = {
> + SecGetPerformance
> +};
> +
> +EFI_PEI_CORE_FV_LOCATION_PPI mPeiCoreFvLocationPpi = {
> + (VOID *) (UINTN) FixedPcdGet32 (PcdFspmBaseAddress)
> +};
> +
> +EFI_PEI_PPI_DESCRIPTOR mPeiCoreFvLocationPpiList[] = {
> + {
> + EFI_PEI_PPI_DESCRIPTOR_PPI,
> + &gEfiPeiCoreFvLocationPpiGuid,
> + &mPeiCoreFvLocationPpi
> + }
> +};
> +
> +EFI_PEI_PPI_DESCRIPTOR mPeiSecPlatformPpi[] = {
> + {
> + EFI_PEI_PPI_DESCRIPTOR_PPI,
> + &gTopOfTemporaryRamPpiGuid,
> + NULL // To be patched later.
> + },
> + {
> + EFI_PEI_PPI_DESCRIPTOR_PPI |
> EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
> + &gPeiSecPerformancePpiGuid,
> + &mSecPerformancePpi
> + },
> +};
> +
> +#define LEGACY_8259_MASK_REGISTER_MASTER 0x21
> +#define LEGACY_8259_MASK_REGISTER_SLAVE 0xA1
> +#define LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_MASTER
> 0x4D0
> +#define LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_SLAVE 0x4D1
> +
> +/**
> + Write to mask and edge/level triggered registers of master and slave 8259
> PICs.
> +
> + @param[in] Mask low byte for master PIC mask register,
> + high byte for slave PIC mask register.
> + @param[in] EdgeLevel low byte for master PIC edge/level triggered
> register,
> + high byte for slave PIC edge/level triggered
> register.
> +
> +**/
> +VOID
> +Interrupt8259WriteMask (
> + IN UINT16 Mask,
> + IN UINT16 EdgeLevel
> + )
> +{
> + IoWrite8 (LEGACY_8259_MASK_REGISTER_MASTER, (UINT8) Mask);
> + IoWrite8 (LEGACY_8259_MASK_REGISTER_SLAVE, (UINT8) (Mask >> 8));
> + IoWrite8 (LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_MASTER,
> (UINT8) EdgeLevel);
> + IoWrite8 (LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_SLAVE,
> (UINT8) (EdgeLevel >> 8));
> +}
> +
> +/**
> + A developer supplied function to perform platform specific operations.
> +
> + It's a developer supplied function to perform any operations appropriate
> to a
> + given platform. It's invoked just before passing control to PEI core by SEC
> + core. Platform developer may modify the SecCoreData passed to PEI Core.
> + It returns a platform specific PPI list that platform wishes to pass to PEI
> core.
> + The Generic SEC core module will merge this list to join the final list
> passed to
> + PEI core.
> +
> + @param[in,out] SecCoreData The same parameter as
> passing to PEI core. It
> + could be overridden by this
> function.
> +
> + @return The platform specific PPI list to be passed to PEI core or
> + NULL if there is no need of such platform specific PPI list.
> +
> +**/
> +EFI_PEI_PPI_DESCRIPTOR *
> +EFIAPI
> +SecPlatformMain (
> + IN OUT EFI_SEC_PEI_HAND_OFF *SecCoreData
> + )
> +{
> + EFI_PEI_PPI_DESCRIPTOR *PpiList;
> + UINT8 TopOfTemporaryRamPpiIndex;
> + UINT8 *CopyDestinationPointer;
> +
> + DEBUG ((DEBUG_INFO, "FSP Wrapper BootFirmwareVolumeBase -
> 0x%x\n", SecCoreData->BootFirmwareVolumeBase));
> + DEBUG ((DEBUG_INFO, "FSP Wrapper BootFirmwareVolumeSize - 0x%x\n",
> SecCoreData->BootFirmwareVolumeSize));
> + DEBUG ((DEBUG_INFO, "FSP Wrapper TemporaryRamBase -
> 0x%x\n", SecCoreData->TemporaryRamBase));
> + DEBUG ((DEBUG_INFO, "FSP Wrapper TemporaryRamSize -
> 0x%x\n", SecCoreData->TemporaryRamSize));
> + DEBUG ((DEBUG_INFO, "FSP Wrapper PeiTemporaryRamBase -
> 0x%x\n", SecCoreData->PeiTemporaryRamBase));
> + DEBUG ((DEBUG_INFO, "FSP Wrapper PeiTemporaryRamSize -
> 0x%x\n", SecCoreData->PeiTemporaryRamSize));
> + DEBUG ((DEBUG_INFO, "FSP Wrapper StackBase -
> 0x%x\n", SecCoreData->StackBase));
> + DEBUG ((DEBUG_INFO, "FSP Wrapper StackSize - 0x%x\n",
> SecCoreData->StackSize));
> +
> + InitializeApicTimer (0, (UINT32) -1, TRUE, 5);
> +
> + //
> + // Set all 8259 interrupts to edge triggered and disabled
> + //
> + Interrupt8259WriteMask (0xFFFF, 0x0000);
> +
> + //
> + // Use middle of Heap as temp buffer, it will be copied by caller.
> + // Do not use Stack, because it will cause wrong calculation on stack by
> PeiCore
> + //
> + PpiList = (VOID *)((UINTN) SecCoreData->PeiTemporaryRamBase + (UINTN)
> SecCoreData->PeiTemporaryRamSize/2);
> + CopyDestinationPointer = (UINT8 *) PpiList;
> + TopOfTemporaryRamPpiIndex = 0;
> + if ((PcdGet8 (PcdFspModeSelection) == 0) && PcdGetBool
> (PcdFspDispatchModeUseFspPeiMain)) {
> + //
> + // In Dispatch mode, wrapper should provide PeiCoreFvLocationPpi.
> + //
> + CopyMem (CopyDestinationPointer, mPeiCoreFvLocationPpiList, sizeof
> (mPeiCoreFvLocationPpiList));
> + TopOfTemporaryRamPpiIndex = 1;
> + CopyDestinationPointer += sizeof (mPeiCoreFvLocationPpiList);
> + }
> + CopyMem (CopyDestinationPointer, mPeiSecPlatformPpi, sizeof
> (mPeiSecPlatformPpi));
> + //
> + // Patch TopOfTemporaryRamPpi
> + //
> + PpiList[TopOfTemporaryRamPpiIndex].Ppi = (VOID *)((UINTN)
> SecCoreData->TemporaryRamBase + SecCoreData->TemporaryRamSize);
> +
> + return PpiList;
> +}
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/
> SecFspWrapperPlatformSecLib/FsptCoreUpd.h
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/
> SecFspWrapperPlatformSecLib/FsptCoreUpd.h
> new file mode 100644
> index 0000000000..a969120501
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/
> SecFspWrapperPlatformSecLib/FsptCoreUpd.h
> @@ -0,0 +1,40 @@
> +/** @file
> +
> +Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> +SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#ifndef __FSPT_CORE_UPD_H__
> +#define __FSPT_CORE_UPD_H__
> +
> +#pragma pack(1)
> +
> +/** Fsp T Core UPD
> +**/
> +typedef struct {
> +
> +/** Offset 0x0020
> +**/
> + UINT32 MicrocodeRegionBase;
> +
> +/** Offset 0x0024
> +**/
> + UINT32 MicrocodeRegionSize;
> +
> +/** Offset 0x0028
> +**/
> + UINT32 CodeRegionBase;
> +
> +/** Offset 0x002C
> +**/
> + UINT32 CodeRegionSize;
> +
> +/** Offset 0x0030
> +**/
> + UINT8 Reserved[16];
> +} FSPT_CORE_UPD;
> +
> +#pragma pack()
> +
> +#endif
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/
> SecFspWrapperPlatformSecLib/Ia32/Fsp.h
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/
> SecFspWrapperPlatformSecLib/Ia32/Fsp.h
> new file mode 100644
> index 0000000000..2acaa373c4
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/
> SecFspWrapperPlatformSecLib/Ia32/Fsp.h
> @@ -0,0 +1,42 @@
> +/** @file
> + Fsp related definitions
> +
> +Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> +SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#ifndef __FSP_H__
> +#define __FSP_H__
> +
> +//
> +// Fv Header
> +//
> +#define FVH_SIGINATURE_OFFSET 0x28
> +#define FVH_SIGINATURE_VALID_VALUE 0x4856465F // valid
> signature:_FVH
> +#define FVH_HEADER_LENGTH_OFFSET 0x30
> +#define FVH_EXTHEADER_OFFSET_OFFSET 0x34
> +#define FVH_EXTHEADER_SIZE_OFFSET 0x10
> +
> +//
> +// Ffs Header
> +//
> +#define FSP_HEADER_GUID_DWORD1 0x912740BE
> +#define FSP_HEADER_GUID_DWORD2 0x47342284
> +#define FSP_HEADER_GUID_DWORD3 0xB08471B9
> +#define FSP_HEADER_GUID_DWORD4 0x0C3F3527
> +#define FFS_HEADER_SIZE_VALUE 0x18
> +
> +//
> +// Section Header
> +//
> +#define SECTION_HEADER_TYPE_OFFSET 0x03
> +#define RAW_SECTION_HEADER_SIZE_VALUE 0x04
> +
> +//
> +// Fsp Header
> +//
> +#define FSP_HEADER_IMAGEBASE_OFFSET 0x1C
> +#define FSP_HEADER_TEMPRAMINIT_OFFSET 0x30
> +
> +#endif
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/
> SecFspWrapperPlatformSecLib/Ia32/PeiCoreEntry.nasm
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/
> SecFspWrapperPlatformSecLib/Ia32/PeiCoreEntry.nasm
> new file mode 100644
> index 0000000000..d6d0b8955f
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/
> SecFspWrapperPlatformSecLib/Ia32/PeiCoreEntry.nasm
> @@ -0,0 +1,130 @@
> +;------------------------------------------------------------------------------
> +;
> +; Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> +; SPDX-License-Identifier: BSD-2-Clause-Patent
> +;
> +; Module Name:
> +;
> +; PeiCoreEntry.nasm
> +;
> +; Abstract:
> +;
> +; Find and call SecStartup
> +;
> +;------------------------------------------------------------------------------
> +
> +SECTION .text
> +
> +extern ASM_PFX(SecStartup)
> +extern ASM_PFX(PlatformInit)
> +
> +global ASM_PFX(CallPeiCoreEntryPoint)
> +ASM_PFX(CallPeiCoreEntryPoint):
> + ;
> + ; Obtain the hob list pointer
> + ;
> + mov eax, [esp+4]
> + ;
> + ; Obtain the stack information
> + ; ECX: start of range
> + ; EDX: end of range
> + ;
> + mov ecx, [esp+8]
> + mov edx, [esp+0xC]
> +
> + ;
> + ; Platform init
> + ;
> + pushad
> + push edx
> + push ecx
> + push eax
> + call ASM_PFX(PlatformInit)
> + pop eax
> + pop eax
> + pop eax
> + popad
> +
> + ;
> + ; Set stack top pointer
> + ;
> + mov esp, edx
> +
> + ;
> + ; Push the hob list pointer
> + ;
> + push eax
> +
> + ;
> + ; Save the value
> + ; ECX: start of range
> + ; EDX: end of range
> + ;
> + mov ebp, esp
> + push ecx
> + push edx
> +
> + ;
> + ; Push processor count to stack first, then BIST status (AP then BSP)
> + ;
> + mov eax, 1
> + cpuid
> + shr ebx, 16
> + and ebx, 0xFF
> + cmp bl, 1
> + jae PushProcessorCount
> +
> + ;
> + ; Some processors report 0 logical processors. Effectively 0 = 1.
> + ; So we fix up the processor count
> + ;
> + inc ebx
> +
> +PushProcessorCount:
> + push ebx
> +
> + ;
> + ; We need to implement a long-term solution for BIST capture. For now,
> we just copy BSP BIST
> + ; for all processor threads
> + ;
> + xor ecx, ecx
> + mov cl, bl
> +PushBist:
> + movd eax, mm0
> + push eax
> + loop PushBist
> +
> + ; Save Time-Stamp Counter
> + movd eax, mm5
> + push eax
> +
> + movd eax, mm6
> + push eax
> +
> + ;
> + ; Pass entry point of the PEI core
> + ;
> + mov edi, 0xFFFFFFE0
> + push DWORD [edi]
> +
> + ;
> + ; Pass BFV into the PEI Core
> + ;
> + mov edi, 0xFFFFFFFC
> + push DWORD [edi]
> +
> + ;
> + ; Pass stack size into the PEI Core
> + ;
> + mov ecx, [ebp - 4]
> + mov edx, [ebp - 8]
> + push ecx ; RamBase
> +
> + sub edx, ecx
> + push edx ; RamSize
> +
> + ;
> + ; Pass Control into the PEI Core
> + ;
> + call ASM_PFX(SecStartup)
> +
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/
> SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/
> SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
> new file mode 100644
> index 0000000000..9eea3c38b7
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/
> SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
> @@ -0,0 +1,361 @@
> +;------------------------------------------------------------------------------
> +;
> +; Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> +; SPDX-License-Identifier: BSD-2-Clause-Patent
> +; Module Name:
> +;
> +; SecEntry.nasm
> +;
> +; Abstract:
> +;
> +; This is the code that goes from real-mode to protected mode.
> +; It consumes the reset vector, calls TempRamInit API from FSP binary.
> +;
> +;------------------------------------------------------------------------------
> +
> +#include "Fsp.h"
> +
> +SECTION .text
> +
> +extern ASM_PFX(CallPeiCoreEntryPoint)
> +extern ASM_PFX(FsptUpdDataPtr)
> +extern ASM_PFX(BoardBeforeTempRamInit)
> +; Pcds
> +extern ASM_PFX(PcdGet32 (PcdFspTemporaryRamSize))
> +extern ASM_PFX(PcdGet32 (PcdFsptBaseAddress))
> +
> +;----------------------------------------------------------------------------
> +;
> +; Procedure: _ModuleEntryPoint
> +;
> +; Input: None
> +;
> +; Output: None
> +;
> +; Destroys: Assume all registers
> +;
> +; Description:
> +;
> +; Transition to non-paged flat-model protected mode from a
> +; hard-coded GDT that provides exactly two descriptors.
> +; This is a bare bones transition to protected mode only
> +; used for a while in PEI and possibly DXE.
> +;
> +; After enabling protected mode, a far jump is executed to
> +; transfer to PEI using the newly loaded GDT.
> +;
> +; Return: None
> +;
> +; MMX Usage:
> +; MM0 = BIST State
> +; MM5 = Save time-stamp counter value high32bit
> +; MM6 = Save time-stamp counter value low32bit.
> +;
> +;----------------------------------------------------------------------------
> +
> +BITS 16
> +align 4
> +global ASM_PFX(_ModuleEntryPoint)
> +ASM_PFX(_ModuleEntryPoint):
> + fninit ; clear any pending Floating
> point exceptions
> + ;
> + ; Store the BIST value in mm0
> + ;
> + movd mm0, eax
> + cli
> +
> + ;
> + ; Check INIT# is asserted by port 0xCF9
> + ;
> + mov dx, 0CF9h
> + in al, dx
> + cmp al, 04h
> + jnz NotWarmStart
> +
> +
> + ;
> + ; @note Issue warm reset, since if CPU only reset is issued not all MSRs
> are restored to their defaults
> + ;
> + mov dx, 0CF9h
> + mov al, 06h
> + out dx, al
> +
> +NotWarmStart:
> + ;
> + ; Save time-stamp counter value
> + ; rdtsc load 64bit time-stamp counter to EDX:EAX
> + ;
> + rdtsc
> + movd mm5, edx
> + movd mm6, eax
> +
> + ;
> + ; Load the GDT table in GdtDesc
> + ;
> + mov esi, GdtDesc
> + DB 66h
> + lgdt [cs:si]
> +
> + ;
> + ; Transition to 16 bit protected mode
> + ;
> + mov eax, cr0 ; Get control register 0
> + or eax, 00000003h ; Set PE bit (bit #0) & MP bit (bit
> #1)
> + mov cr0, eax ; Activate protected mode
> +
> + mov eax, cr4 ; Get control register 4
> + or eax, 00000600h ; Set OSFXSR bit (bit #9) &
> OSXMMEXCPT bit (bit #10)
> + mov cr4, eax
> +
> + ;
> + ; Now we're in 16 bit protected mode
> + ; Set up the selectors for 32 bit protected mode entry
> + ;
> + mov ax, SYS_DATA_SEL
> + mov ds, ax
> + mov es, ax
> + mov fs, ax
> + mov gs, ax
> + mov ss, ax
> +
> + ;
> + ; Transition to Flat 32 bit protected mode
> + ; The jump to a far pointer causes the transition to 32 bit mode
> + ;
> + mov esi, ProtectedModeEntryLinearAddress
> + jmp dword far [cs:si]
> +
> +;----------------------------------------------------------------------------
> +;
> +; Procedure: ProtectedModeEntryPoint
> +;
> +; Input: None
> +;
> +; Output: None
> +;
> +; Destroys: Assume all registers
> +;
> +; Description:
> +;
> +; This function handles:
> +; Call two basic APIs from FSP binary
> +; Initializes stack with some early data (BIST, PEI entry, etc)
> +;
> +; Return: None
> +;
> +;----------------------------------------------------------------------------
> +
> +BITS 32
> +align 4
> +ProtectedModeEntryPoint:
> + ;
> + ; Early board hooks
> + ;
> + mov esp, BoardBeforeTempRamInitRet
> + jmp ASM_PFX(BoardBeforeTempRamInit)
> +
> +BoardBeforeTempRamInitRet:
> +
> + ; Find the fsp info header
> + mov edi, [ASM_PFX(PcdGet32 (PcdFsptBaseAddress))]
> +
> + mov eax, dword [edi + FVH_SIGINATURE_OFFSET]
> + cmp eax, FVH_SIGINATURE_VALID_VALUE
> + jnz FspHeaderNotFound
> +
> + xor eax, eax
> + mov ax, word [edi + FVH_EXTHEADER_OFFSET_OFFSET]
> + cmp ax, 0
> + jnz FspFvExtHeaderExist
> +
> + xor eax, eax
> + mov ax, word [edi + FVH_HEADER_LENGTH_OFFSET] ; Bypass Fv
> Header
> + add edi, eax
> + jmp FspCheckFfsHeader
> +
> +FspFvExtHeaderExist:
> + add edi, eax
> + mov eax, dword [edi + FVH_EXTHEADER_SIZE_OFFSET] ; Bypass Ext Fv
> Header
> + add edi, eax
> +
> + ; Round up to 8 byte alignment
> + mov eax, edi
> + and al, 07h
> + jz FspCheckFfsHeader
> +
> + and edi, 0FFFFFFF8h
> + add edi, 08h
> +
> +FspCheckFfsHeader:
> + ; Check the ffs guid
> + mov eax, dword [edi]
> + cmp eax, FSP_HEADER_GUID_DWORD1
> + jnz FspHeaderNotFound
> +
> + mov eax, dword [edi + 4]
> + cmp eax, FSP_HEADER_GUID_DWORD2
> + jnz FspHeaderNotFound
> +
> + mov eax, dword [edi + 8]
> + cmp eax, FSP_HEADER_GUID_DWORD3
> + jnz FspHeaderNotFound
> +
> + mov eax, dword [edi + 0Ch]
> + cmp eax, FSP_HEADER_GUID_DWORD4
> + jnz FspHeaderNotFound
> +
> + add edi, FFS_HEADER_SIZE_VALUE ; Bypass the ffs header
> +
> + ; Check the section type as raw section
> + mov al, byte [edi + SECTION_HEADER_TYPE_OFFSET]
> + cmp al, 019h
> + jnz FspHeaderNotFound
> +
> + add edi, RAW_SECTION_HEADER_SIZE_VALUE ; Bypass the section
> header
> + jmp FspHeaderFound
> +
> +FspHeaderNotFound:
> + jmp $
> +
> +FspHeaderFound:
> + ; Get the fsp TempRamInit Api address
> + mov eax, dword [edi + FSP_HEADER_IMAGEBASE_OFFSET]
> + add eax, dword [edi + FSP_HEADER_TEMPRAMINIT_OFFSET]
> +
> + ; Setup the hardcode stack
> + mov esp, TempRamInitStack
> +
> + ; Call the fsp TempRamInit Api
> + jmp eax
> +
> +TempRamInitDone:
> + cmp eax, 8000000Eh ;Check if EFI_NOT_FOUND returned. Error
> code for Microcode Update not found.
> + je CallSecFspInit ;If microcode not found, don't hang, but
> continue.
> +
> + cmp eax, 0 ;Check if EFI_SUCCESS retuned.
> + jnz FspApiFailed
> +
> + ; ECX: start of range
> + ; EDX: end of range
> +CallSecFspInit:
> + sub edx, [ASM_PFX(PcdGet32 (PcdFspTemporaryRamSize))] ;
> TemporaryRam for FSP
> + xor eax, eax
> + mov esp, edx
> +
> + ; Align the stack at DWORD
> + add esp, 3
> + and esp, 0FFFFFFFCh
> +
> + push edx
> + push ecx
> + push eax ; zero - no hob list yet
> + call ASM_PFX(CallPeiCoreEntryPoint)
> +
> +FspApiFailed:
> + jmp $
> +
> +align 10h
> +TempRamInitStack:
> + DD TempRamInitDone
> + DD ASM_PFX(FsptUpdDataPtr); TempRamInitParams
> +
> +;
> +; ROM-based Global-Descriptor Table for the Tiano PEI Phase
> +;
> +align 16
> +global ASM_PFX(BootGdtTable)
> +
> +;
> +; GDT[0]: 0x00: Null entry, never used.
> +;
> +NULL_SEL EQU $ - GDT_BASE ; Selector [0]
> +GDT_BASE:
> +ASM_PFX(BootGdtTable):
> + DD 0
> + DD 0
> +;
> +; Linear data segment descriptor
> +;
> +LINEAR_SEL EQU $ - GDT_BASE ; Selector [0x8]
> + DW 0FFFFh ; limit 0xFFFFF
> + DW 0 ; base 0
> + DB 0
> + DB 092h ; present, ring 0, data,
> expand-up, writable
> + DB 0CFh ; page-granular, 32-bit
> + DB 0
> +;
> +; Linear code segment descriptor
> +;
> +LINEAR_CODE_SEL EQU $ - GDT_BASE ; Selector [0x10]
> + DW 0FFFFh ; limit 0xFFFFF
> + DW 0 ; base 0
> + DB 0
> + DB 09Bh ; present, ring 0, data,
> expand-up, not-writable
> + DB 0CFh ; page-granular, 32-bit
> + DB 0
> +;
> +; System data segment descriptor
> +;
> +SYS_DATA_SEL EQU $ - GDT_BASE ; Selector [0x18]
> + DW 0FFFFh ; limit 0xFFFFF
> + DW 0 ; base 0
> + DB 0
> + DB 093h ; present, ring 0, data,
> expand-up, not-writable
> + DB 0CFh ; page-granular, 32-bit
> + DB 0
> +
> +;
> +; System code segment descriptor
> +;
> +SYS_CODE_SEL EQU $ - GDT_BASE ; Selector [0x20]
> + DW 0FFFFh ; limit 0xFFFFF
> + DW 0 ; base 0
> + DB 0
> + DB 09Ah ; present, ring 0, data,
> expand-up, writable
> + DB 0CFh ; page-granular, 32-bit
> + DB 0
> +;
> +; Spare segment descriptor
> +;
> +SYS16_CODE_SEL EQU $ - GDT_BASE ; Selector [0x28]
> + DW 0FFFFh ; limit 0xFFFFF
> + DW 0 ; base 0
> + DB 0Eh ; Changed from F000 to
> E000.
> + DB 09Bh ; present, ring 0, code,
> expand-up, writable
> + DB 00h ; byte-granular, 16-bit
> + DB 0
> +;
> +; Spare segment descriptor
> +;
> +SYS16_DATA_SEL EQU $ - GDT_BASE ; Selector [0x30]
> + DW 0FFFFh ; limit 0xFFFF
> + DW 0 ; base 0
> + DB 0
> + DB 093h ; present, ring 0, data,
> expand-up, not-writable
> + DB 00h ; byte-granular, 16-bit
> + DB 0
> +
> +;
> +; Spare segment descriptor
> +;
> +SPARE5_SEL EQU $ - GDT_BASE ; Selector [0x38]
> + DW 0 ; limit 0
> + DW 0 ; base 0
> + DB 0
> + DB 0 ; present, ring 0, data,
> expand-up, writable
> + DB 0 ; page-granular, 32-bit
> + DB 0
> +GDT_SIZE EQU $ - GDT_BASE ; Size, in bytes
> +
> +;
> +; GDT Descriptor
> +;
> +GdtDesc: ; GDT descriptor
> + DW GDT_SIZE - 1 ; GDT limit
> + DD GDT_BASE ; GDT base address
> +
> +
> +ProtectedModeEntryLinearAddress:
> +ProtectedModeEntryLinear:
> + DD ProtectedModeEntryPoint ; Offset of our 32 bit code
> + DW LINEAR_CODE_SEL
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/
> SecFspWrapperPlatformSecLib/Ia32/Stack.nasm
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/
> SecFspWrapperPlatformSecLib/Ia32/Stack.nasm
> new file mode 100644
> index 0000000000..1396649173
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/
> SecFspWrapperPlatformSecLib/Ia32/Stack.nasm
> @@ -0,0 +1,72 @@
> +;------------------------------------------------------------------------------
> +;
> +; Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> +; SPDX-License-Identifier: BSD-2-Clause-Patent
> +; Abstract:
> +;
> +; Switch the stack from temporary memory to permanent memory.
> +;
> +;------------------------------------------------------------------------------
> +
> + SECTION .text
> +
> +;------------------------------------------------------------------------------
> +; VOID
> +; EFIAPI
> +; SecSwitchStack (
> +; UINT32 TemporaryMemoryBase,
> +; UINT32 PermanentMemoryBase
> +; );
> +;------------------------------------------------------------------------------
> +global ASM_PFX(SecSwitchStack)
> +ASM_PFX(SecSwitchStack):
> + ;
> + ; Save three register: eax, ebx, ecx
> + ;
> + push eax
> + push ebx
> + push ecx
> + push edx
> +
> + ;
> + ; !!CAUTION!! this function address's is pushed into stack after
> + ; migration of whole temporary memory, so need save it to permanent
> + ; memory at first!
> + ;
> +
> + mov ebx, [esp + 20] ; Save the first parameter
> + mov ecx, [esp + 24] ; Save the second parameter
> +
> + ;
> + ; Save this function's return address into permanent memory at first.
> + ; Then, Fixup the esp point to permanent memory
> + ;
> + mov eax, esp
> + sub eax, ebx
> + add eax, ecx
> + mov edx, dword [esp] ; copy pushed register's value to
> permanent memory
> + mov dword [eax], edx
> + mov edx, dword [esp + 4]
> + mov dword [eax + 4], edx
> + mov edx, dword [esp + 8]
> + mov dword [eax + 8], edx
> + mov edx, dword [esp + 12]
> + mov dword [eax + 12], edx
> + mov edx, dword [esp + 16] ; Update this function's return
> address into permanent memory
> + mov dword [eax + 16], edx
> + mov esp, eax ; From now, esp is pointed to
> permanent memory
> +
> + ;
> + ; Fixup the ebp point to permanent memory
> + ;
> + mov eax, ebp
> + sub eax, ebx
> + add eax, ecx
> + mov ebp, eax ; From now, ebp is pointed to
> permanent memory
> +
> + pop edx
> + pop ecx
> + pop ebx
> + pop eax
> + ret
> +
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/
> SecFspWrapperPlatformSecLib/PlatformInit.c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/
> SecFspWrapperPlatformSecLib/PlatformInit.c
> new file mode 100644
> index 0000000000..486c8c7261
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/
> SecFspWrapperPlatformSecLib/PlatformInit.c
> @@ -0,0 +1,47 @@
> +/** @file
> + Provide platform init function.
> +
> +Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> +SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +
> +#include <PiPei.h>
> +#include <Library/DebugLib.h>
> +#include <Library/SerialPortLib.h>
> +#include <Library/SecBoardInitLib.h>
> +#include <Library/TestPointCheckLib.h>
> +
> +/**
> + Platform initialization.
> +
> + @param[in] FspHobList HobList produced by FSP.
> + @param[in] StartOfRange Start of temporary RAM.
> + @param[in] EndOfRange End of temporary RAM.
> +**/
> +VOID
> +EFIAPI
> +PlatformInit (
> + IN VOID *FspHobList,
> + IN VOID *StartOfRange,
> + IN VOID *EndOfRange
> + )
> +{
> + //
> + // Platform initialization
> + // Enable Serial port here
> + //
> + if (PcdGetBool(PcdSecSerialPortDebugEnable)) {
> + SerialPortInitialize ();
> + }
> +
> + DEBUG ((DEBUG_INFO, "PrintPeiCoreEntryPointParam in PlatformInit\n"));
> + DEBUG ((DEBUG_INFO, "FspHobList - 0x%x\n", FspHobList));
> + DEBUG ((DEBUG_INFO, "StartOfRange - 0x%x\n", StartOfRange));
> + DEBUG ((DEBUG_INFO, "EndOfRange - 0x%x\n", EndOfRange));
> +
> + BoardAfterTempRamInit ();
> +
> + TestPointTempMemoryFunction (StartOfRange, EndOfRange);
> +}
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/
> SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/
> SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
> new file mode 100644
> index 0000000000..b17226d43b
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/
> SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
> @@ -0,0 +1,105 @@
> +## @file
> +# Provide FSP wrapper platform sec related function.
> +#
> +# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +##
> +
> +###############################################################
> #################
> +#
> +# Defines Section - statements that will be processed to create a Makefile.
> +#
> +###############################################################
> #################
> +[Defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = SecFspWrapperPlatformSecLib
> + FILE_GUID =
> 4E1C4F95-90EA-47de-9ACC-B8920189A1F5
> + MODULE_TYPE = SEC
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = PlatformSecLib
> +
> +
> +#
> +# The following information is for reference only and not required by the
> build tools.
> +#
> +# VALID_ARCHITECTURES = IA32 X64
> +#
> +
> +###############################################################
> #################
> +#
> +# Sources Section - list of files that are required for the build to succeed.
> +#
> +###############################################################
> #################
> +
> +[Sources]
> + FspWrapperPlatformSecLib.c
> + SecRamInitData.c
> + SecPlatformInformation.c
> + SecGetPerformance.c
> + SecTempRamDone.c
> + PlatformInit.c
> + FsptCoreUpd.h
> +
> +[Sources.IA32]
> + Ia32/SecEntry.nasm
> + Ia32/PeiCoreEntry.nasm
> + Ia32/Stack.nasm
> + Ia32/Fsp.h
> +
> +###############################################################
> #################
> +#
> +# Package Dependency Section - list of Package files that are required for
> +# this module.
> +#
> +###############################################################
> #################
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + UefiCpuPkg/UefiCpuPkg.dec
> + IntelFsp2Pkg/IntelFsp2Pkg.dec
> + IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
> + MinPlatformPkg/MinPlatformPkg.dec
> + CoffeelakeSiliconPkg/SiPkg.dec
> + CoffeeLakeFspBinPkg/CoffeeLakeFspBinPkg.dec
> +
> +[LibraryClasses]
> + LocalApicLib
> + SerialPortLib
> + FspWrapperPlatformLib
> + FspWrapperApiLib
> + SecBoardInitLib
> + TestPointCheckLib
> + PeiServicesTablePointerLib
> +
> +[Ppis]
> + gEfiSecPlatformInformationPpiGuid ## CONSUMES
> + gPeiSecPerformancePpiGuid ## CONSUMES
> + gTopOfTemporaryRamPpiGuid ## PRODUCES
> + gEfiPeiFirmwareVolumeInfoPpiGuid ## PRODUCES
> + gFspTempRamExitPpiGuid ## CONSUMES
> + gPlatformInitTempRamExitPpiGuid ## CONSUMES
> +
> +[Pcd]
> + gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize
> ## CONSUMES
> + gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress
> ## CONSUMES
> + gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize
> ## CONSUMES
> + gMinPlatformPkgTokenSpaceGuid.PcdSecSerialPortDebugEnable
> ## CONSUMES
> +
> +[FixedPcd]
> + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
> ## CONSUMES
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate
> ## CONSUMES
> + gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress
> ## CONSUMES
> + gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize
> ## CONSUMES
> + gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset
> ## CONSUMES
> + gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress
> ## CONSUMES
> + gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize
> ## CONSUMES
> + gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress
> ## CONSUMES
> + gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection
> ## CONSUMES
> + gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable
> ## CONSUMES
> + gSiPkgTokenSpaceGuid.PcdSerialIoUartNumber
> ## CONSUMES
> + gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain
> ## CONSUMES
> + gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength
> ## CONSUMES
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/
> SecFspWrapperPlatformSecLib/SecGetPerformance.c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/
> SecFspWrapperPlatformSecLib/SecGetPerformance.c
> new file mode 100644
> index 0000000000..1e20421239
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/
> SecFspWrapperPlatformSecLib/SecGetPerformance.c
> @@ -0,0 +1,89 @@
> +/** @file
> + Sample to provide SecGetPerformance function.
> +
> +Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> +SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include <PiPei.h>
> +
> +#include <Ppi/SecPerformance.h>
> +#include <Ppi/TopOfTemporaryRam.h>
> +
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/TimerLib.h>
> +#include <Library/DebugLib.h>
> +
> +/**
> + This interface conveys performance information out of the Security (SEC)
> phase into PEI.
> +
> + This service is published by the SEC phase. The SEC phase handoff has an
> optional
> + EFI_PEI_PPI_DESCRIPTOR list as its final argument when control is passed
> from SEC into the
> + PEI Foundation. As such, if the platform supports collecting performance
> data in SEC,
> + this information is encapsulated into the data structure abstracted by this
> service.
> + This information is collected for the boot-strap processor (BSP) on IA-32.
> +
> + @param[in] PeiServices The pointer to the PEI Services Table.
> + @param[in] This The pointer to this instance of the
> PEI_SEC_PERFORMANCE_PPI.
> + @param[out] Performance The pointer to performance data collected
> in SEC phase.
> +
> + @retval EFI_SUCCESS The data was successfully returned.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +SecGetPerformance (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN PEI_SEC_PERFORMANCE_PPI *This,
> + OUT FIRMWARE_SEC_PERFORMANCE *Performance
> + )
> +{
> + UINT32 Size;
> + UINT32 Count;
> + UINTN TopOfTemporaryRam;
> + UINT64 Ticker;
> + VOID *TopOfTemporaryRamPpi;
> + EFI_STATUS Status;
> +
> + DEBUG ((DEBUG_INFO, "SecGetPerformance\n"));
> +
> + Status = (*PeiServices)->LocatePpi (
> + PeiServices,
> + &gTopOfTemporaryRamPpiGuid,
> + 0,
> + NULL,
> + (VOID **) &TopOfTemporaryRamPpi
> + );
> + if (EFI_ERROR (Status)) {
> + return EFI_NOT_FOUND;
> + }
> + //
> + // |--------------| <- TopOfTemporaryRam - BL
> + // | List Ptr |
> + // |--------------|
> + // | BL RAM Start |
> + // |--------------|
> + // | BL RAM End |
> + // |--------------|
> + // |Number of BSPs|
> + // |--------------|
> + // | BIST |
> + // |--------------|
> + // | .... |
> + // |--------------|
> + // | TSC[63:32] |
> + // |--------------|
> + // | TSC[31:00] |
> + // |--------------|
> + //
> + TopOfTemporaryRam = (UINTN) TopOfTemporaryRamPpi - sizeof
> (UINT32);
> + TopOfTemporaryRam -= sizeof (UINT32) * 2;
> + Count = *(UINT32 *)(TopOfTemporaryRam - sizeof
> (UINT32));
> + Size = Count * sizeof (UINT32);
> +
> + Ticker = *(UINT64 *) (TopOfTemporaryRam - sizeof (UINT32) - Size - sizeof
> (UINT32) * 2);
> + Performance->ResetEnd = GetTimeInNanoSecond (Ticker);
> +
> + return EFI_SUCCESS;
> +}
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/
> SecFspWrapperPlatformSecLib/SecPlatformInformation.c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/
> SecFspWrapperPlatformSecLib/SecPlatformInformation.c
> new file mode 100644
> index 0000000000..b0b86ab605
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/
> SecFspWrapperPlatformSecLib/SecPlatformInformation.c
> @@ -0,0 +1,78 @@
> +/** @file
> + Provide SecPlatformInformation function.
> +
> +Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> +SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include <PiPei.h>
> +
> +#include <Ppi/SecPlatformInformation.h>
> +#include <Ppi/TopOfTemporaryRam.h>
> +
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/DebugLib.h>
> +
> +/**
> + This interface conveys state information out of the Security (SEC) phase
> into PEI.
> +
> + @param[in] PeiServices Pointer to the PEI Services
> Table.
> + @param[in,out] StructureSize Pointer to the variable
> describing size of the input buffer.
> + @param[out] PlatformInformationRecord Pointer to the
> EFI_SEC_PLATFORM_INFORMATION_RECORD.
> +
> + @retval EFI_SUCCESS The data was successfully returned.
> + @retval EFI_BUFFER_TOO_SMALL The buffer was too small.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +SecPlatformInformation (
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN OUT UINT64 *StructureSize,
> + OUT EFI_SEC_PLATFORM_INFORMATION_RECORD
> *PlatformInformationRecord
> + )
> +{
> + UINT32 *Bist;
> + UINT32 Size;
> + UINT32 Count;
> + UINTN TopOfTemporaryRam;
> + VOID *TopOfTemporaryRamPpi;
> + EFI_STATUS Status;
> +
> + DEBUG ((DEBUG_INFO, "SecPlatformInformation\n"));
> +
> + Status = (*PeiServices)->LocatePpi (
> + PeiServices,
> + &gTopOfTemporaryRamPpiGuid,
> + 0,
> + NULL,
> + (VOID **) &TopOfTemporaryRamPpi
> + );
> + if (EFI_ERROR (Status)) {
> + return EFI_NOT_FOUND;
> + }
> +
> + //
> + // The entries of BIST information, together with the number of them,
> + // reside in the bottom of stack, left untouched by normal stack operation.
> + // This routine copies the BIST information to the buffer pointed by
> + // PlatformInformationRecord for output.
> + //
> + TopOfTemporaryRam = (UINTN) TopOfTemporaryRamPpi - sizeof
> (UINT32);
> + TopOfTemporaryRam -= sizeof (UINT32) * 2;
> + Count = *((UINT32 *)(TopOfTemporaryRam - sizeof
> (UINT32)));
> + Size = Count * sizeof (IA32_HANDOFF_STATUS);
> +
> + if ((*StructureSize) < (UINT64) Size) {
> + *StructureSize = Size;
> + return EFI_BUFFER_TOO_SMALL;
> + }
> +
> + *StructureSize = Size;
> + Bist = (UINT32 *) (TopOfTemporaryRam - sizeof (UINT32) -
> Size);
> +
> + CopyMem (PlatformInformationRecord, Bist, Size);
> +
> + return EFI_SUCCESS;
> +}
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/
> SecFspWrapperPlatformSecLib/SecRamInitData.c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/
> SecFspWrapperPlatformSecLib/SecRamInitData.c
> new file mode 100644
> index 0000000000..8442e5fbff
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/
> SecFspWrapperPlatformSecLib/SecRamInitData.c
> @@ -0,0 +1,55 @@
> +/** @file
> + Provide TempRamInitParams data.
> +
> +Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> +SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include <Library/PcdLib.h>
> +#include <FspEas.h>
> +#include <FsptUpd.h>
> +
> +#pragma pack(1)
> +
> +GLOBAL_REMOVE_IF_UNREFERENCED CONST FSPT_UPD FsptUpdDataPtr = {
> + // FSP_UPD_HEADER
> + {
> + FSPT_UPD_SIGNATURE,
> + 0x00,
> + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00
> + }
> + },
> + // FSPT_CORE_UPD
> + {
> + ((UINT32) FixedPcdGet64 (PcdCpuMicrocodePatchAddress) +
> FixedPcdGet32 (PcdFlashMicrocodeOffset)),
> + ((UINT32) FixedPcdGet64 (PcdCpuMicrocodePatchRegionSize) -
> FixedPcdGet32 (PcdFlashMicrocodeOffset)),
> + 0, // Set CodeRegionBase as 0, so that caching will be
> 4GB-(CodeRegionSize > LLCSize ? LLCSize : CodeRegionSize) will be used.
> + FixedPcdGet32 (PcdFlashCodeCacheSize),
> + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
> + }
> + },
> + // FSP_T_CONFIG
> + {
> + FixedPcdGet8 (PcdSerialIoUartDebugEnable),
> + FixedPcdGet8 (PcdSerialIoUartNumber),
> + 0,
> + 0,
> + FixedPcdGet32 (PcdSerialClockRate),
> + FixedPcdGet64 (PcdPciExpressBaseAddress),
> + FixedPcdGet32 (PcdPciExpressRegionLength),
> + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00
> + }
> + },
> + // UpdTerminator
> + 0x55AA
> +};
> +#pragma pack()
> +
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/
> SecFspWrapperPlatformSecLib/SecTempRamDone.c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/
> SecFspWrapperPlatformSecLib/SecTempRamDone.c
> new file mode 100644
> index 0000000000..65908ef525
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/
> SecFspWrapperPlatformSecLib/SecTempRamDone.c
> @@ -0,0 +1,93 @@
> +/** @file
> + Provide SecTemporaryRamDone function.
> +
> +Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> +SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include <PiPei.h>
> +
> +#include <Ppi/TemporaryRamDone.h>
> +#include <Ppi/TempRamExitPpi.h>
> +#include <Ppi/PlatformInitTempRamExitPpi.h>
> +
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/DebugAgentLib.h>
> +#include <Library/FspWrapperPlatformLib.h>
> +#include <Library/FspWrapperApiLib.h>
> +#include <Library/PeiServicesTablePointerLib.h>
> +
> +/**
> +This interface disables temporary memory in SEC Phase.
> +**/
> +VOID
> +EFIAPI
> +SecPlatformDisableTemporaryMemory (
> + VOID
> + )
> +{
> + EFI_STATUS Status;
> + VOID *TempRamExitParam;
> + CONST EFI_PEI_SERVICES **PeiServices;
> + FSP_TEMP_RAM_EXIT_PPI *TempRamExitPpi;
> + PLATFORM_INIT_TEMP_RAM_EXIT_PPI *PlatformInitTempRamExitPpi;
> +
> + DEBUG ((DEBUG_INFO, "SecPlatformDisableTemporaryMemory
> enter\n"));
> + PeiServices = GetPeiServicesTablePointer ();
> + ASSERT (PeiServices != NULL);
> + if (PeiServices == NULL) {
> + return;
> + }
> + ASSERT ((*PeiServices) != NULL);
> + if ((*PeiServices) == NULL) {
> + return;
> + }
> + Status = (*PeiServices)->LocatePpi (
> + PeiServices,
> + &gPlatformInitTempRamExitPpiGuid,
> + 0,
> + NULL,
> + (VOID **) &PlatformInitTempRamExitPpi
> + );
> + ASSERT_EFI_ERROR (Status);
> + if (EFI_ERROR (Status)) {
> + return;
> + }
> +
> + Status = PlatformInitTempRamExitPpi->PlatformInitBeforeTempRamExit ();
> + ASSERT_EFI_ERROR (Status);
> +
> + if (PcdGet8 (PcdFspModeSelection) == 1) {
> + //
> + // FSP API mode
> + //
> + TempRamExitParam = UpdateTempRamExitParam ();
> + Status = CallTempRamExit (TempRamExitParam);
> + DEBUG ((DEBUG_INFO, "TempRamExit status: 0x%x\n", Status));
> + ASSERT_EFI_ERROR (Status);
> + } else {
> + //
> + // FSP Dispatch mode
> + //
> + Status = (*PeiServices)->LocatePpi (
> + PeiServices,
> + &gFspTempRamExitPpiGuid,
> + 0,
> + NULL,
> + (VOID **) &TempRamExitPpi
> + );
> + ASSERT_EFI_ERROR (Status);
> + if (EFI_ERROR (Status)) {
> + return;
> + }
> + TempRamExitPpi->TempRamExit (NULL);
> + }
> +
> + Status = PlatformInitTempRamExitPpi->PlatformInitAfterTempRamExit ();
> + ASSERT_EFI_ERROR (Status);
> +
> + return ;
> +}
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Include/Fdf/FlashMa
> pInclude.fdf
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Include/Fdf/FlashMa
> pInclude.fdf
> new file mode 100644
> index 0000000000..41d00ee673
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Include/Fdf/FlashMa
> pInclude.fdf
> @@ -0,0 +1,51 @@
> +## @file
> +# Flash map for the UpXtreme Board.
> +#
> +#
> +# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +##
> +
> +#==============================================================
> ===================#
> +# 8 M BIOS - for FSP wrapper
> +#==============================================================
> ===================#
> +DEFINE FLASH_BASE
> = 0xFF800000 #
> +DEFINE FLASH_SIZE
> = 0x00800000 #
> +DEFINE FLASH_BLOCK_SIZE
> = 0x00010000 #
> +DEFINE FLASH_NUM_BLOCKS
> = 0x00000080 #
> +#==============================================================
> ===================#
> +
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageOffset
> = 0x00000000 # Flash addr (0xFF800000)
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageSize
> = 0x00040000 #
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset =
> 0x00000000 # Flash addr (0xFF800000)
> +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
> = 0x0001E000 #
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset
> = 0x0001E000 # Flash addr (0xFF81E000)
> +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
> = 0x00002000 #
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset
> = 0x00020000 # Flash addr (0xFF820000)
> +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
> = 0x00020000 #
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset
> = 0x00040000 # Flash addr (0xFF840000)
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize
> = 0x00050000 #
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset =
> 0x00090000 # Flash addr (0xFF890000)
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize =
> 0x00070000 #
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset
> = 0x00100000 # Flash addr (0xFF900000)
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize
> = 0x00090000 #
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset
> = 0x00190000 # Flash addr (0xFF990000)
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize
> = 0x00190000 #
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset
> = 0x00320000 # Flash addr (0xFFB20000)
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize
> = 0x00170000 #
> +SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset
> = 0x00490000 # Flash addr (0xFFC90000)
> +SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
> = 0x000B0000 #
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset
> = 0x00540000 # Flash addr (0xFFD40000)
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize
> = 0x00070000 #
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset
> = 0x005B0000 # Flash addr (0xFFDB0000)
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize
> = 0x000EC000 #
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset
> = 0x0069C000 # Flash addr (0xFFE9C000)
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize
> = 0x00014000 #
> +SET
> gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryOffset =
> 0x006B0000 # Flash addr (0xFFEB0000)
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemorySize
> = 0x00010000 #
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset
> = 0x006C0000 # Flash addr (0xFFEC0000)
> +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize
> = 0x00140000 #
> +
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Include/Library/PeiPla
> tformHookLib.h
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Include/Library/PeiPl
> atformHookLib.h
> new file mode 100644
> index 0000000000..febccdf482
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Include/Library/PeiPl
> atformHookLib.h
> @@ -0,0 +1,131 @@
> +/** @file
> + UP Xtreme Platform Hook library.
> +
> + Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PEI_PLATFORM_HOOK_LIB_H_
> +#define _PEI_PLATFORM_HOOK_LIB_H_
> +
> +#include <PlatformInfo.h>
> +#include <Library/PeiServicesLib.h>
> +#include <Library/GpioLib.h>
> +
> +// EC Command to provide one byte of debug indication
> +#define BSSB_DEBUG_INDICATION 0xAE
> +/**
> + Configure EC for specific devices
> +
> + @param[in] PchLan - The PchLan of PCH_SETUP variable.
> + @param[in] BootMode - The current boot mode.
> +**/
> +VOID
> +EcInit (
> + IN UINT8 PchLan,
> + IN EFI_BOOT_MODE BootMode
> + );
> +
> +/**
> + Checks if Premium PMIC present
> +
> + @retval TRUE if present
> + @retval FALSE it discrete/other PMIC
> +**/
> +BOOLEAN
> +IsPremiumPmicPresent (
> + VOID
> + );
> +
> +/**
> + Pmic Programming to supprort LPAL Feature
> +
> + @retval NONE
> +**/
> +VOID
> +PremiumPmicDisableSlpS0Voltage (
> + VOID
> + );
> +
> +/**
> +Pmic Programming to supprort LPAL Feature
> + @retval NONE
> +**/
> +VOID
> +PremiumPmicEnableSlpS0Voltage(
> + VOID
> + );
> +
> +/**
> + Do platform specific programming pre-memory. For example, EC init,
> Chipset programming
> +
> + @retval Status
> +**/
> +EFI_STATUS
> +PlatformSpecificInitPreMem (
> + VOID
> + );
> +
> +/**
> + Do platform specific programming post-memory.
> +
> + @retval Status
> +**/
> +EFI_STATUS
> +PlatformSpecificInit (
> + VOID
> + );
> +
> +/**
> + Configure GPIO and SIO Before Memory is ready.
> +
> + @retval EFI_SUCCESS Operation success.
> +**/
> +EFI_STATUS
> +BoardInitPreMem (
> + VOID
> + );
> +
> +/**
> + Configure GPIO and SIO
> +
> + @retval EFI_SUCCESS Operation success.
> +**/
> +EFI_STATUS
> +BoardInit (
> + VOID
> + );
> +
> +/**
> +Voltage Margining Routine
> +
> +@retval EFI_SUCCESS Operation success
> +**/
> +EFI_STATUS
> +VoltageMarginingRoutine(
> + VOID
> + );
> +
> +/**
> + Detect recovery mode
> +
> + @retval EFI_SUCCESS System in Recovery Mode
> + @retval EFI_UNSUPPORTED System doesn't support Recovery Mode
> + @retval EFI_NOT_FOUND System is not in Recovery Mode
> +**/
> +EFI_STATUS
> +IsRecoveryMode (
> + VOID
> + );
> +
> +/**
> + Early board Configuration before Memory is ready.
> +
> + @retval EFI_SUCCESS Operation success.
> +**/
> +EFI_STATUS
> +BoardInitEarlyPreMem (
> + VOID
> + );
> +
> +#endif
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Include/Library/PeiPla
> tformLib.h
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Include/Library/PeiPl
> atformLib.h
> new file mode 100644
> index 0000000000..2514d2ec44
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Include/Library/PeiPl
> atformLib.h
> @@ -0,0 +1,38 @@
> +/** @file
> + UP Xtreme platform library.
> +
> + Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PEI_PLATFORM_LIB_H_
> +#define _PEI_PLATFORM_LIB_H_
> +
> +#define PEI_DEVICE_DISABLED 0
> +#define PEI_DEVICE_ENABLED 1
> +
> +typedef struct {
> + UINT8 Register;
> + UINT32 Value;
> +} PCH_GPIO_DEV;
> +
> +//
> +// GPIO Initialization Data Structure
> +//
> +typedef struct{
> + PCH_GPIO_DEV Use_Sel;
> + PCH_GPIO_DEV Use_Sel2;
> + PCH_GPIO_DEV Use_Sel3;
> + PCH_GPIO_DEV Io_Sel;
> + PCH_GPIO_DEV Io_Sel2;
> + PCH_GPIO_DEV Io_Sel3;
> + PCH_GPIO_DEV Lvl;
> + PCH_GPIO_DEV Lvl2;
> + PCH_GPIO_DEV Lvl3;
> + PCH_GPIO_DEV Inv;
> + PCH_GPIO_DEV Blink;
> + PCH_GPIO_DEV Rst_Sel;
> + PCH_GPIO_DEV Rst_Sel2;
> +} GPIO_INIT_STRUCT;
> +
> +#endif
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Include/PlatformBoar
> dConfig.h
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Include/PlatformBoar
> dConfig.h
> new file mode 100644
> index 0000000000..db6024a1e4
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Include/PlatformBoar
> dConfig.h
> @@ -0,0 +1,103 @@
> +/** @file
> + Header file for UP Xtreme platform board configuration.
> +
> + Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PLATFORM_BOARD_CONFIG_H
> +#define _PLATFORM_BOARD_CONFIG_H
> +
> +#include <ConfigBlock.h>
> +#include <PchPolicyCommon.h>
> +#include <ConfigBlock/MemoryConfig.h>
> +#include <GpioConfig.h>
> +#include <TbtBoardInfo.h>
> +
> +#define IS_ALIGNED(addr, size) (((addr) & (size - 1)) ? 0 : 1)
> +#define ALIGN16(size) (IS_ALIGNED(size, 16) ? size : ((size + 16) &
> 0xFFF0))
> +
> +#define BOARD_CONFIG_BLOCK_PEI_PREMEM_VERSION 0x00000001
> +#define BOARD_CONFIG_BLOCK_PEI_POSTMEM_VERSION 0x00000001
> +#define BOARD_CONFIG_BLOCK_DXE_VERSION 0x00000001
> +#define BOARD_NO_BATTERY_SUPPORT 0
> +#define BOARD_REAL_BATTERY_SUPPORTED BIT0
> +#define BOARD_VIRTUAL_BATTERY_SUPPORTED BIT1
> +
> +#pragma pack(1)
> +
> +typedef struct {
> + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27
> Config Block Header
> +} BOARD_CONFIG_BLOCK;
> +
> +typedef struct {
> + UINT8 GpioSupport;
> + UINT32 WakeGpioNo;
> + UINT8 HoldRstExpanderNo;
> + UINT32 HoldRstGpioNo;
> + BOOLEAN HoldRstActive;
> + UINT8 PwrEnableExpanderNo;
> + UINT32 PwrEnableGpioNo;
> + BOOLEAN PwrEnableActive;
> +} SWITCH_GRAPHIC_GPIO;
> +
> +typedef struct {
> + UINT8 ClkReqNumber : 4;
> + UINT8 ClkReqSupported : 1;
> + UINT8 DeviceResetPadActiveHigh : 1;
> + UINT32 DeviceResetPad;
> +} ROOT_PORT_CLK_INFO;
> +
> +typedef struct {
> + UINT8 Section;
> + UINT8 Pin;
> +} EXPANDER_GPIO_CONFIG;
> +
> +typedef enum {
> + BoardGpioTypePch,
> + BoardGpioTypeExpander,
> + BoardGpioTypeNotSupported = 0xFF
> +} BOARD_GPIO_TYPE;
> +
> +typedef struct {
> + UINT8 Type;
> + UINT8 Reserved[3]; // alignment for COMMON_GPIO_CONFIG
> + union {
> + UINT32 Pin;
> + EXPANDER_GPIO_CONFIG Expander;
> + } u;
> +} BOARD_GPIO_CONFIG;
> +
> +// Do not change the encoding. It must correspond with
> PCH_PCIE_CLOCK_USAGE from PCH RC.
> +#define NOT_USED 0xFF
> +#define FREE_RUNNING 0x80
> +#define LAN_CLOCK 0x70
> +#define PCIE_PEG 0x40
> +#define PCIE_PCH 0x00
> +
> +typedef struct {
> + UINT32 ClockUsage;
> + UINT32 ClkReqSupported;
> +} PCIE_CLOCK_CONFIG;
> +
> +typedef union {
> + UINT64 Blob;
> + BOARD_GPIO_CONFIG BoardGpioConfig;
> + ROOT_PORT_CLK_INFO Info;
> + PCIE_CLOCK_CONFIG PcieClock;
> +} PCD64_BLOB;
> +
> +typedef union {
> + UINT32 Blob;
> + USB20_AFE Info;
> +} PCD32_BLOB;
> +
> +#ifndef IO_EXPANDER_DISABLED
> +#define IO_EXPANDER_DISABLED 0xFF
> +#endif
> +
> +#define SPD_DATA_SIZE 512
> +
> +#pragma pack()
> +
> +#endif // _PLATFORM_BOARD_CONFIG_H
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Include/PlatformInfo.
> h
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Include/PlatformInfo.
> h
> new file mode 100644
> index 0000000000..88564e3733
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Include/PlatformInfo.
> h
> @@ -0,0 +1,42 @@
> +/** @file
> + GUID used for Platform Info Data entries in the HOB list.
> +
> + Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PLATFORM_INFO_H_
> +#define _PLATFORM_INFO_H_
> +
> +#pragma pack(1)
> +
> +///
> +/// PCH_GPIO_PAD is equivalent to GPIO_PAD which is defined in
> GpioConfig.h
> +///
> +typedef UINT32 PCH_GPIO_PAD; //Copied from GpioConfig.h (need to
> change it based on include)
> +
> +typedef struct {
> +UINT8 Expander;
> +UINT8 Pin;
> +UINT16 Reserved; // Reserved for future use
> +} IO_EXPANDER_PAD;
> +
> +typedef union {
> +PCH_GPIO_PAD PchGpio;
> +IO_EXPANDER_PAD IoExpGpio;
> +} GPIO_PAD_CONFIG;
> +
> +typedef struct {
> +UINT8 GpioType; // 0: Disabled (no GPIO support), 1:
> PCH, 2: I/O Expander
> +UINT8 Reserved[3]; // Reserved for future use
> +GPIO_PAD_CONFIG GpioData;
> +} PACKED_GPIO_CONFIG;
> +
> +typedef union {
> +PACKED_GPIO_CONFIG PackedGpio;
> +UINT64 Data64;
> +} COMMON_GPIO_CONFIG;
> +
> +#pragma pack()
> +
> +#endif
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BaseFuncLib/
> BaseFuncLib.inf
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BaseFuncLib/
> BaseFuncLib.inf
> new file mode 100644
> index 0000000000..602e8da686
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BaseFuncLib/
> BaseFuncLib.inf
> @@ -0,0 +1,33 @@
> +## @file
> +# Component information file for Board Functions Library.
> +#
> +#
> +# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = BaseBoardFuncInitLib
> + FILE_GUID =
> 7ad17b6c-b9b6-4d88-85c4-7366a2bd12a3
> + MODULE_TYPE = PEIM
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = NULL|PEIM
> +
> +[LibraryClasses]
> + BaseLib
> + DebugLib
> +
> +[Packages]
> + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + CoffeelakeSiliconPkg/SiPkg.dec
> +
> +[Sources]
> + Gop.c
> +
> +
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BaseFuncLib/
> Gop.c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BaseFuncLib/
> Gop.c
> new file mode 100644
> index 0000000000..e483032944
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BaseFuncLib/
> Gop.c
> @@ -0,0 +1,38 @@
> +/** @file
> + Others Board's PCD function hook.
> +
> +
> + Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include <Uefi.h>
> +#include <Library/DebugLib.h>
> +#include <GopConfigLib.h>
> +
> +//
> +// Null function for nothing GOP VBT update.
> +//
> +VOID
> +EFIAPI
> +GopVbtSpecificUpdateNull (
> + IN CHILD_STRUCT **ChildStructPtr
> + )
> +{
> + return;
> +}
> +
> +VOID
> +EFIAPI
> +UpXtremeSpecificUpdate (
> + IN CHILD_STRUCT **ChildStructPtr
> + )
> +{
> + ChildStructPtr[1]->DeviceClass = DISPLAY_PORT_ONLY;
> + ChildStructPtr[1]->DVOPort = DISPLAY_PORT_B;
> + ChildStructPtr[2]->DeviceClass = DISPLAY_PORT_HDMI_DVI_COMPATIBLE;
> + ChildStructPtr[2]->DVOPort = DISPLAY_PORT_C;
> + ChildStructPtr[2]->AUX_Channel = AUX_CHANNEL_C;
> + ChildStructPtr[3]->DeviceClass = NO_DEVICE;
> +}
> +
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BaseGpioChe
> ckConflictLib/BaseGpioCheckConflictLib.c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BaseGpioChe
> ckConflictLib/BaseGpioCheckConflictLib.c
> new file mode 100644
> index 0000000000..e42bb7cb91
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BaseGpioChe
> ckConflictLib/BaseGpioCheckConflictLib.c
> @@ -0,0 +1,137 @@
> +/** @file
> + Implementation of BaseGpioCheckConflictLib.
> +
> +
> + Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include <Library/GpioCheckConflictLib.h>
> +#include <Uefi/UefiMultiPhase.h>
> +#include <Pi/PiBootMode.h>
> +#include <Pi/PiHob.h>
> +#include <Library/HobLib.h>
> +#include <Library/DebugLib.h>
> +#include <Private/Library/GpioPrivateLib.h>
> +
> +/**
> + Check Gpio PadMode conflict and report it.
> +
> + @retval none.
> +**/
> +VOID
> +GpioCheckConflict (
> + VOID
> + )
> +{
> + EFI_HOB_GUID_TYPE *GpioCheckConflictHob;
> + GPIO_PAD_MODE_INFO *GpioCheckConflictHobData;
> + UINT32 HobDataSize;
> + UINT32 GpioCount;
> + UINT32 GpioIndex;
> + GPIO_CONFIG GpioActualConfig;
> +
> + GpioCheckConflictHob = NULL;
> + GpioCheckConflictHobData = NULL;
> +
> + DEBUG ((DEBUG_INFO, "GpioCheckConflict Start..\n"));
> +
> + //
> + //Use Guid to find HOB.
> + //
> + GpioCheckConflictHob = (EFI_HOB_GUID_TYPE *) GetFirstGuidHob
> (&gGpioCheckConflictHobGuid);
> + if (GpioCheckConflictHob == NULL) {
> + DEBUG ((DEBUG_INFO, "[Gpio Hob Check] Can't find Gpio Hob.\n"));
> + } else {
> + while (GpioCheckConflictHob != NULL) {
> + //
> + // Find the Data area pointer and Data size from the Hob
> + //
> + GpioCheckConflictHobData = (GPIO_PAD_MODE_INFO *)
> GET_GUID_HOB_DATA (GpioCheckConflictHob);
> + HobDataSize = GET_GUID_HOB_DATA_SIZE (GpioCheckConflictHob);
> +
> + GpioCount = HobDataSize / sizeof (GPIO_PAD_MODE_INFO);
> + DEBUG ((DEBUG_INFO, "[Hob Check] Hob : GpioCount = %d\n",
> GpioCount));
> +
> + //
> + // Probe Gpio entries in Hob and compare which are conflicted
> + //
> + for (GpioIndex = 0; GpioIndex < GpioCount ; GpioIndex++) {
> + GpioGetPadConfig
> (GpioCheckConflictHobData[GpioIndex].GpioPad, &GpioActualConfig);
> + if (GpioCheckConflictHobData[GpioIndex].GpioPadMode !=
> GpioActualConfig.PadMode) {
> + DEBUG ((DEBUG_ERROR, "[Gpio Check] Identified conflict on
> pad %a\n", GpioName (GpioCheckConflictHobData[GpioIndex].GpioPad)));
> + }
> + }
> + //
> + // Find next Hob and return the Hob pointer by the specific Hob Guid
> + //
> + GpioCheckConflictHob = GET_NEXT_HOB (GpioCheckConflictHob);
> + GpioCheckConflictHob = GetNextGuidHob
> (&gGpioCheckConflictHobGuid, GpioCheckConflictHob);
> + }
> +
> + DEBUG ((DEBUG_INFO, "GpioCheckConflict End.\n"));
> + }
> +
> + return;
> +}
> +
> +/**
> + This libaray will create one Hob for each Gpio config table
> + without PadMode is GpioHardwareDefault
> +
> + @param[in] GpioDefinition Point to Platform Gpio table
> + @param[in] GpioTableCount Number of Gpio table entries
> +
> + @retval none.
> +**/
> +VOID
> +CreateGpioCheckConflictHob (
> + IN GPIO_INIT_CONFIG *GpioDefinition,
> + IN UINT16 GpioTableCount
> + )
> +{
> +
> + UINT32 Index;
> + UINT32 GpioIndex;
> + GPIO_PAD_MODE_INFO *GpioCheckConflictHobData;
> + UINT16 GpioCount;
> +
> + GpioCount = 0;
> + GpioIndex = 0;
> +
> + DEBUG ((DEBUG_INFO, "CreateGpioCheckConflictHob Start \n"));
> +
> + for (Index = 0; Index < GpioTableCount ; Index++) {
> + if (GpioDefinition[Index].GpioConfig.PadMode == GpioHardwareDefault)
> {
> + continue;
> + } else {
> + //
> + // Calculate how big size the Hob Data needs
> + //
> + GpioCount++;
> + }
> + }
> +
> + //
> + // Build a HOB tagged with a GUID for identification and returns
> + // the start address of GUID HOB data.
> + //
> + GpioCheckConflictHobData = (GPIO_PAD_MODE_INFO *) BuildGuidHob
> (&gGpioCheckConflictHobGuid , GpioCount * sizeof
> (GPIO_PAD_MODE_INFO));
> +
> + //
> + // Record Non Default Gpio entries to the Hob
> + //
> + for (Index = 0; Index < GpioTableCount; Index++) {
> + if (GpioDefinition[Index].GpioConfig.PadMode == GpioHardwareDefault)
> {
> + continue;
> + } else {
> + GpioCheckConflictHobData[GpioIndex].GpioPad =
> GpioDefinition[Index].GpioPad;
> + GpioCheckConflictHobData[GpioIndex].GpioPadMode =
> GpioDefinition[Index].GpioConfig.PadMode;
> + GpioIndex++;
> + }
> + }
> +
> + DEBUG ((DEBUG_INFO, "CreateGpioCheckConflictHob End \n"));
> + return;
> +}
> +
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BaseGpioChe
> ckConflictLib/BaseGpioCheckConflictLib.inf
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BaseGpioChe
> ckConflictLib/BaseGpioCheckConflictLib.inf
> new file mode 100644
> index 0000000000..24506c3453
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BaseGpioChe
> ckConflictLib/BaseGpioCheckConflictLib.inf
> @@ -0,0 +1,35 @@
> +## @file
> +# Component information file for BaseGpioCheckConflictLib.
> +#
> +#
> +# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x00010017
> + BASE_NAME = BaseGpioCheckConflictLib
> + FILE_GUID =
> C19A848A-F013-4DBF-9C23-F0F74DEA6F14
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = GpioCheckConflictLib
> +
> +[LibraryClasses]
> + DebugLib
> + HobLib
> + GpioLib
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec
> + CoffeelakeSiliconPkg/SiPkg.dec
> +
> +[Sources]
> + BaseGpioCheckConflictLib.c
> +
> +[Guids]
> + gGpioCheckConflictHobGuid
> +
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BaseGpioChe
> ckConflictLibNull/BaseGpioCheckConflictLibNull.c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BaseGpioChe
> ckConflictLibNull/BaseGpioCheckConflictLibNull.c
> new file mode 100644
> index 0000000000..525a9b3e0f
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BaseGpioChe
> ckConflictLibNull/BaseGpioCheckConflictLibNull.c
> @@ -0,0 +1,37 @@
> +/** @file
> + Implementation of BaseGpioCheckConflicLibNull.
> +
> +
> + Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include <Library/GpioCheckConflictLib.h>
> +
> +/**
> + Check Gpio PadMode conflict and report it.
> +**/
> +VOID
> +GpioCheckConflict (
> + VOID
> + )
> +{
> + return;
> +}
> +
> +/**
> + This libaray will create one Hob for each Gpio config table
> + without PadMode is GpioHardwareDefault
> +
> + @param[in] GpioDefinition Point to Platform Gpio table
> + @param[in] GpioTableCount Number of Gpio table entries
> +**/
> +VOID
> +CreateGpioCheckConflictHob (
> + IN GPIO_INIT_CONFIG *GpioDefinition,
> + IN UINT16 GpioTableCount
> + )
> +{
> + return;
> +}
> +
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BaseGpioChe
> ckConflictLibNull/BaseGpioCheckConflictLibNull.inf
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BaseGpioChe
> ckConflictLibNull/BaseGpioCheckConflictLibNull.inf
> new file mode 100644
> index 0000000000..c00cf0b8af
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BaseGpioChe
> ckConflictLibNull/BaseGpioCheckConflictLibNull.inf
> @@ -0,0 +1,32 @@
> +## @file
> +# Component information file for BaseGpioCheckConflictLib.
> +#
> +#
> +# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x00010017
> + BASE_NAME = BaseGpioCheckConflictLibNull
> + FILE_GUID =
> C19A848A-F013-4DBF-9C23-F0F74DEA6F14
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = GpioCheckConflictLib
> +
> +[LibraryClasses]
> + DebugLib
> + HobLib
> + GpioLib
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec
> + CoffeelakeSiliconPkg/SiPkg.dec
> +
> +[Sources]
> + BaseGpioCheckConflictLibNull.c
> +
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BasePlatform
> HookLib/BasePlatformHookLib.c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BasePlatform
> HookLib/BasePlatformHookLib.c
> new file mode 100644
> index 0000000000..119a04b7fd
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BasePlatform
> HookLib/BasePlatformHookLib.c
> @@ -0,0 +1,143 @@
> +
> +/** @file
> + Platform Hook Library instance for the UpXtreme Board
> +
> + Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include <Base.h>
> +#include <GpioPinsCnlLp.h>
> +#include <Library/BaseLib.h>
> +#include <Library/GpioLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/PciSegmentLib.h>
> +#include <Library/PlatformHookLib.h>
> +#include <PchAccess.h>
> +#include <Uefi/UefiBaseType.h>
> +
> +#define LCR_OFFSET (FixedPcdGet32 (PcdSerialRegisterStride) * 0x03)
> +
> +STATIC GPIO_INIT_CONFIG mUartGpioTable[] = {
> + {GPIO_CNL_LP_GPP_C20, {GpioPadModeNative1, GpioHostOwnGpio,
> GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}},//SERIALIO_UART2_RXD
> + {GPIO_CNL_LP_GPP_C21, {GpioPadModeNative1, GpioHostOwnGpio,
> GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}},//SERIALIO_UART2_TXD
> +};
> +
> +/**
> + Retrieve the I/O or MMIO base address register for the PCI UART device.
> +
> + @retval The base address register of the UART device.
> +
> +**/
> +STATIC
> +UINTN
> +GetSerialRegisterBase (
> + VOID
> + )
> +{
> + UINT64 PciAddress;
> + UINT32 BaseAddressBuffer[2];
> + UINT16 Cmd16;
> +
> + PciAddress = PCI_SEGMENT_LIB_ADDRESS (
> + DEFAULT_PCI_SEGMENT_NUMBER_PCH,
> + DEFAULT_PCI_BUS_NUMBER_PCH,
> + PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART2,
> + PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART2,
> + 0
> + );
> +
> + Cmd16 = PciSegmentRead16 (PciAddress + PCI_VENDOR_ID_OFFSET);
> + if (Cmd16 == 0xFFFF) {
> + //
> + // Device might be hidden, return the fixed serial register base address
> + //
> + return (UINTN) FixedPcdGet32 (PcdSerialRegisterBase);
> + } else {
> + if (PciSegmentRead32 (PciAddress + PCI_COMMAND_OFFSET) &
> EFI_PCI_COMMAND_MEMORY_SPACE) {
> + BaseAddressBuffer[0] = PciSegmentRead32 (PciAddress +
> R_SERIAL_IO_CFG_BAR0_LOW) & B_SERIAL_IO_CFG_BAR0_LOW_BAR;
> + BaseAddressBuffer[1] = 0;
> +
> + if ((PciSegmentRead32 (PciAddress + PCI_BASE_ADDRESSREG_OFFSET)
> & 0x6) == 0x4) {
> + BaseAddressBuffer[1] = PciSegmentRead32 (PciAddress +
> R_SERIAL_IO_CFG_BAR0_HIGH);
> + }
> + return *((UINTN *) (&BaseAddressBuffer[0]));
> + } else {
> + return 0;
> + }
> + }
> +}
> +
> +/**
> + Performs platform specific initialization required for the CPU to access
> + the hardware associated with a SerialPortLib instance. This function
> does
> + not initialize the serial port hardware itself. Instead, it initializes
> + hardware devices that are required for the CPU to access the serial port
> + hardware. This function may be called more than once.
> +
> + @retval RETURN_SUCCESS The platform specific initialization
> succeeded.
> + @retval RETURN_DEVICE_ERROR The platform specific initialization
> could not be completed.
> +
> +**/
> +RETURN_STATUS
> +EFIAPI
> +PlatformHookSerialPortInitialize (
> + VOID
> + )
> +{
> + UINT64 PciAddress;
> + UINTN SerialRegisterBase;
> + UINTN SerialRegisterBase1;
> +
> + PciAddress = PCI_SEGMENT_LIB_ADDRESS (
> + DEFAULT_PCI_SEGMENT_NUMBER_PCH,
> + DEFAULT_PCI_BUS_NUMBER_PCH,
> + PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART2,
> + PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART2,
> + 0
> + );
> +
> + SerialRegisterBase = GetSerialRegisterBase ();
> +
> + if (SerialRegisterBase == 0 || SerialRegisterBase == (UINTN) ~0) {
> + return RETURN_DEVICE_ERROR;
> + }
> + SerialRegisterBase1 = SerialRegisterBase + V_SERIAL_IO_CFG_BAR_SIZE;
> +
> + if (
> + (MmioRead8 (SerialRegisterBase + LCR_OFFSET) & 0x3F) !=
> + (FixedPcdGet8 (PcdSerialLineControl) & 0x3F)
> + ) {
> + GpioConfigurePads ((sizeof (mUartGpioTable) / sizeof
> (GPIO_INIT_CONFIG)), mUartGpioTable);
> +
> + PciSegmentWrite32 (PciAddress + R_SERIAL_IO_CFG_BAR0_LOW,
> (UINT32) SerialRegisterBase);
> + PciSegmentWrite32 (PciAddress + R_SERIAL_IO_CFG_BAR1_LOW,
> (UINT32) SerialRegisterBase1);
> + if (sizeof (UINTN) == sizeof (UINT32)) {
> + PciSegmentWrite32 (PciAddress + R_SERIAL_IO_CFG_BAR0_HIGH,
> 0x0);
> + PciSegmentWrite32 (PciAddress + R_SERIAL_IO_CFG_BAR1_HIGH,
> 0x0);
> + } else {
> + PciSegmentWrite32 (PciAddress + R_SERIAL_IO_CFG_BAR0_HIGH,
> (UINT32) RShiftU64 (SerialRegisterBase, 32));
> + PciSegmentWrite32 (PciAddress + R_SERIAL_IO_CFG_BAR1_HIGH,
> (UINT32) RShiftU64 (SerialRegisterBase1, 32));
> + }
> + PciSegmentWrite32 (PciAddress + PCI_COMMAND_OFFSET,
> EFI_PCI_COMMAND_BUS_MASTER | EFI_PCI_COMMAND_MEMORY_SPACE);
> + PciSegmentOr32 (PciAddress + R_SERIAL_IO_CFG_D0I3MAXDEVPG,
> BIT18 | BIT17 | BIT16);
> +
> + //
> + // Get controller out of reset
> + //
> + MmioOr32 (SerialRegisterBase + R_SERIAL_IO_MEM_PPR_RESETS,
> + B_SERIAL_IO_MEM_PPR_RESETS_FUNC |
> B_SERIAL_IO_MEM_PPR_RESETS_APB |
> B_SERIAL_IO_MEM_PPR_RESETS_IDMA);
> +
> + //
> + // Program clock dividers for UARTs
> + //
> + MmioWrite32 (SerialRegisterBase + R_SERIAL_IO_MEM_PPR_CLK,
> + (B_SERIAL_IO_MEM_PPR_CLK_UPDATE |
> (V_SERIAL_IO_MEM_PPR_CLK_N_DIV << 16) |
> + (V_SERIAL_IO_MEM_PPR_CLK_M_DIV << 1) |
> B_SERIAL_IO_MEM_PPR_CLK_EN )
> + );
> + }
> +
> + return RETURN_SUCCESS;
> +}
> +
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BasePlatform
> HookLib/BasePlatformHookLib.inf
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BasePlatform
> HookLib/BasePlatformHookLib.inf
> new file mode 100644
> index 0000000000..b527d90f08
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BasePlatform
> HookLib/BasePlatformHookLib.inf
> @@ -0,0 +1,45 @@
> +## @file
> +# Platform Hook Library instance for the UpXtreme board.
> +#
> +#
> +# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x00010017
> + BASE_NAME = BasePlatformHookLib
> + FILE_GUID =
> E22ADCC6-ED90-4A90-9837-C8E7FF9E963D
> + VERSION_STRING = 1.0
> + MODULE_TYPE = BASE
> + LIBRARY_CLASS = PlatformHookLib
> +#
> +# The following information is for reference only and not required by the
> build tools.
> +#
> +# VALID_ARCHITECTURES = IA32 X64 IPF EBC
> +#
> +
> +[LibraryClasses]
> + BaseLib
> + GpioLib
> + IoLib
> + PcdLib
> + PciSegmentLib
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + MinPlatformPkg/MinPlatformPkg.dec
> + CoffeelakeSiliconPkg/SiPkg.dec
> + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec
> +
> +[Sources]
> + BasePlatformHookLib.c
> +
> +[FixedPcd]
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialLineControl
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardAcpiLib/
> SmmBoardAcpiEnableLib.c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardAcpiLib/
> SmmBoardAcpiEnableLib.c
> new file mode 100644
> index 0000000000..57ba4c7a6f
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardAcpiLib/
> SmmBoardAcpiEnableLib.c
> @@ -0,0 +1,63 @@
> +/** @file
> + SMM Board ACPI Enable Library for the UpXtreme Board
> +
> +
> + Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include <Base.h>
> +#include <Uefi.h>
> +#include <PiDxe.h>
> +#include <Library/BaseLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/BoardAcpiEnableLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/DebugLib.h>
> +
> +EFI_STATUS
> +EFIAPI
> +UpXtremeBoardEnableAcpi (
> + IN BOOLEAN EnableSci
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +UpXtremeBoardDisableAcpi (
> + IN BOOLEAN DisableSci
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +SiliconEnableAcpi (
> + IN BOOLEAN EnableSci
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +SiliconDisableAcpi (
> + IN BOOLEAN DisableSci
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +BoardEnableAcpi (
> + IN BOOLEAN EnableSci
> + )
> +{
> + SiliconEnableAcpi (EnableSci);
> + return UpXtremeBoardEnableAcpi (EnableSci);
> +}
> +
> +EFI_STATUS
> +EFIAPI
> +BoardDisableAcpi (
> + IN BOOLEAN DisableSci
> + )
> +{
> + SiliconDisableAcpi (DisableSci);
> + return UpXtremeBoardDisableAcpi (DisableSci);
> +}
> +
> +
> +
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardAcpiLib/
> SmmBoardAcpiEnableLib.inf
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardAcpiLib/
> SmmBoardAcpiEnableLib.inf
> new file mode 100644
> index 0000000000..b1c685711a
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardAcpiLib/
> SmmBoardAcpiEnableLib.inf
> @@ -0,0 +1,50 @@
> +## @file
> +# SMM Board ACPI Enable Library for the UpXtreme Board
> +#
> +#
> +# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x00010017
> + BASE_NAME = SmmBoardAcpiEnableLib
> + FILE_GUID =
> 549E69AE-D3B3-485B-9C17-AF16E20A58AD
> + VERSION_STRING = 1.0
> + MODULE_TYPE = BASE
> + LIBRARY_CLASS = BoardAcpiEnableLib
> +
> +#
> +# The following information is for reference only and not required by the
> build tools.
> +#
> +# VALID_ARCHITECTURES = IA32 X64 IPF EBC
> +#
> +
> +[LibraryClasses]
> + BaseLib
> + IoLib
> + PciLib
> + MmPciLib
> + PchCycleDecodingLib
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + MinPlatformPkg/MinPlatformPkg.dec
> + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec
> + CoffeelakeSiliconPkg/SiPkg.dec
> +
> +[Pcd]
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSmcExtSmiBitPosition
> ## CONSUMES
> +
> +[Protocols]
> +
> +[Sources]
> + SmmUpXtremeAcpiEnableLib.c
> + SmmSiliconAcpiEnableLib.c
> + SmmBoardAcpiEnableLib.c
> +
> +
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardAcpiLib/
> SmmMultiBoardAcpiSupportLib.c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardAcpiLib/
> SmmMultiBoardAcpiSupportLib.c
> new file mode 100644
> index 0000000000..63881029ad
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardAcpiLib/
> SmmMultiBoardAcpiSupportLib.c
> @@ -0,0 +1,82 @@
> +/** @file
> + SMM Multi-Board ACPI Support Library for the UpXtreme Board
> +
> +
> + Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include <Base.h>
> +#include <Uefi.h>
> +#include <PiDxe.h>
> +#include <Library/BaseLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/BoardAcpiEnableLib.h>
> +#include <Library/MultiBoardAcpiSupportLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/DebugLib.h>
> +
> +#include <PlatformBoardId.h>
> +
> +EFI_STATUS
> +EFIAPI
> +UpXtremeBoardEnableAcpi (
> + IN BOOLEAN EnableSci
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +UpXtremeBoardDisableAcpi (
> + IN BOOLEAN DisableSci
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +SiliconEnableAcpi (
> + IN BOOLEAN EnableSci
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +SiliconDisableAcpi (
> + IN BOOLEAN DisableSci
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +UpXtremeMultiBoardEnableAcpi (
> + IN BOOLEAN EnableSci
> + )
> +{
> + SiliconEnableAcpi (EnableSci);
> + return UpXtremeBoardEnableAcpi (EnableSci);
> +}
> +
> +EFI_STATUS
> +EFIAPI
> +UpXtremeMultiBoardDisableAcpi (
> + IN BOOLEAN DisableSci
> + )
> +{
> + SiliconDisableAcpi (DisableSci);
> + return UpXtremeBoardDisableAcpi (DisableSci);
> +}
> +
> +BOARD_ACPI_ENABLE_FUNC mUpXtremeBoardAcpiEnableFunc = {
> + UpXtremeMultiBoardEnableAcpi,
> + UpXtremeMultiBoardDisableAcpi,
> +};
> +
> +EFI_STATUS
> +EFIAPI
> +SmmUpXtremeMultiBoardAcpiSupportLibConstructor (
> + VOID
> + )
> +{
> + if (LibPcdGetSku () == BoardIdUpXtreme) {
> + return RegisterBoardAcpiEnableFunc
> (&mUpXtremeBoardAcpiEnableFunc);
> + }
> + return EFI_SUCCESS;
> +}
> +
> +
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardAcpiLib/
> SmmMultiBoardAcpiSupportLib.inf
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardAcpiLib/
> SmmMultiBoardAcpiSupportLib.inf
> new file mode 100644
> index 0000000000..5f5493de77
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardAcpiLib/
> SmmMultiBoardAcpiSupportLib.inf
> @@ -0,0 +1,50 @@
> +## @file
> +# SMM Multi-Board ACPI Support Library for the UpXtreme Board
> +#
> +#
> +# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x00010017
> + BASE_NAME =
> SmmUpXtremeMultiBoardAcpiSupportLib
> + FILE_GUID =
> 8929A54E-7ED8-4AB3-BEBB-C0367BDBBFF5
> + VERSION_STRING = 1.0
> + MODULE_TYPE = BASE
> + LIBRARY_CLASS = NULL
> + CONSTRUCTOR =
> SmmUpXtremeMultiBoardAcpiSupportLibConstructor
> +
> +#
> +# The following information is for reference only and not required by the
> build tools.
> +#
> +# VALID_ARCHITECTURES = IA32 X64 IPF EBC
> +#
> +
> +[LibraryClasses]
> + BaseLib
> + IoLib
> + PciLib
> + PmcLib
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + MinPlatformPkg/MinPlatformPkg.dec
> + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec
> + CoffeelakeSiliconPkg/SiPkg.dec
> +
> +[Pcd]
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSmcExtSmiBitPosition
> ## CONSUMES
> +
> +[Protocols]
> +
> +[Sources]
> + SmmUpXtremeAcpiEnableLib.c
> + SmmSiliconAcpiEnableLib.c
> + SmmMultiBoardAcpiSupportLib.c
> +
> +
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardAcpiLib/
> SmmSiliconAcpiEnableLib.c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardAcpiLib/
> SmmSiliconAcpiEnableLib.c
> new file mode 100644
> index 0000000000..23b4fe6dc5
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardAcpiLib/
> SmmSiliconAcpiEnableLib.c
> @@ -0,0 +1,170 @@
> +/** @file
> + SMM Silicon ACPI Enable Library for the UpXtreme Board
> +
> +
> + Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include <Base.h>
> +#include <Uefi.h>
> +#include <PiDxe.h>
> +#include <Library/BaseLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/PciSegmentLib.h>
> +#include <Library/BoardAcpiEnableLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/DebugLib.h>
> +#include <PchAccess.h>
> +#include <Library/MmPciLib.h>
> +#include <Library/PmcLib.h>
> +
> +/**
> + Clear Port 80h
> +
> + SMI handler to enable ACPI mode
> +
> + Dispatched on reads from APM port with value
> EFI_ACPI_ENABLE_SW_SMI
> +
> + Disables the SW SMI Timer.
> + ACPI events are disabled and ACPI event status is cleared.
> + SCI mode is then enabled.
> +
> + Clear SLP SMI status
> + Enable SLP SMI
> +
> + Disable SW SMI Timer
> +
> + Clear all ACPI event status and disable all ACPI events
> +
> + Disable PM sources except power button
> + Clear status bits
> +
> + Disable GPE0 sources
> + Clear status bits
> +
> + Disable GPE1 sources
> + Clear status bits
> +
> + Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4)
> +
> + Enable SCI
> +**/
> +EFI_STATUS
> +EFIAPI
> +SiliconEnableAcpi (
> + IN BOOLEAN EnableSci
> + )
> +{
> +
> + UINT32 OutputValue;
> + UINT32 SmiEn;
> + UINT32 SmiSts;
> + UINT32 ULKMC;
> + UINTN LpcBaseAddress;
> + UINT16 AcpiBaseAddr;
> + UINT32 Pm1Cnt;
> +
> + LpcBaseAddress = PCI_SEGMENT_LIB_ADDRESS(
> + DEFAULT_PCI_SEGMENT_NUMBER_PCH,
> + DEFAULT_PCI_BUS_NUMBER_PCH,
> + PCI_DEVICE_NUMBER_PCH_LPC,
> + PCI_FUNCTION_NUMBER_PCH_LPC,
> + 0
> + );
> + //
> + // Get the ACPI Base Address
> + //
> + AcpiBaseAddr = PmcGetAcpiBase();
> + //
> + // BIOS must also ensure that CF9GR is cleared and locked before handing
> control to the
> + // OS in order to prevent the host from issuing global resets and resetting
> ME
> + //
> + // EDK2: To match PCCG current BIOS behavior, do not lock CF9 Global
> Reset
> + // MmioWrite32 (
> + // PmcBaseAddress + R_PCH_PMC_ETR3),
> + // PmInit);
> +
> + //
> + // Clear Port 80h
> + //
> + IoWrite8 (0x80, 0);
> +
> + //
> + // Disable SW SMI Timer and clean the status
> + //
> + SmiEn = IoRead32 (AcpiBaseAddr + R_ACPI_IO_SMI_EN);
> + SmiEn &= ~(B_ACPI_IO_SMI_EN_LEGACY_USB2 |
> B_ACPI_IO_SMI_EN_SWSMI_TMR | B_ACPI_IO_SMI_EN_LEGACY_USB);
> + IoWrite32 (AcpiBaseAddr + R_ACPI_IO_SMI_EN, SmiEn);
> +
> + SmiSts = IoRead32 (AcpiBaseAddr + R_ACPI_IO_SMI_STS);
> + SmiSts |= B_ACPI_IO_SMI_EN_LEGACY_USB2 |
> B_ACPI_IO_SMI_EN_SWSMI_TMR | B_ACPI_IO_SMI_EN_LEGACY_USB;
> + IoWrite32 (AcpiBaseAddr + R_ACPI_IO_SMI_STS, SmiSts);
> +
> + //
> + // Disable port 60/64 SMI trap if they are enabled
> + //
> + ULKMC = MmioRead32 (LpcBaseAddress + R_LPC_CFG_ULKMC) &
> ~(B_LPC_CFG_ULKMC_60REN | B_LPC_CFG_ULKMC_60WEN |
> B_LPC_CFG_ULKMC_64REN | B_LPC_CFG_ULKMC_64WEN |
> B_LPC_CFG_ULKMC_A20PASSEN);
> + MmioWrite32 (LpcBaseAddress + R_LPC_CFG_ULKMC, ULKMC);
> +
> + //
> + // Disable PM sources except power button
> + //
> + IoWrite16 (AcpiBaseAddr + R_ACPI_IO_PM1_EN,
> B_ACPI_IO_PM1_EN_PWRBTN);
> +
> + //
> + // Clear PM status except Power Button status for RapidStart Resume
> + //
> + IoWrite16 (AcpiBaseAddr + R_ACPI_IO_PM1_STS, 0xFEFF);
> +
> + //
> + // Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4)
> + //
> + IoWrite8 (R_RTC_IO_INDEX_ALT, R_RTC_IO_REGD);
> + IoWrite8 (R_RTC_IO_TARGET_ALT, 0x0);
> +
> + //
> + // Write ALT_GPI_SMI_EN to disable GPI1 (SMC_EXTSMI#)
> + //
> + OutputValue = IoRead32 (AcpiBaseAddr + 0x38);
> + OutputValue = OutputValue & ~(1 << (UINTN) PcdGet8
> (PcdSmcExtSmiBitPosition));
> + IoWrite32 (AcpiBaseAddr + 0x38, OutputValue);
> +
> + //
> + // Enable SCI
> + //
> + if (EnableSci) {
> + Pm1Cnt = IoRead32 (AcpiBaseAddr + R_ACPI_IO_PM1_CNT);
> + Pm1Cnt |= B_ACPI_IO_PM1_CNT_SCI_EN;
> + IoWrite32 (AcpiBaseAddr + R_ACPI_IO_PM1_CNT, Pm1Cnt);
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +EFI_STATUS
> +EFIAPI
> +SiliconDisableAcpi (
> + IN BOOLEAN DisableSci
> + )
> +{
> +
> + UINT16 AcpiBaseAddr;
> + UINT32 Pm1Cnt;
> +
> + //
> + // Get the ACPI Base Address
> + //
> + AcpiBaseAddr = PmcGetAcpiBase();
> + //
> + // Disable SCI
> + //
> + if (DisableSci) {
> + Pm1Cnt = IoRead32 (AcpiBaseAddr + R_ACPI_IO_PM1_CNT);
> + Pm1Cnt &= ~B_ACPI_IO_PM1_CNT_SCI_EN;
> + IoWrite32 (AcpiBaseAddr + R_ACPI_IO_PM1_CNT, Pm1Cnt);
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardAcpiLib/
> SmmUpXtremeAcpiEnableLib.c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardAcpiLib/
> SmmUpXtremeAcpiEnableLib.c
> new file mode 100644
> index 0000000000..2b777aab02
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardAcpiLib/
> SmmUpXtremeAcpiEnableLib.c
> @@ -0,0 +1,40 @@
> +/** @file
> + SMM UpXtreme ACPI Enable Library
> +
> +
> + Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include <Base.h>
> +#include <Uefi.h>
> +#include <PiDxe.h>
> +#include <Library/BaseLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/BoardAcpiTableLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/DebugLib.h>
> +
> +#include <PlatformBoardId.h>
> +
> +EFI_STATUS
> +EFIAPI
> +UpXtremeBoardEnableAcpi (
> + IN BOOLEAN EnableSci
> + )
> +{
> + // enable additional board register
> + return EFI_SUCCESS;
> +}
> +
> +EFI_STATUS
> +EFIAPI
> +UpXtremeBoardDisableAcpi (
> + IN BOOLEAN DisableSci
> + )
> +{
> + // enable additional board register
> + return EFI_SUCCESS;
> +}
> +
> +
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/
> BoardFuncInitPreMem.c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/
> BoardFuncInitPreMem.c
> new file mode 100644
> index 0000000000..09badef00e
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/
> BoardFuncInitPreMem.c
> @@ -0,0 +1,25 @@
> +/** @file
> + Source code for the board configuration init function in Post Memory init
> phase.
> +
> +
> + Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include <GopConfigLib.h>
> +
> +//
> +// Null function for nothing GOP VBT update.
> +//
> +VOID
> +GopVbtSpecificUpdateNull (
> + IN CHILD_STRUCT **ChildStructPtr
> + );
> +
> +//
> +// for CFL U DDR4
> +//
> +VOID
> +UpXtremeSpecificUpdate (
> + IN CHILD_STRUCT **ChildStructPtr
> + );
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/
> BoardInitLib.h
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/
> BoardInitLib.h
> new file mode 100644
> index 0000000000..758cbaa0b6
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/
> BoardInitLib.h
> @@ -0,0 +1,20 @@
> +/** @file
> + Header file for board Init function for Post Memory Init phase.
> +
> +
> + Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PEI_BOARD_INIT_LIB_H_
> +#define _PEI_BOARD_INIT_LIB_H_
> +
> +#include <Uefi.h>
> +#include <Library/BaseLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +#include <Library/DebugLib.h>
> +#include <PlatformBoardId.h>
> +
> +#endif // _PEI_BOARD_INIT_LIB_H_
> +
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/
> BoardPchInitPreMemLib.c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/
> BoardPchInitPreMemLib.c
> new file mode 100644
> index 0000000000..ddeea45175
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/
> BoardPchInitPreMemLib.c
> @@ -0,0 +1,375 @@
> +/** @file
> + Source code for the board PCH configuration Pcd init functions for
> Pre-Memory Init phase.
> +
> +
> + Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include "UpXtremeInit.h"
> +#include <GpioPinsCnlLp.h>
> +#include <GpioPinsCnlH.h>
> +#include <PlatformBoardConfig.h> // for USB 20 AFE & Root Port Clk
> Info.
> +#include <PlatformBoardId.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/GpioLib.h>
> +
> +/**
> + Board Root Port Clock Info configuration init function for PEI pre-memory
> phase.
> +
> + @param[in] BoardId An unsigned integrer represent the board id.
> +
> + @retval EFI_SUCCESS The function completed successfully.
> +**/
> +EFI_STATUS
> +RootPortClkInfoInit (
> + IN UINT16 BoardId
> + )
> +{
> + PCD64_BLOB *Clock;
> + UINT32 Index;
> +
> + Clock = AllocateZeroPool (16 * sizeof (PCD64_BLOB));
> + ASSERT (Clock != NULL);
> + if (Clock == NULL) {
> + return EFI_OUT_OF_RESOURCES;
> + }
> + //
> + // The default clock assignment will be FREE_RUNNING, which
> corresponds to PchClockUsageUnspecified
> + // This is safe but power-consuming setting. If Platform code doesn't
> contain port-clock map for a given board,
> + // the clocks will keep on running anyway, allowing PCIe devices to operate.
> Downside is that clocks will
> + // continue to draw power. To prevent this, remember to provide
> port-clock map for every board.
> + //
> + for (Index = 0; Index < 16; Index++) {
> + Clock[Index].PcieClock.ClkReqSupported = TRUE;
> + Clock[Index].PcieClock.ClockUsage = FREE_RUNNING;
> + }
> +
> + ///
> + /// Assign ClkReq signal to root port. (Base 0)
> + /// For LP, Set 0 - 5
> + /// For H, Set 0 - 15
> + /// Note that if GbE is enabled, ClkReq assigned to GbE will not be
> available for Root Port.
> + ///
> + switch (BoardId) {
> + // CLKREQ
> + case BoardIdUpXtreme:
> + Clock[0].PcieClock.ClockUsage = FREE_RUNNING;
> + Clock[1].PcieClock.ClockUsage = FREE_RUNNING;
> + Clock[2].PcieClock.ClockUsage = FREE_RUNNING;
> + Clock[3].PcieClock.ClockUsage = FREE_RUNNING;
> + Clock[4].PcieClock.ClockUsage = FREE_RUNNING;
> + Clock[5].PcieClock.ClockUsage = FREE_RUNNING;
> + break;
> +
> + default:
> + break;
> + }
> +
> + PcdSet64S (PcdPcieClock0, Clock[ 0].Blob);
> + PcdSet64S (PcdPcieClock1, Clock[ 1].Blob);
> + PcdSet64S (PcdPcieClock2, Clock[ 2].Blob);
> + PcdSet64S (PcdPcieClock3, Clock[ 3].Blob);
> + PcdSet64S (PcdPcieClock4, Clock[ 4].Blob);
> + PcdSet64S (PcdPcieClock5, Clock[ 5].Blob);
> + PcdSet64S (PcdPcieClock6, Clock[ 6].Blob);
> + PcdSet64S (PcdPcieClock7, Clock[ 7].Blob);
> + PcdSet64S (PcdPcieClock8, Clock[ 8].Blob);
> + PcdSet64S (PcdPcieClock9, Clock[ 9].Blob);
> + PcdSet64S (PcdPcieClock10, Clock[10].Blob);
> + PcdSet64S (PcdPcieClock11, Clock[11].Blob);
> + PcdSet64S (PcdPcieClock12, Clock[12].Blob);
> + PcdSet64S (PcdPcieClock13, Clock[13].Blob);
> + PcdSet64S (PcdPcieClock14, Clock[14].Blob);
> + PcdSet64S (PcdPcieClock15, Clock[15].Blob);
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Board USB related configuration init function for PEI pre-memory phase.
> +
> + @param[in] BoardId An unsigned integrer represent the board id.
> +
> + @retval EFI_SUCCESS The function completed successfully.
> +**/
> +EFI_STATUS
> +UsbConfigInit (
> + IN UINT16 BoardId
> + )
> +{
> + PCD32_BLOB *UsbPort20Afe;
> +
> + UsbPort20Afe = AllocateZeroPool (PCH_MAX_USB2_PORTS * sizeof
> (PCD32_BLOB));
> + ASSERT (UsbPort20Afe != NULL);
> + if (UsbPort20Afe == NULL) {
> + return EFI_OUT_OF_RESOURCES;
> + }
> +
> + //
> + // USB2 AFE settings.
> + //
> + UsbPort20Afe[0].Info.Petxiset = 7;
> + UsbPort20Afe[0].Info.Txiset = 5;
> + UsbPort20Afe[0].Info.Predeemp = 3;
> + UsbPort20Afe[0].Info.Pehalfbit = 0;
> +
> + UsbPort20Afe[1].Info.Petxiset = 7;
> + UsbPort20Afe[1].Info.Txiset = 5;
> + UsbPort20Afe[1].Info.Predeemp = 3;
> + UsbPort20Afe[1].Info.Pehalfbit = 0;
> +
> + UsbPort20Afe[2].Info.Petxiset = 7;
> + UsbPort20Afe[2].Info.Txiset = 5;
> + UsbPort20Afe[2].Info.Predeemp = 3;
> + UsbPort20Afe[2].Info.Pehalfbit = 0;
> +
> + UsbPort20Afe[3].Info.Petxiset = 7;
> + UsbPort20Afe[3].Info.Txiset = 5;
> + UsbPort20Afe[3].Info.Predeemp = 3;
> + UsbPort20Afe[3].Info.Pehalfbit = 0;
> +
> + UsbPort20Afe[4].Info.Petxiset = 7;
> + UsbPort20Afe[4].Info.Txiset = 5;
> + UsbPort20Afe[4].Info.Predeemp = 3;
> + UsbPort20Afe[4].Info.Pehalfbit = 0;
> +
> + UsbPort20Afe[5].Info.Petxiset = 7;
> + UsbPort20Afe[5].Info.Txiset = 5;
> + UsbPort20Afe[5].Info.Predeemp = 3;
> + UsbPort20Afe[5].Info.Pehalfbit = 0;
> +
> + UsbPort20Afe[6].Info.Petxiset = 7;
> + UsbPort20Afe[6].Info.Txiset = 5;
> + UsbPort20Afe[6].Info.Predeemp = 3;
> + UsbPort20Afe[6].Info.Pehalfbit = 0;
> +
> + UsbPort20Afe[7].Info.Petxiset = 7;
> + UsbPort20Afe[7].Info.Txiset = 5;
> + UsbPort20Afe[7].Info.Predeemp = 3;
> + UsbPort20Afe[7].Info.Pehalfbit = 0;
> +
> + UsbPort20Afe[8].Info.Petxiset = 7;
> + UsbPort20Afe[8].Info.Txiset = 5;
> + UsbPort20Afe[8].Info.Predeemp = 3;
> + UsbPort20Afe[8].Info.Pehalfbit = 0;
> +
> + UsbPort20Afe[9].Info.Petxiset = 7;
> + UsbPort20Afe[9].Info.Txiset = 5;
> + UsbPort20Afe[9].Info.Predeemp = 3;
> + UsbPort20Afe[9].Info.Pehalfbit = 0;
> +
> + //
> + // USB Port Over Current Pin
> + //
> + PcdSet8S (PcdUsb20OverCurrentPinPort0, UsbOverCurrentPinMax);
> + PcdSet8S (PcdUsb20OverCurrentPinPort1, UsbOverCurrentPinMax);
> + PcdSet8S (PcdUsb20OverCurrentPinPort2, UsbOverCurrentPinMax);
> + PcdSet8S (PcdUsb20OverCurrentPinPort3, UsbOverCurrentPinMax);
> + PcdSet8S (PcdUsb20OverCurrentPinPort4, UsbOverCurrentPinMax);
> + PcdSet8S (PcdUsb20OverCurrentPinPort5, UsbOverCurrentPinMax);
> + PcdSet8S (PcdUsb20OverCurrentPinPort6, UsbOverCurrentPinMax);
> + PcdSet8S (PcdUsb20OverCurrentPinPort7, UsbOverCurrentPinMax);
> + PcdSet8S (PcdUsb20OverCurrentPinPort8, UsbOverCurrentPinMax);
> + PcdSet8S (PcdUsb20OverCurrentPinPort9, UsbOverCurrentPinMax);
> + PcdSet8S (PcdUsb20OverCurrentPinPort10, UsbOverCurrentPinMax);
> + PcdSet8S (PcdUsb20OverCurrentPinPort11, UsbOverCurrentPinMax);
> + PcdSet8S (PcdUsb20OverCurrentPinPort12, UsbOverCurrentPinMax);
> + PcdSet8S (PcdUsb20OverCurrentPinPort13, UsbOverCurrentPinMax);
> + PcdSet8S (PcdUsb20OverCurrentPinPort14, UsbOverCurrentPinMax);
> + PcdSet8S (PcdUsb20OverCurrentPinPort15, UsbOverCurrentPinMax);
> +
> + PcdSet8S (PcdUsb30OverCurrentPinPort0, UsbOverCurrentPinMax);
> + PcdSet8S (PcdUsb30OverCurrentPinPort1, UsbOverCurrentPinMax);
> + PcdSet8S (PcdUsb30OverCurrentPinPort2, UsbOverCurrentPinMax);
> + PcdSet8S (PcdUsb30OverCurrentPinPort3, UsbOverCurrentPinMax);
> + PcdSet8S (PcdUsb30OverCurrentPinPort4, UsbOverCurrentPinMax);
> + PcdSet8S (PcdUsb30OverCurrentPinPort5, UsbOverCurrentPinMax);
> + PcdSet8S (PcdUsb30OverCurrentPinPort6, UsbOverCurrentPinMax);
> + PcdSet8S (PcdUsb30OverCurrentPinPort7, UsbOverCurrentPinMax);
> + PcdSet8S (PcdUsb30OverCurrentPinPort8, UsbOverCurrentPinMax);
> + PcdSet8S (PcdUsb30OverCurrentPinPort9, UsbOverCurrentPinMax);
> +
> + switch (BoardId) {
> + // LP PCH configuration
> + case BoardIdUpXtreme:
> + PcdSet8S (PcdUsb20OverCurrentPinPort0, UsbOverCurrentPin2);
> + PcdSet8S (PcdUsb20OverCurrentPinPort1, UsbOverCurrentPinSkip);
> + PcdSet8S (PcdUsb20OverCurrentPinPort2, UsbOverCurrentPin2);
> + PcdSet8S (PcdUsb20OverCurrentPinPort3, UsbOverCurrentPin2);
> + PcdSet8S (PcdUsb20OverCurrentPinPort4, UsbOverCurrentPin3);
> + PcdSet8S (PcdUsb20OverCurrentPinPort5, UsbOverCurrentPin3);
> + PcdSet8S (PcdUsb20OverCurrentPinPort6, UsbOverCurrentPin3);
> + PcdSet8S (PcdUsb20OverCurrentPinPort7, UsbOverCurrentPin3);
> + PcdSet8S (PcdUsb20OverCurrentPinPort8, UsbOverCurrentPinSkip);
> + PcdSet8S (PcdUsb20OverCurrentPinPort9, UsbOverCurrentPinSkip);
> + PcdSet8S (PcdUsb20OverCurrentPinPort10, UsbOverCurrentPinSkip);
> + PcdSet8S (PcdUsb20OverCurrentPinPort11, UsbOverCurrentPinSkip);
> + PcdSet8S (PcdUsb20OverCurrentPinPort12, UsbOverCurrentPinSkip);
> + PcdSet8S (PcdUsb20OverCurrentPinPort13, UsbOverCurrentPinSkip);
> + PcdSet8S (PcdUsb20OverCurrentPinPort14, UsbOverCurrentPinSkip);
> + PcdSet8S (PcdUsb20OverCurrentPinPort15, UsbOverCurrentPinSkip);
> +
> + PcdSet8S (PcdUsb30OverCurrentPinPort0, UsbOverCurrentPin2);
> + PcdSet8S (PcdUsb30OverCurrentPinPort1, UsbOverCurrentPinSkip);
> + PcdSet8S (PcdUsb30OverCurrentPinPort2, UsbOverCurrentPin2);
> + PcdSet8S (PcdUsb30OverCurrentPinPort3, UsbOverCurrentPin2);
> + PcdSet8S (PcdUsb30OverCurrentPinPort4, UsbOverCurrentPinSkip);
> + PcdSet8S (PcdUsb30OverCurrentPinPort5, UsbOverCurrentPinSkip);
> + PcdSet8S (PcdUsb30OverCurrentPinPort6, UsbOverCurrentPinSkip);
> + PcdSet8S (PcdUsb30OverCurrentPinPort7, UsbOverCurrentPinSkip);
> + PcdSet8S (PcdUsb30OverCurrentPinPort8, UsbOverCurrentPinSkip);
> + PcdSet8S (PcdUsb30OverCurrentPinPort9, UsbOverCurrentPinSkip);
> +
> + // USB2.0 AFE settings
> + UsbPort20Afe[0].Info.Petxiset = 6;
> + UsbPort20Afe[0].Info.Txiset = 0;
> + UsbPort20Afe[0].Info.Predeemp = 3;
> + UsbPort20Afe[0].Info.Pehalfbit = 0;
> +
> + UsbPort20Afe[1].Info.Petxiset = 6;
> + UsbPort20Afe[1].Info.Txiset = 0;
> + UsbPort20Afe[1].Info.Predeemp = 3;
> + UsbPort20Afe[1].Info.Pehalfbit = 0;
> +
> + UsbPort20Afe[2].Info.Petxiset = 6;
> + UsbPort20Afe[2].Info.Txiset = 0;
> + UsbPort20Afe[2].Info.Predeemp = 3;
> + UsbPort20Afe[2].Info.Pehalfbit = 0;
> +
> + UsbPort20Afe[3].Info.Petxiset = 6;
> + UsbPort20Afe[3].Info.Txiset = 0;
> + UsbPort20Afe[3].Info.Predeemp = 3;
> + UsbPort20Afe[3].Info.Pehalfbit = 0;
> +
> + UsbPort20Afe[4].Info.Petxiset = 6;
> + UsbPort20Afe[4].Info.Txiset = 0;
> + UsbPort20Afe[4].Info.Predeemp = 3;
> + UsbPort20Afe[4].Info.Pehalfbit = 0;
> +
> + UsbPort20Afe[5].Info.Petxiset = 6;
> + UsbPort20Afe[5].Info.Txiset = 0;
> + UsbPort20Afe[5].Info.Predeemp = 3;
> + UsbPort20Afe[5].Info.Pehalfbit = 0;
> +
> + UsbPort20Afe[6].Info.Petxiset = 6;
> + UsbPort20Afe[6].Info.Txiset = 0;
> + UsbPort20Afe[6].Info.Predeemp = 3;
> + UsbPort20Afe[6].Info.Pehalfbit = 0;
> +
> + UsbPort20Afe[7].Info.Petxiset = 6;
> + UsbPort20Afe[7].Info.Txiset = 0;
> + UsbPort20Afe[7].Info.Predeemp = 3;
> + UsbPort20Afe[7].Info.Pehalfbit = 0;
> +
> + UsbPort20Afe[8].Info.Petxiset = 6;
> + UsbPort20Afe[8].Info.Txiset = 0;
> + UsbPort20Afe[8].Info.Predeemp = 3;
> + UsbPort20Afe[8].Info.Pehalfbit = 0;
> +
> + UsbPort20Afe[9].Info.Petxiset = 6;
> + UsbPort20Afe[9].Info.Txiset = 0;
> + UsbPort20Afe[9].Info.Predeemp = 3;
> + UsbPort20Afe[9].Info.Pehalfbit = 0;
> + break;
> + }
> +
> + //
> + // Save USB2.0 AFE blobs
> + //
> + PcdSet32S (PcdUsb20Port0Afe, UsbPort20Afe[ 0].Blob);
> + PcdSet32S (PcdUsb20Port1Afe, UsbPort20Afe[ 1].Blob);
> + PcdSet32S (PcdUsb20Port2Afe, UsbPort20Afe[ 2].Blob);
> + PcdSet32S (PcdUsb20Port3Afe, UsbPort20Afe[ 3].Blob);
> + PcdSet32S (PcdUsb20Port4Afe, UsbPort20Afe[ 4].Blob);
> + PcdSet32S (PcdUsb20Port5Afe, UsbPort20Afe[ 5].Blob);
> + PcdSet32S (PcdUsb20Port6Afe, UsbPort20Afe[ 6].Blob);
> + PcdSet32S (PcdUsb20Port7Afe, UsbPort20Afe[ 7].Blob);
> + PcdSet32S (PcdUsb20Port8Afe, UsbPort20Afe[ 8].Blob);
> + PcdSet32S (PcdUsb20Port9Afe, UsbPort20Afe[ 9].Blob);
> + PcdSet32S (PcdUsb20Port10Afe, UsbPort20Afe[10].Blob);
> + PcdSet32S (PcdUsb20Port11Afe, UsbPort20Afe[11].Blob);
> + PcdSet32S (PcdUsb20Port12Afe, UsbPort20Afe[12].Blob);
> + PcdSet32S (PcdUsb20Port13Afe, UsbPort20Afe[13].Blob);
> + PcdSet32S (PcdUsb20Port14Afe, UsbPort20Afe[14].Blob);
> + PcdSet32S (PcdUsb20Port15Afe, UsbPort20Afe[15].Blob);
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Board GPIO Group Tier configuration init function for PEI pre-memory
> phase.
> +
> + @param[in] BoardId An unsigned integrer represent the board id.
> +
> + @retval EFI_SUCCESS The function completed successfully.
> +**/
> +EFI_STATUS
> +GpioGroupTierInit (
> + IN UINT16 BoardId
> + )
> +{
> + //
> + // GPIO Group Tier
> + //
> + switch (BoardId) {
> + case BoardIdUpXtreme:
> + PcdSet32S (PcdGpioGroupToGpeDw0,
> GPIO_CNL_LP_GROUP_GPP_G);
> + PcdSet32S (PcdGpioGroupToGpeDw1, GPIO_CNL_LP_GROUP_SPI);
> + PcdSet32S (PcdGpioGroupToGpeDw2, GPIO_CNL_LP_GROUP_GPP_E);
> + break;
> +
> + default:
> + PcdSet32S (PcdGpioGroupToGpeDw0, 0);
> + PcdSet32S (PcdGpioGroupToGpeDw1, 0);
> + PcdSet32S (PcdGpioGroupToGpeDw2, 0);
> + break;
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + GPIO init function for PEI pre-memory phase.
> +
> + @param[in] BoardId An unsigned integrer represent the board id.
> +
> + @retval EFI_SUCCESS The function completed successfully.
> +**/
> +EFI_STATUS
> +GpioTablePreMemInit (
> + IN UINT16 BoardId
> + )
> +{
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + PmConfig init function for PEI pre-memory phase.
> +
> + @param[in] BoardId An unsigned integrer represent the board id.
> +
> + @retval EFI_SUCCESS The function completed successfully.
> +**/
> +EFI_STATUS
> +PchPmConfigInit (
> + IN UINT16 BoardId
> + )
> +{
> + //
> + // Update PmCofig policy: output voltage of VCCPRIMCORE RAIL when
> SLP_S0# is asserted based on board HW design
> + // 1) Discete VR or Non Premium PMIC: 0.75V (PcdSlpS0Vm075VSupport)
> + // 2) Premium PMIC: runtime control for voltage
> (PcdSlpS0VmRuntimeControl)
> + // Only applys to board with PCH-LP. Board with Discrete PCH doesn't
> need this setting.
> + //
> + switch (BoardId) {
> + case BoardIdUpXtreme:
> + PcdSetBoolS (PcdSlpS0VmRuntimeControl, FALSE);
> + PcdSetBoolS (PcdSlpS0Vm070VSupport, FALSE);
> + PcdSetBoolS (PcdSlpS0Vm075VSupport, FALSE);
> + break;
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/
> BoardSaConfigPreMem.h
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/
> BoardSaConfigPreMem.h
> new file mode 100644
> index 0000000000..e0ca397139
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/
> BoardSaConfigPreMem.h
> @@ -0,0 +1,79 @@
> +/** @file
> + PEI Boards Configurations for PreMem phase.
> +
> +
> + Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _BOARD_SA_CONFIG_PRE_MEM_H_
> +#define _BOARD_SA_CONFIG_PRE_MEM_H_
> +
> +#include <ConfigBlock.h>
> +#include <ConfigBlock/MemoryConfig.h> // for MRC
> Configuration
> +#include <ConfigBlock/SwitchableGraphicsConfig.h> // for PCIE RTD3
> GPIO
> +#include <GpioPinsCnlLp.h> // for GPIO
> definition
> +#include <GpioPinsCnlH.h>
> +#include <SaAccess.h> // for Root Port
> number
> +#include <PchAccess.h> // for Root Port
> number
> +
> +//
> +// The following section contains board-specific CMD/CTL/CLK and DQ/DQS
> mapping, needed for LPDDR3/LPDDR4
> +//
> +
> +//
> +// DQByteMap[0] - ClkDQByteMap:
> +// If clock is per rank, program to [0xFF, 0xFF]
> +// If clock is shared by 2 ranks, program to [0xFF, 0] or [0, 0xFF]
> +// If clock is shared by 2 ranks but does not go to all bytes,
> +// Entry[i] defines which DQ bytes Group i services
> +// DQByteMap[1] - CmdNDQByteMap: Entry[0] is CmdN/CAA and Entry[1] is
> CmdN/CAB
> +// DQByteMap[2] - CmdSDQByteMap: Entry[0] is CmdS/CAA and Entry[1] is
> CmdS/CAB
> +// DQByteMap[3] - CkeDQByteMap : Entry[0] is CKE /CAA and Entry[1] is CKE
> /CAB
> +// For DDR, DQByteMap[3:1] = [0xFF, 0]
> +// DQByteMap[4] - CtlDQByteMap : Always program to [0xFF, 0] since we
> have 1 CTL / rank
> +// Variable only exists to make the code
> easier to use
> +// DQByteMap[5] - CmdVDQByteMap: Always program to [0xFF, 0] since we
> have 1 CA Vref
> +// Variable only exists to make the code
> easier to use
> +//
> +GLOBAL_REMOVE_IF_UNREFERENCED const UINT8
> mDqByteMapUpXtreme[2][6][2] = {
> + // Channel 0:
> + {
> + { 0x0F, 0xF0 }, // CLK0 goes to package 0 - Bytes[3:0], CLK1 goes to
> package 1 - Bytes[7:4]
> + { 0x00, 0xF0 }, // CmdN does not have CAA, CAB goes to Bytes[7:4]
> + { 0x0F, 0xF0 }, // CmdS CAA goes to Bytes[3:0], CmdS CAB goes to
> Byte[7:4]
> + { 0x0F, 0x00 }, // CKE CAA goes to Bytes[3:0], CKE does not have CAB
> + { 0xFF, 0x00 }, // CTL (CS) goes to all bytes
> + { 0xFF, 0x00 } // CA Vref is one for all bytes
> + },
> + // Channel 1:
> + {
> + { 0x33, 0xCC }, // CLK0 goes to package 0 - Bytes[3:0], CLK1 goes to
> package 1 - Bytes[7:4]
> + { 0x00, 0xCC }, // CmdN does not have CAA, CAB goes to Bytes[7:4]
> + { 0x33, 0xCC }, // CmdS CAA goes to Bytes[3:0], CmdS CAB goes to
> Byte[7:4]
> + { 0x33, 0x00 }, // CKE CAA goes to Bytes[3:0], CKE does not have CAB
> + { 0xFF, 0x00 }, // CTL (CS) goes to all bytes
> + { 0xFF, 0x00 } // CA Vref is one for all bytes
> + }
> +};
> +
> +//
> +// DQS byte swizzling between CPU and DRAM
> +//
> +GLOBAL_REMOVE_IF_UNREFERENCED const UINT8
> mDqsMapCpu2DramUpXtreme[2][8] = {
> + { 0, 1, 3, 2, 4, 5, 6, 7 }, // Channel 0
> + { 1, 0, 4, 5, 2, 3, 6, 7 } // Channel 1
> +};
> +
> +//
> +// Reference RCOMP resistors on motherboard
> +//
> +GLOBAL_REMOVE_IF_UNREFERENCED const UINT16
> RcompResistorUpXtreme[SA_MRC_MAX_RCOMP] = { 121, 75, 100 };
> +
> +//
> +// RCOMP target values for RdOdt, WrDS, WrDSCmd, WrDSCtl, WrDSClk
> +//
> +GLOBAL_REMOVE_IF_UNREFERENCED const UINT16
> RcompTargetUpXtreme[SA_MRC_MAX_RCOMP_TARGETS] = { 60, 26, 20, 20,
> 26 };
> +
> +#endif // _BOARD_SA_CONFIG_PRE_MEM_H_
> +
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/
> BoardSaInitPreMemLib.c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/
> BoardSaInitPreMemLib.c
> new file mode 100644
> index 0000000000..df57c83e1d
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/
> BoardSaInitPreMemLib.c
> @@ -0,0 +1,298 @@
> +/** @file
> + Source code for the board SA configuration Pcd init functions in Pre-Memory
> init phase.
> +
> +
> + Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include "BoardSaConfigPreMem.h"
> +#include "SaPolicyCommon.h"
> +#include "UpXtremeInit.h"
> +#include <PlatformBoardConfig.h>
> +#include <Library/CpuPlatformLib.h>
> +
> +//
> +// Display DDI settings for UP Xtreme
> +//
> +GLOBAL_REMOVE_IF_UNREFERENCED const UINT8
> mUpXtremeRowDisplayDdiConfig[9] = {
> + DdiPortAEdp, // DDI Port A Config : DdiPortADisabled = Disabled,
> DdiPortAEdp = eDP, DdiPortAMipiDsi = MIPI DSI
> + DdiHpdEnable, // DDI Port B HPD : DdiHpdDisable = Disable,
> DdiHpdEnable = Enable HPD
> + DdiHpdEnable, // DDI Port C HPD : DdiHpdDisable = Disable,
> DdiHpdEnable = Enable HPD
> + DdiHpdEnable, // DDI Port D HPD : DdiHpdDisable = Disable,
> DdiHpdEnable = Enable HPD
> + DdiHpdEnable, // DDI Port F HPD : DdiHpdDisable = Disable,
> DdiHpdEnable = Enable HPD
> + DdiDdcEnable, // DDI Port B DDC : DdiDisable = Disable,
> DdiDdcEnable = Enable DDC
> + DdiDdcEnable, // DDI Port C DDC : DdiDisable = Disable,
> DdiDdcEnable = Enable DDC
> + DdiDdcEnable, // DDI Port D DDC : DdiDisable = Disable,
> DdiDdcEnable = Enable DDC
> + DdiDisable // DDI Port F DDC : DdiDisable = Disable,
> DdiDdcEnable = Enable DDC
> +};
> +
> +/**
> + MRC configuration init function for PEI pre-memory phase.
> +
> + @param[in] BoardId An unsigned integer represent the
> board id.
> +
> + @retval EFI_SUCCESS The function completed successfully.
> +**/
> +EFI_STATUS
> +SaMiscConfigInit (
> + IN UINT16 BoardId
> + )
> +{
> + //
> + // UserBd
> + //
> + switch (BoardId) {
> + case BoardIdUpXtreme:
> + //
> + // Assign UserBd to 5 which is assigned to MrcInputs->BoardType
> btUser4 for ULT platforms.
> + // This is required to skip Memory voltage programming based on
> GPIO's in MRC
> + //
> + PcdSet8S (PcdSaMiscUserBd, 5); // MrcBoardType btUser4 for UP
> Xtreme (ULT/ULX/Modile Halo)
> + break;
> +
> + default:
> + // MiscPeiPreMemConfig.UserBd = 0 by default.
> + break;
> + }
> +
> + PcdSet16S (PcdSaDdrFreqLimit, 0);
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Board Memory Init related configuration init function for PEI pre-memory
> phase.
> +
> + @param[in] BoardId An unsigned integrer represent the board id.
> +
> + @retval EFI_SUCCESS The function completed successfully.
> +**/
> +EFI_STATUS
> +MrcConfigInit (
> + IN UINT16 BoardId
> + )
> +{
> + CPU_FAMILY CpuFamilyId;
> + UINT8 BomId;
> +
> + CpuFamilyId = GetCpuFamily();
> +
> + if (CpuFamilyId == EnumCpuCflDtHalo) {
> + PcdSetBoolS (PcdDualDimmPerChannelBoardType, TRUE);
> + } else {
> + PcdSetBoolS (PcdDualDimmPerChannelBoardType, FALSE);
> + }
> +
> + //
> + // Example policy for DIMM slots implementation boards:
> + // 1. Assign Smbus address of DIMMs and SpdData will be updated later
> + // by reading from DIMM SPD.
> + // 2. No need to apply hardcoded SpdData buffers here for such board.
> + //
> + // Whiskey Lake U RVP has removable DIMM slots.
> + // So assign all Smbus address of DIMMs and leave PcdMrcSpdData set
> to 0.
> + // Example:
> + // PcdMrcSpdData = 0
> + // PcdMrcSpdDataSize = 0
> + // PcdMrcSpdAddressTable0 = 0xA0
> + // PcdMrcSpdAddressTable1 = 0xA2
> + // PcdMrcSpdAddressTable2 = 0xA4
> + // PcdMrcSpdAddressTable3 = 0xA6
> + //
> + // If a board has soldered down memory. It should use the following
> settings.
> + // Example:
> + // PcdMrcSpdAddressTable0 = 0
> + // PcdMrcSpdAddressTable1 = 0
> + // PcdMrcSpdAddressTable2 = 0
> + // PcdMrcSpdAddressTable3 = 0
> + // PcdMrcSpdData = static data buffer
> + // PcdMrcSpdDataSize = sizeof (static data buffer)
> + //
> +
> + //
> + // SPD Address Table
> + //
> +
> + // BOMID [1:0]
> + // 0: 16G A & B CH
> + // 1: 8G A CH
> + // 2: 8G A & B CH
> + // 3: 4G A CH
> + BomId = PcdGet8(PcdBoardBomId);
> + DEBUG ((DEBUG_INFO, "Up Xtreme Bom ID 0x%x\n",BomId));
> +
> + if ((BomId & BIT1) == BIT1) {
> + PcdSet32S (PcdMrcSpdData, (UINTN) mUpXtremeSamsungDdr4Spd);
> + PcdSet16S (PcdMrcSpdDataSize, mUpXtremeSamsungDdr4SpdSize);
> + DEBUG ((DEBUG_INFO, "Using Xtreme SPD Samsung Ddr4\n"));
> + } else {
> + PcdSet32S (PcdMrcSpdData, (UINTN) mUpXtremeSkhynixDdr4Spd);
> + PcdSet16S (PcdMrcSpdDataSize, mUpXtremeSkhynixDdr4SpdSize);
> + DEBUG ((DEBUG_INFO, "Using Xtreme SPD Skhynix Ddr4\n"));
> + }
> +
> + PcdSet8S (PcdMrcSpdAddressTable0, 0);
> + PcdSet8S (PcdMrcSpdAddressTable1, 0);
> + PcdSet8S (PcdMrcSpdAddressTable2, 0);
> + PcdSet8S (PcdMrcSpdAddressTable3, 0);
> +
> + //
> + // DRAM SPD Data & related configuration
> + //
> + PcdSet32S (PcdMrcDqByteMap, (UINTN) mDqByteMapUpXtreme);
> + PcdSet16S (PcdMrcDqByteMapSize, sizeof (mDqByteMapUpXtreme));
> + PcdSet32S (PcdMrcDqsMapCpu2Dram, (UINTN)
> mDqsMapCpu2DramUpXtreme);
> + PcdSet16S (PcdMrcDqsMapCpu2DramSize, sizeof
> (mDqsMapCpu2DramUpXtreme));
> +
> + switch (BoardId) {
> +
> + case BoardIdUpXtreme:
> + PcdSet32S (PcdMrcRcompResistor, (UINTN)
> RcompResistorUpXtreme);
> + PcdSet32S (PcdMrcRcompTarget, (UINTN) RcompTargetUpXtreme);
> + PcdSetBoolS (PcdMrcDqPinsInterleavedControl, FALSE);
> + PcdSetBoolS (PcdMrcDqPinsInterleaved, FALSE);
> + break;
> +
> + default:
> + break;
> + }
> +
> + //
> + // CA Vref routing: board-dependent
> + // 0 - VREF_CA goes to both CH_A and CH_B (LPDDR3/DDR3L)
> + // 1 - VREF_CA to CH_A, VREF_DQ_A to CH_B (should not be used)
> + // 2 - VREF_CA to CH_A, VREF_DQ_B to CH_B (DDR4)
> + //
> + switch (BoardId) {
> + case BoardIdUpXtreme:
> + PcdSet8S (PcdMrcCaVrefConfig, 2); // DDR4 boards
> + break;
> +
> + default:
> + PcdSet8S (PcdMrcCaVrefConfig, 0); // All DDR3L/LPDDR3/LPDDR4
> boards
> + break;
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Board SA related GPIO configuration init function for PEI pre-memory
> phase.
> +
> + @param[in] BoardId An unsigned integer represent the board id.
> +
> + @retval EFI_SUCCESS The function completed successfully.
> +**/
> +EFI_STATUS
> +SaGpioConfigInit (
> + IN UINT16 BoardId
> + )
> +{
> + //
> + // Update board's GPIO for PEG slot reset
> + //
> + PcdSetBoolS (PcdPegGpioResetControl, TRUE);
> + PcdSetBoolS (PcdPegGpioResetSupoort, FALSE);
> + PcdSet32S (PcdPeg0ResetGpioPad, 0);
> + PcdSetBoolS (PcdPeg0ResetGpioActive, FALSE);
> + PcdSet32S (PcdPeg3ResetGpioPad, 0);
> + PcdSetBoolS (PcdPeg3ResetGpioActive, FALSE);
> +
> + //
> + // PCIE RTD3 GPIO
> + //
> + switch (BoardId) {
> + // todo for UP Xtreme
> + case BoardIdWhiskeyLakeRvp:
> + PcdSet8S(PcdRootPortIndex, 4);
> + PcdSet8S (PcdPcie0GpioSupport, PchGpio);
> + PcdSet32S (PcdPcie0WakeGpioNo, 0);
> + PcdSet8S (PcdPcie0HoldRstExpanderNo, 0);
> + PcdSet32S (PcdPcie0HoldRstGpioNo, GPIO_CNL_LP_GPP_C15);
> + PcdSetBoolS (PcdPcie0HoldRstActive, FALSE);
> + PcdSet8S (PcdPcie0PwrEnableExpanderNo, 0);
> + PcdSet32S (PcdPcie0PwrEnableGpioNo, GPIO_CNL_LP_GPP_C14);
> + PcdSetBoolS (PcdPcie0PwrEnableActive, FALSE);
> +
> + PcdSet8S (PcdPcie1GpioSupport, NotSupported);
> + PcdSet32S (PcdPcie1WakeGpioNo, 0);
> + PcdSet8S (PcdPcie1HoldRstExpanderNo, 0);
> + PcdSet32S (PcdPcie1HoldRstGpioNo, 0);
> + PcdSetBoolS (PcdPcie1HoldRstActive, FALSE);
> + PcdSet8S (PcdPcie1PwrEnableExpanderNo, 0);
> + PcdSet32S (PcdPcie1PwrEnableGpioNo, 0);
> + PcdSetBoolS (PcdPcie1PwrEnableActive, FALSE);
> +
> + PcdSet8S (PcdPcie2GpioSupport, NotSupported);
> + PcdSet32S (PcdPcie2WakeGpioNo, 0);
> + PcdSet8S (PcdPcie2HoldRstExpanderNo, 0);
> + PcdSet32S (PcdPcie2HoldRstGpioNo, 0);
> + PcdSetBoolS (PcdPcie2HoldRstActive, FALSE);
> + PcdSet8S (PcdPcie2PwrEnableExpanderNo, 0);
> + PcdSet32S (PcdPcie2PwrEnableGpioNo, 0);
> + PcdSetBoolS (PcdPcie2PwrEnableActive, FALSE);
> + break;
> +
> + default:
> + PcdSet8S(PcdRootPortIndex, 0xFF);
> + PcdSet8S (PcdPcie0GpioSupport, NotSupported);
> + PcdSet32S (PcdPcie0WakeGpioNo, 0);
> + PcdSet8S (PcdPcie0HoldRstExpanderNo, 0);
> + PcdSet32S (PcdPcie0HoldRstGpioNo, 0);
> + PcdSetBoolS (PcdPcie0HoldRstActive, FALSE);
> + PcdSet8S (PcdPcie0PwrEnableExpanderNo, 0);
> + PcdSet32S (PcdPcie0PwrEnableGpioNo, 0);
> + PcdSetBoolS (PcdPcie0PwrEnableActive, FALSE);
> +
> + PcdSet8S (PcdPcie1GpioSupport, NotSupported);
> + PcdSet32S (PcdPcie1WakeGpioNo, 0);
> + PcdSet8S (PcdPcie1HoldRstExpanderNo, 0);
> + PcdSet32S (PcdPcie1HoldRstGpioNo, 0);
> + PcdSetBoolS (PcdPcie1HoldRstActive, FALSE);
> + PcdSet8S (PcdPcie1PwrEnableExpanderNo, 0);
> + PcdSet32S (PcdPcie1PwrEnableGpioNo, 0);
> + PcdSetBoolS (PcdPcie1PwrEnableActive, FALSE);
> +
> + PcdSet8S (PcdPcie2GpioSupport, NotSupported);
> + PcdSet32S (PcdPcie2WakeGpioNo, 0);
> + PcdSet8S (PcdPcie2HoldRstExpanderNo, 0);
> + PcdSet32S (PcdPcie2HoldRstGpioNo, 0);
> + PcdSetBoolS (PcdPcie2HoldRstActive, FALSE);
> + PcdSet8S (PcdPcie2PwrEnableExpanderNo, 0);
> + PcdSet32S (PcdPcie2PwrEnableGpioNo, 0);
> + PcdSetBoolS (PcdPcie2PwrEnableActive, FALSE);
> + break;
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + SA Display DDI configuration init function for PEI pre-memory phase.
> +
> + @param[in] BoardId An unsigned integer represent the board
> id.
> +
> + @retval EFI_SUCCESS The function completed successfully.
> +**/
> +EFI_STATUS
> +SaDisplayConfigInit (
> + IN UINT16 BoardId
> + )
> +{
> + //
> + // Update Display DDI Config
> + //
> + switch (BoardId) {
> + case BoardIdUpXtreme:
> + PcdSet32S (PcdSaDisplayConfigTable, (UINTN)
> mUpXtremeRowDisplayDdiConfig);
> + PcdSet16S (PcdSaDisplayConfigTableSize, sizeof
> (mUpXtremeRowDisplayDdiConfig));
> + break;
> +
> + default:
> + break;
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/
> GpioTableDefault.c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/
> GpioTableDefault.c
> new file mode 100644
> index 0000000000..9cc8b50023
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/
> GpioTableDefault.c
> @@ -0,0 +1,213 @@
> +/** @file
> + GPIO definition table
> +
> + Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include <GpioPinsCnlLp.h>
> +#include <Library/GpioLib.h>
> +#include <GpioConfig.h>
> +
> +#define END_OF_GPIO_TABLE 0xFFFFFFFF
> +
> +//
> +// CNL U DRR4 Board GPIO table configuration is used as default
> +//
> +GPIO_INIT_CONFIG mGpioTableDefault[] =
> +{
> +// Pmode, GPI_IS, GpioDir, GPIOTxState,
> RxEvCfg, GPIRoutConfig, PadRstCfg, Term,
> + //{GPIO_CNL_LP_GPP_A0, { GpioPadModeNotUsed,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioHostDeepReset, GpioTermNone }},
> + //{GPIO_CNL_LP_GPP_A1, { GpioPadModeNative2,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioHostDeepReset, GpioTermNone }}, //eSPI_IO_0
> + //{GPIO_CNL_LP_GPP_A2, { GpioPadModeNative2,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioHostDeepReset, GpioTermNone }}, //eSPI_IO_1
> + //{GPIO_CNL_LP_GPP_A3, { GpioPadModeNative2,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioHostDeepReset, GpioTermNone }}, //eSPI_IO_2
> + //{GPIO_CNL_LP_GPP_A4, { GpioPadModeNative2,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioHostDeepReset, GpioTermNone }}, //eSPI_IO_2
> + //{GPIO_CNL_LP_GPP_A5, { GpioPadModeNative2,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioHostDeepReset, GpioTermNone }}, //eSPI_CSB
> + //{GPIO_CNL_LP_GPP_A6, { GpioPadModeNotUsed,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioHostDeepReset, GpioTermNone }}, //GPPC_A6_SERIRQ
> + {GPIO_CNL_LP_GPP_A7, { GpioPadModeGpio, GpioHostOwnAcpi,
> GpioDirIn, GpioOutDefault, GpioIntEdge | GpioIntSci,
> GpioHostDeepReset, GpioTermWpu20K, GpioPadConfigUnlock }},
> //SPI_TPM_INT_N
> + //{GPIO_CNL_LP_GPP_A8, { GpioPadModeNotUsed,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioHostDeepReset, GpioTermNone }},
> + //(Default HW) {GPIO_CNL_LP_GPP_A9, { GpioPadModeNative2,
> GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioHostDeepReset, GpioTermNone }}, //eSPI_CLK
> + //{GPIO_CNL_LP_GPP_A10, { GpioPadModeNotUsed,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioHostDeepReset, GpioTermNone }},
> + {GPIO_CNL_LP_GPP_A11, { GpioPadModeGpio, GpioHostOwnAcpi,
> GpioDirInInv, GpioOutDefault, GpioIntLevel|GpioIntSci,
> GpioHostDeepReset, GpioTermWpu20K, GpioPadConfigUnlock }},
> //WWAN_WAKE_N
> + // (RC control) {GPIO_CNL_LP_GPP_A12, { GpioPadModeNative2,
> GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //SLATEMODE_HALLOUT
> + {GPIO_CNL_LP_GPP_A13, { GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset,
> GpioTermNone } }, //DGPU_SEL_SLOT1
> + //(Default HW) {GPIO_CNL_LP_GPP_A14, { GpioPadModeNative2,
> GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioHostDeepReset, GpioTermNone }}, //eSPI_Reset
> + {GPIO_CNL_LP_GPP_A15, { GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset,
> GpioTermNone }}, //SPKR_PD_N
> + {GPIO_CNL_LP_GPP_A16, { GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutLow, GpioIntDefault, GpioPlatformReset,
> GpioTermNone }}, //WFCAM_PWREN
> + //(RC control) {GPIO_CNL_LP_GPP_A17, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirIn, GpioOutDefault, GpioIntDefault,
> GpioHostDeepReset, GpioTermNone }}, //SD_PWREN
> + //(RC control) {GPIO_CNL_LP_GPP_A18, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirIn, GpioOutDefault, GpioIntDefault,
> GpioHostDeepReset, GpioTermWpu20K }}, //ACCEL_INT
> + //(RC control) {GPIO_CNL_LP_GPP_A19, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirIn, GpioOutDefault, GpioIntDefault,
> GpioHostDeepReset, GpioTermWpu20K }}, //ALS_INT
> + //(RC control) {GPIO_CNL_LP_GPP_A20, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirIn, GpioOutDefault, GpioIntDefault,
> GpioHostDeepReset, GpioTermWpu20K }}, //HUMAN_PRESENCE_INT
> + //(RC control) {GPIO_CNL_LP_GPP_A21, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirIn, GpioOutDefault, GpioIntDefault,
> GpioHostDeepReset, GpioTermWpu20K }}, //HALL_SENSOR_INT
> + //(RC control) {GPIO_CNL_LP_GPP_A22, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //IVCAM_WAKE
> + //(RC control) {GPIO_CNL_LP_GPP_A23, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirIn, GpioOutDefault, GpioIntDefault,
> GpioHostDeepReset, GpioTermWpu20K }}, //SHARED_INT
> + //(Not used) {GPIO_CNL_LP_GPP_B0, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirOut, GpioOutDefault, GpioIntDis,
> GpioResetDefault, GpioTermNone }}, //CORE_VID0
> + //(Not used) {GPIO_CNL_LP_GPP_B1, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirOut, GpioOutDefault, GpioIntDis,
> GpioResetDefault, GpioTermNone }}, //CORE_VID0
> + {GPIO_CNL_LP_GPP_B2, { GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset,
> GpioTermNone, GpioPadConfigUnlock | GpioOutputStateUnlock } },
> //BT_UART_WAKE
> + {GPIO_CNL_LP_GPP_B3, { GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioPlatformReset,
> GpioTermNone, GpioPadConfigUnlock | GpioOutputStateUnlock }},
> //FORCE_PAD_INT
> + {GPIO_CNL_LP_GPP_B4, { GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone ,
> GpioPadConfigUnlock} }, //BT_DISABLE_N
> + //(RC control) {GPIO_CNL_LP_GPP_B5, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //WWAN_CLK_REQ
> + //(RC control) {GPIO_CNL_LP_GPP_B6, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //PCIE_NAND_CLK_REQ
> + //(RC control) {GPIO_CNL_LP_GPP_B7, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //LAN_CLK_REQ
> + //(RC control) {GPIO_CNL_LP_GPP_B8, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //WLAN_CLK_REQ
> + //(RC control) {GPIO_CNL_LP_GPP_B9, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //PCIE_SLOT1_CLK_REQ
> + //(RC control) {GPIO_CNL_LP_GPP_B10, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //PCIE_SLOT2_CLK_REQ
> + {GPIO_CNL_LP_GPP_B11, { GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset,
> GpioTermNone }},
> + //(Default HW) {GPIO_CNL_LP_GPP_B12, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioResetDefault, GpioTermNone }}, //PM_SLP_S0_N
> + //(Default HW) {GPIO_CNL_LP_GPP_B13, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioResetDefault, GpioTermNone }}, //PLT_RST_N
> + {GPIO_CNL_LP_GPP_B14, { GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset,
> GpioTermNone}}, //TCH_PNL_PWR_EN
> + //(CSME Pad) {GPIO_CNL_LP_GPP_B15, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis,
> GpioPlatformReset, GpioTermNone }}, //NFC_DFU
> + { GPIO_CNL_LP_GPP_B16, { GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioPlatformReset,
> GpioTermNone, GpioPadConfigUnlock } }, //FPS_INT_N
> + { GPIO_CNL_LP_GPP_B17, { GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone,
> GpioPadConfigUnlock} }, //FPS_RESET_N
> + {GPIO_CNL_LP_GPP_B18, { GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone }},
> //TBT_CIO_PWR_EN
> + //(RC control) {GPIO_CNL_LP_GPP_B19, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //GSPI1_CS_FPS
> + //(RC control) {GPIO_CNL_LP_GPP_B20, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //GSPI1_CLK_FPS
> + //(RC control) {GPIO_CNL_LP_GPP_B21, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //GSPI1_MISO_FPS
> + //(RC control) {GPIO_CNL_LP_GPP_B22, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //GSPI1_MOSI_FPS
> + {GPIO_CNL_LP_GPP_B23, { GpioPadModeGpio, GpioHostOwnDefault,
> GpioDirOut, GpioOutHigh, GpioIntDefault, GpioHostDeepReset,
> GpioTermNone}}, //EC_SLP_S0_CS_N
> + //(RC control) {GPIO_CNL_LP_GPP_C0, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault,
> GpioHostDeepReset, GpioTermNone }}, //SMB_CLK
> + //(RC control) {GPIO_CNL_LP_GPP_C1, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault,
> GpioHostDeepReset, GpioTermNone }}, //SMB_DATA
> + {GPIO_CNL_LP_GPP_C2, { GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset,
> GpioTermNone }}, //WIFI_RF_KILL_N
> + //(CSME Pad) {GPIO_CNL_LP_GPP_C3, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault,
> GpioHostDeepReset, GpioTermNone }}, //SML0_CLK
> + //(CSME Pad) {GPIO_CNL_LP_GPP_C4, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault,
> GpioHostDeepReset, GpioTermNone }}, //SML0_DATA
> + {GPIO_CNL_LP_GPP_C5, { GpioPadModeGpio, GpioHostOwnAcpi,
> GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci,
> GpioHostDeepReset, GpioTermNone, GpioPadConfigUnlock }},
> //WIFI_WAKE_N
> + //(Not used) {GPIO_CNL_LP_GPP_C6, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault,
> GpioHostDeepReset, GpioTermNone }},
> + //(Not used) {GPIO_CNL_LP_GPP_C7, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault,
> GpioHostDeepReset, GpioTermNone }},
> + { GPIO_CNL_LP_GPP_C8, { GpioPadModeGpio, GpioHostOwnAcpi,
> GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntApic,
> GpioHostDeepReset, GpioTermWpu20K } }, //CODEC_INT_N
> + { GPIO_CNL_LP_GPP_C9, { GpioPadModeGpio, GpioHostOwnAcpi,
> GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntSci, GpioPlatformReset,
> GpioTermWpu20K, GpioPadConfigUnlock }}, //TBT_CIO_PLUG_EVENT_N
> + {GPIO_CNL_LP_GPP_C10, { GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutLow, GpioIntDefault, GpioPlatformReset,
> GpioTermNone}}, //TBT_FORCE_PWR
> + {GPIO_CNL_LP_GPP_C11, { GpioPadModeGpio, GpioHostOwnAcpi,
> GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioHostDeepReset,
> GpioTermWpu20K, GpioPadConfigUnlock } }, //IVCAM_WAKE_N
> + {GPIO_CNL_LP_GPP_C12, { GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutLow, GpioIntDis, GpioPlatformReset,
> GpioTermNone}}, //PCIE_NAND_RST_N
> + {GPIO_CNL_LP_GPP_C13, { GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset,
> GpioTermNone}}, //PCIE_NAND_PWREN_N
> + {GPIO_CNL_LP_GPP_C14, { GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutLow, GpioIntDis, GpioPlatformReset,
> GpioTermNone}}, //SLOT1_PWREN_N
> + {GPIO_CNL_LP_GPP_C15, { GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset,
> GpioTermNone}}, //SLOT1_RST_N
> + //(RC control) {GPIO_CNL_LP_GPP_C16, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //I2C0_SDA
> + //(RC control) {GPIO_CNL_LP_GPP_C17, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //I2C0_SCL
> + //(RC control) {GPIO_CNL_LP_GPP_C18, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //I2C1_SDA
> + //(RC control) {GPIO_CNL_LP_GPP_C19, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //I2C1_SCL
> + //(RC control) {GPIO_CNL_LP_GPP_C20, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //UART2_RXD
> + //(RC control) {GPIO_CNL_LP_GPP_C21, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //UART2_TXD
> + //(RC control) {GPIO_CNL_LP_GPP_C22, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //UART2_RTS
> + //(RC control) {GPIO_CNL_LP_GPP_C23, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //UART2_CTS
> + //(CSME Pad) {GPIO_CNL_LP_GPP_D0, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //SPI1_TCH_PNL_CS0_N
> + //(CSME Pad) {GPIO_CNL_LP_GPP_D1, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //SPI1_TCH_PNL_CLK_N
> + //(CSME Pad) {GPIO_CNL_LP_GPP_D2, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //SPI1_TCH_PNL_MISO
> + //(CSME Pad) {GPIO_CNL_LP_GPP_D3, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //SPI1_TCH_PNL_MOSI
> + //(RC control) {GPIO_CNL_LP_GPP_D4, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //IMGCLKOUT
> + //(RC control) {GPIO_CNL_LP_GPP_D5, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //ISH_I2C0_SDA
> + //(RC control) {GPIO_CNL_LP_GPP_D6, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //ISH_I2C0_SCL
> + //(RC control) {GPIO_CNL_LP_GPP_D7, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //ISH_I2C1_SDA
> + //(RC control) {GPIO_CNL_LP_GPP_D8, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //ISH_I2C1_SCL
> + {GPIO_CNL_LP_GPP_D9, { GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset,
> GpioTermNone }}, //TCH_PNL2_RST_N
> + {GPIO_CNL_LP_GPP_D10, { GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirIn, GpioOutDefault, GpioIntEdge | GpioIntApic,
> GpioPlatformReset, GpioTermNone, GpioPadConfigUnlock }},
> //TCH_PNL2_INT_N
> + {GPIO_CNL_LP_GPP_D11, { GpioPadModeGpio, GpioHostOwnAcpi,
> GpioDirInInv , GpioOutDefault, GpioIntLevel| GpioIntSci,
> GpioPlatformReset, GpioTermWpu20K, GpioPadConfigUnlock }},
> //SLOT1_WAKE_N
> + //(CSME Pad) {GPIO_CNL_LP_GPP_D12, { GpioPadModeGpio,
> GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //NFC_RST_N
> + {GPIO_CNL_LP_GPP_D13, { GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutLow, GpioIntDis, GpioResumeReset,
> GpioTermNone }}, //WWAN_PWREN
> + {GPIO_CNL_LP_GPP_D14, { GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset,
> GpioTermNone }}, //TCH_PNL_RST_N
> + //(CSME Pad) {GPIO_CNL_LP_GPP_D15, { GpioPadModeGpio,
> GpioHostOwnGpio, GpioDirIn, GpioOutDefault,
> GpioIntLevel|GpioIntDefault, GpioPlatformReset, GpioTermNone }},
> //NFC_INT_N
> + {GPIO_CNL_LP_GPP_D16, { GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirIn, GpioOutDefault, GpioIntLevel|GpioIntSci,
> GpioHostDeepReset, GpioTermNone, GpioPadConfigUnlock }},
> //WIGIG_WAKE_N
> + //(RC control) {GPIO_CNL_LP_GPP_D17, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioHostDeepReset, GpioTermNone }}, //DMIC_CLK_1
> + //(RC control) {GPIO_CNL_LP_GPP_D18, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioHostDeepReset, GpioTermNone }}, //DMIC_DATA_1
> + //(RC control) {GPIO_CNL_LP_GPP_D19, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioHostDeepReset, GpioTermNone }}, //DMIC_CLK_0
> + //(RC control) {GPIO_CNL_LP_GPP_D20, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioHostDeepReset, GpioTermNone }}, //DMIC_DATA_0
> + {GPIO_CNL_LP_GPP_D21, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //SPI1_TCH_PNL_IO2
> + {GPIO_CNL_LP_GPP_D22, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //SPI1_TCH_PNL_IO3
> + //(RC control) {GPIO_CNL_LP_GPP_D23, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirOut, GpioOutDefault, GpioIntDefault,
> GpioHostDeepReset, GpioTermNone }}, //SSP_MCLK
> + //(Not used) {GPIO_CNL_LP_GPP_E0, { GpioPadModeGpio,
> GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel|GpioIntSci,
> GpioPlatformReset, GpioTermWpu20K }}, //Reserved for SATA/PCIE detect
> + //(RC control) {GPIO_CNL_LP_GPP_E1, { GpioPadModeNative1,
> GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel|GpioIntSci,
> GpioPlatformReset, GpioTermNone }}, //M.2_SSD_DET
> + {GPIO_CNL_LP_GPP_E2, { GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirIn, GpioOutDefault, GpioIntDis, GpioPlatformReset,
> GpioTermWpu20K}}, //Reserved for SATA HP val
> + {GPIO_CNL_LP_GPP_E3, { GpioPadModeGpio, GpioHostOwnAcpi,
> GpioDirIn, GpioOutDefault, GpioIntEdge|GpioIntSmi, GpioPlatformReset,
> GpioTermNone}}, //EC_SMI_N
> + {GPIO_CNL_LP_GPP_E4, { GpioPadModeGpio, GpioHostOwnAcpi,
> GpioDirIn, GpioOutDefault, GpioIntLevel|GpioIntSci, GpioPlatformReset,
> GpioTermNone, GpioPadConfigUnlock }}, //DGPU_PWROK
> + //(RC control) {GPIO_CNL_LP_GPP_E5, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirIn, GpioOutDefault,
> GpioIntLevel|GpioIntDefault, GpioPlatformReset, GpioTermNone }},
> //SSD_DEVSLP
> + //(RC control) {GPIO_CNL_LP_GPP_E6, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirIn, GpioOutDefault,
> GpioIntLevel|GpioIntDefault, GpioPlatformReset, GpioTermNone }},
> //HDD_DEVSLP
> + {GPIO_CNL_LP_GPP_E7, { GpioPadModeGpio, GpioHostOwnDefault,
> GpioDirIn, GpioOutDefault, GpioIntEdge|GpioIntDefault,
> GpioPlatformReset, GpioTermNone, GpioPadConfigUnlock }},
> //TCH_PNL_INT_N
> + //(RC control) {GPIO_CNL_LP_GPP_E8, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //SATA_LED_N
> + //(RC control) {GPIO_CNL_LP_GPP_E9, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirIn, GpioOutDefault, GpioIntDefault,
> GpioHostDeepReset, GpioTermNone }}, //BSSB_CLK
> + //(RC control) {GPIO_CNL_LP_GPP_E10, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirIn, GpioOutDefault, GpioIntDefault,
> GpioHostDeepReset, GpioTermNone }}, //BSSB_DI
> + //(RC control) {GPIO_CNL_LP_GPP_E11, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioHostDeepReset, GpioTermNone }}, //USB_OC_2
> + //(RC control) {GPIO_CNL_LP_GPP_E12, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioHostDeepReset, GpioTermNone }}, //USB_OC_3
> + //(RC control) {GPIO_CNL_LP_GPP_E13, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //DDI1_HPD
> + //(RC control) {GPIO_CNL_LP_GPP_E14, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //DDI2_HPD_EC
> + //(RC control) {GPIO_CNL_LP_GPP_E15, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //DDI3_HPD
> + //(RC control) {GPIO_CNL_LP_GPP_E16, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //DDI4_HPD
> + //(RC control) {GPIO_CNL_LP_GPP_E17, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //EDP_HPD
> + //(RC control) {GPIO_CNL_LP_GPP_E18, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //DDI1_CTRL_CLK
> + //(RC control) {GPIO_CNL_LP_GPP_E19, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //DDI1_CTRL_DATA
> + //(RC control) {GPIO_CNL_LP_GPP_E20, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //DDI2_CTRL_CLK
> + //(RC control) {GPIO_CNL_LP_GPP_E21, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //DDI2_CTRL_DATA
> + //(RC control) {GPIO_CNL_LP_GPP_E22, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //DDI3_CTRL_CLK
> + //(RC control) {GPIO_CNL_LP_GPP_E23, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //DDI3_CTRL_DATA
> + //(Not used){GPIO_CNL_LP_GPP_F0, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirIn, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //GPP_F0_COEX3
> + {GPIO_CNL_LP_GPP_F1, { GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutHigh, GpioIntDis, GpioResumeReset,
> GpioTermWpu20K }}, //WWAN_RST_N
> + {GPIO_CNL_LP_GPP_F2, { GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset,
> GpioTermNone }}, //SATA_HDD_PWREN
> + {GPIO_CNL_LP_GPP_F3, { GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutLow, GpioIntDefault, GpioPlatformReset,
> GpioTermNone }}, //WF_CLK_EN
> + //(RC control) {GPIO_CNL_LP_GPP_F4, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioResetDefault, GpioTermNone }}, //CNV_BRI_DT_UART0_RTSB
> + //(RC control) {GPIO_CNL_LP_GPP_F5, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioResetDefault, GpioTermNone }}, //CNV_BRI_RSP_UART0_RXD
> + //(RC control) {GPIO_CNL_LP_GPP_F6, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioResetDefault, GpioTermNone }}, //CNV_RGI_DT_UART0_TXD
> + //(RC control) {GPIO_CNL_LP_GPP_F7, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioResetDefault, GpioTermNone }}, //CNV_RGI_RSP_UART0_CTSB
> + {GPIO_CNL_LP_GPP_F8, { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault,
> GpioTermNone }}, //CNV_MFUART2_RXD
> + {GPIO_CNL_LP_GPP_F9, { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault,
> GpioTermNone }}, //CNV_MFUART2_TXD
> +
> + //Also need to assign same GPIO pin to PcdRecoveryModeGpio which will
> be used at IsRecoveryMode()
> + {GPIO_CNL_LP_GPP_F10, { GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirIn, GpioOutDefault, GpioIntDefault, GpioPlatformReset,
> GpioTermNone}}, //BIOS_REC
> +
> + //(RC control) {GPIO_CNL_LP_GPP_F11, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //GPP_F11_EMMC_CMD
> + //(RC control) {GPIO_CNL_LP_GPP_F12, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //GPP_F12_EMMC_DATA0
> + //(RC control) {GPIO_CNL_LP_GPP_F13, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //GPP_F13_EMMC_DATA1
> + //(RC control) {GPIO_CNL_LP_GPP_F14, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //GPP_F14_EMMC_DATA2
> + //(RC control) {GPIO_CNL_LP_GPP_F15, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //GPP_F15_EMMC_DATA3
> + //(RC control) {GPIO_CNL_LP_GPP_F16, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //GPP_F16_EMMC_DATA4
> + //(RC control) {GPIO_CNL_LP_GPP_F17, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //GPP_F17_EMMC_DATA5
> + //(RC control) {GPIO_CNL_LP_GPP_F18, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //GPP_F18_EMMC_DATA6
> + //(RC control) {GPIO_CNL_LP_GPP_F19, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //GPP_F19_EMMC_DATA7
> + //(RC control) {GPIO_CNL_LP_GPP_F20, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //GPP_F20_EMMC_RCLK
> + //(RC control) {GPIO_CNL_LP_GPP_F21, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //GPP_F21_EMMC_CLK
> + //(RC control) {GPIO_CNL_LP_GPP_F22, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //GPP_F22_EMMC_RESETB
> + //{GPIO_CNL_LP_GPP_F23, { GpioPadModeNotUsed,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioResetDefault, GpioTermNone }}, //GPP_F_23
> + //(RC control) {GPIO_CNL_LP_GPP_G0, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioResetDefault, GpioTermNative }}, //GPP_G_0_SD3_CMD
> + //(RC control) {GPIO_CNL_LP_GPP_G1, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioResetDefault, GpioTermNative }}, //GPP_G_1_SD3_D0_SD4_RCLK_P
> + //(RC control) {GPIO_CNL_LP_GPP_G2, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioResetDefault, GpioTermNative }}, //GPP_G_2_SD3_D1_SD4_RCLK_N
> + //(RC control) {GPIO_CNL_LP_GPP_G3, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioResetDefault, GpioTermNative }}, //GPP_G_3_SD3_D2
> + //(RC control) {GPIO_CNL_LP_GPP_G4, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioResetDefault, GpioTermNative }}, //GPP_G_4_SD3_D3
> + {GPIO_CNL_LP_GPP_G5, { GpioHardwareDefault, GpioHostOwnDefault,
> GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault,
> GpioTermWpu20K }}, //GPP_G_5_SD3_CDB
> + //(Default HW) {GPIO_CNL_LP_GPP_G6, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioResetDefault, GpioTermNone }}, //GPP_G_6_SD3_CLK
> + {GPIO_CNL_LP_GPP_G7, { GpioHardwareDefault, GpioHostOwnDefault,
> GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault,
> GpioTermWpd20K }}, //GPP_G_7_SD3_WP
> + //{GPIO_CNL_LP_GPP_H0, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioHostDeepReset, GpioTermNone }}, //GPP_H_0_SSP2_SCLK
> + //{GPIO_CNL_LP_GPP_H1, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioHostDeepReset, GpioTermNone }}, //GPP_H_1_SSP2_SFRM
> + //{GPIO_CNL_LP_GPP_H2, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioHostDeepReset, GpioTermNone }}, //GPP_H_2_SSP2_TXD
> + //{GPIO_CNL_LP_GPP_H3, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioHostDeepReset, GpioTermNone }}, //GPP_H_3_SSP2_RXD
> + //(RC control) {GPIO_CNL_LP_GPP_H4, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //GPP_H_4_I2C2_SDA
> + //(RC control) {GPIO_CNL_LP_GPP_H5, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //GPP_H_5_I2C2_SCL
> + //(RC control) {GPIO_CNL_LP_GPP_H6, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //GPP_H_6_I2C3_SDA
> + //(RC control) {GPIO_CNL_LP_GPP_H7, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //GPP_H_7_I2C3_SCL
> + //(RC control) {GPIO_CNL_LP_GPP_H8, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //GPP_H_8_I2C4_SDA
> + //(RC control) {GPIO_CNL_LP_GPP_H9, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //GPP_H_9_I2C4_SCL
> + {GPIO_CNL_LP_GPP_H10, { GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset,
> GpioTermNone }}, //IVCAM_PWREN
> + {GPIO_CNL_LP_GPP_H11, { GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset,
> GpioTermNone }}, //IVCAM_RECOVERY
> + {GPIO_CNL_LP_GPP_H12, { GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset,
> GpioTermNone }}, //IRIS_STROBE
> + {GPIO_CNL_LP_GPP_H13, { GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset,
> GpioTermNone }}, //IVCAM_MUX_SEL0
> + {GPIO_CNL_LP_GPP_H14, { GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutLow, GpioIntDefault, GpioPlatformReset,
> GpioTermNone, GpioPadUnlock }}, //UF_CAM_PRIVACY_LED
> + {GPIO_CNL_LP_GPP_H15, { GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset,
> GpioTermNone }}, //IVCAM_KEY
> + //(Not used) {GPIO_CNL_LP_GPP_H16, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //DDI4_CTRL_CLK
> + //(Not used) {GPIO_CNL_LP_GPP_H17, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //DDI4_CTRL_DATA
> + //(Default HW) {GPIO_CNL_LP_GPP_H18, { GpioPadModeNative1,
> GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //VCCIO_LPM
> + {GPIO_CNL_LP_GPP_H19, { GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset,
> GpioTermNone }}, //IVCAM_MUX_SEL1
> + //(RC control) {GPIO_CNL_LP_GPP_H20, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //IMGCLKOUT_WF_CAM
> + //(Not used) {GPIO_CNL_LP_GPP_H21, { GpioPadModeNotUsed,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //GPP_H21
> + {GPIO_CNL_LP_GPP_H22, { GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset,
> GpioTermNone }}, //WF_CAM_RST
> + //(Not used) {GPIO_CNL_LP_GPP_H23, { GpioPadModeNotUsed,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioPlatformReset, GpioTermNone }}, //GPP_H23
> + //(Default HW) {GPIO_CNL_LP_GPD0, { GpioPadModeNative1,
> GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioResetDefault, GpioTermNone }}, //PM_BATLOW_N
> + //(Default HW) {GPIO_CNL_LP_GPD1, { GpioPadModeNative1,
> GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioResetDefault, GpioTermNone }}, //BC_ACOK
> + //(Default HW) {GPIO_CNL_LP_GPD2, { GpioPadModeNative1,
> GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioResetDefault, GpioTermNone }}, //LAN_WAKE
> + //(Default HW) {GPIO_CNL_LP_GPD3, { GpioPadModeNative1,
> GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioResetDefault, GpioTermNone }}, //PM_PWRBTN_N
> + //(Default HW) {GPIO_CNL_LP_GPD4, { GpioPadModeNative1,
> GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioResetDefault, GpioTermNone }}, //PM_SLP_S3_N
> + //(Default HW) {GPIO_CNL_LP_GPD5, { GpioPadModeNative1,
> GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioResetDefault, GpioTermNone }}, //PM_SLP_S4_N
> + //(Default HW) {GPIO_CNL_LP_GPD6, { GpioPadModeNative1,
> GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioResetDefault, GpioTermNone }}, //SLP_A_N
> + //{GPIO_CNL_LP_GPD7, { GpioPadModeNotUsed,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioResetDefault, GpioTermNone }}, //GPD_7
> + //(Default HW) {GPIO_CNL_LP_GPD8, { GpioPadModeNative1,
> GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioResetDefault, GpioTermNone }}, //SUS_CLK
> + //(Default HW) {GPIO_CNL_LP_GPD9, { GpioPadModeNative1,
> GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioResetDefault, GpioTermNone }}, //PM_SLP_WLAN_N
> + //(Default HW) {GPIO_CNL_LP_GPD10, { GpioPadModeNative1,
> GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioResetDefault, GpioTermNone }}, //PM_SLP_S5_N
> + //(Default HW) {GPIO_CNL_LP_GPD11, { GpioPadModeNative1,
> GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioResetDefault, GpioTermNone }}, //LANPHY_EN
> + {GPIO_CNL_LP_PECI, { GpioHardwareDefault, GpioHostOwnDefault,
> GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset,
> GpioTermWpd20K }}, // 20K PD for PECI
> +};
> +UINT16 mGpioTableDefaultSize = sizeof (mGpioTableDefault) / sizeof
> (GPIO_INIT_CONFIG);
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/
> GpioTableUpXtreme.c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/
> GpioTableUpXtreme.c
> new file mode 100644
> index 0000000000..4ce7e7450d
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/
> GpioTableUpXtreme.c
> @@ -0,0 +1,217 @@
> +/** @file
> + GPIO definition table for the UP Xtreme
> +
> + Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include <GpioPinsCnlLp.h>
> +#include <Library/GpioLib.h>
> +#include <GpioConfig.h>
> +
> +GPIO_INIT_CONFIG mGpioTableUpXtreme[] =
> +{
> + {GPIO_CNL_LP_GPP_A0, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> + {GPIO_CNL_LP_GPP_A1, { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge,
> GpioHostDeepReset, GpioTermNative }},
> + {GPIO_CNL_LP_GPP_A2, { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge,
> GpioHostDeepReset, GpioTermNative }},
> + {GPIO_CNL_LP_GPP_A3, { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge,
> GpioHostDeepReset, GpioTermNative }},
> + {GPIO_CNL_LP_GPP_A4, { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge,
> GpioHostDeepReset, GpioTermNative }},
> + {GPIO_CNL_LP_GPP_A5, { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge,
> GpioHostDeepReset, GpioTermNone }},
> + {GPIO_CNL_LP_GPP_A6, { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge,
> GpioHostDeepReset, GpioTermNone }},
> + {GPIO_CNL_LP_GPP_A7, { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge,
> GpioHostDeepReset, GpioTermNone }},
> + {GPIO_CNL_LP_GPP_A8, { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge,
> GpioHostDeepReset, GpioTermNone }},
> + {GPIO_CNL_LP_GPP_A9, { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge,
> GpioHostDeepReset, GpioTermWpd20K }},
> + {GPIO_CNL_LP_GPP_A10, { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge,
> GpioHostDeepReset, GpioTermWpd20K }},
> + {GPIO_CNL_LP_GPP_A11, { GpioPadModeGpio, GpioHostOwnDefault,
> GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge,
> GpioHostDeepReset, GpioTermNone }},
> + //(RC control) {GPIO_CNL_LP_GPP_A12, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> + {GPIO_CNL_LP_GPP_A13, { GpioPadModeGpio, GpioHostOwnDefault,
> GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge,
> GpioHostDeepReset, GpioTermNone }},
> + {GPIO_CNL_LP_GPP_A14, { GpioPadModeGpio, GpioHostOwnDefault,
> GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge,
> GpioHostDeepReset, GpioTermNone }},
> + {GPIO_CNL_LP_GPP_A15, { GpioPadModeGpio, GpioHostOwnDefault,
> GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge,
> GpioHostDeepReset, GpioTermNone }},
> + {GPIO_CNL_LP_GPP_A16, { GpioPadModeGpio, GpioHostOwnDefault,
> GpioDirOut, GpioOutLow, GpioIntDefault | GpioIntEdge,
> GpioPlatformReset, GpioTermWpd20K }},
> + {GPIO_CNL_LP_GPP_A17, { GpioPadModeGpio, GpioHostOwnDefault,
> GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge,
> GpioHostDeepReset, GpioTermNone }},
> + {GPIO_CNL_LP_GPP_A18, { GpioPadModeGpio, GpioHostOwnDefault,
> GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge,
> GpioHostDeepReset, GpioTermNone }},
> + {GPIO_CNL_LP_GPP_A19, { GpioPadModeGpio, GpioHostOwnDefault,
> GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge,
> GpioHostDeepReset, GpioTermNone }},
> + {GPIO_CNL_LP_GPP_A20, { GpioPadModeGpio, GpioHostOwnDefault,
> GpioDirOut, GpioOutLow, GpioIntDefault | GpioIntEdge,
> GpioResumeReset, GpioTermWpu20K }},
> + {GPIO_CNL_LP_GPP_A21, { GpioPadModeGpio, GpioHostOwnDefault,
> GpioDirOut, GpioOutHigh, GpioIntDefault | GpioIntEdge,
> GpioResumeReset, GpioTermWpu20K }},
> + {GPIO_CNL_LP_GPP_A22, { GpioPadModeGpio, GpioHostOwnDefault,
> GpioDirOut, GpioOutLow, GpioIntDefault | GpioIntEdge,
> GpioResumeReset, GpioTermWpu20K }},
> + {GPIO_CNL_LP_GPP_A23, { GpioPadModeGpio, GpioHostOwnDefault,
> GpioDirOut, GpioOutHigh, GpioIntDefault | GpioIntEdge,
> GpioResumeReset, GpioTermWpu20K }},
> +
> + {GPIO_CNL_LP_GPP_B0, { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge,
> GpioHostDeepReset, GpioTermNone }},
> + {GPIO_CNL_LP_GPP_B1, { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge,
> GpioHostDeepReset, GpioTermNone }},
> + {GPIO_CNL_LP_GPP_B2, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> + {GPIO_CNL_LP_GPP_B3, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> + {GPIO_CNL_LP_GPP_B4, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> + //(RC control) {GPIO_CNL_LP_GPP_B5, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> + //(RC control) {GPIO_CNL_LP_GPP_B6, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> + //(RC control) {GPIO_CNL_LP_GPP_B7, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> + //(RC control) {GPIO_CNL_LP_GPP_B8, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> + //(RC control) {GPIO_CNL_LP_GPP_B9, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> + //(RC control) {GPIO_CNL_LP_GPP_B10, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> + {GPIO_CNL_LP_GPP_B11, { GpioPadModeGpio, GpioHostOwnDefault,
> GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge,
> GpioHostDeepReset, GpioTermNone }},
> + {GPIO_CNL_LP_GPP_B12, { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge,
> GpioHostDeepReset, GpioTermNone }},
> + {GPIO_CNL_LP_GPP_B13, { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge,
> GpioHostDeepReset, GpioTermNone }},
> + {GPIO_CNL_LP_GPP_B14, { GpioPadModeGpio, GpioHostOwnDefault,
> GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge,
> GpioHostDeepReset, GpioTermNone }},
> + {GPIO_CNL_LP_GPP_B15, { GpioPadModeGpio, GpioHostOwnDefault,
> GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge,
> GpioHostDeepReset, GpioTermNone }},
> + {GPIO_CNL_LP_GPP_B16, { GpioPadModeGpio, GpioHostOwnDefault,
> GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge,
> GpioHostDeepReset, GpioTermNone }},
> + {GPIO_CNL_LP_GPP_B17, { GpioPadModeGpio, GpioHostOwnDefault,
> GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge,
> GpioHostDeepReset, GpioTermNone }},
> + {GPIO_CNL_LP_GPP_B18, { GpioPadModeGpio, GpioHostOwnDefault,
> GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge,
> GpioHostDeepReset, GpioTermNone }},
> + //(RC control) {GPIO_CNL_LP_GPP_B19, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> + //(RC control) {GPIO_CNL_LP_GPP_B20, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> + //(RC control) {GPIO_CNL_LP_GPP_B21, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> + //(RC control) {GPIO_CNL_LP_GPP_B22, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> + {GPIO_CNL_LP_GPP_B23, { GpioPadModeGpio, GpioHostOwnDefault,
> GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge,
> GpioHostDeepReset, GpioTermNone }},
> +
> + //(RC control) {GPIO_CNL_LP_GPP_C0, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> + //(RC control) {GPIO_CNL_LP_GPP_C1, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> + {GPIO_CNL_LP_GPP_C2, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> + //(CSME control) {GPIO_CNL_LP_GPP_C3, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> + //(CSME control) {GPIO_CNL_LP_GPP_C4, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> + {GPIO_CNL_LP_GPP_C5, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> + {GPIO_CNL_LP_GPP_C6, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> + {GPIO_CNL_LP_GPP_C7, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> + {GPIO_CNL_LP_GPP_C8, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> + {GPIO_CNL_LP_GPP_C9, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> + {GPIO_CNL_LP_GPP_C10, { GpioPadModeGpio, GpioHostOwnDefault,
> GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge,
> GpioHostDeepReset, GpioTermNone }},
> + {GPIO_CNL_LP_GPP_C11, { GpioPadModeGpio, GpioHostOwnDefault,
> GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge,
> GpioHostDeepReset, GpioTermNone }},
> + {GPIO_CNL_LP_GPP_C12, { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge,
> GpioHostDeepReset, GpioTermNone }},
> + {GPIO_CNL_LP_GPP_C13, { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge,
> GpioHostDeepReset, GpioTermNone }},
> + {GPIO_CNL_LP_GPP_C14, { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge,
> GpioHostDeepReset, GpioTermNone }},
> + {GPIO_CNL_LP_GPP_C15, { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge,
> GpioHostDeepReset, GpioTermNone }},
> + //(RC control) {GPIO_CNL_LP_GPP_C16, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> + //(RC control) {GPIO_CNL_LP_GPP_C17, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> + //(RC control) {GPIO_CNL_LP_GPP_C18, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> + //(RC control) {GPIO_CNL_LP_GPP_C19, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> + //(RC control) {GPIO_CNL_LP_GPP_C20, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> + //(RC control) {GPIO_CNL_LP_GPP_C21, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> + //(RC control) {GPIO_CNL_LP_GPP_C22, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> + //(RC control) {GPIO_CNL_LP_GPP_C23, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> +
> + //(CSME control) {GPIO_CNL_LP_GPP_D0, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> + //(CSME control) {GPIO_CNL_LP_GPP_D1, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirNone, GpioOutHigh, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> + //(CSME control) {GPIO_CNL_LP_GPP_D2, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> + //(CSME control) {GPIO_CNL_LP_GPP_D3, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> + //(RC control) {GPIO_CNL_LP_GPP_D4, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirOut, GpioOutHigh, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermWpu20K }},
> + //(RC control) {GPIO_CNL_LP_GPP_D5, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> + //(RC control) {GPIO_CNL_LP_GPP_D6, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> + //(RC control) {GPIO_CNL_LP_GPP_D7, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> + //(RC control) {GPIO_CNL_LP_GPP_D8, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> + {GPIO_CNL_LP_GPP_D9, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> + {GPIO_CNL_LP_GPP_D10, { GpioPadModeGpio, GpioHostOwnDefault,
> GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge,
> GpioHostDeepReset, GpioTermNone }},
> + {GPIO_CNL_LP_GPP_D11, { GpioPadModeGpio, GpioHostOwnDefault,
> GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge,
> GpioHostDeepReset, GpioTermNone }},
> + {GPIO_CNL_LP_GPP_D12, { GpioPadModeGpio, GpioHostOwnDefault,
> GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge,
> GpioHostDeepReset, GpioTermNone }},
> + {GPIO_CNL_LP_GPP_D13, { GpioPadModeGpio, GpioHostOwnDefault,
> GpioDirOut, GpioOutHigh, GpioIntDefault | GpioIntEdge,
> GpioResumeReset, GpioTermNone }},
> + {GPIO_CNL_LP_GPP_D14, { GpioPadModeGpio, GpioHostOwnDefault,
> GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge,
> GpioHostDeepReset, GpioTermNone }},
> + {GPIO_CNL_LP_GPP_D15, { GpioPadModeGpio, GpioHostOwnDefault,
> GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge,
> GpioHostDeepReset, GpioTermNone }},
> + {GPIO_CNL_LP_GPP_D16, { GpioPadModeGpio, GpioHostOwnDefault,
> GpioDirOut, GpioOutHigh, GpioIntDefault | GpioIntEdge,
> GpioHostDeepReset, GpioTermWpu20K }},
> + //(RC control) {GPIO_CNL_LP_GPP_D17, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> + //(RC control) {GPIO_CNL_LP_GPP_D18, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> + //(RC control) {GPIO_CNL_LP_GPP_D19, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> + //(RC control) {GPIO_CNL_LP_GPP_D20, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> + //(CSME control) {GPIO_CNL_LP_GPP_D21, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> + //(CSME control) {GPIO_CNL_LP_GPP_D22, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> + //(RC control) {GPIO_CNL_LP_GPP_D23, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> +
> + {GPIO_CNL_LP_GPP_E0, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> + //(RC control) {GPIO_CNL_LP_GPP_E1, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //M.2_SSD_DET
> + {GPIO_CNL_LP_GPP_E2, { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge,
> GpioHostDeepReset, GpioTermNone }}, //Reserved for SATA HP val
> + {GPIO_CNL_LP_GPP_E3, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //EC_SMI_N
> + {GPIO_CNL_LP_GPP_E4, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> //DGPU_PWROK
> + //(RC control) {GPIO_CNL_LP_GPP_E5, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //SSD_DEVSLP
> + //(RC control) {GPIO_CNL_LP_GPP_E6, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //HDD_DEVSLP
> + {GPIO_CNL_LP_GPP_E7, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> //TCH_PNL_INT_N
> + //(RC control) {GPIO_CNL_LP_GPP_E8, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //SATA_LED_N
> + //(RC control) {GPIO_CNL_LP_GPP_E9, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //BSSB_CLK
> + //(RC control) {GPIO_CNL_LP_GPP_E10, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //BSSB_DI
> + //(RC control) {GPIO_CNL_LP_GPP_E11, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //USB_OC_2
> + //(RC control) {GPIO_CNL_LP_GPP_E12, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //USB_OC_3
> + //(RC control) {GPIO_CNL_LP_GPP_E13, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //DDI1_HPD
> + //(RC control) {GPIO_CNL_LP_GPP_E14, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //DDI2_HPD_EC
> + //(RC control) {GPIO_CNL_LP_GPP_E15, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirOut, GpioOutHigh, GpioIntDefault |
> GpioIntEdge, GpioPlatformReset, GpioTermNone }}, //DDI3_HPD
> + //(RC control) {GPIO_CNL_LP_GPP_E16, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //DDI4_HPD
> + //(RC control) {GPIO_CNL_LP_GPP_E17, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //EDP_HPD
> + //(RC control) {GPIO_CNL_LP_GPP_E18, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> //DDI1_CTRL_CLK
> + //(RC control) {GPIO_CNL_LP_GPP_E19, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> //DDI1_CTRL_DATA
> + //(RC control) {GPIO_CNL_LP_GPP_E20, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> //DDI2_CTRL_CLK
> + //(RC control) {GPIO_CNL_LP_GPP_E21, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> //DDI2_CTRL_DATA
> + //(RC control) {GPIO_CNL_LP_GPP_E22, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> //DDI3_CTRL_CLK
> + //(RC control) {GPIO_CNL_LP_GPP_E23, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> //DDI3_CTRL_DATA
> +
> + {GPIO_CNL_LP_GPP_F0, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> //GPP_F0_COEX3
> + {GPIO_CNL_LP_GPP_F1, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> //WWAN_RST_N
> + {GPIO_CNL_LP_GPP_F2, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> //SATA_HDD_PWREN
> + {GPIO_CNL_LP_GPP_F3, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //WF_CLK_EN
> + {GPIO_CNL_LP_GPP_F4, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> //CNV_BRI_DT_UART0_RTSB
> + {GPIO_CNL_LP_GPP_F5, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> //CNV_BRI_RSP_UART0_RXD
> + {GPIO_CNL_LP_GPP_F6, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> //CNV_RGI_DT_UART0_TXD
> + {GPIO_CNL_LP_GPP_F7, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> //CNV_RGI_RSP_UART0_CTSB
> + {GPIO_CNL_LP_GPP_F8, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> //CNV_MFUART2_RXD
> + {GPIO_CNL_LP_GPP_F9, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> //CNV_MFUART2_TXD
> + {GPIO_CNL_LP_GPP_F10, { GpioPadModeGpio, GpioHostOwnDefault,
> GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge,
> GpioHostDeepReset, GpioTermNone }}, //BIOS_REC
> +
> + {GPIO_CNL_LP_GPP_F11, {GpioPadModeNative1, GpioHostOwnGpio,
> GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}},//EMMC_CMD
> + {GPIO_CNL_LP_GPP_F12, {GpioPadModeNative1, GpioHostOwnGpio,
> GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}},//EMMC_DATA0
> + {GPIO_CNL_LP_GPP_F13, {GpioPadModeNative1, GpioHostOwnGpio,
> GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}},//EMMC_DATA1
> + {GPIO_CNL_LP_GPP_F14, {GpioPadModeNative1, GpioHostOwnGpio,
> GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}},//EMMC_DATA2
> + {GPIO_CNL_LP_GPP_F15, {GpioPadModeNative1, GpioHostOwnGpio,
> GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}},//EMMC_DATA3
> + {GPIO_CNL_LP_GPP_F16, {GpioPadModeNative1, GpioHostOwnGpio,
> GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}},//EMMC_DATA4
> + {GPIO_CNL_LP_GPP_F17, {GpioPadModeNative1, GpioHostOwnGpio,
> GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}},//EMMC_DATA5
> + {GPIO_CNL_LP_GPP_F18, {GpioPadModeNative1, GpioHostOwnGpio,
> GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}},//EMMC_DATA6
> + {GPIO_CNL_LP_GPP_F19, {GpioPadModeNative1, GpioHostOwnGpio,
> GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}},//EMMC_DATA7
> + {GPIO_CNL_LP_GPP_F20, {GpioPadModeNative1, GpioHostOwnGpio,
> GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}},//EMMC_RCLK
> + {GPIO_CNL_LP_GPP_F21, {GpioPadModeNative1, GpioHostOwnGpio,
> GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}},//EMMC_CLK
> + {GPIO_CNL_LP_GPP_F22, {GpioPadModeNative1, GpioHostOwnGpio,
> GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset,
> GpioTermNone}},//EMMC_RESETB
> +
> + //(RC control) {GPIO_CNL_LP_GPP_F23, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //GPP_F_23
> +
> + //(RC control) {GPIO_CNL_LP_GPP_G0, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> //GPP_G_0_SD3_CMD
> + //(RC control) {GPIO_CNL_LP_GPP_G1, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> //GPP_G_1_SD3_D0_SD4_RCLK_P
> + //(RC control) {GPIO_CNL_LP_GPP_G2, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> //GPP_G_2_SD3_D1_SD4_RCLK_N
> + //(RC control) {GPIO_CNL_LP_GPP_G3, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> //GPP_G_3_SD3_D2
> + //(RC control) {GPIO_CNL_LP_GPP_G4, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> //GPP_G_4_SD3_D3
> + {GPIO_CNL_LP_GPP_G5, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> //GPP_G_5_SD3_CDB
> + {GPIO_CNL_LP_GPP_G6, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> //GPP_G_6_SD3_CLK
> + {GPIO_CNL_LP_GPP_G7, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> //GPP_G_7_SD3_WP
> +
> + //H0-H3 -> Under GPIO table for GPIO Termination -20K WPU
> + {GPIO_CNL_LP_GPP_H0, { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge,
> GpioHostDeepReset, GpioTermNone }}, //GPP_H_0_SSP2_SCLK
> + {GPIO_CNL_LP_GPP_H1, { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge,
> GpioHostDeepReset, GpioTermNone }}, //GPP_H_1_SSP2_SFRM
> + {GPIO_CNL_LP_GPP_H2, { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge,
> GpioHostDeepReset, GpioTermNone }}, //GPP_H_2_SSP2_TXD
> + {GPIO_CNL_LP_GPP_H3, { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge,
> GpioHostDeepReset, GpioTermNone }}, //GPP_H_3_SSP2_RXD
> + //(RC control) {GPIO_CNL_LP_GPP_H4, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirin, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> //GPP_H_4_I2C2_SDA
> + //(RC control) {GPIO_CNL_LP_GPP_H5, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirin, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> //GPP_H_5_I2C2_SCL
> + //(RC control) {GPIO_CNL_LP_GPP_H6, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> //GPP_H_6_I2C3_SDA
> + //(RC control) {GPIO_CNL_LP_GPP_H7, { GpioPadModeNative1,
> GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> //GPP_H_7_I2C3_SCL
> + //(RC control) {GPIO_CNL_LP_GPP_H8, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> //GPP_H_8_I2C4_SDA
> + //(RC control) {GPIO_CNL_LP_GPP_H9, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> //GPP_H_9_I2C4_SCL
> + {GPIO_CNL_LP_GPP_H10, { GpioPadModeGpio, GpioHostOwnDefault,
> GpioDirOut, GpioOutHigh, GpioIntDefault | GpioIntEdge,
> GpioHostDeepReset, GpioTermNone }}, //IVCAM_PWREN
> + {GPIO_CNL_LP_GPP_H11, { GpioPadModeGpio, GpioHostOwnDefault,
> GpioDirOut, GpioOutHigh, GpioIntDefault | GpioIntEdge,
> GpioHostDeepReset, GpioTermNone }}, //IVCAM_RECOVERY
> + {GPIO_CNL_LP_GPP_H12, { GpioPadModeGpio, GpioHostOwnDefault,
> GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge,
> GpioHostDeepReset, GpioTermNone }}, //IRIS_STROBE
> + {GPIO_CNL_LP_GPP_H13, { GpioPadModeGpio, GpioHostOwnDefault,
> GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge,
> GpioHostDeepReset, GpioTermNone }}, //IVCAM_MUX_SEL0
> + {GPIO_CNL_LP_GPP_H14, { GpioPadModeGpio, GpioHostOwnDefault,
> GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge,
> GpioHostDeepReset, GpioTermNone }}, //UF_CAM_PRIVACY_LED
> + {GPIO_CNL_LP_GPP_H15, { GpioPadModeGpio, GpioHostOwnDefault,
> GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge,
> GpioHostDeepReset, GpioTermNone }}, //IVCAM_KEY
> + {GPIO_CNL_LP_GPP_H16, { GpioPadModeGpio, GpioHostOwnDefault,
> GpioDirOut, GpioOutHigh, GpioIntDefault | GpioIntEdge,
> GpioResumeReset, GpioTermNone }}, //DDI4_CTRL_CLK
> + {GPIO_CNL_LP_GPP_H17, { GpioPadModeGpio, GpioHostOwnDefault,
> GpioDirOut, GpioOutHigh, GpioIntDefault | GpioIntEdge,
> GpioResumeReset, GpioTermNone }}, //DDI4_CTRL_DATA
> + {GPIO_CNL_LP_GPP_H18, { GpioPadModeNative1, GpioHostOwnDefault,
> GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge,
> GpioHostDeepReset, GpioTermNone }}, //VCCIO_LPM
> + {GPIO_CNL_LP_GPP_H19, { GpioPadModeGpio, GpioHostOwnDefault,
> GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge,
> GpioHostDeepReset, GpioTermNone }}, //IVCAM_MUX_SEL1
> + //(RC control) {GPIO_CNL_LP_GPP_H20, { GpioPadModeGpio,
> GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault |
> GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
> //IMGCLKOUT_WF_CAM
> + {GPIO_CNL_LP_GPP_H21, { GpioPadModeGpio, GpioHostOwnDefault,
> GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge,
> GpioHostDeepReset, GpioTermNone }}, //GPP_H21
> + {GPIO_CNL_LP_GPP_H22, { GpioPadModeGpio, GpioHostOwnDefault,
> GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge,
> GpioHostDeepReset, GpioTermNone }}, //WF_CAM_RST
> + {GPIO_CNL_LP_GPP_H23, { GpioPadModeGpio, GpioHostOwnDefault,
> GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge,
> GpioHostDeepReset, GpioTermNone }}, //GPP_H23
> +
> + //(Default HW) {GPIO_CNL_LP_GPD0, { GpioPadModeNative1,
> GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioResetDefault, GpioTermNone }}, //PM_BATLOW_N
> + //(Default HW) {GPIO_CNL_LP_GPD1, { GpioPadModeNative1,
> GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioResetDefault, GpioTermNone }}, //BC_ACOK
> + //(Default HW) {GPIO_CNL_LP_GPD2, { GpioPadModeNative1,
> GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioResetDefault, GpioTermNone }}, //LAN_WAKE
> + //(Default HW) {GPIO_CNL_LP_GPD3, { GpioPadModeNative1,
> GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioResetDefault, GpioTermNone }}, //PM_PWRBTN_N
> + //(Default HW) {GPIO_CNL_LP_GPD4, { GpioPadModeNative1,
> GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioResetDefault, GpioTermNone }}, //PM_SLP_S3_N
> + //(Default HW) {GPIO_CNL_LP_GPD5, { GpioPadModeNative1,
> GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioResetDefault, GpioTermNone }}, //PM_SLP_S4_N
> + //(Default HW) {GPIO_CNL_LP_GPD6, { GpioPadModeNative1,
> GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioResetDefault, GpioTermNone }}, //SLP_A_N
> + //{GPIO_CNL_LP_GPD7, { GpioPadModeNotUsed,
> GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioResetDefault, GpioTermNone }}, //GPD_7
> + //(Default HW) {GPIO_CNL_LP_GPD8, { GpioPadModeNative1,
> GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioResetDefault, GpioTermNone }}, //SUS_CLK
> + //(Default HW) {GPIO_CNL_LP_GPD9, { GpioPadModeNative1,
> GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioResetDefault, GpioTermNone }}, //PM_SLP_WLAN_N
> + //(Default HW) {GPIO_CNL_LP_GPD10, { GpioPadModeNative1,
> GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioResetDefault, GpioTermNone }}, //PM_SLP_S5_N
> + //(Default HW) {GPIO_CNL_LP_GPD11, { GpioPadModeNative1,
> GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault,
> GpioResetDefault, GpioTermNone }}, //LANPHY_EN
> +
> + {GPIO_CNL_LP_PECI, { GpioHardwareDefault, GpioHostOwnDefault,
> GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault,
> GpioTermDefault }}, // PECI
> +};
> +UINT16 mGpioTableUpXtremeSize = sizeof (mGpioTableUpXtreme) / sizeof
> (GPIO_INIT_CONFIG);
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/
> PchHdaVerbTables.h
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/
> PchHdaVerbTables.h
> new file mode 100644
> index 0000000000..2e4bef3246
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/
> PchHdaVerbTables.h
> @@ -0,0 +1,3014 @@
> +/** @file
> +
> + Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PCH_HDA_VERB_TABLES_H_
> +#define _PCH_HDA_VERB_TABLES_H_
> +
> +#include <Ppi/SiPolicy.h>
> +
> +HDAUDIO_VERB_TABLE HdaVerbTableDisplayAudio =
> HDAUDIO_VERB_TABLE_INIT (
> + //
> + // VerbTable: CFL Display Audio Codec
> + // Revision ID = 0xFF
> + // Codec Vendor: 0x8086280B
> + //
> + 0x8086, 0x280B,
> + 0xFF, 0xFF,
> + //
> + // Display Audio Verb Table
> + //
> + // For GEN9, the Vendor Node ID is 08h
> + // Port to be exposed to the inbox driver in the vanilla mode: PORT C -
> BIT[7:6] = 01b
> + 0x00878140,
> + // Pin Widget 5 - PORT B - Configuration Default: 0x18560010
> + 0x00571C10,
> + 0x00571D00,
> + 0x00571E56,
> + 0x00571F18,
> + // Pin Widget 6 - PORT C - Configuration Default: 0x18560020
> + 0x00671C20,
> + 0x00671D00,
> + 0x00671E56,
> + 0x00671F18,
> + // Pin Widget 7 - PORT D - Configuration Default: 0x18560030
> + 0x00771C30,
> + 0x00771D00,
> + 0x00771E56,
> + 0x00771F18,
> + // Disable the third converter and third Pin (NID 08h)
> + 0x00878140
> +);
> +
> +//
> +//codecs verb tables
> +//
> +HDAUDIO_VERB_TABLE HdaVerbTableAlc700 = HDAUDIO_VERB_TABLE_INIT
> (
> + //
> + // VerbTable: (Realtek ALC700)
> + // Revision ID = 0xff
> + // Codec Verb Table
> + // Codec Address: CAd value (0/1/2)
> + // Codec Vendor: 0x10EC0700
> + //
> + 0x10EC, 0x0700,
> + 0xFF, 0xFF,
> +
> //==============================================================
> =====================================
> + //
> + // Realtek Semiconductor Corp.
> + //
> +
> //==============================================================
> =====================================
> +
> + //Realtek High Definition Audio Configuration - Version : 5.0.3.0
> + //Realtek HD Audio Codec : ALC700
> + //PCI PnP ID : PCI\VEN_8086&DEV_2668&SUBSYS_72708086
> + //HDA Codec PnP ID :
> HDAUDIO\FUNC_01&VEN_10EC&DEV_0700&SUBSYS_10EC10F2
> + //The number of verb command block : 17
> +
> + // NID 0x12 : 0x411111F0
> + // NID 0x13 : 0x40000000
> + // NID 0x14 : 0x411111F0
> + // NID 0x15 : 0x411111F0
> + // NID 0x16 : 0x411111F0
> + // NID 0x17 : 0x90170110
> + // NID 0x18 : 0x411111F0
> + // NID 0x19 : 0x04A11030
> + // NID 0x1A : 0x411111F0
> + // NID 0x1B : 0x411111F0
> + // NID 0x1D : 0x40622005
> + // NID 0x1E : 0x411111F0
> + // NID 0x1F : 0x411111F0
> + // NID 0x21 : 0x04211020
> + // NID 0x29 : 0x411111F0
> +
> + //===== HDA Codec Subsystem ID Verb-table =====
> + //HDA Codec Subsystem ID : 0x10EC10F2
> + 0x001720F2,
> + 0x00172110,
> + 0x001722EC,
> + 0x00172310,
> +
> + //===== Pin Widget Verb-table =====
> + //Widget node 0x01 :
> + 0x0017FF00,
> + 0x0017FF00,
> + 0x0017FF00,
> + 0x0017FF00,
> + //Pin widget 0x12 - DMIC
> + 0x01271C00,
> + 0x01271D00,
> + 0x01271E00,
> + 0x01271F40,
> + //Pin widget 0x13 - DMIC
> + 0x01371C00,
> + 0x01371D00,
> + 0x01371E00,
> + 0x01371F40,
> + //Pin widget 0x14 - FRONT (Port-D)
> + 0x01471CF0,
> + 0x01471D11,
> + 0x01471E11,
> + 0x01471F41,
> + //Pin widget 0x15 - I2S-OUT
> + 0x01571CF0,
> + 0x01571D11,
> + 0x01571E11,
> + 0x01571F41,
> + //Pin widget 0x16 - LINE3 (Port-B)
> + 0x01671CF0,
> + 0x01671D11,
> + 0x01671E11,
> + 0x01671F41,
> + //Pin widget 0x17 - I2S-OUT
> + 0x01771C10,
> + 0x01771D01,
> + 0x01771E17,
> + 0x01771F90,
> + //Pin widget 0x18 - I2S-IN
> + 0x01871CF0,
> + 0x01871D11,
> + 0x01871E11,
> + 0x01871F41,
> + //Pin widget 0x19 - MIC2 (Port-F)
> + 0x01971C30,
> + 0x01971D10,
> + 0x01971EA1,
> + 0x01971F04,
> + //Pin widget 0x1A - LINE1 (Port-C)
> + 0x01A71CF0,
> + 0x01A71D11,
> + 0x01A71E11,
> + 0x01A71F41,
> + //Pin widget 0x1B - LINE2 (Port-E)
> + 0x01B71CF0,
> + 0x01B71D11,
> + 0x01B71E11,
> + 0x01B71F41,
> + //Pin widget 0x1D - PC-BEEP
> + 0x01D71C05,
> + 0x01D71D20,
> + 0x01D71E62,
> + 0x01D71F40,
> + //Pin widget 0x1E - S/PDIF-OUT
> + 0x01E71CF0,
> + 0x01E71D11,
> + 0x01E71E11,
> + 0x01E71F41,
> + //Pin widget 0x1F - S/PDIF-IN
> + 0x01F71CF0,
> + 0x01F71D11,
> + 0x01F71E11,
> + 0x01F71F41,
> + //Pin widget 0x21 - HP-OUT (Port-I)
> + 0x02171C20,
> + 0x02171D10,
> + 0x02171E21,
> + 0x02171F04,
> + //Pin widget 0x29 - I2S-IN
> + 0x02971CF0,
> + 0x02971D11,
> + 0x02971E11,
> + 0x02971F41,
> + //Widget node 0x20 :
> + 0x02050045,
> + 0x02045289,
> + 0x0205004A,
> + 0x0204201B,
> + //Widget node 0x20 - 1 :
> + 0x05850000,
> + 0x05843888,
> + 0x0205006F,
> + 0x02042C0B,
> +
> +
> + //Widget node 0X20 for ALC1305 20160603 update
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040000,
> + 0x02050028,
> + 0x02040000,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040004,
> + 0x02050028,
> + 0x02040600,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204003C,
> + 0x02050028,
> + 0x0204FFD0,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040080,
> + 0x02050028,
> + 0x02040080,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040080,
> + 0x02050028,
> + 0x02040880,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204003A,
> + 0x02050028,
> + 0x02040DFE,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204006A,
> + 0x02050028,
> + 0x0204005D,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204006C,
> + 0x02050028,
> + 0x02040442,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040005,
> + 0x02050028,
> + 0x02040880,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040006,
> + 0x02050028,
> + 0x02040000,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040008,
> + 0x02050028,
> + 0x0204B000,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204002E,
> + 0x02050028,
> + 0x02040800,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204006A,
> + 0x02050028,
> + 0x020400C3,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204006C,
> + 0x02050028,
> + 0x0204D4A0,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204006A,
> + 0x02050028,
> + 0x020400CC,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204006C,
> + 0x02050028,
> + 0x0204400A,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204006A,
> + 0x02050028,
> + 0x020400C1,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204006C,
> + 0x02050028,
> + 0x02040320,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040039,
> + 0x02050028,
> + 0x02040000,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204003B,
> + 0x02050028,
> + 0x0204FFFF,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204003C,
> + 0x02050028,
> + 0x0204FC20,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204003A,
> + 0x02050028,
> + 0x02041DFE,
> + 0x02050029,
> + 0x0204B024,
> + //
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x020400C0,
> + 0x02050028,
> + 0x020401FA,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x020400C1,
> + 0x02050028,
> + 0x0204DE23,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x020400C2,
> + 0x02050028,
> + 0x02041C00,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x020400C3,
> + 0x02050028,
> + 0x02040000,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x020400C4,
> + 0x02050028,
> + 0x02040200,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x020400C5,
> + 0x02050028,
> + 0x02040000,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x020400C6,
> + 0x02050028,
> + 0x020403F5,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x020400C7,
> + 0x02050028,
> + 0x0204AF1B,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x020400C8,
> + 0x02050028,
> + 0x02041E0A,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x020400C9,
> + 0x02050028,
> + 0x0204368E,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x020400CA,
> + 0x02050028,
> + 0x020401FA,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x020400CB,
> + 0x02050028,
> + 0x0204DE23,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x020400CC,
> + 0x02050028,
> + 0x02041C00,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x020400CD,
> + 0x02050028,
> + 0x02040000,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x020400CE,
> + 0x02050028,
> + 0x02040200,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x020400CF,
> + 0x02050028,
> + 0x02040000,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x020400D0,
> + 0x02050028,
> + 0x020403F5,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x020400D1,
> + 0x02050028,
> + 0x0204AF1B,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x020400D2,
> + 0x02050028,
> + 0x02041E0A,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x020400D3,
> + 0x02050028,
> + 0x0204368E,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040040,
> + 0x02050028,
> + 0x0204800F,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040062,
> + 0x02050028,
> + 0x02048000,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040063,
> + 0x02050028,
> + 0x02044848,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040064,
> + 0x02050028,
> + 0x02040800,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040065,
> + 0x02050028,
> + 0x02040000,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040066,
> + 0x02050028,
> + 0x02044004,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040067,
> + 0x02050028,
> + 0x02040802,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040068,
> + 0x02050028,
> + 0x0204890F,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040069,
> + 0x02050028,
> + 0x0204E021,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040070,
> + 0x02050028,
> + 0x02040000,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040071,
> + 0x02050000,
> + 0x02043330,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040072,
> + 0x02050000,
> + 0x02043333,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040073,
> + 0x02050028,
> + 0x02040000,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040074,
> + 0x02050028,
> + 0x02040000,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040075,
> + 0x02050028,
> + 0x02040000,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040076,
> + 0x02050028,
> + 0x02040000,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040050,
> + 0x02050028,
> + 0x020402EC,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040051,
> + 0x02050028,
> + 0x02044909,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040052,
> + 0x02050028,
> + 0x020440B0,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040046,
> + 0x02050028,
> + 0x0204C22E,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040047,
> + 0x02050028,
> + 0x02040C00,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040048,
> + 0x02050028,
> + 0x02040000,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040049,
> + 0x02050028,
> + 0x02040000,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204004A,
> + 0x02050028,
> + 0x02040000,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204004B,
> + 0x02050028,
> + 0x02041C00,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204006A,
> + 0x02050028,
> + 0x02040090,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204006C,
> + 0x02050028,
> + 0x0204721F,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204009E,
> + 0x02050028,
> + 0x02040001,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040004,
> + 0x02050028,
> + 0x02040500,
> + 0x02050029,
> + 0x0204B024
> +); // HdaVerbTableAlc700
> +
> +HDAUDIO_VERB_TABLE HdaVerbTableAlc701 = HDAUDIO_VERB_TABLE_INIT
> (
> + //
> + // VerbTable: (Realtek ALC701)
> + // Revision ID = 0xff
> + // Codec Verb Table
> + // Codec Address: CAd value (0/1/2)
> + // Codec Vendor: 0x10EC0701
> + //
> + 0x10EC, 0x0701,
> + 0xFF, 0xFF,
> +
> //==============================================================
> =====================================
> + //
> + // Realtek Semiconductor Corp.
> + //
> +
> //==============================================================
> =====================================
> +
> + //Realtek High Definition Audio Configuration - Version : 5.0.3.0
> + //Realtek HD Audio Codec : ALC701
> + //PCI PnP ID : PCI\VEN_8086&DEV_2668&SUBSYS_72708086
> + //HDA Codec PnP ID :
> HDAUDIO\FUNC_01&VEN_10EC&DEV_0701&SUBSYS_10EC1124
> + //The number of verb command block : 17
> +
> + // NID 0x12 : 0x411111F0
> + // NID 0x13 : 0x40000000
> + // NID 0x14 : 0x411111F0
> + // NID 0x15 : 0x411111F0
> + // NID 0x16 : 0x411111F0
> + // NID 0x17 : 0x90170110
> + // NID 0x18 : 0x411111F0
> + // NID 0x19 : 0x04A11030
> + // NID 0x1A : 0x411111F0
> + // NID 0x1B : 0x411111F0
> + // NID 0x1D : 0x40610041
> + // NID 0x1E : 0x411111F0
> + // NID 0x1F : 0x411111F0
> + // NID 0x21 : 0x04211020
> + // NID 0x29 : 0x411111F0
> +
> +
> + //===== HDA Codec Subsystem ID Verb-table =====
> + //HDA Codec Subsystem ID : 0x10EC1124
> + 0x00172024,
> + 0x00172111,
> + 0x001722EC,
> + 0x00172310,
> + //===== Pin Widget Verb-table =====
> + //Widget node 0x01 :
> + 0x0017FF00,
> + 0x0017FF00,
> + 0x0017FF00,
> + 0x0017FF00,
> + //Pin widget 0x12 - DMIC
> + 0x01271C00,
> + 0x01271D00,
> + 0x01271E00,
> + 0x01271F40,
> + //Pin widget 0x13 - DMIC
> + 0x01371C00,
> + 0x01371D00,
> + 0x01371E00,
> + 0x01371F40,
> + //Pin widget 0x14 - FRONT (Port-D)
> + 0x01471CF0,
> + 0x01471D11,
> + 0x01471E11,
> + 0x01471F41,
> + //Pin widget 0x15 - I2S-OUT
> + 0x01571CF0,
> + 0x01571D11,
> + 0x01571E11,
> + 0x01571F41,
> + //Pin widget 0x16 - LINE3 (Port-B)
> + 0x01671CF0,
> + 0x01671D11,
> + 0x01671E11,
> + 0x01671F41,
> + //Pin widget 0x17 - I2S-OUT
> + 0x01771C10,
> + 0x01771D01,
> + 0x01771E17,
> + 0x01771F90,
> + //Pin widget 0x18 - I2S-IN
> + 0x01871CF0,
> + 0x01871D11,
> + 0x01871E11,
> + 0x01871F41,
> + //Pin widget 0x19 - MIC2 (Port-F)
> + 0x01971C30,
> + 0x01971D10,
> + 0x01971EA1,
> + 0x01971F04,
> + //Pin widget 0x1A - LINE1 (Port-C)
> + 0x01A71CF0,
> + 0x01A71D11,
> + 0x01A71E11,
> + 0x01A71F41,
> + //Pin widget 0x1B - LINE2 (Port-E)
> + 0x01B71CF0,
> + 0x01B71D11,
> + 0x01B71E11,
> + 0x01B71F41,
> + //Pin widget 0x1D - PC-BEEP
> + 0x01D71C41,
> + 0x01D71D00,
> + 0x01D71E61,
> + 0x01D71F40,
> + //Pin widget 0x1E - S/PDIF-OUT
> + 0x01E71CF0,
> + 0x01E71D11,
> + 0x01E71E11,
> + 0x01E71F41,
> + //Pin widget 0x1F - S/PDIF-IN
> + 0x01F71CF0,
> + 0x01F71D11,
> + 0x01F71E11,
> + 0x01F71F41,
> + //Pin widget 0x21 - HP-OUT (Port-I)
> + 0x02171C20,
> + 0x02171D10,
> + 0x02171E21,
> + 0x02171F04,
> + //Pin widget 0x29 - I2S-IN
> + 0x02971CF0,
> + 0x02971D11,
> + 0x02971E11,
> + 0x02971F41,
> + //Widget node 0x20 :
> + 0x02050045,
> + 0x02045289,
> + 0x0205004A,
> + 0x0204201B,
> + //Widget node 0x20 - 1 :
> + 0x05850000,
> + 0x05843888,
> + 0x0205006F,
> + 0x02042C0B
> +); // HdaVerbTableAlc701
> +
> +HDAUDIO_VERB_TABLE HdaVerbTableAlc274 = HDAUDIO_VERB_TABLE_INIT
> (
> + //
> + // VerbTable: (Realtek ALC274)
> + // Revision ID = 0xff
> + // Codec Verb Table
> + // Codec Address: CAd value (0/1/2)
> + // Codec Vendor: 0x10EC0274
> + //
> + 0x10EC, 0x0274,
> + 0xFF, 0xFF,
> +
> //==============================================================
> =====================================
> + //
> + // Realtek Semiconductor Corp.
> + //
> +
> //==============================================================
> =====================================
> +
> + //Realtek High Definition Audio Configuration - Version : 5.0.3.0
> + //Realtek HD Audio Codec : ALC274
> + //PCI PnP ID : PCI\VEN_8086&DEV_2668&SUBSYS_72708086
> + //HDA Codec PnP ID :
> HDAUDIO\FUNC_01&VEN_10EC&DEV_0274&SUBSYS_10EC10F6
> + //The number of verb command block : 16
> +
> + // NID 0x12 : 0x40000000
> + // NID 0x13 : 0x411111F0
> + // NID 0x14 : 0x411111F0
> + // NID 0x15 : 0x411111F0
> + // NID 0x16 : 0x411111F0
> + // NID 0x17 : 0x411111F0
> + // NID 0x18 : 0x411111F0
> + // NID 0x19 : 0x04A11020
> + // NID 0x1A : 0x411111F0
> + // NID 0x1B : 0x411111F0
> + // NID 0x1D : 0x40451B05
> + // NID 0x1E : 0x411111F0
> + // NID 0x1F : 0x411111F0
> + // NID 0x21 : 0x04211010
> +
> +
> + //===== HDA Codec Subsystem ID Verb-table =====
> + //,DA Codec Subsystem ID : 0x10EC10F6
> + 0x001720F6,
> + 0x00172110,
> + 0x001722EC,
> + 0x00172310,
> +
> + //===== Pin Widget Verb-table =====
> + //Widget node 0x01 :
> + 0x0017FF00,
> + 0x0017FF00,
> + 0x0017FF00,
> + 0x0017FF00,
> + //Pin widget 0x12 - DMIC
> + 0x01271C00,
> + 0x01271D00,
> + 0x01271E00,
> + 0x01271F40,
> + //Pin widget 0x13 - DMIC
> + 0x01371CF0,
> + 0x01371D11,
> + 0x01371E11,
> + 0x01371F41,
> + //Pin widget 0x14 - NPC
> + 0x01471CF0,
> + 0x01471D11,
> + 0x01471E11,
> + 0x01471F41,
> + //Pin widget 0x15 - I2S_OUT2
> + 0x01571CF0,
> + 0x01571D11,
> + 0x01571E11,
> + 0x01571F41,
> + //Pin widget 0x16 - LINE3 (Port-B)
> + 0x01671CF0,
> + 0x01671D11,
> + 0x01671E11,
> + 0x01671F41,
> + //Pin widget 0x17 - I2S_OUT1
> + 0x01771CF0,
> + 0x01771D11,
> + 0x01771E11,
> + 0x01771F41,
> + //Pin widget 0x18 - I2S_IN
> + 0x01871CF0,
> + 0x01871D11,
> + 0x01871E11,
> + 0x01871F41,
> + //Pin widget 0x19 - MIC2 (Port-F)
> + 0x01971C20,
> + 0x01971D10,
> + 0x01971EA1,
> + 0x01971F04,
> + //Pin widget 0x1A - LINE1 (Port-C)
> + 0x01A71CF0,
> + 0x01A71D11,
> + 0x01A71E11,
> + 0x01A71F41,
> + //Pin widget 0x1B - LINE2 (Port-E)
> + 0x01B71CF0,
> + 0x01B71D11,
> + 0x01B71E11,
> + 0x01B71F41,
> + //Pin widget 0x1D - PC-BEEP
> + 0x01D71C05,
> + 0x01D71D1B,
> + 0x01D71E45,
> + 0x01D71F40,
> + //Pin widget 0x1E - S/PDIF-OUT
> + 0x01E71CF0,
> + 0x01E71D11,
> + 0x01E71E11,
> + 0x01E71F41,
> + //Pin widget 0x1F - S/PDIF-IN
> + 0x01F71CF0,
> + 0x01F71D11,
> + 0x01F71E11,
> + 0x01F71F41,
> + //Pin widget 0x21 - HP-OUT (Port-I)
> + 0x02171C10,
> + 0x02171D10,
> + 0x02171E21,
> + 0x02171F04,
> + //Widget node 0x20 :
> + 0x02050045,
> + 0x02045289,
> + 0x0205006F,
> + 0x02042C0B,
> + //Widget node 0x20 - 1 :
> + 0x02050035,
> + 0x02048968,
> + 0x05B50001,
> + 0x05B48540,
> + //Widget node 0x20 - 2 :
> + 0x05850000,
> + 0x05843888,
> + 0x05850000,
> + 0x05843888,
> + //Widget node 0x20 - 3 :
> + 0x0205004A,
> + 0x0204201B,
> + 0x0205004A,
> + 0x0204201B
> +); //HdaVerbTableAlc274
> +
> +//
> +// CFL S Audio Codec
> +//
> +STATIC HDAUDIO_VERB_TABLE CflSHdaVerbTableAlc700 =
> HDAUDIO_VERB_TABLE_INIT (
> + //
> + // VerbTable: (Realtek ALC700) CFL S RVP
> + // Revision ID = 0xff
> + // Codec Verb Table
> + // Codec Address: CAd value (0/1/2)
> + // Codec Vendor: 0x10EC0700
> + //
> + 0x10EC, 0x0700,
> + 0xFF, 0xFF,
> +
> +
> //==============================================================
> =====================================
> + //
> + // Realtek Semiconductor Corp.
> + //
> +
> //==============================================================
> =====================================
> +
> + //Realtek High Definition Audio Configuration - Version : 5.0.3.1
> + //Realtek HD Audio Codec : ALC700
> + //PCI PnP ID : PCI\VEN_8086&DEV_2668&SUBSYS_72708086
> + //HDA Codec PnP ID :
> HDAUDIO\FUNC_01&VEN_10EC&DEV_0700&SUBSYS_10EC112C
> + //The number of verb command block : 17
> +
> + // NID 0x12 : 0x90A60130
> + // NID 0x13 : 0x40000000
> + // NID 0x14 : 0x411111F0
> + // NID 0x15 : 0x411111F0
> + // NID 0x16 : 0x03011010
> + // NID 0x17 : 0x90170120
> + // NID 0x18 : 0x411111F0
> + // NID 0x19 : 0x04A1103E
> + // NID 0x1A : 0x411111F0
> + // NID 0x1B : 0x03A11040
> + // NID 0x1D : 0x40600001
> + // NID 0x1E : 0x411111F0
> + // NID 0x1F : 0x411111F0
> + // NID 0x21 : 0x0421102F
> + // NID 0x29 : 0x411111F0
> +
> +
> + //===== HDA Codec Subsystem ID Verb-table =====
> + //HDA Codec Subsystem ID : 0x10EC112C
> + 0x0017202C,
> + 0x00172111,
> + 0x001722EC,
> + 0x00172310,
> +
> +
> + //===== Pin Widget Verb-table =====
> + //Widget node 0x01 :
> + 0x0017FF00,
> + 0x0017FF00,
> + 0x0017FF00,
> + 0x0017FF00,
> + //Pin widget 0x12 - DMIC
> + 0x01271C30,
> + 0x01271D01,
> + 0x01271EA6,
> + 0x01271F90,
> + //Pin widget 0x13 - DMIC
> + 0x01371C00,
> + 0x01371D00,
> + 0x01371E00,
> + 0x01371F40,
> + //Pin widget 0x14 - FRONT (Port-D)
> + 0x01471CF0,
> + 0x01471D11,
> + 0x01471E11,
> + 0x01471F41,
> + //Pin widget 0x15 - I2S-OUT
> + 0x01571CF0,
> + 0x01571D11,
> + 0x01571E11,
> + 0x01571F41,
> + //Pin widget 0x16 - LINE3 (Port-B)
> + 0x01671C10,
> + 0x01671D10,
> + 0x01671E01,
> + 0x01671F03,
> + //Pin widget 0x17 - I2S-OUT
> + 0x01771C20,
> + 0x01771D01,
> + 0x01771E17,
> + 0x01771F90,
> + //Pin widget 0x18 - I2S-IN
> + 0x01871CF0,
> + 0x01871D11,
> + 0x01871E11,
> + 0x01871F41,
> + //Pin widget 0x19 - MIC2 (Port-F)
> + 0x01971C3E,
> + 0x01971D10,
> + 0x01971EA1,
> + 0x01971F04,
> + //Pin widget 0x1A - LINE1 (Port-C)
> + 0x01A71CF0,
> + 0x01A71D11,
> + 0x01A71E11,
> + 0x01A71F41,
> + //Pin widget 0x1B - LINE2 (Port-E)
> + 0x01B71C40,
> + 0x01B71D10,
> + 0x01B71EA1,
> + 0x01B71F03,
> + //Pin widget 0x1D - PC-BEEP
> + 0x01D71C01,
> + 0x01D71D00,
> + 0x01D71E60,
> + 0x01D71F40,
> + //Pin widget 0x1E - S/PDIF-OUT
> + 0x01E71CF0,
> + 0x01E71D11,
> + 0x01E71E11,
> + 0x01E71F41,
> + //Pin widget 0x1F - S/PDIF-IN
> + 0x01F71CF0,
> + 0x01F71D11,
> + 0x01F71E11,
> + 0x01F71F41,
> + //Pin widget 0x21 - HP-OUT (Port-I)
> + 0x02171C2F,
> + 0x02171D10,
> + 0x02171E21,
> + 0x02171F04,
> + //Pin widget 0x29 - I2S-IN
> + 0x02971CF0,
> + 0x02971D11,
> + 0x02971E11,
> + 0x02971F41,
> +
> + //Widget node 0x20 - 0 FAKE JD unplug
> + 0x02050008,
> + 0x0204A80F,
> + 0x02050008,
> + 0x0204A80F,
> + //Widget node 0x20 - 1 : LINE2-VREFO( MIC2-vrefo-R) base on verb_707h
> of NID 1Bh , HP-JD gating MIC2-vrefo-L, bypass DAC02 DRE(NID5B bit14)
> + 0x0205006B,
> + 0x02044260,
> + 0x0205006B,
> + 0x02044260,
> + //Widget node 0x20 - 2 : //remove NID 58 realted setting for ALC700
> + 0x05B50010,
> + 0x05B45C1D,
> + 0x0205006F,
> + 0x02040F8B, //Zeek, 0F8Bh
> + //Widget node 0x20 -3 : MIC2-Vrefo-R and MIC2-vrefo-L to independent
> control
> + 0x02050045,
> + 0x02045089,
> + 0x0205004A,
> + 0x0204201B,
> + //Widget node 0x20 - 4 From JD detect
> + 0x02050008,
> + 0x0204A807,
> + 0x02050008,
> + 0x0204A807,
> + //Widget node 0x20 - 5 Pull high ALC700 GPIO5 for AMP1305 PD pin and
> enable I2S BCLK first
> + 0x02050090,
> + 0x02040424,
> + 0x00171620,
> + 0x00171720,
> +
> + 0x00171520,
> + 0x01770740,
> + 0x01770740,
> + 0x01770740,
> +
> +
> + //Widget node 0X20 for ALC1305 20181023 update 2W/4ohm to
> remove ALC1305 EQ setting
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040000,
> + 0x02050028,
> + 0x02040000,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204006A,
> + 0x02050028,
> + 0x020400CF,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204006C,
> + 0x02050028,
> + 0x02045548,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204003F,
> + 0x02050028,
> + 0x02041000,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040004,
> + 0x02050028,
> + 0x02040600,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204003C,
> + 0x02050028,
> + 0x0204FFD0,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040080,
> + 0x02050028,
> + 0x02040080,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040080,
> + 0x02050028,
> + 0x02040880,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204003A,
> + 0x02050028,
> + 0x02040DFE,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204006A,
> + 0x02050028,
> + 0x0204005D,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204006C,
> + 0x02050028,
> + 0x02040442,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040005,
> + 0x02050028,
> + 0x02040880,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040006,
> + 0x02050028,
> + 0x02040000,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040008,
> + 0x02050028,
> + 0x0204B000,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204002E,
> + 0x02050028,
> + 0x02040800,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204006A,
> + 0x02050028,
> + 0x020400C3,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204006C,
> + 0x02050028,
> + 0x0204D4A0,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204006A,
> + 0x02050028,
> + 0x020400CC,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204006C,
> + 0x02050028,
> + 0x0204400A,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204006A,
> + 0x02050028,
> + 0x020400C1,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204006C,
> + 0x02050028,
> + 0x02040320,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040039,
> + 0x02050028,
> + 0x02040000,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204003B,
> + 0x02050028,
> + 0x0204FFFF,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204003C,
> + 0x02050028,
> + 0x0204FC20,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204006A,
> + 0x02050028,
> + 0x02040006,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204006C,
> + 0x02050028,
> + 0x020400C0,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204003C,
> + 0x02050028,
> + 0x0204FCA0,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204003C,
> + 0x02050028,
> + 0x0204FCE0,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204003C,
> + 0x02050028,
> + 0x0204FCF0,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040080,
> + 0x02050028,
> + 0x02040080,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040080,
> + 0x02050028,
> + 0x02040880,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040080,
> + 0x02050028,
> + 0x02040880,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204003C,
> + 0x02050028,
> + 0x0204FCE0,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204003C,
> + 0x02050028,
> + 0x0204FCA0,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204003C,
> + 0x02050028,
> + 0x0204FC20,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204006A,
> + 0x02050028,
> + 0x02040006,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204006C,
> + 0x02050028,
> + 0x02040000,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040080,
> + 0x02050028,
> + 0x02040000,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x020400C0,
> + 0x02050028,
> + 0x020401F0,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x020400C1,
> + 0x02050028,
> + 0x0204C1C7,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x020400C2,
> + 0x02050028,
> + 0x02041C00,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x020400C3,
> + 0x02050028,
> + 0x02040000,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x020400C4,
> + 0x02050028,
> + 0x02040200,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x020400C5,
> + 0x02050028,
> + 0x02040000,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x020400C6,
> + 0x02050028,
> + 0x020403E1,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x020400C7,
> + 0x02050028,
> + 0x02040F5A,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x020400C8,
> + 0x02050028,
> + 0x02041E1E,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x020400C9,
> + 0x02050028,
> + 0x0204083F,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x020400CA,
> + 0x02050028,
> + 0x020401F0,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x020400CB,
> + 0x02050028,
> + 0x0204C1C7,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x020400CC,
> + 0x02050028,
> + 0x02041C00,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x020400CD,
> + 0x02050028,
> + 0x02040000,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x020400CE,
> + 0x02050028,
> + 0x02040200,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x020400CF,
> + 0x02050028,
> + 0x02040000,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x020400D0,
> + 0x02050028,
> + 0x020403E1,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x020400D1,
> + 0x02050028,
> + 0x02040F5A,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x020400D2,
> + 0x02050028,
> + 0x02041E1E,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x020400D3,
> + 0x02050028,
> + 0x0204083F,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040062,
> + 0x02050028,
> + 0x02048000,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040063,
> + 0x02050028,
> + 0x02045F5F,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040064,
> + 0x02050028,
> + 0x02042000,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040065,
> + 0x02050028,
> + 0x02040000,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040066,
> + 0x02050028,
> + 0x02044004,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040067,
> + 0x02050028,
> + 0x02040802,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040068,
> + 0x02050028,
> + 0x0204890F,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040069,
> + 0x02050028,
> + 0x0204E021,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040070,
> + 0x02050028,
> + 0x02048012,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040071,
> + 0x02050028,
> + 0x02043450,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040072,
> + 0x02050028,
> + 0x02040123,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040073,
> + 0x02050028,
> + 0x02044543,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040074,
> + 0x02050028,
> + 0x02042100,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040075,
> + 0x02050028,
> + 0x02044321,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040076,
> + 0x02050028,
> + 0x02040000,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040050,
> + 0x02050028,
> + 0x02048200,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040051,
> + 0x02050028,
> + 0x02040707,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040052,
> + 0x02050028,
> + 0x02044090,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204006A,
> + 0x02050028,
> + 0x02040090,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204006C,
> + 0x02050028,
> + 0x0204721F,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040012,
> + 0x02050028,
> + 0x0204DFDF,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204009E,
> + 0x02050028,
> + 0x02040000,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040004,
> + 0x02050028,
> + 0x02040500,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040060,
> + 0x02050028,
> + 0x02042213,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204003A,
> + 0x02050028,
> + 0x02041DFE,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204003F,
> + 0x02050028,
> + 0x02043000,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040040,
> + 0x02050028,
> + 0x0204000C,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040046,
> + 0x02050028,
> + 0x0204C22E,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204004B,
> + 0x02050028,
> + 0x02040000,
> + 0x02050029,
> + 0x0204B024
> +);
> +
> +
> +//
> +// WHL codecs verb tables
> +//
> +HDAUDIO_VERB_TABLE WhlHdaVerbTableAlc700 =
> HDAUDIO_VERB_TABLE_INIT (
> + //
> + // VerbTable: (Realtek ALC700) WHL RVP
> + // Revision ID = 0xff
> + // Codec Verb Table for WHL PCH boards
> + // Codec Address: CAd value (0/1/2)
> + // Codec Vendor: 0x10EC0700
> + //
> + 0x10EC, 0x0700,
> + 0xFF, 0xFF,
> +
> //==============================================================
> =====================================
> + //
> + // Realtek Semiconductor Corp.
> + //
> +
> //==============================================================
> =====================================
> +
> + //Realtek High Definition Audio Configuration - Version : 5.0.3.1
> + //Realtek HD Audio Codec : ALC700
> + //PCI PnP ID : PCI\VEN_8086&DEV_2668&SUBSYS_72708086
> + //HDA Codec PnP ID :
> HDAUDIO\FUNC_01&VEN_10EC&DEV_0700&SUBSYS_10EC10F2
> + //The number of verb command block : 17
> +
> + // NID 0x12 : 0x411111F0
> + // NID 0x13 : 0x40000000
> + // NID 0x14 : 0x411111F0
> + // NID 0x15 : 0x411111F0
> + // NID 0x16 : 0x411111F0
> + // NID 0x17 : 0x90170110
> + // NID 0x18 : 0x411111F0
> + // NID 0x19 : 0x02A19040
> + // NID 0x1A : 0x411111F0
> + // NID 0x1B : 0x411111F0
> + // NID 0x1D : 0x40638029
> + // NID 0x1E : 0x411111F0
> + // NID 0x1F : 0x411111F0
> + // NID 0x21 : 0x02211020
> + // NID 0x29 : 0x411111F0
> +
> + //===== HDA Codec Subsystem ID Verb-table =====
> + //HDA Codec Subsystem ID : 0x10EC10F2
> + 0x001720F2,
> + 0x00172110,
> + 0x001722EC,
> + 0x00172310,
> +
> + //===== Pin Widget Verb-table =====
> + //Widget node 0x01 :
> + 0x0017FF00,
> + 0x0017FF00,
> + 0x0017FF00,
> + 0x0017FF00,
> + //Pin widget 0x12 - DMIC
> + 0x01271CF0,
> + 0x01271D11,
> + 0x01271E11,
> + 0x01271F41,
> + //Pin widget 0x13 - DMIC
> + 0x01371C00,
> + 0x01371D00,
> + 0x01371E00,
> + 0x01371F40,
> + //Pin widget 0x14 - FRONT (Port-D)
> + 0x01471CF0,
> + 0x01471D11,
> + 0x01471E11,
> + 0x01471F41,
> + //Pin widget 0x15 - I2S-OUT
> + 0x01571CF0,
> + 0x01571D11,
> + 0x01571E11,
> + 0x01571F41,
> + //Pin widget 0x16 - LINE3 (Port-B)
> + 0x01671CF0,
> + 0x01671D11,
> + 0x01671E11,
> + 0x01671F41,
> + //Pin widget 0x17 - I2S-OUT
> + 0x01771C10,
> + 0x01771D01,
> + 0x01771E17,
> + 0x01771F90,
> + //Pin widget 0x18 - I2S-IN
> + 0x01871CF0,
> + 0x01871D11,
> + 0x01871E11,
> + 0x01871F41,
> + //Pin widget 0x19 - MIC2 (Port-F)
> + 0x01971C40,
> + 0x01971D90,
> + 0x01971EA1,
> + 0x01971F02,
> + //Pin widget 0x1A - LINE1 (Port-C)
> + 0x01A71CF0,
> + 0x01A71D11,
> + 0x01A71E11,
> + 0x01A71F41,
> + //Pin widget 0x1B - LINE2 (Port-E)
> + 0x01B71CF0,
> + 0x01B71D11,
> + 0x01B71E11,
> + 0x01B71F41,
> + //Pin widget 0x1D - PC-BEEP
> + 0x01D71C29,
> + 0x01D71D80,
> + 0x01D71E63,
> + 0x01D71F40,
> + //Pin widget 0x1E - S/PDIF-OUT
> + 0x01E71CF0,
> + 0x01E71D11,
> + 0x01E71E11,
> + 0x01E71F41,
> + //Pin widget 0x1F - S/PDIF-IN
> + 0x01F71CF0,
> + 0x01F71D11,
> + 0x01F71E11,
> + 0x01F71F41,
> + //Pin widget 0x21 - HP-OUT (Port-I)
> + 0x02171C20,
> + 0x02171D10,
> + 0x02171E21,
> + 0x02171F02,
> + //Pin widget 0x29 - I2S-IN
> + 0x02971CF0,
> + 0x02971D11,
> + 0x02971E11,
> + 0x02971F41,
> + //Widget node 0x20 - 0 FAKE JD unplug
> + 0x02050008,
> + 0x0204A80F,
> + 0x02050008,
> + 0x0204A80F,
> +
> + //Widget node 0x20 - 1 : //remove NID 58 realted setting for ALC700
> bypass DAC02 DRE(NID5B bit14)
> + 0x05B50010,
> + 0x05B45C1D,
> + 0x0205006F,
> + 0x02040F8B, //Zeek, 0F8Bh
> +
> + //Widget node 0x20 -2:
> + 0x02050045,
> + 0x02045089,
> + 0x0205004A,
> + 0x0204201B,
> +
> + //Widget node 0x20 - 3 From JD detect
> + 0x02050008,
> + 0x0204A807,
> + 0x02050008,
> + 0x0204A807,
> +
> + //Widget node 0x20 - 4 Pull high ALC700 GPIO5 for AMP1305 PD pin and
> enable I2S BCLK first
> + 0x02050090,
> + 0x02040424,
> + 0x00171620,
> + 0x00171720,
> +
> + 0x00171520,
> + 0x01770740,
> + 0x01770740,
> + 0x01770740,
> +
> + //Widget node 0x20 for ALC1305 20181105 update 2W/4ohm to
> remove ALC1305 EQ setting and enable ALC1305 silencet detect to prevent I2S
> noise
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040000,
> + 0x02050028,
> + 0x02040000,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204006A,
> + 0x02050028,
> + 0x020400CF,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204006C,
> + 0x02050028,
> + 0x02045548,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204003F,
> + 0x02050028,
> + 0x02041000,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040004,
> + 0x02050028,
> + 0x02040600,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204003C,
> + 0x02050028,
> + 0x0204FFD0,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040080,
> + 0x02050028,
> + 0x02040080,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040080,
> + 0x02050028,
> + 0x02040880,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204003A,
> + 0x02050028,
> + 0x02040DFE,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204006A,
> + 0x02050028,
> + 0x0204005D,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204006C,
> + 0x02050028,
> + 0x02040442,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040005,
> + 0x02050028,
> + 0x02040880,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040006,
> + 0x02050028,
> + 0x02040000,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040008,
> + 0x02050028,
> + 0x0204B000,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204002E,
> + 0x02050028,
> + 0x02040800,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204006A,
> + 0x02050028,
> + 0x020400C3,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204006C,
> + 0x02050028,
> + 0x0204D4A0,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204006A,
> + 0x02050028,
> + 0x020400CC,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204006C,
> + 0x02050028,
> + 0x0204400A,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204006A,
> + 0x02050028,
> + 0x020400C1,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204006C,
> + 0x02050028,
> + 0x02040320,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040039,
> + 0x02050028,
> + 0x02040000,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204003B,
> + 0x02050028,
> + 0x0204FFFF,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204003C,
> + 0x02050028,
> + 0x0204FC20,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204006A,
> + 0x02050028,
> + 0x02040006,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204006C,
> + 0x02050028,
> + 0x020400C0,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204003C,
> + 0x02050028,
> + 0x0204FCA0,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204003C,
> + 0x02050028,
> + 0x0204FCE0,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204003C,
> + 0x02050028,
> + 0x0204FCF0,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040080,
> + 0x02050028,
> + 0x02040080,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040080,
> + 0x02050028,
> + 0x02040880,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040080,
> + 0x02050028,
> + 0x02040880,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204003C,
> + 0x02050028,
> + 0x0204FCE0,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204003C,
> + 0x02050028,
> + 0x0204FCA0,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204003C,
> + 0x02050028,
> + 0x0204FC20,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204006A,
> + 0x02050028,
> + 0x02040006,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204006C,
> + 0x02050028,
> + 0x02040000,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040080,
> + 0x02050028,
> + 0x02040000,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x020400C0,
> + 0x02050028,
> + 0x020401F0,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x020400C1,
> + 0x02050028,
> + 0x0204C1C7,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x020400C2,
> + 0x02050028,
> + 0x02041C00,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x020400C3,
> + 0x02050028,
> + 0x02040000,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x020400C4,
> + 0x02050028,
> + 0x02040200,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x020400C5,
> + 0x02050028,
> + 0x02040000,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x020400C6,
> + 0x02050028,
> + 0x020403E1,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x020400C7,
> + 0x02050028,
> + 0x02040F5A,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x020400C8,
> + 0x02050028,
> + 0x02041E1E,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x020400C9,
> + 0x02050028,
> + 0x0204083F,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x020400CA,
> + 0x02050028,
> + 0x020401F0,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x020400CB,
> + 0x02050028,
> + 0x0204C1C7,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x020400CC,
> + 0x02050028,
> + 0x02041C00,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x020400CD,
> + 0x02050028,
> + 0x02040000,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x020400CE,
> + 0x02050028,
> + 0x02040200,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x020400CF,
> + 0x02050028,
> + 0x02040000,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x020400D0,
> + 0x02050028,
> + 0x020403E1,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x020400D1,
> + 0x02050028,
> + 0x02040F5A,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x020400D2,
> + 0x02050028,
> + 0x02041E1E,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x020400D3,
> + 0x02050028,
> + 0x0204083F,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040062,
> + 0x02050028,
> + 0x02048000,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040063,
> + 0x02050028,
> + 0x02045F5F,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040064,
> + 0x02050028,
> + 0x02042000,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040065,
> + 0x02050028,
> + 0x02040000,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040066,
> + 0x02050028,
> + 0x02044004,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040067,
> + 0x02050028,
> + 0x02040802,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040068,
> + 0x02050028,
> + 0x0204890F,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040069,
> + 0x02050028,
> + 0x0204E021,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040070,
> + 0x02050028,
> + 0x02048012,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040071,
> + 0x02050028,
> + 0x02043450,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040072,
> + 0x02050028,
> + 0x02040123,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040073,
> + 0x02050028,
> + 0x02044543,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040074,
> + 0x02050028,
> + 0x02042100,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040075,
> + 0x02050028,
> + 0x02044321,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040076,
> + 0x02050028,
> + 0x02040000,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040050,
> + 0x02050028,
> + 0x02048200,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040051,
> + 0x02050028,
> + 0x02040707,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040052,
> + 0x02050028,
> + 0x02044090,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204006A,
> + 0x02050028,
> + 0x02040090,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204006C,
> + 0x02050028,
> + 0x0204721F,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040012,
> + 0x02050028,
> + 0x0204DFDF,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204009E,
> + 0x02050028,
> + 0x02040000,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040004,
> + 0x02050028,
> + 0x02040500,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040060,
> + 0x02050028,
> + 0x0204E213,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204003A,
> + 0x02050028,
> + 0x02041DFE,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204003F,
> + 0x02050028,
> + 0x02043000,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040040,
> + 0x02050028,
> + 0x0204000C,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x02040046,
> + 0x02050028,
> + 0x0204422E,
> + 0x02050029,
> + 0x0204B024,
> +
> + 0x02050024,
> + 0x02040010,
> + 0x02050026,
> + 0x0204004B,
> + 0x02050028,
> + 0x02040000,
> + 0x02050029,
> + 0x0204B024
> +); // WhlHdaVerbTableAlc700
> +
> +#endif // _PCH_HDA_VERB_TABLES_H_
> +
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/
> PeiBoardInitPostMemLib.c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/
> PeiBoardInitPostMemLib.c
> new file mode 100644
> index 0000000000..d268b216a9
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/
> PeiBoardInitPostMemLib.c
> @@ -0,0 +1,40 @@
> +/** @file
> + Platform Hook Library instances
> +
> +
> + Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include <PiPei.h>
> +#include <Library/BaseLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/BoardInitLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/DebugLib.h>
> +
> +EFI_STATUS
> +EFIAPI
> +UpXtremeBoardInitBeforeSiliconInit (
> + VOID
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +BoardInitBeforeSiliconInit (
> + VOID
> + )
> +{
> + UpXtremeBoardInitBeforeSiliconInit ();
> + return EFI_SUCCESS;
> +}
> +
> +EFI_STATUS
> +EFIAPI
> +BoardInitAfterSiliconInit (
> + VOID
> + )
> +{
> + return EFI_SUCCESS;
> +}
> +
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/
> PeiBoardInitPostMemLib.inf
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/
> PeiBoardInitPostMemLib.inf
> new file mode 100644
> index 0000000000..1565279938
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/
> PeiBoardInitPostMemLib.inf
> @@ -0,0 +1,57 @@
> +## @file
> +# Component information file for UpXtremeInitLib in PEI post memory
> phase.
> +#
> +#
> +# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = PeiBoardPostMemInitLib
> + FILE_GUID =
> 7fcc3900-d38d-419f-826b-72481e8b5509
> + MODULE_TYPE = PEIM
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = BoardInitLib
> +
> +[LibraryClasses]
> + BaseLib
> + BaseMemoryLib
> + DebugLib
> + GpioExpanderLib
> + GpioLib
> + HdaVerbTableLib
> + MemoryAllocationLib
> + PcdLib
> + SiliconInitLib
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + SecurityPkg/SecurityPkg.dec
> + IntelSiliconPkg/IntelSiliconPkg.dec
> + CoffeelakeSiliconPkg/SiPkg.dec
> + MinPlatformPkg/MinPlatformPkg.dec
> + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec
> +
> +[Sources]
> + PeiUpXtremeInitPostMemLib.c
> + PeiBoardInitPostMemLib.c
> + GpioTableDefault.c
> + GpioTableUpXtreme.c
> +
> +[Pcd]
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableSize
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableTouchPanel
> +
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTable
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTableSize
> +
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardUcmcGpioTable
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardUcmcGpioTableSize
> +
> + gEfiSecurityPkgTokenSpaceGuid.PcdTpm2CurrentIrqNum
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/
> PeiBoardInitPreMemLib.c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/
> PeiBoardInitPreMemLib.c
> new file mode 100644
> index 0000000000..d7ad81d4c2
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/
> PeiBoardInitPreMemLib.c
> @@ -0,0 +1,106 @@
> +/** @file
> + Platform Hook Library instances
> +
> +
> + Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include <PiPei.h>
> +#include <Library/BaseLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/BoardInitLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/DebugLib.h>
> +
> +EFI_STATUS
> +EFIAPI
> +UpXtremeBoardDetect (
> + VOID
> + );
> +
> +EFI_BOOT_MODE
> +EFIAPI
> +UpXtremeBoardBootModeDetect (
> + VOID
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +UpXtremeBoardDebugInit (
> + VOID
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +UpXtremeBoardInitBeforeMemoryInit (
> + VOID
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +BoardDetect (
> + VOID
> + )
> +{
> + UpXtremeBoardDetect ();
> + return EFI_SUCCESS;
> +}
> +
> +EFI_STATUS
> +EFIAPI
> +BoardDebugInit (
> + VOID
> + )
> +{
> + UpXtremeBoardDebugInit ();
> + return EFI_SUCCESS;
> +}
> +
> +EFI_BOOT_MODE
> +EFIAPI
> +BoardBootModeDetect (
> + VOID
> + )
> +{
> + return UpXtremeBoardBootModeDetect ();
> +}
> +
> +EFI_STATUS
> +EFIAPI
> +BoardInitBeforeMemoryInit (
> + VOID
> + )
> +{
> + UpXtremeBoardInitBeforeMemoryInit ();
> + return EFI_SUCCESS;
> +}
> +
> +EFI_STATUS
> +EFIAPI
> +BoardInitAfterMemoryInit (
> + VOID
> + )
> +{
> + return EFI_SUCCESS;
> +}
> +
> +EFI_STATUS
> +EFIAPI
> +BoardInitBeforeTempRamExit (
> + VOID
> + )
> +{
> + return EFI_SUCCESS;
> +}
> +
> +EFI_STATUS
> +EFIAPI
> +BoardInitAfterTempRamExit (
> + VOID
> + )
> +{
> + return EFI_SUCCESS;
> +}
> +
> +
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/
> PeiBoardInitPreMemLib.inf
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/
> PeiBoardInitPreMemLib.inf
> new file mode 100644
> index 0000000000..5166a915a2
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/
> PeiBoardInitPreMemLib.inf
> @@ -0,0 +1,124 @@
> +## @file
> +# Component information file for PEI UpXtreme Board Init Pre-Mem Library
> +#
> +#
> +# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = PeiBoardInitPreMemLib
> + FILE_GUID =
> ec3675bc-1470-417d-826e-37378140213d
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = BoardInitLib
> +
> +[LibraryClasses]
> + BaseLib
> + DebugLib
> + BaseMemoryLib
> + MemoryAllocationLib
> + PcdLib
> + SiliconInitLib
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + IntelSiliconPkg/IntelSiliconPkg.dec
> + CoffeelakeSiliconPkg/SiPkg.dec
> + MinPlatformPkg/MinPlatformPkg.dec
> + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec
> +
> +[Sources]
> + PeiUpXtremeDetect.c
> + PeiUpXtremeInitPreMemLib.c
> + UpXtremeHsioPtssTables.c
> + PeiBoardInitPreMemLib.c
> +
> +[Guids]
> + gDebugConfigHobGuid ## CONSUMES
> +
> +[FixedPcd]
> + gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable
> +
> +[Pcd]
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioConfigDefaultPort
> +
> + # PCH-LP HSIO PTSS Table
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size
> +
> + # SA Misc Config
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSaMiscUserBd
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMap
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMapSize
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2Dram
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdData
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdDataSize
> +
> + # PEG Reset By GPIO
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0WakeGpioNo
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstExpanderNo
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstGpioNo
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstActive
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableGpioNo
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableActive
> +
> +
> + # SPD Address Table
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable0
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable1
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable2
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable3
> +
> + # USB 2.0 Port AFE
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port0Afe
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port1Afe
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port2Afe
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port3Afe
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port4Afe
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port5Afe
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port6Afe
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port7Afe
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port8Afe
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port9Afe
> +
> + # USB 2.0 Port Over Current Pin
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort0
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort1
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort2
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort3
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort4
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort5
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort6
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort7
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort8
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort9
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort10
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort11
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort12
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort13
> +
> + # USB 3.0 Port Over Current Pin
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort0
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort1
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort2
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort3
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort4
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort5
> +
> + # Misc
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdIoExpanderPresent
> +
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/
> PeiMultiBoardInitPostMemLib.c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/
> PeiMultiBoardInitPostMemLib.c
> new file mode 100644
> index 0000000000..ddcd8ed15f
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/
> PeiMultiBoardInitPostMemLib.c
> @@ -0,0 +1,41 @@
> +/** @file
> + Platform Hook Library instances
> +
> +
> + Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include <PiPei.h>
> +#include <Library/BaseLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/BoardInitLib.h>
> +#include <Library/MultiBoardInitSupportLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/DebugLib.h>
> +
> +#include <PlatformBoardId.h>
> +
> +EFI_STATUS
> +EFIAPI
> +UpXtremeBoardInitBeforeSiliconInit (
> + VOID
> + );
> +
> +BOARD_POST_MEM_INIT_FUNC mUpXtremeBoardInitFunc = {
> + UpXtremeBoardInitBeforeSiliconInit,
> + NULL, // BoardInitAfterSiliconInit
> +};
> +
> +EFI_STATUS
> +EFIAPI
> +PeiUpXtremeMultiBoardInitLibConstructor (
> + VOID
> + )
> +{
> + if (LibPcdGetSku () == BoardIdUpXtreme) {
> + return RegisterBoardPostMemInit (&mUpXtremeBoardInitFunc);
> + }
> + return EFI_SUCCESS;
> +}
> +
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/
> PeiMultiBoardInitPostMemLib.inf
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/
> PeiMultiBoardInitPostMemLib.inf
> new file mode 100644
> index 0000000000..87e9dfde92
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/
> PeiMultiBoardInitPostMemLib.inf
> @@ -0,0 +1,202 @@
> +## @file
> +# Component information file for UpXtremeInitLib in PEI post memory
> phase.
> +#
> +#
> +# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = PeiUpXtremeMultiBoardInitLib
> + FILE_GUID =
> C7D39F17-E5BA-41D9-8DFE-FF9017499280
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = NULL
> + CONSTRUCTOR =
> PeiUpXtremeMultiBoardInitLibConstructor
> +
> +[LibraryClasses]
> + BaseLib
> + DebugLib
> + BaseMemoryLib
> + MemoryAllocationLib
> + GpioExpanderLib
> + PcdLib
> + MultiBoardInitSupportLib
> + HdaVerbTableLib
> + PeiPlatformHookLib
> + PeiPolicyInitLib
> + PchInfoLib
> + SiliconInitLib
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + SecurityPkg/SecurityPkg.dec
> + CoffeelakeSiliconPkg/SiPkg.dec
> + IntelSiliconPkg/IntelSiliconPkg.dec
> + MinPlatformPkg/MinPlatformPkg.dec
> + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec
> +
> +[Sources]
> + PeiUpXtremeInitPostMemLib.c
> + PeiMultiBoardInitPostMemLib.c
> + GpioTableDefault.c
> + GpioTableUpXtreme.c
> +
> +[Pcd]
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableSize
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableTouchPanel
> +
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTable
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTableSize
> +
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardUcmcGpioTable
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardUcmcGpioTableSize
> +
> + #===========================================================
> + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase
> + # Board Init Table List
> +
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTablePreMem
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTablePreMemSize
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOnEar
> lyPreMem
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOnEar
> lyPreMemSize
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOffEar
> lyPreMem
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOffEar
> lyPreMemSize
> +
> + # WWAN Full Card Power Off and reset pins
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdWwanFullCardPowerOffGpio
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdWwanBbrstGpio
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdWwanPerstGpio
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdWwanPerstGpioPolarity
> +
> + # SA Misc Config
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSaMiscMmioSizeAdjustment
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqPinsInterleavedContro
> l
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqPinsInterleaved
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSaDdrFreqLimit
> +
> + # Display DDI
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSaDisplayConfigTable
> ## PRODUCES
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSaDisplayConfigTableSize
> ## PRODUCES
> +
> + # PEG Reset By GPIO
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPegGpioResetControl
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPegGpioResetSupoort
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPeg0ResetGpioPad
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPeg0ResetGpioActive
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPeg3ResetGpioPad
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPeg3ResetGpioActive
> +
> + # PCIE RTD3 GPIO
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRootPortDev
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRootPortFunc
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRootPortIndex
> +
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0GpioSupport
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1GpioSupport
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1WakeGpioNo
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1HoldRstExpanderNo
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1HoldRstGpioNo
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1HoldRstActive
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1PwrEnableExpanderNo
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1PwrEnableGpioNo
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1PwrEnableActive
> +
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2GpioSupport
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2WakeGpioNo
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2HoldRstExpanderNo
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2HoldRstGpioNo
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2HoldRstActive
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2PwrEnableExpanderNo
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2PwrEnableGpioNo
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2PwrEnableActive
> +
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3GpioSupport
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3WakeGpioNo
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3HoldRstExpanderNo
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3HoldRstGpioNo
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3HoldRstActive
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3PwrEnableExpanderNo
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3PwrEnableGpioNo
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3PwrEnableActive
> +
> + # CA Vref Configuration
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcCaVrefConfig
> +
> + # PCIe Clock Info
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock0
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock1
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock2
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock3
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock4
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock5
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock6
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock7
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock8
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock9
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock10
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock11
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock12
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock13
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock14
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock15
> +
> + # USB 2.0 Port AFE
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port10Afe
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port11Afe
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port12Afe
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port13Afe
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port14Afe
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port15Afe
> +
> + # USB 2.0 Port Over Current Pin
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort14
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort15
> +
> + # USB 3.0 Port Over Current Pin
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort6
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort7
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort8
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort9
> +
> + # GPIO Group Tier
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw0
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw1
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw2
> +
> + # Pch PmConfig Policy
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSlpS0VmRuntimeControl
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSlpS0Vm070VSupport
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSlpS0Vm075VSupport
> +
> + # Misc
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPc8374SioKbcPresent
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdOddPowerInitEnable
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdIvCamInitPresent
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRecoveryModeGpio
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMobileDramPresent
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdCpuVboostEnable
> +
> +
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpdPresent
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardRev
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardBomId
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPlatformType
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDualDimmPerChannelBoard
> Type
> +
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable2
> ## CONSUMES
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable2Size
> ## CONSUMES
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDebugUsbUartEnable
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMipiCamGpioEnable
> + # TPM interrupt
> + gEfiSecurityPkgTokenSpaceGuid.PcdTpm2CurrentIrqNum
> +
> +[Guids]
> + gAttemptUsbFirstHotkeyInfoHobGuid ## CONSUMES
> + gCnlPchLpChipsetInitTableDxGuid ## CONSUMES
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/
> PeiMultiBoardInitPreMemLib.c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/
> PeiMultiBoardInitPreMemLib.c
> new file mode 100644
> index 0000000000..18a44ca534
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/
> PeiMultiBoardInitPreMemLib.c
> @@ -0,0 +1,83 @@
> +/** @file
> + Platform Hook Library instances
> +
> +
> + Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include <PiPei.h>
> +#include <Library/BaseLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/BoardInitLib.h>
> +#include <Library/MultiBoardInitSupportLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/DebugLib.h>
> +
> +#include <PlatformBoardId.h>
> +
> +EFI_STATUS
> +EFIAPI
> +UpXtremeBoardDetect (
> + VOID
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +UpXtremeMultiBoardDetect (
> + VOID
> + );
> +
> +EFI_BOOT_MODE
> +EFIAPI
> +UpXtremeBoardBootModeDetect (
> + VOID
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +UpXtremeBoardDebugInit (
> + VOID
> + );
> +
> +EFI_STATUS
> +EFIAPI
> +UpXtremeBoardInitBeforeMemoryInit (
> + VOID
> + );
> +
> +BOARD_DETECT_FUNC mUpXtremeBoardDetectFunc = {
> + UpXtremeMultiBoardDetect
> +};
> +
> +BOARD_PRE_MEM_INIT_FUNC mUpXtremeBoardPreMemInitFunc = {
> + UpXtremeBoardDebugInit,
> + UpXtremeBoardBootModeDetect,
> + UpXtremeBoardInitBeforeMemoryInit,
> + NULL, // BoardInitAfterMemoryInit
> + NULL, // BoardInitBeforeTempRamExit
> + NULL, // BoardInitAfterTempRamExit
> +};
> +
> +EFI_STATUS
> +EFIAPI
> +UpXtremeMultiBoardDetect (
> + VOID
> + )
> +{
> + UpXtremeBoardDetect ();
> + if (LibPcdGetSku () == BoardIdUpXtreme) {
> + RegisterBoardPreMemInit (&mUpXtremeBoardPreMemInitFunc);
> + }
> + return EFI_SUCCESS;
> +}
> +
> +EFI_STATUS
> +EFIAPI
> +PeiUpXtremeMultiBoardInitPreMemLibConstructor (
> + VOID
> + )
> +{
> + return RegisterBoardDetect (&mUpXtremeBoardDetectFunc);
> +}
> +
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/
> PeiMultiBoardInitPreMemLib.inf
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/
> PeiMultiBoardInitPreMemLib.inf
> new file mode 100644
> index 0000000000..2903bdacae
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/
> PeiMultiBoardInitPreMemLib.inf
> @@ -0,0 +1,308 @@
> +## @file
> +# Component information file for PEI UpXtreme Board Init Pre-Mem Library
> +#
> +#
> +# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME =
> PeiUpXtremeMultiBoardInitPreMemLib
> + FILE_GUID =
> EA05BD43-136F-45EE-BBBA-27D75817574F
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = NULL
> + CONSTRUCTOR =
> PeiUpXtremeMultiBoardInitPreMemLibConstructor
> +
> +[LibraryClasses]
> + BaseLib
> + BaseMemoryLib
> + DebugLib
> + GpioLib
> + MemoryAllocationLib
> + MultiBoardInitSupportLib
> + OcWdtLib
> + PcdLib
> + PchResetLib
> + PeiPlatformHookLib
> + PeiPolicyInitLib
> + PlatformHookLib
> + SiliconInitLib
> + StallPpiLib
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + UefiCpuPkg/UefiCpuPkg.dec
> + IntelSiliconPkg/IntelSiliconPkg.dec
> + CoffeelakeSiliconPkg/SiPkg.dec
> + MinPlatformPkg/MinPlatformPkg.dec
> + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec
> +
> +[Sources]
> + PeiUpXtremeInitPreMemLib.c
> + UpXtremeHsioPtssTables.c
> + UpXtremeSpdTable.c
> + PeiMultiBoardInitPreMemLib.c
> + PeiUpXtremeDetect.c
> + BoardSaInitPreMemLib.c
> + BoardPchInitPreMemLib.c
> + BoardFuncInitPreMem.c
> +
> +[Ppis]
> + gEfiPeiReadOnlyVariable2PpiGuid
> + gEfiPeiMemoryDiscoveredPpiGuid ## CONSUMES
> + gEfiPeiResetPpiGuid ## PRODUCES
> +
> +[Guids]
> + gDebugConfigHobGuid ## CONSUMES
> + gPchGeneralPreMemConfigGuid ## CONSUMES
> + gTcoWdtHobGuid ## CONSUMES
> +
> +[Pcd]
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioConfigDefaultPort
> +
> + # PCH-LP HSIO PTSS Table
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size
> +
> + # PCH-H HSIO PTSS Table
> +
> #gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1
> +
> #gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2
> +
> #gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1Siz
> e
> +
> #gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2Siz
> e
> +
> + # SA Misc Config
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSaMiscUserBd
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMap
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMapSize
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2Dram
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdData
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdDataSize
> +
> + # PEG Reset By GPIO
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0WakeGpioNo
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstExpanderNo
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstGpioNo
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstActive
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableGpioNo
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableActive
> +
> +
> + # SPD Address Table
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable0
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable1
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable2
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable3
> +
> + # USB 2.0 Port AFE
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port0Afe
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port1Afe
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port2Afe
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port3Afe
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port4Afe
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port5Afe
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port6Afe
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port7Afe
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port8Afe
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port9Afe
> +
> + # USB 2.0 Port Over Current Pin
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort0
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort1
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort2
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort3
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort4
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort5
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort6
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort7
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort8
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort9
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort10
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort11
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort12
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort13
> +
> + # USB 3.0 Port Over Current Pin
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort0
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort1
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort2
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort3
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort4
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort5
> +
> + # Misc
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdIoExpanderPresent
> +
> + #===========================================================
> + # Board Init Table List
> +
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTablePreMem
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTablePreMemSize
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOnEar
> lyPreMem
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOnEar
> lyPreMemSize
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOffEar
> lyPreMem
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOffEar
> lyPreMemSize
> +
> + # WWAN Full Card Power Off and reset pins
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdWwanFullCardPowerOffGpio
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdWwanBbrstGpio
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdWwanPerstGpio
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdWwanPerstGpioPolarity
> +
> + # SA Misc Config
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSaMiscMmioSizeAdjustment
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqPinsInterleavedContro
> l
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqPinsInterleaved
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSaDdrFreqLimit
> +
> + # Display DDI
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSaDisplayConfigTable
> ## PRODUCES
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSaDisplayConfigTableSize
> ## PRODUCES
> +
> + # PEG Reset By GPIO
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPegGpioResetControl
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPegGpioResetSupoort
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPeg0ResetGpioPad
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPeg0ResetGpioActive
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPeg3ResetGpioPad
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPeg3ResetGpioActive
> +
> + # PCIE RTD3 GPIO
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRootPortDev
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRootPortFunc
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRootPortIndex
> +
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0GpioSupport
> +
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1GpioSupport
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1WakeGpioNo
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1HoldRstExpanderNo
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1HoldRstGpioNo
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1HoldRstActive
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1PwrEnableExpanderNo
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1PwrEnableGpioNo
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1PwrEnableActive
> +
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2GpioSupport
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2WakeGpioNo
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2HoldRstExpanderNo
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2HoldRstGpioNo
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2HoldRstActive
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2PwrEnableExpanderNo
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2PwrEnableGpioNo
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2PwrEnableActive
> +
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3GpioSupport
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3WakeGpioNo
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3HoldRstExpanderNo
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3HoldRstGpioNo
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3HoldRstActive
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3PwrEnableExpanderNo
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3PwrEnableGpioNo
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3PwrEnableActive
> +
> + # CA Vref Configuration
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcCaVrefConfig
> +
> + # PCIe Clock Info
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock0
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock1
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock2
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock3
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock4
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock5
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock6
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock7
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock8
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock9
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock10
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock11
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock12
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock13
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock14
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock15
> +
> + # USB 2.0 Port AFE
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port10Afe
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port11Afe
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port12Afe
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port13Afe
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port14Afe
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port15Afe
> +
> + # USB 2.0 Port Over Current Pin
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort14
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort15
> +
> + # USB 3.0 Port Over Current Pin
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort6
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort7
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort8
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort9
> +
> + # GPIO Group Tier
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw0
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw1
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw2
> +
> + # Pch PmConfig Policy
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSlpS0VmRuntimeControl
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSlpS0Vm070VSupport
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSlpS0Vm075VSupport
> +
> + # Misc
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPc8374SioKbcPresent
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdOddPowerInitEnable
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdIvCamInitPresent
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRecoveryModeGpio
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMobileDramPresent
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdCpuVboostEnable
> +
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpdPresent
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardRev
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardBomId
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPlatformType
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDualDimmPerChannelBoard
> Type
> +
> + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress
> + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize
> + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES
> + gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength ##
> CONSUMES
> +
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieWwanEnable
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdWwanResetWorkaround
> ## PRODUCES
> + gSiPkgTokenSpaceGuid.PcdTcoBaseAddress
> +
> + gSiPkgTokenSpaceGuid.PcdSerialIoUartEnable ## CONSUMES
> + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate ##
> CONSUMES
> + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel ## CONSUMES
> +
> + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize
> + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemorySize
> + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize
> + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize
> + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize
> + gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
> +
> +[FixedPcd]
> + gSiPkgTokenSpaceGuid.PcdMchBaseAddress ##
> CONSUMES
> + gSiPkgTokenSpaceGuid.PcdMchMmioSize ##
> CONSUMES
> + gPlatformModuleTokenSpaceGuid.PcdDmiBaseAddress ##
> CONSUMES
> + gPlatformModuleTokenSpaceGuid.PcdDmiMmioSize ##
> CONSUMES
> + gPlatformModuleTokenSpaceGuid.PcdEpBaseAddress ##
> CONSUMES
> + gPlatformModuleTokenSpaceGuid.PcdEpMmioSize ##
> CONSUMES
> + gPlatformModuleTokenSpaceGuid.PcdGdxcBaseAddress ##
> CONSUMES
> + gPlatformModuleTokenSpaceGuid.PcdGdxcMmioSize ##
> CONSUMES
> + gPlatformModuleTokenSpaceGuid.PcdApicLocalAddress ## CONSUMES
> + gPlatformModuleTokenSpaceGuid.PcdApicLocalMmioSize ## CONSUMES
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/
> PeiUpXtremeDetect.c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/
> PeiUpXtremeDetect.c
> new file mode 100644
> index 0000000000..5860ab364b
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/
> PeiUpXtremeDetect.c
> @@ -0,0 +1,192 @@
> +/** @file
> +
> + Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include <PiPei.h>
> +#include <SaPolicyCommon.h>
> +#include <Library/DebugLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/HobLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/PchCycleDecodingLib.h>
> +#include <Library/PciLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/BaseMemoryLib.h>
> +
> +#include <Library/PeiSaPolicyLib.h>
> +#include <Library/BoardInitLib.h>
> +#include <PchAccess.h>
> +#include <Library/GpioNativeLib.h>
> +#include <Library/GpioLib.h>
> +#include <Library/PchPcrLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/GpioExpanderLib.h>
> +
> +
> +#include <GpioPinsSklLp.h>
> +#include <GpioPinsSklH.h>
> +#include <SioRegs.h>
> +#include <GpioPinsCnlLp.h>
> +#include <CpuRegs.h>
> +//#include <CpuDataStruct.h>
> +#include <CpuAccess.h>
> +#include <Register/Cpuid.h>
> +#include "UpXtremeInit.h"
> +#include <ConfigBlock.h>
> +#include <ConfigBlock/MemoryConfig.h>
> +
> +
> +
> +
> +CONST UINT32 mUpxGpioBomPad[] = {
> + GPIO_CNL_LP_GPP_C10, // BRD_ID2
> + GPIO_CNL_LP_GPP_C9, // BRD_ID1
> + GPIO_CNL_LP_GPP_C8, // BRD_ID0
> + GPIO_CNL_LP_GPP_A23, // DDR_ID2
> + GPIO_CNL_LP_GPP_A18, // DDR_ID1
> + GPIO_CNL_LP_GPP_C11, // DDR_ID0
> +};
> +
> +CONST GPIO_INIT_CONFIG mUpxBomGpioTemplate = {
> + GPIO_CNL_LP_GPP_C10, {GpioPadModeGpio, GpioHostOwnGpio,
> GpioDirIn, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}
> +};
> +
> +/**
> + Prints the processor information
> +**/
> +VOID
> +PrintCpuInformation (
> + VOID
> + )
> +{
> + UINT32 MaximumExtendedFunction;
> + UINT16 CpuDid;
> + UINT32 CpuFamilyModel;
> + UINT8 CpuStepping;
> + EFI_CPUID_REGISTER Cpuid;
> + //
> + // Array to store brand string from 3 brand string leafs with
> + // 4 32-bit brand string values per leaf and an extra value to
> + // null terminate the string.
> + //
> + UINT32 BrandString[3 * 4 + 1];
> + CHAR8 *AsciiBrandString;
> + CHAR16 *UnicodeBrandString;
> + UINTN Length;
> +
> + AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaximumExtendedFunction,
> NULL, NULL, NULL);
> +
> + ZeroMem (&BrandString, sizeof (BrandString));
> + if (CPUID_BRAND_STRING1 <= MaximumExtendedFunction) {
> + AsmCpuid (
> + CPUID_BRAND_STRING1,
> + &BrandString[0],
> + &BrandString[1],
> + &BrandString[2],
> + &BrandString[3]
> + );
> + }
> + if (CPUID_BRAND_STRING2 <= MaximumExtendedFunction) {
> + AsmCpuid (
> + CPUID_BRAND_STRING2,
> + &BrandString[4],
> + &BrandString[5],
> + &BrandString[6],
> + &BrandString[7]
> + );
> + }
> + if (CPUID_BRAND_STRING3 <= MaximumExtendedFunction) {
> + AsmCpuid (
> + CPUID_BRAND_STRING3,
> + &BrandString[8],
> + &BrandString[9],
> + &BrandString[10],
> + &BrandString[11]
> + );
> + }
> +
> + //
> + // Skip spaces at the beginning of the brand string
> + //
> + for (AsciiBrandString = (CHAR8 *)BrandString; *AsciiBrandString == ' ';
> AsciiBrandString++);
> +
> + DEBUG ((DEBUG_INFO, "Processor Brand String = %a\n",
> AsciiBrandString));
> +
> + //
> + // Convert ASCII brand string to an allocated Unicode brand string
> + //
> + Length = AsciiStrLen (AsciiBrandString) + 1;
> + UnicodeBrandString = AllocatePool (Length * sizeof (CHAR16));
> + AsciiStrToUnicodeStrS (AsciiBrandString, UnicodeBrandString, Length);
> +
> + DEBUG ((DEBUG_INFO, "Processor Unicode Brand String = %s\n",
> UnicodeBrandString));
> +
> + ///
> + /// Read the CPUID & DID information
> + ///
> + AsmCpuid (CPUID_VERSION_INFO, &Cpuid.RegEax, &Cpuid.RegEbx,
> &Cpuid.RegEcx, &Cpuid.RegEdx);
> + CpuFamilyModel = Cpuid.RegEax & CPUID_FULL_FAMILY_MODEL;
> + CpuStepping = (Cpuid.RegEax & 0xF);
> + CpuDid = PciRead16 (PCI_LIB_ADDRESS (SA_MC_BUS, SA_MC_DEV,
> SA_MC_FUN, R_SA_MC_DEVICE_ID));
> +
> + DEBUG ((DEBUG_ERROR, "CpuFamilyModel 0x%X, CpuStepping 0x%X,
> CpuDid 0x%X\n", CpuFamilyModel, CpuStepping, CpuDid));
> +}
> +
> +
> +EFI_STATUS
> +EFIAPI
> +UpXtremeBoardDetect (
> + VOID
> + )
> +{
> + UINT32 GpioData;
> + GPIO_INIT_CONFIG UpxBomGpioTemplate;
> + UINT8 BomId;
> + UINT8 Index;
> + UINTN NumberOfGpios;
> + EFI_STATUS Status;
> +
> + DEBUG ((DEBUG_INFO, "UpXtremeDetectionCallback\n"));
> +
> + PrintCpuInformation ();
> +
> + if (LibPcdGetSku () != 0) {
> + return EFI_SUCCESS;
> + }
> +
> + BomId = 0;
> + NumberOfGpios = ARRAY_SIZE (mUpxGpioBomPad);
> +
> + LibPcdSetSku (BoardIdUpXtreme);
> +
> + DEBUG ((DEBUG_INFO, "SKU_ID: 0x%x\n", LibPcdGetSku ()));
> + ASSERT (LibPcdGetSku () == BoardIdUpXtreme);
> +
> + CopyMem (&UpxBomGpioTemplate, &mUpxBomGpioTemplate,
> sizeof(UpxBomGpioTemplate));
> +
> + // Initialize all GPIO pins to input
> + for (Index = 0; Index < NumberOfGpios; Index++) {
> + UpxBomGpioTemplate.GpioPad = mUpxGpioBomPad[Index];
> + GpioConfigurePads (1, &UpxBomGpioTemplate);
> + }
> +
> + // Sample the GPIO pin level
> + for (Index = 0; Index < NumberOfGpios; Index++) {
> + Status = GpioGetInputValue (mUpxGpioBomPad[Index], &GpioData);
> + if (EFI_ERROR(Status)) {
> + break;
> + }
> + BomId = (BomId << 1) + (GpioData & 1);
> + }
> +
> + if (Index == NumberOfGpios) {
> + PcdSet8S(PcdBoardBomId, BomId);
> + }
> +
> + DEBUG ((DEBUG_INFO, "BOM_ID 0x%x\n", PcdGet8(PcdBoardBomId)));
> + return EFI_SUCCESS;
> +}
> +
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/
> PeiUpXtremeInitPostMemLib.c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/
> PeiUpXtremeInitPostMemLib.c
> new file mode 100644
> index 0000000000..65433bc453
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/
> PeiUpXtremeInitPostMemLib.c
> @@ -0,0 +1,416 @@
> +/** @file
> +
> + Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include <PiPei.h>
> +#include <SaPolicyCommon.h>
> +#include <Library/DebugLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/HdaVerbTableLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/HobLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/PchCycleDecodingLib.h>
> +#include <Library/PciLib.h>
> +#include <Library/PeiSaPolicyLib.h>
> +#include <Library/BoardInitLib.h>
> +#include <Library/ConfigBlockLib.h>
> +#include <PchAccess.h>
> +#include <Library/GpioNativeLib.h>
> +#include <Library/GpioLib.h>
> +#include <GpioPinsSklLp.h>
> +#include <GpioPinsSklH.h>
> +#include <Library/GpioExpanderLib.h>
> +#include <SioRegs.h>
> +#include <Library/PchPcrLib.h>
> +#include <IoExpander.h>
> +#include <AttemptUsbFirst.h>
> +#include <PeiPlatformHookLib.h>
> +#include <Library/PeiPolicyInitLib.h>
> +#include <Library/PchInfoLib.h>
> +#include <FirwmareConfigurations.h>
> +#include "UpXtremeInit.h"
> +
> +/**
> +GPIO init function for PEI post memory phase.
> +
> +@param[in] BoardId An unsigned integrer represent the board id.
> +
> +@retval EFI_SUCCESS The function completed successfully.
> +**/
> +EFI_STATUS
> +BoardGpioInit (
> + IN UINT16 BoardId
> + )
> +{
> + //
> + // GPIO Table Init.
> + //
> + switch (BoardId) {
> +
> + case BoardIdUpXtreme:
> + PcdSet32S (PcdBoardGpioTable, (UINTN) mGpioTableUpXtreme);
> + PcdSet16S (PcdBoardGpioTableSize, mGpioTableUpXtremeSize);
> + break;
> +
> + default:
> + DEBUG ((DEBUG_INFO, "For Unknown Board ID..Use Default GPIO
> Table...\n"));
> + PcdSet32S (PcdBoardGpioTable, (UINTN) mGpioTableDefault);
> + PcdSet16S (PcdBoardGpioTableSize, mGpioTableDefaultSize);
> + break;
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> +Touch panel GPIO init function for PEI post memory phase.
> +
> +@param[in] BoardId An unsigned integrer represent the board id.
> +
> +@retval EFI_SUCCESS The function completed successfully.
> +**/
> +EFI_STATUS
> +TouchPanelGpioInit (
> + IN UINT16 BoardId
> + )
> +{
> + switch (BoardId) {
> + default:
> + PcdSet32S(PcdBoardGpioTableTouchPanel, 0);
> + break;
> + }
> + return EFI_SUCCESS;
> +}
> +
> +/**
> +Misc. init function for PEI post memory phase.
> +
> +@param[in] BoardId An unsigned integrer represent the board id.
> +
> +@retval EFI_SUCCESS The function completed successfully.
> +**/
> +EFI_STATUS
> +BoardMiscInit (
> + IN UINT16 BoardId
> + )
> +{
> + PcdSetBoolS(PcdDebugUsbUartEnable, FALSE);
> +
> + switch (BoardId) {
> +
> + // todo for UP Xtreme
> + case BoardIdWhiskeyLakeRvp:
> +
> + PcdSetBoolS(PcdMipiCamGpioEnable, TRUE);
> + break;
> +
> + default:
> + PcdSetBoolS(PcdMipiCamGpioEnable, FALSE);
> + break;
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> +Security GPIO init function for PEI post memory phase.
> +
> +@param[in] BoardId An unsigned integrer represent the board id.
> +
> +@retval EFI_SUCCESS The function completed successfully.
> +**/
> +EFI_STATUS
> +BoardSecurityInit (
> + IN UINT16 BoardId
> + )
> +{
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Board configuration initialization in the post-memory boot phase.
> +
> +**/
> +VOID
> +BoardConfigInit (
> + VOID
> + )
> +{
> + EFI_STATUS Status;
> + UINT16 BoardId;
> +
> + BoardId = BoardIdUpXtreme;
> +
> + Status = BoardGpioInit (BoardId);
> + ASSERT_EFI_ERROR (Status);
> +
> + Status = TouchPanelGpioInit (BoardId);
> + ASSERT_EFI_ERROR (Status);
> +
> + Status = HdaVerbTableInit (BoardId);
> + ASSERT_EFI_ERROR (Status);
> +
> + Status = BoardMiscInit (BoardId);
> + ASSERT_EFI_ERROR (Status);
> +
> + Status = BoardSecurityInit (BoardId);
> + ASSERT_EFI_ERROR (Status);
> +}
> +
> +//@todo Review this functionality and if it is required for WHL SDS
> +/**
> +Create the HOB for hotkey status for 'Attempt USB First' feature
> +
> +@retval EFI_SUCCESS HOB Creating successful.
> +@retval Others HOB Creating failed.
> +**/
> +EFI_STATUS
> +CreateAttemptUsbFirstHotkeyInfoHob (
> + VOID
> + )
> +{
> + EFI_STATUS Status;
> + ATTEMPT_USB_FIRST_HOTKEY_INFO AttemptUsbFirstHotkeyInfo;
> +
> + Status = EFI_SUCCESS;
> +
> + ZeroMem(
> + &AttemptUsbFirstHotkeyInfo,
> + sizeof(AttemptUsbFirstHotkeyInfo)
> + );
> +
> + AttemptUsbFirstHotkeyInfo.RevisonId = 0;
> + AttemptUsbFirstHotkeyInfo.HotkeyTriggered = FALSE;
> +
> + ///
> + /// Build HOB for Attempt USB First feature
> + ///
> + BuildGuidDataHob(
> + &gAttemptUsbFirstHotkeyInfoHobGuid,
> + &(AttemptUsbFirstHotkeyInfo),
> + sizeof(ATTEMPT_USB_FIRST_HOTKEY_INFO)
> + );
> +
> + return Status;
> +}
> +
> +/**
> +Search and identify the physical address of a
> +file module inside the FW_BINARIES_FV_SIGNED FV
> +
> +@retval EFI_SUCCESS If address has been found
> +@retval Others If address has not been found
> +**/
> +EFI_STATUS
> +FindModuleInFlash2 (
> + IN EFI_FIRMWARE_VOLUME_HEADER *FvHeader,
> + IN EFI_GUID *GuidPtr,
> + IN OUT UINT32 *ModulePtr,
> + IN OUT UINT32 *ModuleSize
> + )
> +{
> + EFI_FFS_FILE_HEADER *FfsHeader;
> + EFI_FV_FILE_INFO FileInfo;
> + EFI_PEI_FILE_HANDLE FileHandle;
> + EFI_COMMON_SECTION_HEADER *SectionHeader;
> + VOID *FileBuffer;
> + EFI_STATUS Status;
> +
> + FfsHeader = NULL;
> + FileHandle = NULL;
> + SectionHeader = NULL;
> + FileBuffer = NULL;
> +
> + while (TRUE) {
> + //
> + // Locate FV_IMAGE file type in the FW_BINARIES_FV_SIGNED firmware
> volume
> + //
> + Status =
> PeiServicesFfsFindNextFile(EFI_FV_FILETYPE_FIRMWARE_VOLUME_IMAGE,
> FvHeader, &FileHandle);
> + if (EFI_ERROR(Status)) {
> + // unable to find FV_IMAGE file in this FV
> + break;
> + }
> +
> + FfsHeader = (EFI_FFS_FILE_HEADER*)FileHandle;
> + DEBUG((DEBUG_INFO, "FfsHeader 0x%X:\n", FfsHeader));
> + DEBUG((DEBUG_INFO, " Name = 0x%g\n", &FfsHeader->Name));
> + DEBUG((DEBUG_INFO, " Type = 0x%X\n", FfsHeader->Type));
> + if (IS_FFS_FILE2(FfsHeader)) {
> + DEBUG((DEBUG_INFO, " Size = 0x%X\n", FFS_FILE2_SIZE(FfsHeader)));
> + }
> + else {
> + DEBUG((DEBUG_INFO, " Size = 0x%X\n", FFS_FILE_SIZE(FfsHeader)));
> + }
> +
> + //
> + // Locate FW_BINARIES_FV FV_IMAGE Section
> + //
> + Status =
> PeiServicesFfsFindSectionData(EFI_SECTION_FIRMWARE_VOLUME_IMAGE,
> FileHandle, &FileBuffer);
> + if (EFI_ERROR(Status)) {
> + // continue to search for the next FV_IMAGE file
> + DEBUG((DEBUG_INFO, "FW_BINARIES_FV section not found. Status =
> %r\n", Status));
> + continue;
> + }
> +
> + SectionHeader = (EFI_COMMON_SECTION_HEADER *)FileBuffer;
> + DEBUG((DEBUG_INFO, "GUIDED SectionHeader 0x%X:\n",
> + (UINT32)(UINT8 *)SectionHeader));
> + if (IS_SECTION2(SectionHeader)) {
> + DEBUG((DEBUG_INFO, " Guid = 0x%g\n",
> + &((EFI_GUID_DEFINED_SECTION2
> *)SectionHeader)->SectionDefinitionGuid));
> + DEBUG((DEBUG_INFO, " DataOfset = 0x%X\n",
> + ((EFI_GUID_DEFINED_SECTION2 *)SectionHeader)->DataOffset));
> + }
> + else {
> + DEBUG((DEBUG_INFO, " Guid = 0x%g\n",
> + &((EFI_GUID_DEFINED_SECTION
> *)SectionHeader)->SectionDefinitionGuid));
> + DEBUG((DEBUG_INFO, " DataOfset = 0x%X\n",
> + ((EFI_GUID_DEFINED_SECTION *)SectionHeader)->DataOffset));
> + }
> + DEBUG((DEBUG_INFO, " Type = 0x%X\n", SectionHeader->Type));
> +
> + //
> + // Locate Firmware File System file within Firmware Volume
> + //
> + Status = PeiServicesFfsFindFileByName(GuidPtr, FileBuffer, (VOID
> **)&FfsHeader);
> + if (EFI_ERROR(Status)) {
> + // continue to search for the next FV_IMAGE file
> + DEBUG((DEBUG_INFO, "Module not found. Status = %r\n", Status));
> + continue;
> + }
> +
> + *ModulePtr = (UINT32)((UINT8 *)FfsHeader +
> sizeof(EFI_FFS_FILE_HEADER));
> +
> + //
> + // Get File Information
> + //
> + Status = PeiServicesFfsGetFileInfo(FfsHeader, &FileInfo);
> + if (!EFI_ERROR(Status)) {
> + *ModuleSize = (UINT32)FileInfo.BufferSize;
> + DEBUG((DEBUG_INFO, "Module {0x%g} found at = 0x%X, Size =
> 0x%X\n",
> + &FfsHeader->Name, *ModulePtr, *ModuleSize));
> + return Status;
> + }
> + }
> +
> + return EFI_NOT_FOUND;
> +}
> +
> +/**
> +Get the ChipsetInit Binary pointer.
> +
> +@retval EFI_SUCCESS - ChipsetInit Binary found.
> +@retval EFI_NOT_FOUND - ChipsetInit Binary not found.
> +**/
> +EFI_STATUS
> +UpdateChipsetInitPtr (
> + VOID
> + )
> +{
> + EFI_STATUS Status;
> + PCH_STEPPING PchStep;
> + EFI_FIRMWARE_VOLUME_HEADER *FvHeader;
> + EFI_GUID *ChipsetInitBinaryGuidPtr;
> + SI_POLICY_PPI *SiPolicyPpi;
> + PCH_HSIO_CONFIG *HsioConfig;
> + UINT32 ModuleAddr;
> + UINT32 ModuleSize;
> +
> + ModuleAddr = 0;
> + ModuleSize = 0;
> + PchStep = PchStepping();
> +
> + Status = PeiServicesLocatePpi(
> + &gSiPolicyPpiGuid,
> + 0,
> + NULL,
> + (VOID **)&SiPolicyPpi
> + );
> + ASSERT_EFI_ERROR(Status);
> +
> + Status = GetConfigBlock((VOID *)SiPolicyPpi, &gHsioConfigGuid, (VOID
> *)&HsioConfig);
> + ASSERT_EFI_ERROR(Status);
> +
> + ChipsetInitBinaryGuidPtr = NULL;
> + if (IsPchLp()) {
> + switch (PchStep) {
> + case PCH_D0:
> + case PCH_D1:
> + ChipsetInitBinaryGuidPtr = &gCnlPchLpChipsetInitTableDxGuid;
> + DEBUG((DEBUG_INFO, "Using CnlPchLpChipsetInitTable_Dx table
> \n"));
> + break;
> + default:
> + return EFI_NOT_FOUND;
> + }
> + }
> + else {
> + return EFI_NOT_FOUND;
> + }
> +
> + //
> + // Locate Firmware Volume header
> + //
> + FvHeader = (EFI_FIRMWARE_VOLUME_HEADER *)
> FixedPcdGet32(PcdFlashFvPostMemoryBase);
> + Status = FindModuleInFlash2(FvHeader, ChipsetInitBinaryGuidPtr,
> &ModuleAddr, &ModuleSize);
> + //
> + // Get ChipsetInit Binary Pointer
> + //
> + HsioConfig->ChipsetInitBinPtr = ModuleAddr;
> +
> + //
> + // Get File Size
> + //
> + HsioConfig->ChipsetInitBinLen = ModuleSize;
> +
> + DEBUG((DEBUG_INFO, "ChipsetInit Binary Location: %x\n",
> HsioConfig->ChipsetInitBinPtr));
> + DEBUG((DEBUG_INFO, "ChipsetInit Binary Size: %x\n",
> HsioConfig->ChipsetInitBinLen));
> +
> + return Status;
> +}
> +
> +/**
> + Configure GPIO and SIO
> +
> + @retval EFI_SUCCESS Operation success.
> +**/
> +EFI_STATUS
> +EFIAPI
> +UpXtremeBoardInitBeforeSiliconInit (
> + VOID
> + )
> +{
> + EFI_STATUS Status;
> + UINT8 FwConfig;
> +
> + BoardConfigInit();
> + //
> + // Configure GPIO and SIO
> + //
> + Status = BoardInit();
> + ASSERT_EFI_ERROR(Status);
> +
> + FwConfig = FwConfigProduction;
> + PeiPolicyInit(FwConfig);
> +
> + //
> + // Create USB Boot First hotkey information HOB
> + //
> + CreateAttemptUsbFirstHotkeyInfoHob();
> +
> + //
> + // Initializing Platform Specific Programming
> + //
> + Status = PlatformSpecificInit();
> + ASSERT_EFI_ERROR(Status);
> +
> + //
> + // Update ChipsetInitPtr
> + //
> + Status = UpdateChipsetInitPtr();
> +
> + return EFI_SUCCESS;
> +}
> +
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/
> PeiUpXtremeInitPreMemLib.c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/
> PeiUpXtremeInitPreMemLib.c
> new file mode 100644
> index 0000000000..0d55078943
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/
> PeiUpXtremeInitPreMemLib.c
> @@ -0,0 +1,659 @@
> +/** @file
> +
> + Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include <PiPei.h>
> +#include <SaPolicyCommon.h>
> +#include <Library/DebugLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/HobLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/PchCycleDecodingLib.h>
> +#include <Library/PciLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/BaseMemoryLib.h>
> +
> +#include <Library/PeiSaPolicyLib.h>
> +#include <Library/BoardInitLib.h>
> +#include <PchAccess.h>
> +#include <Library/GpioNativeLib.h>
> +#include <Library/GpioLib.h>
> +#include <GpioPinsSklLp.h>
> +#include <GpioPinsSklH.h>
> +#include <Library/GpioExpanderLib.h>
> +#include <SioRegs.h>
> +#include <Library/PchPcrLib.h>
> +
> +#include "UpXtremeInit.h"
> +#include <ConfigBlock.h>
> +#include <Setup.h>
> +#include <ConfigBlock/MemoryConfig.h>
> +#include <Library/PeiServicesLib.h>
> +#include <Library/PchPcrLib.h>
> +#include <Library/PchInfoLib.h>
> +#include <Register/PchRegsPcr.h>
> +#include <Library/PchResetLib.h>
> +#include <Register/PchRegsLpc.h>
> +#include <Library/StallPpiLib.h>
> +#include <Library/PeiPolicyInitLib.h>
> +#include <Ppi/Reset.h>
> +#include <PlatformBoardConfig.h>
> +#include <GpioPinsCnlLp.h>
> +#include <Library/PmcLib.h>
> +#include <Library/PciSegmentLib.h>
> +#include <PeiPlatformHookLib.h>
> +#include <FirwmareConfigurations.h>
> +#include <Guid/TcoWdtHob.h>
> +#include <Library/OcWdtLib.h>
> +#include <CpuRegs.h>
> +#include <Library/BaseLib.h>
> +
> +///
> +/// Reset Generator I/O Port
> +///
> +#define RESET_GENERATOR_PORT 0xCF9
> +
> +
> +#define MSR_CACHE_VARIABLE_MTRR_BASE 0x00000200
> +#define CACHE_WRITEPROTECTED 5
> +
> +typedef struct {
> + EFI_PHYSICAL_ADDRESS BaseAddress;
> + UINT64 Length;
> +} MEMORY_MAP;
> +
> +GLOBAL_REMOVE_IF_UNREFERENCED MEMORY_MAP MmioMap[] = {
> + { FixedPcdGet64(PcdApicLocalAddress),
> FixedPcdGet32(PcdApicLocalMmioSize) },
> + { FixedPcdGet64(PcdMchBaseAddress),
> FixedPcdGet32(PcdMchMmioSize) },
> + { FixedPcdGet64(PcdDmiBaseAddress),
> FixedPcdGet32(PcdDmiMmioSize) },
> + { FixedPcdGet64(PcdEpBaseAddress), FixedPcdGet32(PcdEpMmioSize) },
> + { FixedPcdGet64(PcdGdxcBaseAddress),
> FixedPcdGet32(PcdGdxcMmioSize) }
> +};
> +
> +EFI_STATUS
> +MrcConfigInit(
> + IN UINT16 BoardId
> +);
> +
> +EFI_STATUS
> +SaGpioConfigInit(
> + IN UINT16 BoardId
> +);
> +
> +EFI_STATUS
> + SaMiscConfigInit(
> +IN UINT16 BoardId
> +);
> +
> +EFI_STATUS
> + RootPortClkInfoInit(
> +IN UINT16 BoardId
> +);
> +
> +EFI_STATUS
> + UsbConfigInit(
> +IN UINT16 BoardId
> +);
> +
> +EFI_STATUS
> +GpioGroupTierInit(
> + IN UINT16 BoardId
> +);
> +
> +EFI_STATUS
> +GpioTablePreMemInit(
> + IN UINT16 BoardId
> +);
> +
> +EFI_STATUS
> +PchPmConfigInit(
> + IN UINT16 BoardId
> +);
> +
> +EFI_STATUS
> +SaDisplayConfigInit(
> + IN UINT16 BoardId
> +);
> +
> +EFI_STATUS
> +EFIAPI
> +PlatformInitPreMemCallBack(
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
> + IN VOID *Ppi
> +);
> +
> +EFI_STATUS
> +EFIAPI
> +MemoryDiscoveredPpiNotify(
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
> + IN VOID *Ppi
> +);
> +
> +EFI_STATUS
> +EFIAPI
> +PchReset(
> + IN CONST EFI_PEI_SERVICES **PeiServices
> +);
> +
> +static EFI_PEI_RESET_PPI mResetPpi = {
> + PchReset
> +};
> +
> +static EFI_PEI_PPI_DESCRIPTOR mPreMemPpiList[] = {
> + {
> + (EFI_PEI_PPI_DESCRIPTOR_PPI |
> EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
> + &gEfiPeiResetPpiGuid,
> + &mResetPpi
> + }
> +};
> +
> +static EFI_PEI_NOTIFY_DESCRIPTOR mPreMemNotifyList = {
> + (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK |
> EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
> + &gEfiPeiReadOnlyVariable2PpiGuid,
> + (EFI_PEIM_NOTIFY_ENTRY_POINT)PlatformInitPreMemCallBack
> +};
> +
> +static EFI_PEI_NOTIFY_DESCRIPTOR mMemDiscoveredNotifyList = {
> + (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK |
> EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
> + &gEfiPeiMemoryDiscoveredPpiGuid,
> + (EFI_PEIM_NOTIFY_ENTRY_POINT)MemoryDiscoveredPpiNotify
> +};
> +
> +/**
> +Board misc init function for PEI pre-memory phase.
> +
> +@param[in] BoardId An unsigned integer represent the board id.
> +
> +@retval EFI_SUCCESS The function completed successfully.
> +**/
> +EFI_STATUS
> +BoardMiscInitPreMem(
> + IN UINT16 BoardId
> + )
> +{
> + //
> + // Configure WWAN Full Card Power Off and reset pins
> + //
> + switch (BoardId) {
> + // todo for UP Xtreme
> + case BoardIdWhiskeyLakeRvp:
> + //
> + // According to board default settings, GPP_D16 is used to
> enable/disable modem
> + // power. An alternative way to contol modem power is to toggle
> FCP_OFF via GPP_D13
> + // but board rework is required.
> + //
> + PcdSet32S (PcdWwanFullCardPowerOffGpio,
> GPIO_CNL_LP_GPP_D16);
> + PcdSet32S (PcdWwanBbrstGpio, GPIO_CNL_LP_GPP_F1);
> + PcdSet32S (PcdWwanPerstGpio, GPIO_CNL_LP_GPP_E15);
> + PcdSet8S (PcdWwanPerstGpioPolarity, 1);
> + break;
> +
> + default:
> + break;
> + }
> +
> + //
> + // Pc8374SioKbc Present
> + //
> + PcdSetBoolS (PcdPc8374SioKbcPresent, FALSE);
> +
> + return EFI_SUCCESS;
> +}
> +
> +//@todo it should be moved to Si Pkg.
> +/**
> +Early Platform PCH initialization
> +**/
> +VOID
> +EarlyPlatformPchInit(
> + VOID
> +)
> +{
> + UINT8 Data8;
> + UINT16 Data16;
> + UINT8 TcoRebootHappened;
> + TCO_WDT_HOB *TcoWdtHobPtr;
> + EFI_STATUS Status;
> +
> + ///
> + /// Halt the TCO timer
> + ///
> + Data16 = IoRead16 (PcdGet16 (PcdTcoBaseAddress) +
> R_TCO_IO_TCO1_CNT);
> + Data16 |= B_TCO_IO_TCO1_CNT_TMR_HLT;
> + IoWrite16 (PcdGet16 (PcdTcoBaseAddress) + R_TCO_IO_TCO1_CNT,
> Data16);
> +
> + ///
> + /// Read the Second TO status bit
> + ///
> + Data8 = IoRead8 (PcdGet16 (PcdTcoBaseAddress) + R_TCO_IO_TCO2_STS);
> + if ((Data8 & B_TCO_IO_TCO2_STS_SECOND_TO) ==
> B_TCO_IO_TCO2_STS_SECOND_TO) {
> + TcoRebootHappened = 1;
> + DEBUG ((DEBUG_INFO, "PlatformInitPreMem - TCO Second TO status bit
> is set. This might be a TCO reboot\n"));
> + }
> + else {
> + TcoRebootHappened = 0;
> + }
> +
> + ///
> + /// Create HOB
> + ///
> + Status = PeiServicesCreateHob (EFI_HOB_TYPE_GUID_EXTENSION, sizeof
> (TCO_WDT_HOB), (VOID **) &TcoWdtHobPtr);
> + if (!EFI_ERROR (Status)) {
> + TcoWdtHobPtr->Header.Name = gTcoWdtHobGuid;
> + TcoWdtHobPtr->TcoRebootHappened = TcoRebootHappened;
> + }
> +
> + ///
> + /// Clear the Second TO status bit
> + ///
> + IoWrite8 (PcdGet16(PcdTcoBaseAddress) + R_TCO_IO_TCO2_STS,
> B_TCO_IO_TCO2_STS_SECOND_TO);
> +}
> +
> +/**
> + Board configuration initialization in the pre-memory boot phase.
> +
> +**/
> +VOID
> +BoardConfigInitPreMem (
> + VOID
> + )
> +{
> + EFI_STATUS Status;
> + UINT16 BoardId;
> +
> + BoardId = BoardIdUpXtreme;
> +
> + Status = MrcConfigInit (BoardId);
> + ASSERT_EFI_ERROR (Status);
> +
> + Status = SaGpioConfigInit (BoardId);
> + ASSERT_EFI_ERROR (Status);
> +
> + Status = SaMiscConfigInit (BoardId);
> + ASSERT_EFI_ERROR (Status);
> +
> + Status = RootPortClkInfoInit (BoardId);
> + ASSERT_EFI_ERROR (Status);
> +
> + Status = UsbConfigInit (BoardId);
> + ASSERT_EFI_ERROR (Status);
> +
> + Status = GpioGroupTierInit (BoardId);
> + ASSERT_EFI_ERROR (Status);
> +
> + Status = GpioTablePreMemInit (BoardId);
> + ASSERT_EFI_ERROR (Status);
> +
> + Status = PchPmConfigInit (BoardId);
> + ASSERT_EFI_ERROR (Status);
> +
> + Status = BoardMiscInitPreMem (BoardId);
> + ASSERT_EFI_ERROR (Status);
> +
> + Status = SaDisplayConfigInit (BoardId);
> + ASSERT_EFI_ERROR (Status);
> +}
> +
> +/**
> +This function handles PlatformInit task after PeiReadOnlyVariable2 PPI
> produced
> +
> +@param[in] PeiServices Pointer to PEI Services Table.
> +@param[in] NotifyDesc Pointer to the descriptor for the Notification
> event that
> + caused this function to execute.
> +@param[in] Ppi Pointer to the PPI data associated with this
> function.
> +
> +@retval EFI_SUCCESS The function completes successfully
> +@retval others
> +**/
> +EFI_STATUS
> +EFIAPI
> +PlatformInitPreMemCallBack(
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
> + IN VOID *Ppi
> +)
> +{
> + EFI_STATUS Status;
> + UINT16 ABase;
> + UINT8 FwConfig;
> +
> + //
> + // Init Board Config Pcd.
> + //
> + BoardConfigInitPreMem ();
> +
> + FwConfig = FwConfigProduction;
> + PcdSetBoolS (PcdPcieWwanEnable, FALSE);
> + PcdSetBoolS (PcdWwanResetWorkaround, FALSE);
> +
> + //
> + // Early Board Configuration before memory is ready.
> + //
> + Status = BoardInitEarlyPreMem ();
> + ASSERT_EFI_ERROR (Status);
> +
> + ///
> + /// If there was unexpected reset but no WDT expiration and no resume
> from S3/S4,
> + /// clear unexpected reset status and enforce expiration. This is to inform
> Firmware
> + /// which has no access to unexpected reset status bit, that something
> went wrong.
> + ///
> + OcWdtResetCheck ();
> +
> + Status = OcWdtInit ();
> + ASSERT_EFI_ERROR (Status);
> +
> + //
> + // Initialize Intel PEI Platform Policy
> + //
> + PeiPolicyInitPreMem (FwConfig);
> +
> + ///
> + /// Configure GPIO and SIO
> + ///
> + Status = BoardInitPreMem ();
> + ASSERT_EFI_ERROR (Status);
> +
> + ABase = PmcGetAcpiBase ();
> +
> + ///
> + /// Clear all pending SMI. On S3 clear power button enable so it will not
> generate an SMI.
> + ///
> + IoWrite16 (ABase + R_ACPI_IO_PM1_EN, 0);
> + IoWrite32 (ABase + R_ACPI_IO_GPE0_EN_127_96, 0);
> +
> + ///
> + /// Install Pre Memory PPIs
> + ///
> + Status = PeiServicesInstallPpi (&mPreMemPpiList[0]);
> + ASSERT_EFI_ERROR (Status);
> +
> + return Status;
> +}
> +
> +/**
> +Provide hard reset PPI service.
> +To generate full hard reset, write 0x0E to PCH RESET_GENERATOR_PORT
> (0xCF9).
> +
> +@param[in] PeiServices General purpose services available to
> every PEIM.
> +
> +@retval Not return System reset occured.
> +@retval EFI_DEVICE_ERROR Device error, could not reset the system.
> +**/
> +EFI_STATUS
> +EFIAPI
> +PchReset(
> + IN CONST EFI_PEI_SERVICES **PeiServices
> +)
> +{
> + DEBUG ((DEBUG_INFO, "Perform Cold Reset\n"));
> + IoWrite8 (RESET_GENERATOR_PORT, 0x0E);
> +
> + CpuDeadLoop ();
> +
> + ///
> + /// System reset occured, should never reach at this line.
> + ///
> + ASSERT_EFI_ERROR (EFI_DEVICE_ERROR);
> +
> + return EFI_DEVICE_ERROR;
> +}
> +
> +/**
> +Install Firmware Volume Hob's once there is main memory
> +
> +@param[in] PeiServices General purpose services available to
> every PEIM.
> +@param[in] NotifyDescriptor Notify that this module published.
> +@param[in] Ppi PPI that was installed.
> +
> +@retval EFI_SUCCESS The function completed successfully.
> +**/
> +EFI_STATUS
> +EFIAPI
> +MemoryDiscoveredPpiNotify(
> + IN CONST EFI_PEI_SERVICES **PeiServices,
> + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
> + IN VOID *Ppi
> +)
> +{
> + EFI_STATUS Status;
> + EFI_BOOT_MODE BootMode;
> + UINTN Index;
> + UINT8 PhysicalAddressBits;
> + UINT32 RegEax;
> + MEMORY_MAP PcieMmioMap;
> +
> + Index = 0;
> +
> + Status = PeiServicesGetBootMode (&BootMode);
> + ASSERT_EFI_ERROR (Status);
> +
> + AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
> + if (RegEax >= 0x80000008) {
> + AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
> + PhysicalAddressBits = (UINT8) RegEax;
> + }
> + else {
> + PhysicalAddressBits = 36;
> + }
> +
> + ///
> + /// Create a CPU hand-off information
> + ///
> + BuildCpuHob (PhysicalAddressBits, 16);
> +
> + ///
> + /// Build Memory Mapped IO Resource which is used to build E820 Table
> in LegacyBios.
> + ///
> + PcieMmioMap.BaseAddress = FixedPcdGet64
> (PcdPciExpressBaseAddress);
> + PcieMmioMap.Length = PcdGet32 (PcdPciExpressRegionLength);
> +
> + BuildResourceDescriptorHob (
> + EFI_RESOURCE_MEMORY_MAPPED_IO,
> + (EFI_RESOURCE_ATTRIBUTE_PRESENT |
> + EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
> + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
> + PcieMmioMap.BaseAddress,
> + PcieMmioMap.Length
> + );
> + BuildMemoryAllocationHob (
> + PcieMmioMap.BaseAddress,
> + PcieMmioMap.Length,
> + EfiMemoryMappedIO
> + );
> + for (Index = 0; Index < sizeof (MmioMap) / (sizeof (MEMORY_MAP));
> Index++) {
> + BuildResourceDescriptorHob (
> + EFI_RESOURCE_MEMORY_MAPPED_IO,
> + (EFI_RESOURCE_ATTRIBUTE_PRESENT |
> + EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
> + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
> + MmioMap[Index].BaseAddress,
> + MmioMap[Index].Length
> + );
> + BuildMemoryAllocationHob (
> + MmioMap[Index].BaseAddress,
> + MmioMap[Index].Length,
> + EfiMemoryMappedIO
> + );
> + }
> +
> + //
> + // Report resource HOB for flash FV
> + //
> + BuildResourceDescriptorHob (
> + EFI_RESOURCE_MEMORY_MAPPED_IO,
> + (EFI_RESOURCE_ATTRIBUTE_PRESENT |
> + EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
> + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
> + (UINTN) FixedPcdGet32 (PcdFlashAreaBaseAddress),
> + (UINTN) FixedPcdGet32 (PcdFlashAreaSize)
> + );
> + BuildMemoryAllocationHob (
> + (UINTN) FixedPcdGet32 (PcdFlashAreaBaseAddress),
> + (UINTN) FixedPcdGet32 (PcdFlashAreaSize),
> + EfiMemoryMappedIO
> + );
> +
> + BuildFvHob (
> + (UINTN) FixedPcdGet32 (PcdFlashAreaBaseAddress),
> + (UINTN) FixedPcdGet32 (PcdFlashAreaSize)
> + );
> +
> + return Status;
> +}
> +
> +
> +/**
> + Increases the code cache size
> +**/
> +VOID
> +EFIAPI
> +EnlargeCodeCacheRegion (
> + VOID
> + )
> +{
> + UINT32 MsrIndex;
> + UINT32 NewCodeCacheSize;
> + UINT32 AdjustedSize;
> + UINT64 MaskLen;
> +
> + //
> + // MTRR is patched to enable a larger code cache to avoid performance
> penalty.
> + //
> + NewCodeCacheSize = PcdGet32 (PcdFlashFvPreMemorySize) + PcdGet32
> (PcdFlashFvAdvancedPreMemorySize) + \
> + PcdGet32 (PcdFlashFvFspTSize) + PcdGet32 (PcdFlashFvFspMSize) + \
> + PcdGet32 (PcdFlashFvFspSSize) + PcdGet32
> (PcdFlashMicrocodeFvSize);
> +
> + MaskLen = (AsmReadMsr64 (MSR_CACHE_VARIABLE_MTRR_BASE + 1) |
> (SIZE_4GB - 1)) + 1;
> + MsrIndex = MSR_CACHE_VARIABLE_MTRR_BASE + 1 * 2;
When this code running some MTRR already configured for CAR and we should not assume this MTRR index always can be overridden.
How about we use FSP-T UPD to override default CAR initialization if default result cannot satisfy such board?
FSP-T UPD:
/** Offset 0x0028
**/
UINT32 CodeRegionBase;
/** Offset 0x002C
**/
UINT32 CodeRegionSize;
> + AdjustedSize = GetPowerOfTwo32 (NewCodeCacheSize);
> + if (NewCodeCacheSize > AdjustedSize) {
> + AdjustedSize <<= 1;
> + }
> +
> + AsmWriteMsr64 (MsrIndex, (SIZE_4GB - AdjustedSize) |
> CACHE_WRITEPROTECTED);
> + AsmWriteMsr64 (MsrIndex + 1, (MaskLen - AdjustedSize) |
> B_CACHE_MTRR_VALID);
> +}
> +
> +/**
> + Board configuration init function for PEI pre-memory phase.
> +
> + @retval EFI_SUCCESS The function completed successfully.
> + @retval EFI_INVALID_PARAMETER The parameter is NULL.
> +**/
> +EFI_STATUS
> +EFIAPI
> +UpXtremeInitPreMem (
> + VOID
> + )
> +{
> + EFI_STATUS Status;
> +
> + ///
> + /// Install Stall PPI
> + ///
> + Status = InstallStallPpi ();
> + ASSERT_EFI_ERROR (Status);
> +
> + ///@todo it should be moved to Si Pkg.
> + ///
> + /// Do Early PCH init
> + ///
> + EarlyPlatformPchInit ();
> +
> + //
> + // Install PCH RESET PPI and EFI RESET2 PeiService
> + //
> + Status = PchInitializeReset ();
> + ASSERT_EFI_ERROR (Status);
> +
> + EnlargeCodeCacheRegion ();
> +
> + ///
> + /// Performing PlatformInitPreMemCallBack after PeiReadOnlyVariable2
> PPI produced
> + ///
> + Status = PeiServicesNotifyPpi (&mPreMemNotifyList);
> +
> + ///
> + /// After code reorangized, memorycallback will run because the PPI is
> already
> + /// installed when code run to here, it is supposed that the
> InstallEfiMemory is
> + /// done before.
> + ///
> + Status = PeiServicesNotifyPpi (&mMemDiscoveredNotifyList);
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Configure GPIO and SIO before memory ready
> +
> + @retval EFI_SUCCESS Operation success.
> +**/
> +EFI_STATUS
> +EFIAPI
> +UpXtremeBoardInitBeforeMemoryInit (
> + VOID
> + )
> +{
> + UpXtremeInitPreMem ();
> +
> + return EFI_SUCCESS;
> +}
> +
> +EFI_STATUS
> +EFIAPI
> +UpXtremeBoardDebugInit (
> + VOID
> + )
> +{
> + // Serial port initialization is performed in the
> PlatformHookSerialPortInitialize ()
> + // function invoked by SerialPortInitialize () in SerialPortLib
> +DEBUG_CODE_BEGIN();
> + DEBUG_CONFIG_DATA_HOB *DebugConfigDataHob;
> +
> + DebugConfigDataHob = BuildGuidHob (&gDebugConfigHobGuid, sizeof
> (DEBUG_CONFIG_DATA_HOB));
> + ASSERT (DebugConfigDataHob != NULL);
> + if (DebugConfigDataHob == NULL) {
> + DEBUG ((DEBUG_ERROR, "Build Debug Config Hob failed!\n"));
> + return EFI_OUT_OF_RESOURCES;
> + }
> +
> + switch (PcdGet32 (PcdSerialBaudRate)) {
> + case 9600:
> + DebugConfigDataHob->SerialDebugBaudRate = 3;
> + break;
> + case 19200:
> + DebugConfigDataHob->SerialDebugBaudRate = 4;
> + break;
> + case 57600:
> + DebugConfigDataHob->SerialDebugBaudRate = 6;
> + break;
> + default:
> + DebugConfigDataHob->SerialDebugBaudRate = 7;
> + }
> + DebugConfigDataHob->SerialDebug = 0x3;
> + DebugConfigDataHob->RamDebugInterface = 0;
> + DebugConfigDataHob->UartDebugInterface = 0;
> + DebugConfigDataHob->Usb3DebugInterface = 0;
> + DebugConfigDataHob->SerialIoDebugInterface = (FeaturePcdGet
> (PcdSerialIoUartEnable)) ? 1 : 0;
> + DebugConfigDataHob->TraceHubDebugInterface = 0;
> +
> +DEBUG_CODE_END();
> +
> + return EFI_SUCCESS;
> +}
> +
> +EFI_BOOT_MODE
> +EFIAPI
> +UpXtremeBoardBootModeDetect (
> + VOID
> + )
> +{
> + return BOOT_WITH_FULL_CONFIGURATION;
> +}
> +
> +
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/
> UpXtremeHsioPtssTables.c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/
> UpXtremeHsioPtssTables.c
> new file mode 100644
> index 0000000000..7e1320a5ac
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/
> UpXtremeHsioPtssTables.c
> @@ -0,0 +1,32 @@
> +/** @file
> + UpXtreme HSIO PTSS H File
> +
> +
> + Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _UPEXTREME_HSIO_PTSS_H_
> +#define _UPEXTREME_HSIO_PTSS_H_
> +
> +#include <PchHsioPtssTables.h>
> +
> +#ifndef HSIO_PTSS_TABLE_SIZE
> +#define HSIO_PTSS_TABLE_SIZE(A) A##_Size = sizeof (A) / sizeof
> (HSIO_PTSS_TABLES)
> +#endif
> +
> +//BoardId UpXtreme
> +HSIO_PTSS_TABLES PchLpHsioPtss_Cx_UpXtreme[] = {
> + {{14, 0, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, 0}
> +};
> +
> +UINT16 PchLpHsioPtss_Cx_UpXtreme_Size =
> sizeof(PchLpHsioPtss_Cx_UpXtreme) / sizeof(HSIO_PTSS_TABLES);
> +
> +HSIO_PTSS_TABLES PchLpHsioPtss_Bx_UpXtreme[] = {
> + {{14, 0, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, 0},
> +};
> +
> +UINT16 PchLpHsioPtss_Bx_UpXtreme_Size =
> sizeof(PchLpHsioPtss_Bx_UpXtreme) / sizeof(HSIO_PTSS_TABLES);
> +
> +#endif // _UPEXTREME_HSIO_PTSS_H_
> +
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/
> UpXtremeInit.h
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/
> UpXtremeInit.h
> new file mode 100644
> index 0000000000..75333c492c
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/
> UpXtremeInit.h
> @@ -0,0 +1,44 @@
> +/** @file
> +
> + Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _UP_XTREME_INIT_H_
> +#define _UP_XTREME_INIT_H_
> +
> +#include <Uefi.h>
> +#include <IoExpander.h>
> +#include <PlatformBoardId.h>
> +#include <Library/BaseLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/GpioLib.h>
> +#include <Ppi/SiPolicy.h>
> +#include <PchHsioPtssTables.h>
> +
> +extern const UINT8 mUpXtremeSamsungDdr4Spd[];
> +extern const UINT16 mUpXtremeSamsungDdr4SpdSize;
> +extern const UINT8 mUpXtremeSkhynixDdr4Spd[];
> +extern const UINT16 mUpXtremeSkhynixDdr4SpdSize;
> +
> +extern HSIO_PTSS_TABLES PchLpHsioPtss_Bx_UpXtreme[];
> +extern UINT16 PchLpHsioPtss_Bx_UpXtreme_Size;
> +extern HSIO_PTSS_TABLES PchLpHsioPtss_Cx_UpXtreme[];
> +extern UINT16 PchLpHsioPtss_Cx_UpXtreme_Size;
> +
> +extern GPIO_INIT_CONFIG mGpioTableWhlUDdr4PreMem[];
> +extern UINT16 mGpioTableWhlUDdr4PreMemSize;
> +extern GPIO_INIT_CONFIG mGpioTableWhlUDdr4WwanOnEarlyPreMem[];
> +extern UINT16 mGpioTableWhlUDdr4WwanOnEarlyPreMemSize;
> +extern GPIO_INIT_CONFIG mGpioTableWhlUDdr4WwanOffEarlyPreMem[];
> +extern UINT16 mGpioTableWhlUDdr4WwanOffEarlyPreMemSize;
> +
> +extern GPIO_INIT_CONFIG mGpioTableUpXtreme[];
> +extern UINT16 mGpioTableUpXtremeSize;
> +extern GPIO_INIT_CONFIG mGpioTableDefault[];
> +extern UINT16 mGpioTableDefaultSize;
> +
> +#endif // _UP_XTREME_INIT_H_
> +
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/
> UpXtremeSpdTable.c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/
> UpXtremeSpdTable.c
> new file mode 100644
> index 0000000000..85f29bd59d
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/
> UpXtremeSpdTable.c
> @@ -0,0 +1,86 @@
> +/** @file
> + UpXtreme Serial Presence Data (SPD)
> +
> +
> + Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _UPXTREME_SPD_TABLE_H_
> +#define _UPXTREME_SPD_TABLE_H_
> +
> +GLOBAL_REMOVE_IF_UNREFERENCED const UINT8
> mUpXtremeSkhynixDdr4Spd[] = {
> + 0x23, 0x11, 0x0C, 0x03, 0x85, 0x21, 0x00, 0x08, 0x00, 0x60, 0x00, 0x03,
> 0x01, 0x03, 0x00, 0x00,
> + 0x00, 0x00, 0x07, 0x0D, 0xF8, 0x0F, 0x00, 0x00, 0x6E, 0x6E, 0x6E, 0x11,
> 0x00, 0x6E, 0xF0, 0x0A,
> + 0x20, 0x08, 0x00, 0x05, 0x00, 0xA8, 0x1B, 0x28, 0x28, 0x00, 0x78, 0x00,
> 0x14, 0x3C, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x16, 0x36, 0x0B, 0x35,
> + 0x16, 0x36, 0x0B, 0x35, 0x00, 0x00, 0x16, 0x36, 0x0B, 0x35, 0x16, 0x36,
> 0x0B, 0x35, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x9C, 0xB5, 0x00, 0x00, 0x00, 0x00,
> 0xE7, 0xD6, 0x89, 0x02,
> + 0x0F, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0xC0, 0xE2,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00, 0x00,
> + 0x80, 0xAD, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x4D, 0x41,
> 0x41, 0x35, 0x31, 0x53,
> + 0x36, 0x41, 0x4D, 0x52, 0x36, 0x4E, 0x2D, 0x55, 0x48, 0x20, 0x20, 0x20,
> 0x20, 0x00, 0x80, 0xAD,
> + 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0xDD, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00, 0x00
> +};
> +
> +GLOBAL_REMOVE_IF_UNREFERENCED const UINT16
> mUpXtremeSkhynixDdr4SpdSize = sizeof (mUpXtremeSkhynixDdr4Spd);
> +
> +GLOBAL_REMOVE_IF_UNREFERENCED const UINT8
> mUpXtremeSamsungDdr4Spd[] = {
> + 0x23, 0x11, 0x0C, 0x03, 0x45, 0x21, 0x00, 0x08, 0x00, 0x60, 0x00, 0x03,
> 0x02, 0x03, 0x80, 0x00,
> + 0x00, 0x00, 0x07, 0x0D, 0xF8, 0x0F, 0x00, 0x00, 0x6E, 0x6E, 0x6E, 0x11,
> 0x00, 0x6E, 0xF0, 0x0A,
> + 0x20, 0x08, 0x00, 0x05, 0x00, 0xF0, 0x2B, 0x34, 0x28, 0x00, 0x78, 0x00,
> 0x14, 0x3C, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x16, 0x36, 0x0B, 0x35,
> + 0x16, 0x36, 0x0B, 0x35, 0x00, 0x00, 0x16, 0x36, 0x0B, 0x35, 0x16, 0x36,
> 0x0B, 0x35, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x9C, 0xB5, 0x00, 0x00, 0x00, 0x00,
> 0xE7, 0xD6, 0xB8, 0x4A,
> + 0x0F, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0xC0, 0xE2,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00, 0x00,
> + 0x08, 0xF7, 0x4B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x44, 0x34, 0x53,
> 0x53, 0x31, 0x32, 0x31,
> + 0x36, 0x31, 0x53, 0x48, 0x32, 0x34, 0x41, 0x2D, 0x42, 0x20, 0x20, 0x20,
> 0x20, 0x00, 0x80, 0xCE,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> 0x00, 0x00, 0x00, 0x00
> +};
> +
> +GLOBAL_REMOVE_IF_UNREFERENCED const UINT16
> mUpXtremeSamsungDdr4SpdSize = sizeof (mUpXtremeSamsungDdr4Spd);
> +
> +#endif
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/DxePolicyBoar
> dConfigLib/DxePolicyBoardConfig.h
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/DxePolicyBoa
> rdConfigLib/DxePolicyBoardConfig.h
> new file mode 100644
> index 0000000000..c420873002
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/DxePolicyBoa
> rdConfigLib/DxePolicyBoardConfig.h
> @@ -0,0 +1,19 @@
> +/** @file
> + Header file for DxePolicyBoardConfig library instance.
> +
> +
> + Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _DXE_POLICY_BOARD_CONFIG_H_
> +#define _DXE_POLICY_BOARD_CONFIG_H_
> +
> +#include <PiDxe.h>
> +#include <Library/DebugLib.h>
> +#include <Library/HobLib.h>
> +#include <Library/DxePolicyBoardConfigLib.h>
> +
> +
> +#endif
> +
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/DxePolicyBoar
> dConfigLib/DxePolicyBoardConfigLib.inf
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/DxePolicyBoa
> rdConfigLib/DxePolicyBoardConfigLib.inf
> new file mode 100644
> index 0000000000..8d414102ee
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/DxePolicyBoa
> rdConfigLib/DxePolicyBoardConfigLib.inf
> @@ -0,0 +1,45 @@
> +## @file
> +# Module Information file for DxePolicyBoardConfigLib Library
> +#
> +#
> +# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x00010017
> + BASE_NAME = DxePolicyBoardConfigLib
> + FILE_GUID =
> 17836E9F-7188-4640-80A3-B4441585FFE9
> + VERSION_STRING = 1.0
> + MODULE_TYPE = DXE_DRIVER
> + LIBRARY_CLASS = DxePolicyUpdateLib|DXE_DRIVER
> +
> +#
> +# VALID_ARCHITECTURES = IA32 X64 IPF EBC
> +#
> +
> +[Sources]
> + DxeSaPolicyBoardConfig.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + IntelSiliconPkg/IntelSiliconPkg.dec
> + CoffeelakeSiliconPkg/SiPkg.dec
> + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec
> +
> +[LibraryClasses]
> + UefiBootServicesTableLib
> + UefiRuntimeServicesTableLib
> + BaseLib
> + BaseMemoryLib
> + PcdLib
> + DebugLib
> + HobLib
> + ConfigBlockLib
> +
> +[Guids]
> + gMemoryDxeConfigGuid ## CONSUMES
> +
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/DxePolicyBoar
> dConfigLib/DxeSaPolicyBoardConfig.c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/DxePolicyBoa
> rdConfigLib/DxeSaPolicyBoardConfig.c
> new file mode 100644
> index 0000000000..78edbab5ad
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/DxePolicyBoa
> rdConfigLib/DxeSaPolicyBoardConfig.c
> @@ -0,0 +1,36 @@
> +/** @file
> + Intel DXE SA Policy update by board configuration
> +
> +
> + Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include "DxePolicyBoardConfig.h"
> +#include <Library/ConfigBlockLib.h>
> +
> +/**
> + This function performs DXE SA Policy update by board configuration.
> +
> + @param[in, out] DxeSaPolicy DXE SA Policy
> +
> + @retval EFI_SUCCESS The SI Policy is successfully updated.
> + @retval Others The SI Policy is not successfully
> updated.
> +**/
> +EFI_STATUS
> +EFIAPI
> +UpdateDxeSaPolicyBoardConfig (
> + IN OUT SA_POLICY_PROTOCOL *DxeSaPolicy
> + )
> +{
> + EFI_STATUS Status;
> + MEMORY_DXE_CONFIG *MemoryDxeConfig;
> +
> + DEBUG((DEBUG_INFO, "Updating SA Policy by board config in DXE\n"));
> +
> + Status = GetConfigBlock ((VOID *)DxeSaPolicy, &gMemoryDxeConfigGuid,
> (VOID *)&MemoryDxeConfig);
> + ASSERT_EFI_ERROR (Status);
> +
> + return Status;
> +}
> +
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPlatformH
> ookLib/PeiPlatformHookLib.c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPlatformH
> ookLib/PeiPlatformHookLib.c
> new file mode 100644
> index 0000000000..9b14c2457b
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPlatformH
> ookLib/PeiPlatformHookLib.c
> @@ -0,0 +1,298 @@
> +/** @file
> + PEI Library Functions. Initialize GPIOs
> +
> +
> + Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include <PiPei.h>
> +#include <PeiPlatformHookLib.h>
> +#include <SaPolicyCommon.h>
> +#include <Library/DebugLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/HobLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/TimerLib.h>
> +#include <Library/PchCycleDecodingLib.h>
> +#include <Library/PeiPlatformLib.h>
> +#include <Library/PciSegmentLib.h>
> +#include <Library/PeiServicesLib.h>
> +#include <Library/PmcLib.h>
> +#include <Library/PeiSaPolicyLib.h>
> +#include <PchAccess.h>
> +#include <Library/CpuPlatformLib.h>
> +#include <Library/GpioNativeLib.h>
> +#include <Library/GpioLib.h>
> +#include <GpioPinsCnlLp.h>
> +#include <GpioPinsCnlH.h>
> +#include <Library/PchInfoLib.h>
> +#include <Library/CnviLib.h>
> +#include <SioRegs.h>
> +#include <PlatformBoardConfig.h>
> +#include <Library/PchPcrLib.h>
> +#include <Library/GpioCheckConflictLib.h>
> +
> +#define SIO_RUNTIME_REG_BASE_ADDRESS
> 0x0680
> +
> +#define RECOVERY_MODE_GPIO_PIN 0
> // Platform specific @todo use PCD
> +
> +#define MANUFACTURE_MODE_GPIO_PIN 0
> // Platform specific @todo use PCD
> +
> +/**
> + Configures GPIO
> +
> + @param[in] GpioTable Point to Platform Gpio table
> + @param[in] GpioTableCount Number of Gpio table entries
> +
> +**/
> +VOID
> +ConfigureGpio (
> + IN GPIO_INIT_CONFIG *GpioDefinition,
> + IN UINT16 GpioTableCount
> + )
> +{
> + DEBUG ((DEBUG_INFO, "ConfigureGpio() Start\n"));
> +
> + CreateGpioCheckConflictHob (GpioDefinition, GpioTableCount);
> +
> + GpioConfigurePads (GpioTableCount, GpioDefinition);
> +
> + DEBUG ((DEBUG_INFO, "ConfigureGpio() End\n"));
> +}
> +
> +/**
> + Configure GPIO group GPE tier.
> +
> + @retval none.
> +**/
> +VOID
> +GpioGroupTierInitHook(
> + VOID
> + )
> +{
> + DEBUG ((DEBUG_INFO, "GpioGroupTierInitHook Start\n"));
> +
> + if (PcdGet32 (PcdGpioGroupToGpeDw0)) {
> + GpioSetGroupToGpeDwX (PcdGet32 (PcdGpioGroupToGpeDw0),
> + PcdGet32 (PcdGpioGroupToGpeDw1),
> + PcdGet32 (PcdGpioGroupToGpeDw2));
> + }
> + DEBUG ((DEBUG_INFO, "GpioGroupTierInitHook End\n"));
> +}
> +
> +/**
> + Configure single GPIO pad for touchpanel interrupt
> +**/
> +VOID
> +TouchpanelGpioInit (
> + VOID
> + )
> +{
> + GPIO_INIT_CONFIG* TouchpanelPad;
> + GPIO_PAD_OWN PadOwnVal;
> +
> + PadOwnVal = 0;
> + TouchpanelPad = (VOID *) (UINTN) PcdGet32
> (PcdBoardGpioTableTouchPanel);
> + if (TouchpanelPad != NULL) {
> + GpioGetPadOwnership (TouchpanelPad->GpioPad, &PadOwnVal);
> + if (PadOwnVal == GpioPadOwnHost) {
> + GpioConfigurePads (1, TouchpanelPad);
> + }
> + }
> +}
> +
> +/**
> + Configure GPIO Before Memory is not ready.
> +
> +**/
> +VOID
> +GpioInitPreMem (
> + VOID
> + )
> +{
> + if (PcdGet32 (PcdBoardGpioTablePreMem) != 0 && PcdGet16
> (PcdBoardGpioTablePreMemSize) != 0) {
> + ConfigureGpio ((VOID *) (UINTN) PcdGet32
> (PcdBoardGpioTablePreMem), (UINTN) PcdGet16
> (PcdBoardGpioTablePreMemSize));
> + }
> +}
> +
> +/**
> + Basic GPIO configuration before memory is ready
> +
> +**/
> +VOID
> +GpioInitEarlyPreMem (
> + VOID
> + )
> +{
> + GPIO_CONFIG BbrstConfig;
> + UINT32 WwanBbrstGpio;
> +
> + WwanBbrstGpio = PcdGet32 (PcdWwanBbrstGpio);
> +
> + if (WwanBbrstGpio) {
> + //
> + // BIOS needs to put modem in OFF state for the two scenarios below.
> + // 1. Modem RESET# is not asserted via PLTRST# in the previous sleep
> state
> + // 2. Modem is disabled via setup option
> + //
> + GpioGetPadConfig (WwanBbrstGpio, &BbrstConfig);
> + if ((PcdGetBool (PcdPcieWwanEnable) == FALSE) ||
> + (PcdGetBool (PcdWwanResetWorkaround) == TRUE &&
> + BbrstConfig.Direction == GpioDirOut &&
> + BbrstConfig.OutputState == GpioOutHigh)) {
> + //
> + // Assert FULL_CARD_POWER_OFF#, RESET# and PERST# GPIOs
> + //
> + if (PcdGet32 (PcdBoardGpioTableWwanOffEarlyPreMem) != 0 &&
> PcdGet16 (PcdBoardGpioTableWwanOffEarlyPreMemSize) != 0) {
> + ConfigureGpio ((VOID *) (UINTN) PcdGet32
> (PcdBoardGpioTableWwanOffEarlyPreMem), (UINTN) PcdGet16
> (PcdBoardGpioTableWwanOffEarlyPreMemSize));
> + }
> + if (PcdGetBool (PcdPcieWwanEnable) == TRUE && PcdGetBool
> (PcdWwanResetWorkaround) == TRUE) {
> + MicroSecondDelay (1 * 1000); // Delay by 1ms
> + }
> + }
> +
> + //
> + // Turn ON modem power and de-assert RESET# and PERST# GPIOs
> + //
> + if (PcdGetBool (PcdPcieWwanEnable) == TRUE) {
> + if (PcdGet32 (PcdBoardGpioTableWwanOnEarlyPreMem) != 0 &&
> PcdGet16 (PcdBoardGpioTableWwanOnEarlyPreMemSize) != 0) {
> + ConfigureGpio ((VOID *) (UINTN) PcdGet32
> (PcdBoardGpioTableWwanOnEarlyPreMem), (UINTN) PcdGet16
> (PcdBoardGpioTableWwanOnEarlyPreMemSize));
> + }
> + }
> + }
> +}
> +
> +/**
> + Configure GPIO
> +
> +**/
> +VOID
> +GpioInit (
> + VOID
> + )
> +{
> + ConfigureGpio ((VOID *) (UINTN) PcdGet32 (PcdBoardGpioTable), (UINTN)
> PcdGet16 (PcdBoardGpioTableSize));
> +
> + if (PcdGet32 (PcdBoardGpioTable2)) {
> + ConfigureGpio ((VOID *) (UINTN) PcdGet32 (PcdBoardGpioTable2),
> (UINTN) PcdGet16 (PcdBoardGpioTable2Size));
> + }
> +
> + TouchpanelGpioInit ();
> +
> + //
> + // Lock pads after initializing platform GPIO.
> + // Pads which were requested to be unlocked during configuration
> + // will not be locked.
> + //
> + GpioLockPads ();
> +
> + return;
> +}
> +
> +/**
> + Configure Super IO
> +
> +**/
> +VOID
> +SioInit (
> + VOID
> + )
> +{
> + //
> + // Program and Enable Default Super IO Configuration Port Addresses and
> range
> + //
> + PchLpcGenIoRangeSet (PcdGet16 (PcdLpcSioConfigDefaultPort) & (~0xF),
> 0x10);
> +
> + PchLpcGenIoRangeSet (SIO_RUNTIME_REG_BASE_ADDRESS & (~0x7F),
> 0x10);
> +
> + return;
> +}
> +
> +/**
> + Configure GPIO and SIO before memory ready
> +
> + @retval EFI_SUCCESS Operation success.
> +**/
> +EFI_STATUS
> +BoardInitPreMem (
> + VOID
> + )
> +{
> + //
> + // Obtain Platform Info from HOB.
> + //
> + GpioInitPreMem ();
> + GpioGroupTierInitHook ();
> + SioInit ();
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Configure GPIO and SIO
> +
> + @retval EFI_SUCCESS Operation success.
> +**/
> +EFI_STATUS
> +BoardInit (
> + VOID
> + )
> +{
> +
> + GpioInit ();
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Do platform specific programming post-memory.
> +
> + @retval EFI_SUCCESS The function completed successfully.
> +**/
> +
> +EFI_STATUS
> +PlatformSpecificInit (
> + VOID
> + )
> +{
> + GPIO_CONFIG GpioConfig;
> +
> + if (IsCnlPch ()) {
> +
> + //
> + // Tristate unused pins by audio link mode.
> + //
> + ZeroMem(&GpioConfig, sizeof(GPIO_CONFIG));
> + GpioConfig.PadMode = GpioPadModeGpio;
> + GpioConfig.HostSoftPadOwn = GpioHostOwnGpio;
> + GpioConfig.Direction = GpioDirNone;
> + GpioConfig.OutputState = GpioOutDefault;
> + GpioConfig.InterruptConfig = GpioIntDis;
> + GpioConfig.PowerConfig = GpioPlatformReset;
> + GpioConfig.ElectricalConfig = GpioTermNone;
> +
> + GpioSetPadConfig (GPIO_CNL_LP_SSP1_SFRM, &GpioConfig);
> + GpioSetPadConfig (GPIO_CNL_LP_SSP1_TXD, &GpioConfig);
> +
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +/**
> + Early Board Configuration before memory is ready
> +
> + @retval EFI_SUCCESS Operation success.
> +**/
> +EFI_STATUS
> +BoardInitEarlyPreMem (
> + VOID
> + )
> +{
> + GpioInitEarlyPreMem ();
> +
> + return EFI_SUCCESS;
> +}
> +
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPlatformH
> ookLib/PeiPlatformHookLib.inf
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPlatformH
> ookLib/PeiPlatformHookLib.inf
> new file mode 100644
> index 0000000000..04349d9469
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPlatformH
> ookLib/PeiPlatformHookLib.inf
> @@ -0,0 +1,95 @@
> +## @file
> +#
> +# Copyright (c) 2020 Intel Corporation. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x00010017
> + BASE_NAME = PeiPlatformHookLib
> + FILE_GUID =
> AD901798-B0DA-4B20-B90C-283F886E76D0
> + VERSION_STRING = 1.0
> + MODULE_TYPE = PEIM
> + LIBRARY_CLASS = PeiPlatformHookLib|PEIM
> PEI_CORE SEC
> +
> +[LibraryClasses]
> + DebugLib
> + BaseMemoryLib
> + IoLib
> + HobLib
> + PcdLib
> + TimerLib
> + PchCycleDecodingLib
> + GpioLib
> + CpuPlatformLib
> + PeiServicesLib
> + ConfigBlockLib
> + PeiSaPolicyLib
> + GpioExpanderLib
> + PmcLib
> + PchPcrLib
> + PciSegmentLib
> + GpioCheckConflictLib
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + IntelSiliconPkg/IntelSiliconPkg.dec
> + CoffeelakeSiliconPkg/SiPkg.dec
> + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec
> +
> +[Pcd]
> + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
> ## CONSUMES
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioConfigDefaultPort
> ## CONSUMES
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSioBaseAddress
> ## CONSUMES
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdIoExpanderPresent
> ## CONSUMES
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDebugUsbUartEnable
> ## CONSUMES
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMipiCamGpioEnable
> ## CONSUMES
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable
> ## CONSUMES
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableSize
> ## CONSUMES
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable2
> ## CONSUMES
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable2Size
> ## CONSUMES
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTable
> ## CONSUMES
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTableSize
> ## CONSUMES
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTable2
> ## CONSUMES
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTable2Size
> ## CONSUMES
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableTouchPanel
> ## CONSUMES
> +
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTablePreMem
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTablePreMemSize
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOnEar
> lyPreMem
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOnEar
> lyPreMemSize
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOffEar
> lyPreMem
> +
> gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOffEar
> lyPreMemSize
> +
> + # GPIO Group Tier
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw0
> ## CONSUMES
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw1
> ## CONSUMES
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw2
> ## CONSUMES
> +
> + # Misc
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdIoExpanderPresent
> ## CONSUMES
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPc8374SioKbcPresent
> ## CONSUMES
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdOddPowerInitEnable
> ## CONSUMES
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdIvCamInitPresent
> ## CONSUMES
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRecoveryModeGpio
> ## CONSUMES
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdCpuVboostEnable
> ## CONSUMES
> +
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdWwanBbrstGpio
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieWwanEnable
> + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdWwanResetWorkaround
> +
> +[Sources]
> + PeiPlatformHookLib.c
> +
> +[Ppis]
> + gEfiPeiReadOnlyVariable2PpiGuid ## CONSUMES
> + gSiPolicyPpiGuid ## CONSUMES
> +
> +[Guids]
> + gSaDataHobGuid ## CONSUMES
> + gEfiGlobalVariableGuid ## CONSUMES
> + gGpioCheckConflictHobGuid ## CONSUMES
> +
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoar
> dConfigLib/PeiCpuPolicyBoardConfig.c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoar
> dConfigLib/PeiCpuPolicyBoardConfig.c
> new file mode 100644
> index 0000000000..d1d1920823
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoar
> dConfigLib/PeiCpuPolicyBoardConfig.c
> @@ -0,0 +1,49 @@
> +/** @file
> + Intel PEI CPU Policy update by board configuration
> +
> +
> + Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include "PeiPolicyBoardConfig.h"
> +#include <Library/ConfigBlockLib.h>
> +
> +/**
> + This function performs PEI CPU Policy update by board configuration.
> +
> + @param[in, out] SiPolicy The SI Policy PPI instance
> +
> + @retval EFI_SUCCESS The SI Policy is successfully updated.
> + @retval Others The SI Policy is not successfully
> updated.
> +**/
> +EFI_STATUS
> +EFIAPI
> +UpdatePeiCpuPolicyBoardConfig (
> + IN OUT SI_POLICY_PPI *SiPolicyPpi
> + )
> +{
> + EFI_STATUS Status;
> + SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig;
> + SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi;
> + CPU_CONFIG *CpuConfig;
> +
> + DEBUG((DEBUG_INFO, "Updating CPU Policy by board config in Post
> Mem\n"));
> +
> + Status = PeiServicesLocatePpi(
> + &gSiPreMemPolicyPpiGuid,
> + 0,
> + NULL,
> + (VOID **)&SiPreMemPolicyPpi
> + );
> + ASSERT_EFI_ERROR(Status);
> +
> + Status = GetConfigBlock((VOID *) SiPreMemPolicyPpi,
> &gSaMiscPeiPreMemConfigGuid, (VOID *) &MiscPeiPreMemConfig);
> + ASSERT_EFI_ERROR(Status);
> +
> + Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuConfigGuid, (VOID *)
> &CpuConfig);
> + ASSERT_EFI_ERROR (Status);
> +
> + return Status;
> +}
> +
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoar
> dConfigLib/PeiCpuPolicyBoardConfigPreMem.c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoar
> dConfigLib/PeiCpuPolicyBoardConfigPreMem.c
> new file mode 100644
> index 0000000000..2b80a268e6
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoar
> dConfigLib/PeiCpuPolicyBoardConfigPreMem.c
> @@ -0,0 +1,29 @@
> +/** @file
> + Intel PEI CPU Pre-Memory Policy update by board configuration
> +
> +
> + Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include "PeiPolicyBoardConfig.h"
> +#include <Library/ConfigBlockLib.h>
> +
> +/**
> + This function performs PEI CPU Pre-Memory Policy update by board
> configuration.
> +
> + @param[in, out] SiPolicy The SI PreMem Policy PPI instance
> +
> + @retval EFI_SUCCESS The SI Policy is successfully updated.
> + @retval Others The SI Policy is not successfully
> updated.
> +**/
> +EFI_STATUS
> +EFIAPI
> +UpdatePeiCpuPolicyBoardConfigPreMem (
> + IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi
> + )
> +{
> +
> + return EFI_SUCCESS;
> +}
> +
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoar
> dConfigLib/PeiMePolicyBoardConfig.c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoar
> dConfigLib/PeiMePolicyBoardConfig.c
> new file mode 100644
> index 0000000000..cff2b03ca9
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoar
> dConfigLib/PeiMePolicyBoardConfig.c
> @@ -0,0 +1,36 @@
> +/** @file
> + Intel PEI ME Policy update by board configuration
> +
> +
> + Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include "PeiPolicyBoardConfig.h"
> +#include <Library/ConfigBlockLib.h>
> +
> +/**
> + This function performs PEI ME Policy update by board configuration.
> +
> + @param[in, out] SiPolicy The SI Policy PPI instance
> +
> + @retval EFI_SUCCESS The SI Policy is successfully updated.
> + @retval Others The SI Policy is not successfully
> updated.
> +**/
> +EFI_STATUS
> +EFIAPI
> +UpdatePeiMePolicyBoardConfig (
> + IN OUT SI_POLICY_PPI *SiPolicyPpi
> + )
> +{
> + EFI_STATUS Status;
> + ME_PEI_CONFIG *MePeiConfig;
> +
> + DEBUG((DEBUG_INFO, "Updating ME Policy by board config in Post
> Mem\n"));
> +
> + Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gMePeiConfigGuid, (VOID
> *) &MePeiConfig);
> + ASSERT_EFI_ERROR (Status);
> +
> + return Status;
> +}
> +
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoar
> dConfigLib/PeiMePolicyBoardConfigPreMem.c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoar
> dConfigLib/PeiMePolicyBoardConfigPreMem.c
> new file mode 100644
> index 0000000000..610b6b8cb5
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoar
> dConfigLib/PeiMePolicyBoardConfigPreMem.c
> @@ -0,0 +1,37 @@
> +/** @file
> + Intel PEI ME Pre-Memory Policy update by board configuration
> +
> +
> + Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include "PeiPolicyBoardConfig.h"
> +#include <Library/ConfigBlockLib.h>
> +
> +/**
> + This function performs PEI ME Pre-Memory Policy update by board
> configuration.
> +
> + @param[in, out] SiPolicy The SI PreMem Policy PPI instance
> +
> + @retval EFI_SUCCESS The SI Policy is successfully updated.
> + @retval Others The SI Policy is not successfully
> updated.
> +**/
> +EFI_STATUS
> +EFIAPI
> +UpdatePeiMePolicyBoardConfigPreMem (
> + IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi
> + )
> +{
> + EFI_STATUS Status;
> + ME_PEI_PREMEM_CONFIG *MePeiPreMemConfig;
> +
> + DEBUG((DEBUG_INFO, "Updating ME Policy by board config in Pre
> Mem\n"));
> +
> + Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi,
> &gMePeiPreMemConfigGuid, (VOID *) &MePeiPreMemConfig);
> + ASSERT_EFI_ERROR (Status);
> +
> + return Status;
> +}
> +
> +
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoar
> dConfigLib/PeiPchPolicyBoardConfig.c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoar
> dConfigLib/PeiPchPolicyBoardConfig.c
> new file mode 100644
> index 0000000000..a3b3a63eec
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoar
> dConfigLib/PeiPchPolicyBoardConfig.c
> @@ -0,0 +1,36 @@
> +/** @file
> + Intel PEI PCH Policy update by board configuration
> +
> +
> + Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include "PeiPolicyBoardConfig.h"
> +#include <Library/ConfigBlockLib.h>
> +
> +/**
> + This function performs PEI PCH Policy update by board configuration.
> +
> + @param[in, out] SiPolicy The SI Policy PPI instance
> +
> + @retval EFI_SUCCESS The SI Policy is successfully updated.
> + @retval Others The SI Policy is not successfully
> updated.
> +**/
> +EFI_STATUS
> +EFIAPI
> +UpdatePeiPchPolicyBoardConfig (
> + IN OUT SI_POLICY_PPI *SiPolicyPpi
> + )
> +{
> + EFI_STATUS Status;
> + PCH_GENERAL_CONFIG *PchGeneralConfig;
> +
> + DEBUG((DEBUG_INFO, "Updating PCH Policy by board config in Post
> Mem\n"));
> +
> + Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gPchGeneralConfigGuid,
> (VOID *) &PchGeneralConfig);
> + ASSERT_EFI_ERROR (Status);
> +
> + return Status;
> +}
> +
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoar
> dConfigLib/PeiPchPolicyBoardConfigPreMem.c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoar
> dConfigLib/PeiPchPolicyBoardConfigPreMem.c
> new file mode 100644
> index 0000000000..01bb75525b
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoar
> dConfigLib/PeiPchPolicyBoardConfigPreMem.c
> @@ -0,0 +1,37 @@
> +/** @file
> + Intel PEI PCH Pre-Memory Policy update by board configuration
> +
> +
> + Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include "PeiPolicyBoardConfig.h"
> +#include <Library/ConfigBlockLib.h>
> +
> +/**
> + This function performs PEI PCH Pre-Memory Policy update by board
> configuration.
> +
> + @param[in, out] SiPolicy The SI PreMem Policy PPI instance
> +
> + @retval EFI_SUCCESS The SI Policy is successfully updated.
> + @retval Others The SI Policy is not successfully
> updated.
> +**/
> +EFI_STATUS
> +EFIAPI
> +UpdatePeiPchPolicyBoardConfigPreMem (
> + IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi
> + )
> +{
> + EFI_STATUS Status;
> + PCH_GENERAL_PREMEM_CONFIG *PchGeneralPreMemConfig;
> +
> + DEBUG((DEBUG_INFO, "Updating PCH Policy by board config in Pre
> Mem\n"));
> +
> + Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi,
> &gPchGeneralPreMemConfigGuid, (VOID *) &PchGeneralPreMemConfig);
> + ASSERT_EFI_ERROR (Status);
> +
> + return Status;
> +}
> +
> +
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoar
> dConfigLib/PeiPolicyBoardConfig.h
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoar
> dConfigLib/PeiPolicyBoardConfig.h
> new file mode 100644
> index 0000000000..64f6c67639
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoar
> dConfigLib/PeiPolicyBoardConfig.h
> @@ -0,0 +1,22 @@
> +/** @file
> + Header file for PeiPolicyBoardConfig library instance.
> +
> +
> + Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#ifndef _PEI_POLICY_BOARD_CONFIG_H_
> +#define _PEI_POLICY_BOARD_CONFIG_H_
> +
> +#include <PiPei.h>
> +#include <ConfigBlock/MePeiConfig.h>
> +#include <Library/PeiServicesLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/HobLib.h>
> +#include <Library/PeiPolicyBoardConfigLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/BaseMemoryLib.h>
> +
> +#endif
> +
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoar
> dConfigLib/PeiPolicyBoardConfigLib.inf
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoar
> dConfigLib/PeiPolicyBoardConfigLib.inf
> new file mode 100644
> index 0000000000..aaf0abbf04
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoar
> dConfigLib/PeiPolicyBoardConfigLib.inf
> @@ -0,0 +1,71 @@
> +## @file
> +# Module Information file for PeiPolicyBoardConfigLib Library
> +#
> +#
> +# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x00010017
> + BASE_NAME = PeiPolicyBoardConfigLib
> + FILE_GUID =
> B1E959E3-9DCA-4D6F-938C-420C3BF5D820
> + VERSION_STRING = 1.0
> + MODULE_TYPE = PEIM
> + LIBRARY_CLASS = PeiPolicyBoardConfigLib|PEIM
> PEI_CORE SEC
> +
> +[Sources]
> + PeiCpuPolicyBoardConfigPreMem.c
> + PeiCpuPolicyBoardConfig.c
> + PeiMePolicyBoardConfigPreMem.c
> + PeiMePolicyBoardConfig.c
> + PeiPchPolicyBoardConfigPreMem.c
> + PeiPchPolicyBoardConfig.c
> + PeiSaPolicyBoardConfigPreMem.c
> + PeiSaPolicyBoardConfig.c
> + PeiSiPolicyBoardConfig.c
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + SecurityPkg/SecurityPkg.dec
> + IntelSiliconPkg/IntelSiliconPkg.dec
> + CoffeelakeSiliconPkg/SiPkg.dec
> + MinPlatformPkg/MinPlatformPkg.dec
> + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec
> +
> +[LibraryClasses]
> + PcdLib
> + DebugLib
> + HobLib
> + ConfigBlockLib
> + IoLib
> + BaseCryptLib
> + BaseMemoryLib
> +
> +[Guids]
> + gCpuSecurityPreMemConfigGuid ## CONSUMES
> + gMePeiPreMemConfigGuid ## CONSUMES
> + gPchGeneralPreMemConfigGuid ## CONSUMES
> + gSaMiscPeiPreMemConfigGuid ## CONSUMES
> + gCpuConfigGuid ## CONSUMES
> + gPchGeneralConfigGuid ## CONSUMES
> + gEfiTpmDeviceInstanceTpm20DtpmGuid
> + gEfiTpmDeviceInstanceTpm12Guid
> +
> +[Ppis]
> + gEfiPeiReadOnlyVariable2PpiGuid ## CONSUMES
> +
> +[Pcd]
> + gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress ##
> CONSUMES
> + gPlatformModuleTokenSpaceGuid.PcdDmiBaseAddress ##
> CONSUMES
> + gPlatformModuleTokenSpaceGuid.PcdEpBaseAddress ## CONSUMES
> + gPlatformModuleTokenSpaceGuid.PcdEdramBaseAddress ##
> CONSUMES
> + gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid ## CONSUMES
> +
> +[FixedPcd]
> + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize
> ## CONSUMES
> +
> +
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoar
> dConfigLib/PeiSaPolicyBoardConfig.c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoar
> dConfigLib/PeiSaPolicyBoardConfig.c
> new file mode 100644
> index 0000000000..a8f6860bd0
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoar
> dConfigLib/PeiSaPolicyBoardConfig.c
> @@ -0,0 +1,36 @@
> +/** @file
> + Intel PEI SA Policy update by board configuration
> +
> +
> + Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include "PeiPolicyBoardConfig.h"
> +#include <Library/ConfigBlockLib.h>
> +
> +/**
> + This function performs PEI SA Policy update by board configuration.
> +
> + @param[in, out] SiPolicy The SI Policy PPI instance
> +
> + @retval EFI_SUCCESS The SI Policy is successfully updated.
> + @retval Others The SI Policy is not successfully
> updated.
> +**/
> +EFI_STATUS
> +EFIAPI
> +UpdatePeiSaPolicyBoardConfig (
> + IN OUT SI_POLICY_PPI *SiPolicyPpi
> + )
> +{
> + EFI_STATUS Status;
> + GRAPHICS_PEI_CONFIG *GtConfig;
> +
> + DEBUG((DEBUG_INFO, "Updating SA Policy by board config in Post
> Mem\n"));
> +
> + Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gGraphicsPeiConfigGuid,
> (VOID *)&GtConfig);
> + ASSERT_EFI_ERROR (Status);
> +
> + return Status;
> +}
> +
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoar
> dConfigLib/PeiSaPolicyBoardConfigPreMem.c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoar
> dConfigLib/PeiSaPolicyBoardConfigPreMem.c
> new file mode 100644
> index 0000000000..c1c6915b10
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoar
> dConfigLib/PeiSaPolicyBoardConfigPreMem.c
> @@ -0,0 +1,30 @@
> +/** @file
> + Intel PEI SA Pre-Memory Policy update by board configuration
> +
> +
> + Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include "PeiPolicyBoardConfig.h"
> +#include <ConfigBlock/SaMiscPeiPreMemConfig.h>
> +#include <Library/ConfigBlockLib.h>
> +
> +/**
> + This function performs PEI SA Pre-Memory Policy update by board
> configuration.
> +
> + @param[in, out] SiPolicy The SI PreMem Policy PPI instance
> +
> + @retval EFI_SUCCESS The SI Policy is successfully updated.
> + @retval Others The SI Policy is not successfully
> updated.
> +**/
> +EFI_STATUS
> +EFIAPI
> +UpdatePeiSaPolicyBoardConfigPreMem (
> + IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi
> + )
> +{
> + return EFI_SUCCESS;
> +}
> +
> +
> diff --git
> a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoar
> dConfigLib/PeiSiPolicyBoardConfig.c
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoar
> dConfigLib/PeiSiPolicyBoardConfig.c
> new file mode 100644
> index 0000000000..e8dd2b9609
> --- /dev/null
> +++
> b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoar
> dConfigLib/PeiSiPolicyBoardConfig.c
> @@ -0,0 +1,27 @@
> +/** @file
> + Intel PEI SA Policy update by board configuration
> +
> +
> + Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +**/
> +
> +#include "PeiPolicyBoardConfig.h"
> +
> +/**
> + This function performs PEI SI Policy update by board configuration.
> +
> + @param[in, out] SiPolicy The SI Policy PPI instance
> +
> + @retval EFI_SUCCESS The SI Policy is successfully updated.
> + @retval Others The SI Policy is not successfully
> updated.
> +**/
> +EFI_STATUS
> +EFIAPI
> +UpdatePeiSiPolicyBoardConfig (
> + IN OUT SI_POLICY_PPI *SiPolicyPpi
> + )
> +{
> + return EFI_SUCCESS;
> +}
> +
> --
> 2.19.1.windows.1
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [edk2-platforms] [PATCH v3 3/4] WhiskeylakeOpenBoardPkg/UpXtreme: Add Includes and Libraries
2020-02-21 0:49 ` [edk2-platforms] [PATCH v3 3/4] WhiskeylakeOpenBoardPkg/UpXtreme: Add Includes and Libraries Agyeman, Prince
2020-02-21 2:00 ` Chiu, Chasel
@ 2020-02-21 2:26 ` Nate DeSimone
1 sibling, 0 replies; 7+ messages in thread
From: Nate DeSimone @ 2020-02-21 2:26 UTC (permalink / raw)
To: Agyeman, Prince, devel@edk2.groups.io; +Cc: Chiu, Chasel
Hi Prince,
Agreed with Chasel. Once the MTRRs are programmed by FSP-T, you cannot change them again until after MRC is done. Note that after changing the MTRRs one must execute a WBINVD instruction for the new values to take effect. However, while we are in Cache-As-RAM mode a WBINVD will destroy the contents of memory which will immediately cause a CATERR.
This can be remedied by adjusting the CodeRegionBase & CodeRegionSize UPDs provided to TempRamInit() so that the MTRRs will be set properly at the very beginning.
Thanks,
Nate
-----Original Message-----
From: Agyeman, Prince <prince.agyeman@intel.com>
Sent: Thursday, February 20, 2020 4:49 PM
To: devel@edk2.groups.io
Cc: Chiu, Chasel <chasel.chiu@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>
Subject: [edk2-platforms] [PATCH v3 3/4] WhiskeylakeOpenBoardPkg/UpXtreme: Add Includes and Libraries
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2191
Adds the Include directory and UpXtreme board-specific library
class instances.
Co-authored-by: Michael Kubacki <michael.a.kubacki@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Signed-off-by: Prince Agyeman <prince.agyeman@intel.com>
---
.../PeiFspMiscUpdUpdateLib.c | 110 +
.../PeiFspPolicyUpdateLib.c | 126 +
.../PeiMiscPolicyUpdate.h | 25 +
.../PeiPchPolicyUpdate.c | 300 ++
.../PeiPchPolicyUpdate.h | 28 +
.../PeiPchPolicyUpdatePreMem.c | 39 +
.../PeiSaPolicyUpdate.c | 158 +
.../PeiSaPolicyUpdate.h | 45 +
.../PeiSaPolicyUpdatePreMem.c | 124 +
.../PeiSiliconPolicyUpdateLibFsp.inf | 144 +
.../FspWrapperPlatformSecLib.c | 186 +
.../SecFspWrapperPlatformSecLib/FsptCoreUpd.h | 40 +
.../SecFspWrapperPlatformSecLib/Ia32/Fsp.h | 42 +
.../Ia32/PeiCoreEntry.nasm | 130 +
.../Ia32/SecEntry.nasm | 361 ++
.../Ia32/Stack.nasm | 72 +
.../PlatformInit.c | 47 +
.../SecFspWrapperPlatformSecLib.inf | 105 +
.../SecGetPerformance.c | 89 +
.../SecPlatformInformation.c | 78 +
.../SecRamInitData.c | 55 +
.../SecTempRamDone.c | 93 +
.../UpXtreme/Include/Fdf/FlashMapInclude.fdf | 51 +
.../Include/Library/PeiPlatformHookLib.h | 131 +
.../UpXtreme/Include/Library/PeiPlatformLib.h | 38 +
.../UpXtreme/Include/PlatformBoardConfig.h | 103 +
.../UpXtreme/Include/PlatformInfo.h | 42 +
.../Library/BaseFuncLib/BaseFuncLib.inf | 33 +
.../UpXtreme/Library/BaseFuncLib/Gop.c | 38 +
.../BaseGpioCheckConflictLib.c | 137 +
.../BaseGpioCheckConflictLib.inf | 35 +
.../BaseGpioCheckConflictLibNull.c | 37 +
.../BaseGpioCheckConflictLibNull.inf | 32 +
.../BasePlatformHookLib/BasePlatformHookLib.c | 143 +
.../BasePlatformHookLib.inf | 45 +
.../BoardAcpiLib/SmmBoardAcpiEnableLib.c | 63 +
.../BoardAcpiLib/SmmBoardAcpiEnableLib.inf | 50 +
.../SmmMultiBoardAcpiSupportLib.c | 82 +
.../SmmMultiBoardAcpiSupportLib.inf | 50 +
.../BoardAcpiLib/SmmSiliconAcpiEnableLib.c | 170 +
.../BoardAcpiLib/SmmUpXtremeAcpiEnableLib.c | 40 +
.../BoardInitLib/BoardFuncInitPreMem.c | 25 +
.../Library/BoardInitLib/BoardInitLib.h | 20 +
.../BoardInitLib/BoardPchInitPreMemLib.c | 375 ++
.../BoardInitLib/BoardSaConfigPreMem.h | 79 +
.../BoardInitLib/BoardSaInitPreMemLib.c | 298 ++
.../Library/BoardInitLib/GpioTableDefault.c | 213 ++
.../Library/BoardInitLib/GpioTableUpXtreme.c | 217 ++
.../Library/BoardInitLib/PchHdaVerbTables.h | 3014 +++++++++++++++++
.../BoardInitLib/PeiBoardInitPostMemLib.c | 40 +
.../BoardInitLib/PeiBoardInitPostMemLib.inf | 57 +
.../BoardInitLib/PeiBoardInitPreMemLib.c | 106 +
.../BoardInitLib/PeiBoardInitPreMemLib.inf | 124 +
.../PeiMultiBoardInitPostMemLib.c | 41 +
.../PeiMultiBoardInitPostMemLib.inf | 202 ++
.../BoardInitLib/PeiMultiBoardInitPreMemLib.c | 83 +
.../PeiMultiBoardInitPreMemLib.inf | 308 ++
.../Library/BoardInitLib/PeiUpXtremeDetect.c | 192 ++
.../BoardInitLib/PeiUpXtremeInitPostMemLib.c | 416 +++
.../BoardInitLib/PeiUpXtremeInitPreMemLib.c | 659 ++++
.../BoardInitLib/UpXtremeHsioPtssTables.c | 32 +
.../Library/BoardInitLib/UpXtremeInit.h | 44 +
.../Library/BoardInitLib/UpXtremeSpdTable.c | 86 +
.../DxePolicyBoardConfig.h | 19 +
.../DxePolicyBoardConfigLib.inf | 45 +
.../DxeSaPolicyBoardConfig.c | 36 +
.../PeiPlatformHookLib/PeiPlatformHookLib.c | 298 ++
.../PeiPlatformHookLib/PeiPlatformHookLib.inf | 95 +
.../PeiCpuPolicyBoardConfig.c | 49 +
.../PeiCpuPolicyBoardConfigPreMem.c | 29 +
.../PeiMePolicyBoardConfig.c | 36 +
.../PeiMePolicyBoardConfigPreMem.c | 37 +
.../PeiPchPolicyBoardConfig.c | 36 +
.../PeiPchPolicyBoardConfigPreMem.c | 37 +
.../PeiPolicyBoardConfig.h | 22 +
.../PeiPolicyBoardConfigLib.inf | 71 +
.../PeiSaPolicyBoardConfig.c | 36 +
.../PeiSaPolicyBoardConfigPreMem.c | 30 +
.../PeiSiPolicyBoardConfig.c | 27 +
79 files changed, 11251 insertions(+)
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspPolicyUpdateLib.c
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiMiscPolicyUpdate.h
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.c
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.h
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdatePreMem.c
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.h
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecFspWrapperPlatformSecLib/FspWrapperPlatformSecLib.c
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Fsp.h
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/PeiCoreEntry.nasm
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Stack.nasm
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecFspWrapperPlatformSecLib/PlatformInit.c
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecGetPerformance.c
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecPlatformInformation.c
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecRamInitData.c
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecTempRamDone.c
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Include/Fdf/FlashMapInclude.fdf
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Include/Library/PeiPlatformHookLib.h
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Include/Library/PeiPlatformLib.h
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Include/PlatformBoardConfig.h
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Include/PlatformInfo.h
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BaseFuncLib/BaseFuncLib.inf
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BaseFuncLib/Gop.c
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BaseGpioCheckConflictLib/BaseGpioCheckConflictLib.c
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BaseGpioCheckConflictLib/BaseGpioCheckConflictLib.inf
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BaseGpioCheckConflictLibNull/BaseGpioCheckConflictLibNull.c
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BaseGpioCheckConflictLibNull/BaseGpioCheckConflictLibNull.inf
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BasePlatformHookLib/BasePlatformHookLib.c
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BasePlatformHookLib/BasePlatformHookLib.inf
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.c
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardAcpiLib/SmmUpXtremeAcpiEnableLib.c
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/BoardFuncInitPreMem.c
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/BoardInitLib.h
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/BoardPchInitPreMemLib.c
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/BoardSaConfigPreMem.h
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/BoardSaInitPreMemLib.c
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/GpioTableDefault.c
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/GpioTableUpXtreme.c
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/PchHdaVerbTables.h
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/PeiBoardInitPostMemLib.c
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/PeiBoardInitPostMemLib.inf
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/PeiBoardInitPreMemLib.c
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/PeiBoardInitPreMemLib.inf
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.c
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.c
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/PeiUpXtremeDetect.c
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/PeiUpXtremeInitPostMemLib.c
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/PeiUpXtremeInitPreMemLib.c
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/UpXtremeHsioPtssTables.c
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/UpXtremeInit.h
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/UpXtremeSpdTable.c
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/DxePolicyBoardConfigLib/DxePolicyBoardConfig.h
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/DxePolicyBoardConfigLib/DxePolicyBoardConfigLib.inf
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/DxePolicyBoardConfigLib/DxeSaPolicyBoardConfig.c
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPlatformHookLib/PeiPlatformHookLib.c
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPlatformHookLib/PeiPlatformHookLib.inf
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoardConfigLib/PeiCpuPolicyBoardConfig.c
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoardConfigLib/PeiCpuPolicyBoardConfigPreMem.c
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoardConfigLib/PeiMePolicyBoardConfig.c
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoardConfigLib/PeiMePolicyBoardConfigPreMem.c
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoardConfigLib/PeiPchPolicyBoardConfig.c
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoardConfigLib/PeiPchPolicyBoardConfigPreMem.c
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoardConfigLib/PeiPolicyBoardConfig.h
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoardConfigLib/PeiPolicyBoardConfigLib.inf
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoardConfigLib/PeiSaPolicyBoardConfig.c
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoardConfigLib/PeiSaPolicyBoardConfigPreMem.c
create mode 100644 Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoardConfigLib/PeiSiPolicyBoardConfig.c
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
new file mode 100644
index 0000000000..145deb5de3
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
@@ -0,0 +1,110 @@
+/** @file
+ Implementation of Fsp Misc UPD Initialization.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiPei.h>
+
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PeiLib.h>
+#include <Library/ConfigBlockLib.h>
+#include <Library/PeiServicesLib.h>
+
+#include <FspEas.h>
+#include <FspmUpd.h>
+#include <FspsUpd.h>
+
+#include <Library/MemoryAllocationLib.h>
+#include <Library/DebugLib.h>
+#include <Library/DebugPrintErrorLevelLib.h>
+#include <Library/PciLib.h>
+#include <Ppi/ReadOnlyVariable2.h>
+#include <Guid/MemoryOverwriteControl.h>
+#include <PchAccess.h>
+#include <Platform.h>
+
+#include "PeiMiscPolicyUpdate.h"
+
+/**
+ Performs FSP Misc UPD initialization.
+
+ @param[in,out] FspmUpd Pointer to FSPM_UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+ @retval EFI_NOT_FOUND An instance of gEfiPeiReadOnlyVariable2PpiGuid
+ could not be located.
+ @retval EFI_OUT_OF_RESOURCES Insufficent resources to allocate a memory buffer.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspMiscUpdUpdatePreMem (
+ IN OUT FSPM_UPD *FspmUpd
+ )
+{
+ EFI_STATUS Status;
+ EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices;
+ UINTN VariableSize;
+ VOID *MemorySavedData;
+
+ Status = PeiServicesLocatePpi (
+ &gEfiPeiReadOnlyVariable2PpiGuid,
+ 0,
+ NULL,
+ (VOID **) &VariableServices
+ );
+ if (EFI_ERROR (Status)) {
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+ }
+
+ VariableSize = 0;
+ MemorySavedData = NULL;
+ Status = VariableServices->GetVariable (
+ VariableServices,
+ L"MemoryConfig",
+ &gFspNonVolatileStorageHobGuid,
+ NULL,
+ &VariableSize,
+ MemorySavedData
+ );
+ if (Status == EFI_BUFFER_TOO_SMALL) {
+ MemorySavedData = AllocatePool (VariableSize);
+ if (MemorySavedData == NULL) {
+ ASSERT (MemorySavedData != NULL);
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ DEBUG ((DEBUG_INFO, "VariableSize is 0x%x\n", VariableSize));
+ Status = VariableServices->GetVariable (
+ VariableServices,
+ L"MemoryConfig",
+ &gFspNonVolatileStorageHobGuid,
+ NULL,
+ &VariableSize,
+ MemorySavedData
+ );
+ if (Status == EFI_SUCCESS) {
+ FspmUpd->FspmArchUpd.NvsBufferPtr = MemorySavedData;
+ } else {
+ FspmUpd->FspmArchUpd.NvsBufferPtr = NULL;
+ DEBUG ((DEBUG_ERROR, "Fail to retrieve Variable:\"MemoryConfig\" gMemoryConfigVariableGuid, Status = %r\n", Status));
+ ASSERT_EFI_ERROR (Status);
+ }
+ }
+
+ FspmUpd->FspmConfig.TsegSize = FixedPcdGet32 (PcdTsegSize);
+ FspmUpd->FspmConfig.CpuRatio = 0;
+ FspmUpd->FspmConfig.CaVrefConfig = PcdGet8 (PcdMrcCaVrefConfig);
+ FspmUpd->FspmConfig.PlatformMemorySize = PEI_MIN_MEMORY_SIZE;
+ FspmUpd->FspmConfig.PcdSerialDebugLevel = 3;
+ FspmUpd->FspmConfig.SafeMode = 0;
+ FspmUpd->FspmConfig.PeciC10Reset = 0;
+
+ return EFI_SUCCESS;
+}
+
+
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspPolicyUpdateLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspPolicyUpdateLib.c
new file mode 100644
index 0000000000..1381c426ca
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspPolicyUpdateLib.c
@@ -0,0 +1,126 @@
+/** @file
+ Provide FSP wrapper platform related function.
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiPei.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/FspWrapperApiLib.h>
+#include <Library/SiliconPolicyUpdateLib.h>
+
+#include <FspEas.h>
+#include <FspmUpd.h>
+#include <FspsUpd.h>
+
+#include "PeiSaPolicyUpdate.h"
+#include "PeiMiscPolicyUpdate.h"
+
+/**
+ Performs FSP PCH PEI Policy initialization.
+
+ @param[in][out] FspsUpd Pointer to FSP UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+ @retval EFI_NOT_FOUND Fail to locate required PPI.
+ @retval Other FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspPchPolicyUpdate (
+ IN OUT FSPS_UPD *FspsUpd
+ );
+
+VOID
+InternalPrintVariableData (
+ IN UINT8 *Data8,
+ IN UINTN DataSize
+ )
+{
+ UINTN Index;
+
+ for (Index = 0; Index < DataSize; Index++) {
+ if (Index % 0x10 == 0) {
+ DEBUG ((DEBUG_INFO, "\n%08X:", Index));
+ }
+ DEBUG ((DEBUG_INFO, " %02X", *Data8++));
+ }
+ DEBUG ((DEBUG_INFO, "\n"));
+}
+
+/**
+ Performs silicon pre-mem policy update.
+
+ The meaning of Policy is defined by silicon code.
+ It could be the raw data, a handle, a PPI, etc.
+
+ The input Policy must be returned by SiliconPolicyDonePreMem().
+
+ 1) In FSP path, the input Policy should be FspmUpd.
+ A platform may use this API to update the FSPM UPD policy initialized
+ by the silicon module or the default UPD data.
+ The output of FSPM UPD data from this API is the final UPD data.
+
+ 2) In non-FSP path, the board may use additional way to get
+ the silicon policy data field based upon the input Policy.
+
+ @param[in, out] Policy Pointer to policy.
+
+ @return the updated policy.
+**/
+VOID *
+EFIAPI
+SiliconPolicyUpdatePreMem (
+ IN OUT VOID *FspmUpd
+ )
+{
+ FSPM_UPD *FspmUpdDataPtr;
+
+ FspmUpdDataPtr = FspmUpd;
+
+ PeiFspSaPolicyUpdatePreMem (FspmUpdDataPtr);
+ PeiFspMiscUpdUpdatePreMem (FspmUpdDataPtr);
+ InternalPrintVariableData ((VOID *) FspmUpdDataPtr, sizeof (FSPM_UPD));
+
+ return FspmUpd;
+}
+
+/**
+ Performs silicon post-mem policy update.
+
+ The meaning of Policy is defined by silicon code.
+ It could be the raw data, a handle, a PPI, etc.
+
+ The input Policy must be returned by SiliconPolicyDonePostMem().
+
+ 1) In FSP path, the input Policy should be FspsUpd.
+ A platform may use this API to update the FSPS UPD policy initialized
+ by the silicon module or the default UPD data.
+ The output of FSPS UPD data from this API is the final UPD data.
+
+ 2) In non-FSP path, the board may use additional way to get
+ the silicon policy data field based upon the input Policy.
+
+ @param[in, out] Policy Pointer to policy.
+
+ @return the updated policy.
+**/
+VOID *
+EFIAPI
+SiliconPolicyUpdatePostMem (
+ IN OUT VOID *FspsUpd
+ )
+{
+ FSPS_UPD *FspsUpdDataPtr;
+
+ FspsUpdDataPtr = FspsUpd;
+
+ PeiFspPchPolicyUpdate (FspsUpd);
+ InternalPrintVariableData ((VOID * ) FspsUpdDataPtr, sizeof (FSPS_UPD));
+
+ return FspsUpd;
+}
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiMiscPolicyUpdate.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiMiscPolicyUpdate.h
new file mode 100644
index 0000000000..1f2e82cf43
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiMiscPolicyUpdate.h
@@ -0,0 +1,25 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_MISC_POLICY_UPDATE_H_
+#define _PEI_MISC_POLICY_UPDATE_H_
+
+#include <FspmUpd.h>
+
+/**
+ Performs FSP Misc UPD initialization.
+
+ @param[in][out] FspmUpd Pointer to FSPM_UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspMiscUpdUpdatePreMem (
+ IN OUT FSPM_UPD *FspmUpd
+ );
+
+#endif
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.c
new file mode 100644
index 0000000000..a089fecd3c
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.c
@@ -0,0 +1,300 @@
+/** @file
+ This file is SampleCode of the library for Intel PCH PEI Policy initialization.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiPchPolicyUpdate.h"
+#include <Library/BaseMemoryLib.h>
+#include <Library/HdaVerbTableLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/HobLib.h>
+#include <Guid/GlobalVariable.h>
+#include <Library/PchGbeLib.h>
+#include <Library/PchInfoLib.h>
+#include <Library/PchPcrLib.h>
+#include <Library/PchHsioLib.h>
+#include <Library/PchSerialIoLib.h>
+#include <Library/PchPcieRpLib.h>
+#include <GpioConfig.h>
+#include <GpioPinsSklH.h>
+#include <Library/DebugLib.h>
+#include <Library/PchGbeLib.h>
+#include <PcieDeviceOverrideTable.h>
+
+CONST UINT8 mPchSerialIoDevMode[PCH_MAX_SERIALIO_CONTROLLERS] = {
+ 1 /* I2C0 */, 1 /* I2C1 */, 0 /* I2C2 */, 0 /* I2C3 */, 0 /* I2C4 */, 0 /* I2C5 */,
+ 0 /* SPI0 */, 0 /* SPI1 */, 0 /* SPI2 */, 1 /* UART0 */, 0 /* UART1 */, 3 /* UART2 */
+};
+
+CONST UINT8 mPchLpSerialIoDevMode[PCH_MAX_SERIALIO_CONTROLLERS] = {
+ 1 /* I2C0 */, 1 /* I2C1 */, 0 /* I2C2 */, 0 /* I2C3 */, 0 /* I2C4 */, 0 /* I2C5 */,
+ 0 /* SPI0 */, 0 /* SPI1 */, 0 /* SPI2 */, 0 /* UART0 */, 0 /* UART1 */, 0 /* UART2 */
+};
+
+/**
+ Performs FSP PCH PEI Policy initialization.
+
+ @param[in][out] FspsUpd Pointer to FSP UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+ @retval EFI_NOT_FOUND Fail to locate required PPI.
+ @retval Other FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspPchPolicyUpdate (
+ IN OUT FSPS_UPD *FspsUpd
+ )
+{
+ UINT32 Index;
+ UINT32 Length;
+
+ FspsUpd->FspsConfig.PchPcieDeviceOverrideTablePtr = (UINT32) mPcieDeviceTable;
+
+ FspsUpd->FspsConfig.PchPmSlpS3MinAssert = 0;
+ FspsUpd->FspsConfig.PchPmSlpS4MinAssert = 0;
+ FspsUpd->FspsConfig.PchPmSlpSusMinAssert = 0;
+ FspsUpd->FspsConfig.PchPmSlpAMinAssert = 0;
+ FspsUpd->FspsConfig.PchPmLpcClockRun = 1;
+ FspsUpd->FspsConfig.EnableTcoTimer = 0;
+ FspsUpd->FspsConfig.Enable8254ClockGating = 0;
+ FspsUpd->FspsConfig.Enable8254ClockGatingOnS3 = 0;
+
+ FspsUpd->FspsConfig.ScsEmmcEnabled = 1;
+ FspsUpd->FspsConfig.ScsEmmcHs400Enabled = 1;
+ FspsUpd->FspsConfig.ScsSdCardEnabled = 0;
+ FspsUpd->FspsConfig.ScsUfsEnabled = 0;
+
+ FspsUpd->FspsConfig.SataPwrOptEnable = 1;
+
+ FspsUpd->FspsConfig.GpioIrqRoute = 14;
+ FspsUpd->FspsConfig.SciIrqSelect = 9;
+ FspsUpd->FspsConfig.TcoIrqEnable = 0;
+ FspsUpd->FspsConfig.TcoIrqSelect = 9;
+
+ AddPlatformVerbTables (
+ PchHdaCodecPlatformOnboard,
+ &(FspsUpd->FspsConfig.PchHdaVerbTableEntryNum),
+ &(FspsUpd->FspsConfig.PchHdaVerbTablePtr)
+ );
+
+DEBUG_CODE_BEGIN();
+ if (
+ (FixedPcdGet8 (PcdSerialIoUartDebugEnable) == 1) &&
+ FspsUpd->FspsConfig.SerialIoDevMode[PchSerialIoIndexUart0 + PcdGet8 (PcdSerialIoUartNumber)] == PchSerialIoDisabled
+ ) {
+ FspsUpd->FspsConfig.SerialIoDevMode[PchSerialIoIndexUart0 + PcdGet8 (PcdSerialIoUartNumber)] = PchSerialIoHidden;
+ }
+ FspsUpd->FspsConfig.SerialIoDebugUartNumber = PcdGet8 (PcdSerialIoUartNumber);
+ FspsUpd->FspsConfig.SerialIoEnableDebugUartAfterPost = TRUE;
+ FspsUpd->FspsConfig.SerialIoUartHwFlowCtrl[PcdGet8 (PcdSerialIoUartNumber)] = 0;
+DEBUG_CODE_END();
+
+ //
+ // SerialIo config
+ //
+ if (IsPchLp()) {
+ CopyMem (&FspsUpd->FspsConfig.SerialIoDevMode, mPchLpSerialIoDevMode, PCH_MAX_SERIALIO_CONTROLLERS);
+ } else {
+ CopyMem (&FspsUpd->FspsConfig.SerialIoDevMode, mPchSerialIoDevMode, PCH_MAX_SERIALIO_CONTROLLERS);
+ }
+
+ // Set debug UART in PCI mode
+ FspsUpd->FspsConfig.SerialIoDevMode[PCH_MAX_SERIALIO_I2C_CONTROLLERS + PCH_MAX_SERIALIO_SPI_CONTROLLERS + 2] = 1;
+
+ FspsUpd->FspsConfig.SerialIoSpiCsPolarity[0] = 1;
+ FspsUpd->FspsConfig.SerialIoSpiCsPolarity[1] = 0;
+ FspsUpd->FspsConfig.SerialIoSpiCsPolarity[2] = 0;
+ FspsUpd->FspsConfig.SerialIoUartHwFlowCtrl[0] = 1;
+ FspsUpd->FspsConfig.SerialIoUartHwFlowCtrl[1] = 1;
+ FspsUpd->FspsConfig.SerialIoUartHwFlowCtrl[2] = 1;
+ FspsUpd->FspsConfig.PchSerialIoI2cPadsTermination[0] = 1;
+ FspsUpd->FspsConfig.PchSerialIoI2cPadsTermination[1] = 1;
+ FspsUpd->FspsConfig.PchSerialIoI2cPadsTermination[2] = 1;
+ FspsUpd->FspsConfig.PchSerialIoI2cPadsTermination[3] = 1;
+ FspsUpd->FspsConfig.PchSerialIoI2cPadsTermination[4] = 1;
+ FspsUpd->FspsConfig.PchSerialIoI2cPadsTermination[5] = 1;
+
+ //
+ // USB config
+ //
+ FspsUpd->FspsConfig.XdciEnable = FALSE;
+ FspsUpd->FspsConfig.PchEnableComplianceMode = FALSE;
+ FspsUpd->FspsConfig.UsbPdoProgramming = TRUE;
+ FspsUpd->FspsConfig.PchUsbOverCurrentEnable = TRUE;
+ FspsUpd->FspsConfig.PchUsb2PhySusPgEnable = TRUE;
+ FspsUpd->FspsTestConfig.PchXhciOcLock = TRUE;
+
+ Length = GetPchXhciMaxUsb2PortNum ();
+ for (Index = 0; Index < Length; Index++) {
+ FspsUpd->FspsConfig.PortUsb20Enable[Index] = TRUE;
+ FspsUpd->FspsConfig.Usb2OverCurrentPin[Index] = UsbOverCurrentPinMax;
+ FspsUpd->FspsConfig.Usb2AfePetxiset[Index] = 7;
+ FspsUpd->FspsConfig.Usb2AfeTxiset[Index] = 5;
+ FspsUpd->FspsConfig.Usb2AfePredeemp[Index] = 3;
+ FspsUpd->FspsConfig.Usb2AfePehalfbit[Index] = 0;
+ }
+
+ Length = GetPchXhciMaxUsb3PortNum ();
+ for (Index = 0; Index < Length; Index++) {
+ FspsUpd->FspsConfig.PortUsb30Enable[Index] = TRUE;
+ FspsUpd->FspsConfig.Usb3OverCurrentPin[Index] = UsbOverCurrentPinMax;
+ FspsUpd->FspsConfig.Usb3HsioTxDeEmphEnable[Index] = 0;
+ FspsUpd->FspsConfig.Usb3HsioTxDeEmph[Index] = 0;
+ FspsUpd->FspsConfig.Usb3HsioTxDownscaleAmpEnable[Index] = 0;
+ FspsUpd->FspsConfig.Usb3HsioTxDownscaleAmp[Index] = 0;
+ FspsUpd->FspsConfig.PchUsbHsioRxTuningEnable[Index] = 0;
+ FspsUpd->FspsConfig.PchUsbHsioRxTuningParameters[Index] = 3;
+ FspsUpd->FspsConfig.PchUsbHsioFilterSel[Index] = 0;
+ }
+
+ if (IsPchLp()) {
+ FspsUpd->FspsConfig.Usb2OverCurrentPin[0] = UsbOverCurrentPin2;
+ FspsUpd->FspsConfig.Usb2OverCurrentPin[1] = UsbOverCurrentPinSkip;
+ FspsUpd->FspsConfig.Usb2OverCurrentPin[2] = UsbOverCurrentPin2;
+ FspsUpd->FspsConfig.Usb2OverCurrentPin[3] = UsbOverCurrentPin2;
+ FspsUpd->FspsConfig.Usb2OverCurrentPin[4] = UsbOverCurrentPin3;
+ FspsUpd->FspsConfig.Usb2OverCurrentPin[5] = UsbOverCurrentPin3;
+ FspsUpd->FspsConfig.Usb2OverCurrentPin[6] = UsbOverCurrentPin3;
+ FspsUpd->FspsConfig.Usb2OverCurrentPin[7] = UsbOverCurrentPin3;
+ FspsUpd->FspsConfig.Usb2OverCurrentPin[8] = UsbOverCurrentPinSkip;
+ FspsUpd->FspsConfig.Usb2OverCurrentPin[9] = UsbOverCurrentPinSkip;
+ FspsUpd->FspsConfig.Usb2OverCurrentPin[10] = UsbOverCurrentPinSkip;
+ FspsUpd->FspsConfig.Usb2OverCurrentPin[11] = UsbOverCurrentPinSkip;
+ FspsUpd->FspsConfig.Usb2OverCurrentPin[12] = UsbOverCurrentPinSkip;
+ FspsUpd->FspsConfig.Usb2OverCurrentPin[13] = UsbOverCurrentPinSkip;
+ FspsUpd->FspsConfig.Usb2OverCurrentPin[14] = UsbOverCurrentPinSkip;
+ FspsUpd->FspsConfig.Usb2OverCurrentPin[15] = UsbOverCurrentPinSkip;
+
+ FspsUpd->FspsConfig.Usb3OverCurrentPin[0] = UsbOverCurrentPin2;
+ FspsUpd->FspsConfig.Usb3OverCurrentPin[1] = UsbOverCurrentPinSkip;
+ FspsUpd->FspsConfig.Usb3OverCurrentPin[2] = UsbOverCurrentPin2;
+ FspsUpd->FspsConfig.Usb3OverCurrentPin[3] = UsbOverCurrentPin2;
+ FspsUpd->FspsConfig.Usb3OverCurrentPin[4] = UsbOverCurrentPinSkip;
+ FspsUpd->FspsConfig.Usb3OverCurrentPin[5] = UsbOverCurrentPinSkip;
+ FspsUpd->FspsConfig.Usb3OverCurrentPin[6] = UsbOverCurrentPinSkip;
+ FspsUpd->FspsConfig.Usb3OverCurrentPin[7] = UsbOverCurrentPinSkip;
+ FspsUpd->FspsConfig.Usb3OverCurrentPin[8] = UsbOverCurrentPinSkip;
+ FspsUpd->FspsConfig.Usb3OverCurrentPin[9] = UsbOverCurrentPinSkip;
+
+ Length = GetPchUsb2MaxPhysicalPortNum ();
+ for (Index = 0; Index < Length; Index++) {
+ FspsUpd->FspsConfig.Usb2AfePetxiset[Index] = 6;
+ FspsUpd->FspsConfig.Usb2AfeTxiset[Index] = 0;
+ FspsUpd->FspsConfig.Usb2AfePredeemp[Index] = 3;
+ FspsUpd->FspsConfig.Usb2AfePehalfbit[Index] = 0;
+ }
+ } else {
+ FspsUpd->FspsConfig.Usb2OverCurrentPin[0] = UsbOverCurrentPin4;
+ FspsUpd->FspsConfig.Usb2OverCurrentPin[1] = UsbOverCurrentPin0;
+ FspsUpd->FspsConfig.Usb2OverCurrentPin[2] = UsbOverCurrentPin2;
+ FspsUpd->FspsConfig.Usb2OverCurrentPin[3] = UsbOverCurrentPin5;
+ FspsUpd->FspsConfig.Usb2OverCurrentPin[4] = UsbOverCurrentPin5;
+ FspsUpd->FspsConfig.Usb2OverCurrentPin[5] = UsbOverCurrentPin0;
+ FspsUpd->FspsConfig.Usb2OverCurrentPin[6] = UsbOverCurrentPin1;
+ FspsUpd->FspsConfig.Usb2OverCurrentPin[7] = UsbOverCurrentPin1;
+ FspsUpd->FspsConfig.Usb2OverCurrentPin[8] = UsbOverCurrentPinSkip;
+ FspsUpd->FspsConfig.Usb2OverCurrentPin[9] = UsbOverCurrentPin3;
+ FspsUpd->FspsConfig.Usb2OverCurrentPin[10] = UsbOverCurrentPin3;
+ FspsUpd->FspsConfig.Usb2OverCurrentPin[11] = UsbOverCurrentPin6;
+ FspsUpd->FspsConfig.Usb2OverCurrentPin[12] = UsbOverCurrentPin6;
+ FspsUpd->FspsConfig.Usb2OverCurrentPin[13] = UsbOverCurrentPin0;
+
+ FspsUpd->FspsConfig.Usb3OverCurrentPin[0] = UsbOverCurrentPin4;
+ FspsUpd->FspsConfig.Usb3OverCurrentPin[1] = UsbOverCurrentPin0;
+ FspsUpd->FspsConfig.Usb3OverCurrentPin[2] = UsbOverCurrentPin2;
+ FspsUpd->FspsConfig.Usb3OverCurrentPin[3] = UsbOverCurrentPin5;
+ FspsUpd->FspsConfig.Usb3OverCurrentPin[4] = UsbOverCurrentPin5;
+ FspsUpd->FspsConfig.Usb3OverCurrentPin[5] = UsbOverCurrentPin0;
+ FspsUpd->FspsConfig.Usb3OverCurrentPin[6] = UsbOverCurrentPin1;
+ FspsUpd->FspsConfig.Usb3OverCurrentPin[7] = UsbOverCurrentPin1;
+ FspsUpd->FspsConfig.Usb3OverCurrentPin[8] = UsbOverCurrentPinSkip;
+ FspsUpd->FspsConfig.Usb3OverCurrentPin[9] = UsbOverCurrentPin3;
+
+ FspsUpd->FspsConfig.Usb2AfePetxiset[0] = 7;
+ FspsUpd->FspsConfig.Usb2AfeTxiset[0] = 0;
+ FspsUpd->FspsConfig.Usb2AfePredeemp[0] = 3;
+ FspsUpd->FspsConfig.Usb2AfePehalfbit[0] = 0;
+
+ FspsUpd->FspsConfig.Usb2AfePetxiset[1] = 6;
+ FspsUpd->FspsConfig.Usb2AfeTxiset[1] = 0;
+ FspsUpd->FspsConfig.Usb2AfePredeemp[1] = 3;
+ FspsUpd->FspsConfig.Usb2AfePehalfbit[1] = 0;
+
+ FspsUpd->FspsConfig.Usb2AfePetxiset[2] = 6;
+ FspsUpd->FspsConfig.Usb2AfeTxiset[2] = 0;
+ FspsUpd->FspsConfig.Usb2AfePredeemp[2] = 3;
+ FspsUpd->FspsConfig.Usb2AfePehalfbit[2] = 0;
+
+ FspsUpd->FspsConfig.Usb2AfePetxiset[3] = 6;
+ FspsUpd->FspsConfig.Usb2AfeTxiset[3] = 0;
+ FspsUpd->FspsConfig.Usb2AfePredeemp[3] = 3;
+ FspsUpd->FspsConfig.Usb2AfePehalfbit[3] = 0;
+
+ FspsUpd->FspsConfig.Usb2AfePetxiset[4] = 6;
+ FspsUpd->FspsConfig.Usb2AfeTxiset[4] = 0;
+ FspsUpd->FspsConfig.Usb2AfePredeemp[4] = 3;
+ FspsUpd->FspsConfig.Usb2AfePehalfbit[4] = 0;
+
+ FspsUpd->FspsConfig.Usb2AfePetxiset[5] = 6;
+ FspsUpd->FspsConfig.Usb2AfeTxiset[5] = 0;
+ FspsUpd->FspsConfig.Usb2AfePredeemp[5] = 3;
+ FspsUpd->FspsConfig.Usb2AfePehalfbit[5] = 0;
+
+ FspsUpd->FspsConfig.Usb2AfePetxiset[6] = 7;
+ FspsUpd->FspsConfig.Usb2AfeTxiset[6] = 0;
+ FspsUpd->FspsConfig.Usb2AfePredeemp[6] = 3;
+ FspsUpd->FspsConfig.Usb2AfePehalfbit[6] = 0;
+
+ FspsUpd->FspsConfig.Usb2AfePetxiset[7] = 7;
+ FspsUpd->FspsConfig.Usb2AfeTxiset[7] = 0;
+ FspsUpd->FspsConfig.Usb2AfePredeemp[7] = 3;
+ FspsUpd->FspsConfig.Usb2AfePehalfbit[7] = 0;
+
+ FspsUpd->FspsConfig.Usb2AfePetxiset[8] = 6;
+ FspsUpd->FspsConfig.Usb2AfeTxiset[8] = 0;
+ FspsUpd->FspsConfig.Usb2AfePredeemp[8] = 3;
+ FspsUpd->FspsConfig.Usb2AfePehalfbit[8] = 0;
+
+ FspsUpd->FspsConfig.Usb2AfePetxiset[9] = 6;
+ FspsUpd->FspsConfig.Usb2AfeTxiset[9] = 0;
+ FspsUpd->FspsConfig.Usb2AfePredeemp[9] = 3;
+ FspsUpd->FspsConfig.Usb2AfePehalfbit[9] = 0;
+
+ FspsUpd->FspsConfig.Usb2AfePetxiset[10] = 6;
+ FspsUpd->FspsConfig.Usb2AfeTxiset[10] = 0;
+ FspsUpd->FspsConfig.Usb2AfePredeemp[10] = 3;
+ FspsUpd->FspsConfig.Usb2AfePehalfbit[10] = 0;
+
+ FspsUpd->FspsConfig.Usb2AfePetxiset[11] = 7;
+ FspsUpd->FspsConfig.Usb2AfeTxiset[11] = 0;
+ FspsUpd->FspsConfig.Usb2AfePredeemp[11] = 3;
+ FspsUpd->FspsConfig.Usb2AfePehalfbit[11] = 0;
+
+ FspsUpd->FspsConfig.Usb2AfePetxiset[12] = 7;
+ FspsUpd->FspsConfig.Usb2AfeTxiset[12] = 0;
+ FspsUpd->FspsConfig.Usb2AfePredeemp[12] = 3;
+ FspsUpd->FspsConfig.Usb2AfePehalfbit[12] = 0;
+
+ FspsUpd->FspsConfig.Usb2AfePetxiset[13] = 7;
+ FspsUpd->FspsConfig.Usb2AfeTxiset[13] = 0;
+ FspsUpd->FspsConfig.Usb2AfePredeemp[13] = 3;
+ FspsUpd->FspsConfig.Usb2AfePehalfbit[13] = 0;
+ }
+
+ FspsUpd->FspsConfig.PcieSwEqCoeffListCm[0] = 4;
+ FspsUpd->FspsConfig.PcieSwEqCoeffListCp[0] = 8;
+ FspsUpd->FspsConfig.PcieSwEqCoeffListCm[1] = 6;
+ FspsUpd->FspsConfig.PcieSwEqCoeffListCp[1] = 2;
+ FspsUpd->FspsConfig.PcieSwEqCoeffListCm[2] = 8;
+ FspsUpd->FspsConfig.PcieSwEqCoeffListCp[2] = 6;
+ FspsUpd->FspsConfig.PcieSwEqCoeffListCm[3] = 10;
+ FspsUpd->FspsConfig.PcieSwEqCoeffListCp[3] = 8;
+ FspsUpd->FspsConfig.PcieSwEqCoeffListCm[4] = 12;
+ FspsUpd->FspsConfig.PcieSwEqCoeffListCp[4] = 2;
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.h
new file mode 100644
index 0000000000..3d8dfa4c08
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.h
@@ -0,0 +1,28 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_PCH_POLICY_UPDATE_H_
+#define _PEI_PCH_POLICY_UPDATE_H_
+
+//
+// External include files do NOT need to be explicitly specified in real EDKII
+// environment
+//
+#include <PiPei.h>
+
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PciLib.h>
+#include <Ppi/SiPolicy.h>
+#include <Library/MmPciLib.h>
+#include <Library/ConfigBlockLib.h>
+
+#include <FspEas.h>
+#include <FspmUpd.h>
+#include <FspsUpd.h>
+
+#endif
+
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdatePreMem.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdatePreMem.c
new file mode 100644
index 0000000000..cbe9bf8fbb
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdatePreMem.c
@@ -0,0 +1,39 @@
+/** @file
+ This file is SampleCode of the library for Intel PCH PEI Policy initialization.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiPchPolicyUpdate.h"
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/HobLib.h>
+#include <Guid/GlobalVariable.h>
+#include <Library/PchInfoLib.h>
+#include <Library/PchPcrLib.h>
+#include <Library/PchHsioLib.h>
+#include <Library/PchPcieRpLib.h>
+#include <PchHsioPtssTables.h>
+#include <Library/DebugLib.h>
+
+/**
+ Performs FSP PCH PEI Policy pre mem initialization.
+
+ @param[in][out] FspmUpd Pointer to FSP UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+ @retval EFI_NOT_FOUND Fail to locate required PPI.
+ @retval Other FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspPchPolicyUpdatePreMem (
+ IN OUT FSPM_UPD *FspmUpd
+ )
+{
+ return EFI_SUCCESS;
+}
+
+
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c
new file mode 100644
index 0000000000..f051a5bca5
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c
@@ -0,0 +1,158 @@
+/** @file
+Do Platform Stage System Agent initialization.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiSaPolicyUpdate.h"
+#include <Guid/MemoryTypeInformation.h>
+#include <Library/HobLib.h>
+#include <PchAccess.h>
+#include <SaAccess.h>
+#include <Pi/PiFirmwareFile.h>
+#include <Pi/PiPeiCis.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PeiSaPolicyLib.h>
+#include <Library/PeiLib.h>
+
+CONST UINT8 mPxRcConfig[8] = { 11, 10, 11, 11, 11, 11, 11, 11 };
+
+/**
+ Performs FSP SA PEI Policy initialization.
+
+ @param[in][out] FspsUpd Pointer to FSP UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+ @retval EFI_NOT_FOUND Fail to locate required PPI.
+ @retval Other FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspSaPolicyUpdate (
+ IN OUT FSPS_UPD *FspsUpd
+ )
+{
+ VOID *Buffer;
+ VOID *MemBuffer;
+ UINT32 Size;
+
+ DEBUG((DEBUG_INFO, "\nUpdating SA Policy in Post Mem\n"));
+
+ FspsUpd->FspsConfig.PeiGraphicsPeimInit = 1;
+
+ Size = 0;
+ Buffer = NULL;
+ PeiGetSectionFromAnyFv (PcdGetPtr (PcdGraphicsVbtGuid), EFI_SECTION_RAW, 0, &Buffer, &Size);
+ if (Buffer == NULL) {
+ DEBUG((DEBUG_WARN, "Could not locate VBT\n"));
+ } else {
+ MemBuffer = (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size));
+ if ((MemBuffer != NULL) && (Buffer != NULL)) {
+ CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size);
+ FspsUpd->FspsConfig.GraphicsConfigPtr = (UINT32)(UINTN)MemBuffer;
+ } else {
+ DEBUG((DEBUG_WARN, "Error in locating / copying VBT.\n"));
+ FspsUpd->FspsConfig.GraphicsConfigPtr = 0;
+ }
+ }
+ DEBUG((DEBUG_INFO, "Vbt Pointer from PeiGetSectionFromFv is 0x%x\n", FspsUpd->FspsConfig.GraphicsConfigPtr));
+ DEBUG((DEBUG_INFO, "Vbt Size from PeiGetSectionFromFv is 0x%x\n", Size));
+
+ Size = 0;
+ Buffer = NULL;
+ PeiGetSectionFromAnyFv (&gTianoLogoGuid, EFI_SECTION_RAW, 0, &Buffer, &Size);
+ if (Buffer == NULL) {
+ DEBUG((DEBUG_WARN, "Could not locate Logo\n"));
+ } else {
+ MemBuffer = (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size));
+ if ((MemBuffer != NULL) && (Buffer != NULL)) {
+ CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size);
+ FspsUpd->FspsConfig.LogoPtr = (UINT32)(UINTN)MemBuffer;
+ FspsUpd->FspsConfig.LogoSize = Size;
+ } else {
+ DEBUG((DEBUG_WARN, "Error in locating / copying LogoPtr.\n"));
+ FspsUpd->FspsConfig.LogoPtr = 0;
+ FspsUpd->FspsConfig.LogoSize = 0;
+ }
+ }
+ DEBUG((DEBUG_INFO, "LogoPtr from PeiGetSectionFromFv is 0x%x\n", FspsUpd->FspsConfig.LogoPtr));
+ DEBUG((DEBUG_INFO, "LogoSize from PeiGetSectionFromFv is 0x%x\n", FspsUpd->FspsConfig.LogoSize));
+
+ CopyMem (&FspsUpd->FspsConfig.PxRcConfig, mPxRcConfig, sizeof(mPxRcConfig));
+
+ //
+ // CPU power management config
+ //
+ FspsUpd->FspsConfig.TdcEnable[0] = 0x1;
+ FspsUpd->FspsConfig.TdcEnable[1] = 0x1;
+ FspsUpd->FspsConfig.TdcEnable[3] = 0x1;
+ FspsUpd->FspsConfig.TdcPowerLimit[1] = 0x2b0;
+ FspsUpd->FspsConfig.TdcPowerLimit[3] = 0xc8;
+ FspsUpd->FspsConfig.AcLoadline[0] = 0x406;
+ FspsUpd->FspsConfig.AcLoadline[1] = 0xb4;
+ FspsUpd->FspsConfig.AcLoadline[3] = 0x10e;
+ FspsUpd->FspsConfig.DcLoadline[0] = 0x406;
+ FspsUpd->FspsConfig.DcLoadline[1] = 0xb4;
+ FspsUpd->FspsConfig.DcLoadline[3] = 0x10e;
+ FspsUpd->FspsConfig.Psi1Threshold[0] = 0x50;
+ FspsUpd->FspsConfig.Psi1Threshold[1] = 0x50;
+ FspsUpd->FspsConfig.Psi1Threshold[2] = 0x50;
+ FspsUpd->FspsConfig.Psi1Threshold[3] = 0x50;
+ FspsUpd->FspsConfig.Psi1Threshold[4] = 0x50;
+ FspsUpd->FspsConfig.Psi2Threshold[0] = 0x14;
+ FspsUpd->FspsConfig.Psi2Threshold[1] = 0x14;
+ FspsUpd->FspsConfig.Psi2Threshold[2] = 0x14;
+ FspsUpd->FspsConfig.Psi2Threshold[3] = 0x14;
+ FspsUpd->FspsConfig.Psi2Threshold[4] = 0x14;
+ FspsUpd->FspsConfig.Psi3Threshold[0] = 0x4;
+ FspsUpd->FspsConfig.Psi3Threshold[1] = 0x4;
+ FspsUpd->FspsConfig.Psi3Threshold[2] = 0x4;
+ FspsUpd->FspsConfig.Psi3Threshold[3] = 0x4;
+ FspsUpd->FspsConfig.Psi3Threshold[4] = 0x4;
+ FspsUpd->FspsConfig.IccMax[0] = 0x2c;
+ FspsUpd->FspsConfig.IccMax[1] = 0x230;
+ FspsUpd->FspsConfig.IccMax[3] = 0x80;
+ FspsUpd->FspsConfig.McivrSpreadSpectrum = 0x3;
+
+ FspsUpd->FspsTestConfig.OneCoreRatioLimit = 0x29;
+ FspsUpd->FspsTestConfig.TwoCoreRatioLimit = 0x28;
+ FspsUpd->FspsTestConfig.ThreeCoreRatioLimit = 0x27;
+ FspsUpd->FspsTestConfig.FourCoreRatioLimit = 0x26;
+ FspsUpd->FspsTestConfig.FiveCoreRatioLimit = 0x25;
+ FspsUpd->FspsTestConfig.SixCoreRatioLimit = 0x24;
+ FspsUpd->FspsTestConfig.TccActivationOffset = 0x0;
+ FspsUpd->FspsTestConfig.TccOffsetClamp = 0x0;
+
+ FspsUpd->FspsTestConfig.PowerLimit1 = 0x0;
+ FspsUpd->FspsTestConfig.PowerLimit2Power = 0x0;
+ FspsUpd->FspsTestConfig.PowerLimit3 = 0x0;
+ FspsUpd->FspsTestConfig.PowerLimit4 = 0x0;
+ FspsUpd->FspsTestConfig.Custom1PowerLimit1 = 0x0;
+ FspsUpd->FspsTestConfig.Custom1PowerLimit2 = 0x0;
+ FspsUpd->FspsTestConfig.Custom2PowerLimit1 = 0x0;
+ FspsUpd->FspsTestConfig.Custom2PowerLimit2 = 0x0;
+ FspsUpd->FspsTestConfig.Custom3PowerLimit1 = 0x0;
+ FspsUpd->FspsTestConfig.Custom3PowerLimit2 = 0x0;
+ FspsUpd->FspsTestConfig.Custom1PowerLimit1Time = 0x0;
+ FspsUpd->FspsTestConfig.Custom1TurboActivationRatio = 0x0;
+ FspsUpd->FspsTestConfig.Custom2PowerLimit1Time = 0x0;
+ FspsUpd->FspsTestConfig.Custom2TurboActivationRatio = 0x0;
+ FspsUpd->FspsTestConfig.Custom3PowerLimit1Time = 0x0;
+ FspsUpd->FspsTestConfig.Custom3TurboActivationRatio = 0x0;
+
+ FspsUpd->FspsTestConfig.VoltageOptimization = 0x0;
+ FspsUpd->FspsTestConfig.TStates = 0x0;
+ FspsUpd->FspsTestConfig.ProcHotResponse = 0x0;
+ FspsUpd->FspsTestConfig.Cx = 0x1;
+ FspsUpd->FspsTestConfig.PkgCStateLimit = 0xff;
+ FspsUpd->FspsTestConfig.MaxRatio = 0x8;
+ FspsUpd->FspsTestConfig.PsysPmax = 0x0;
+ FspsUpd->FspsTestConfig.CstateLatencyControl0Irtl = 0x4e;
+
+ return EFI_SUCCESS;
+}
+
+
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.h
new file mode 100644
index 0000000000..1728d3e123
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.h
@@ -0,0 +1,45 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_SA_POLICY_UPDATE_H_
+#define _PEI_SA_POLICY_UPDATE_H_
+
+//
+// External include files do NOT need to be explicitly specified in real EDKII
+// environment
+//
+#include <SaPolicyCommon.h>
+#include <Library/DebugPrintErrorLevelLib.h>
+#include <CpuRegs.h>
+#include <Library/CpuPlatformLib.h>
+#include "PeiPchPolicyUpdate.h"
+#include <Library/PcdLib.h>
+#include <CpuAccess.h>
+
+#include <FspEas.h>
+#include <FspmUpd.h>
+#include <FspsUpd.h>
+
+extern EFI_GUID gTianoLogoGuid;
+
+/**
+ Performs FSP SA PEI Policy initialization in pre-memory.
+
+ @param[in][out] FspmUpd Pointer to FSP UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+ @retval EFI_NOT_FOUND Fail to locate required PPI.
+ @retval Other FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspSaPolicyUpdatePreMem (
+ IN OUT FSPM_UPD *FspmUpd
+ );
+
+#endif
+
+
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c
new file mode 100644
index 0000000000..3fb74c8838
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c
@@ -0,0 +1,124 @@
+/** @file
+ System Agent policy update.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiSaPolicyUpdate.h"
+#include <CpuRegs.h>
+#include <Library/CpuPlatformLib.h>
+#include <Guid/MemoryTypeInformation.h>
+#include <Guid/MemoryOverwriteControl.h>
+#include <Library/HobLib.h>
+#include <PchAccess.h>
+#include <SaAccess.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PeiSaPolicyLib.h>
+#include <Library/GpioLib.h>
+#include <GpioPinsSklH.h>
+
+
+/**
+ Performs FSP SA PEI Policy initialization in pre-memory.
+
+ @param[in][out] FspmUpd Pointer to FSP UPD Data.
+
+ @retval EFI_SUCCESS FSP UPD Data is updated.
+ @retval EFI_NOT_FOUND Fail to locate required PPI.
+ @retval Other FSP UPD Data update process fail.
+**/
+EFI_STATUS
+EFIAPI
+PeiFspSaPolicyUpdatePreMem (
+ IN OUT FSPM_UPD *FspmUpd
+ )
+{
+ VOID *Buffer;
+ UINT8 BomId;
+
+ FspmUpd->FspmConfig.SpdAddressTable[0] = PcdGet8 (PcdMrcSpdAddressTable0);
+ FspmUpd->FspmConfig.SpdAddressTable[1] = PcdGet8 (PcdMrcSpdAddressTable1);
+ FspmUpd->FspmConfig.SpdAddressTable[2] = PcdGet8 (PcdMrcSpdAddressTable2);
+ FspmUpd->FspmConfig.SpdAddressTable[3] = PcdGet8 (PcdMrcSpdAddressTable3);
+ FspmUpd->FspmConfig.MemorySpdDataLen = PcdGet16 (PcdMrcSpdDataSize);
+
+ //
+ // If SpdAddressTable are not all 0, it means DIMM slots implemented and
+ // MemorySpdPtr* already updated by reading SPD from DIMM in SiliconPolicyInitPreMem.
+ //
+ // If SpdAddressTable all 0, this is memory down design and hardcoded SpdData
+ // should be applied to MemorySpdPtr*.
+ //
+ if ((PcdGet8 (PcdMrcSpdAddressTable0) == 0) && (PcdGet8 (PcdMrcSpdAddressTable1) == 0)
+ && (PcdGet8 (PcdMrcSpdAddressTable2) == 0) && (PcdGet8 (PcdMrcSpdAddressTable3) == 0)) {
+ DEBUG ((DEBUG_INFO, "Using static SPD data for down memory.\n"));
+
+ // BOMID [1:0]
+ // 0: 16G A & B CH
+ // 1: 8G A CH
+ // 2: 8G A & B CH
+ // 3: 4G A CH
+ BomId = PcdGet8(PcdBoardBomId);
+
+ if ((BomId & BIT0) == BIT0) {
+ // Single Channel
+ FspmUpd->FspmConfig.MemorySpdPtr00 = PcdGet32 (PcdMrcSpdData);
+ FspmUpd->FspmConfig.MemorySpdPtr01 = 0;
+ FspmUpd->FspmConfig.MemorySpdPtr10 = 0;
+ FspmUpd->FspmConfig.MemorySpdPtr11 = 0;
+ }else{
+ // Dual Channel
+ FspmUpd->FspmConfig.MemorySpdPtr00 = PcdGet32 (PcdMrcSpdData);
+ FspmUpd->FspmConfig.MemorySpdPtr01 = 0;
+ FspmUpd->FspmConfig.MemorySpdPtr10 = PcdGet32 (PcdMrcSpdData);
+ FspmUpd->FspmConfig.MemorySpdPtr11 = 0;
+ }
+ // CopyMem (
+ // (VOID *) (UINTN) FspmUpd->FspmConfig.MemorySpdPtr00,
+ // (VOID *) (UINTN) PcdGet32 (PcdMrcSpdData),
+ // PcdGet16 (PcdMrcSpdDataSize)
+ // );
+ // CopyMem (
+ // (VOID *) (UINTN) FspmUpd->FspmConfig.MemorySpdPtr10,
+ // (VOID *) (UINTN) PcdGet32 (PcdMrcSpdData),
+ // PcdGet16 (PcdMrcSpdDataSize)
+ // );
+ }
+
+ DEBUG((DEBUG_INFO, "Updating Dq Byte Map and DQS Byte Swizzling Settings...\n"));
+ Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcDqByteMap);
+ if (Buffer) {
+ CopyMem ((VOID *) FspmUpd->FspmConfig.DqByteMapCh0, Buffer, sizeof (FspmUpd->FspmConfig.DqByteMapCh0));
+ CopyMem (
+ (VOID *) FspmUpd->FspmConfig.DqByteMapCh1,
+ (UINT8 *) Buffer + sizeof (FspmUpd->FspmConfig.DqByteMapCh0),
+ sizeof (FspmUpd->FspmConfig.DqByteMapCh1)
+ );
+ }
+ Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcDqsMapCpu2Dram);
+ if (Buffer) {
+ CopyMem ((VOID *) FspmUpd->FspmConfig.DqsMapCpu2DramCh0, Buffer, sizeof (FspmUpd->FspmConfig.DqsMapCpu2DramCh0));
+ CopyMem (
+ (VOID *) FspmUpd->FspmConfig.DqsMapCpu2DramCh1,
+ (UINT8 *) Buffer + sizeof (FspmUpd->FspmConfig.DqsMapCpu2DramCh0),
+ sizeof (FspmUpd->FspmConfig.DqsMapCpu2DramCh1)
+ );
+ }
+
+ DEBUG((DEBUG_INFO, "Updating Dq Pins Interleaved,Rcomp Resistor & Rcomp Target Settings...\n"));
+ FspmUpd->FspmConfig.DqPinsInterleaved = (PcdGetBool (PcdMrcDqPinsInterleaved) ? 1 : 0);
+ Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcRcompResistor);
+ if (Buffer) {
+ CopyMem ((VOID *) FspmUpd->FspmConfig.RcompResistor, Buffer, sizeof (FspmUpd->FspmConfig.RcompResistor));
+ }
+ Buffer = (VOID *) (UINTN) PcdGet32 (PcdMrcRcompTarget);
+ if (Buffer) {
+ CopyMem ((VOID *) FspmUpd->FspmConfig.RcompTarget, Buffer, sizeof (FspmUpd->FspmConfig.RcompTarget));
+ }
+ return EFI_SUCCESS;
+}
+
+
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf
new file mode 100644
index 0000000000..529c2f1253
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf
@@ -0,0 +1,144 @@
+## @file
+# FSP silicon policy updates for the Up Xtreme board.
+#
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = SiliconPolicyUpdateLibFsp
+ FILE_GUID = 392554A5-CC26-4941-B536-6A71BEE4EE49
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SiliconPolicyUpdateLib
+
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64
+#
+
+################################################################################
+#
+# Sources Section - list of files that are required for the build to succeed.
+#
+################################################################################
+
+[Sources]
+ PeiFspPolicyUpdateLib.c
+ PeiPchPolicyUpdatePreMem.c
+ PeiPchPolicyUpdate.c
+ PeiSaPolicyUpdatePreMem.c
+ PeiSaPolicyUpdate.c
+ PeiFspMiscUpdUpdateLib.c
+
+################################################################################
+#
+# Package Dependency Section - list of Package files that are required for
+# this module.
+#
+################################################################################
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ IntelFsp2Pkg/IntelFsp2Pkg.dec
+ IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
+ IntelSiliconPkg/IntelSiliconPkg.dec
+ CoffeelakeSiliconPkg/SiPkg.dec
+ CoffeeLakeFspBinPkg/CoffeeLakeFspBinPkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec
+
+[LibraryClasses.IA32]
+ FspWrapperApiLib
+ OcWdtLib
+ PchResetLib
+ FspWrapperPlatformLib
+ BaseMemoryLib
+ CpuPlatformLib
+ DebugLib
+ HdaVerbTableLib
+ HobLib
+ IoLib
+ PcdLib
+ PostCodeLib
+ SmbusLib
+ ConfigBlockLib
+ PeiSaPolicyLib
+ PchGbeLib
+ PchInfoLib
+ PchHsioLib
+ PchPcieRpLib
+ MemoryAllocationLib
+ DebugPrintErrorLevelLib
+ SiPolicyLib
+ PchGbeLib
+ TimerLib
+ GpioLib
+ PeiLib
+
+[FixedPcd]
+ gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdTsegSize ## CONSUMES
+
+[Pcd]
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMap ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2Dram ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqPinsInterleaved ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdData ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdDataSize ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcCaVrefConfig ## CONSUMES
+
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdSerialIoUartNumber ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdSmmbaseSwSmi ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSaDdrFreqLimit ## CONSUMES
+
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable1
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable2
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable1Size
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable2Size
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size
+
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable1
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable2
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable1Size
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable2Size
+
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGraphicsVbtGuid
+
+ # SPD Address Table
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable0
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable1
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable2
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable3
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardBomId
+
+[Guids]
+ gFspNonVolatileStorageHobGuid ## CONSUMES
+ gTianoLogoGuid ## CONSUMES
+ gEfiMemoryOverwriteControlDataGuid
+
+[Depex]
+ gEdkiiVTdInfoPpiGuid
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecFspWrapperPlatformSecLib/FspWrapperPlatformSecLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecFspWrapperPlatformSecLib/FspWrapperPlatformSecLib.c
new file mode 100644
index 0000000000..91ca226092
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecFspWrapperPlatformSecLib/FspWrapperPlatformSecLib.c
@@ -0,0 +1,186 @@
+/** @file
+ Provide FSP wrapper platform sec related function.
+
+Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiPei.h>
+
+#include <Ppi/SecPlatformInformation.h>
+#include <Ppi/SecPerformance.h>
+#include <Ppi/FirmwareVolumeInfo.h>
+#include <Ppi/TopOfTemporaryRam.h>
+#include <Ppi/PeiCoreFvLocation.h>
+#include <Guid/FirmwareFileSystem2.h>
+
+#include <Library/LocalApicLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+
+/**
+ This interface conveys state information out of the Security (SEC) phase into PEI.
+
+ @param[in] PeiServices Pointer to the PEI Services Table.
+ @param[in,out] StructureSize Pointer to the variable describing size of the input buffer.
+ @param[out] PlatformInformationRecord Pointer to the EFI_SEC_PLATFORM_INFORMATION_RECORD.
+
+ @retval EFI_SUCCESS The data was successfully returned.
+ @retval EFI_BUFFER_TOO_SMALL The buffer was too small.
+
+**/
+EFI_STATUS
+EFIAPI
+SecPlatformInformation (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN OUT UINT64 *StructureSize,
+ OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord
+ );
+
+/**
+ This interface conveys performance information out of the Security (SEC) phase into PEI.
+
+ This service is published by the SEC phase. The SEC phase handoff has an optional
+ EFI_PEI_PPI_DESCRIPTOR list as its final argument when control is passed from SEC into the
+ PEI Foundation. As such, if the platform supports collecting performance data in SEC,
+ this information is encapsulated into the data structure abstracted by this service.
+ This information is collected for the boot-strap processor (BSP) on IA-32.
+
+ @param[in] PeiServices The pointer to the PEI Services Table.
+ @param[in] This The pointer to this instance of the PEI_SEC_PERFORMANCE_PPI.
+ @param[out] Performance The pointer to performance data collected in SEC phase.
+
+ @retval EFI_SUCCESS The data was successfully returned.
+
+**/
+EFI_STATUS
+EFIAPI
+SecGetPerformance (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN PEI_SEC_PERFORMANCE_PPI *This,
+ OUT FIRMWARE_SEC_PERFORMANCE *Performance
+ );
+
+PEI_SEC_PERFORMANCE_PPI mSecPerformancePpi = {
+ SecGetPerformance
+};
+
+EFI_PEI_CORE_FV_LOCATION_PPI mPeiCoreFvLocationPpi = {
+ (VOID *) (UINTN) FixedPcdGet32 (PcdFspmBaseAddress)
+};
+
+EFI_PEI_PPI_DESCRIPTOR mPeiCoreFvLocationPpiList[] = {
+ {
+ EFI_PEI_PPI_DESCRIPTOR_PPI,
+ &gEfiPeiCoreFvLocationPpiGuid,
+ &mPeiCoreFvLocationPpi
+ }
+};
+
+EFI_PEI_PPI_DESCRIPTOR mPeiSecPlatformPpi[] = {
+ {
+ EFI_PEI_PPI_DESCRIPTOR_PPI,
+ &gTopOfTemporaryRamPpiGuid,
+ NULL // To be patched later.
+ },
+ {
+ EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
+ &gPeiSecPerformancePpiGuid,
+ &mSecPerformancePpi
+ },
+};
+
+#define LEGACY_8259_MASK_REGISTER_MASTER 0x21
+#define LEGACY_8259_MASK_REGISTER_SLAVE 0xA1
+#define LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_MASTER 0x4D0
+#define LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_SLAVE 0x4D1
+
+/**
+ Write to mask and edge/level triggered registers of master and slave 8259 PICs.
+
+ @param[in] Mask low byte for master PIC mask register,
+ high byte for slave PIC mask register.
+ @param[in] EdgeLevel low byte for master PIC edge/level triggered register,
+ high byte for slave PIC edge/level triggered register.
+
+**/
+VOID
+Interrupt8259WriteMask (
+ IN UINT16 Mask,
+ IN UINT16 EdgeLevel
+ )
+{
+ IoWrite8 (LEGACY_8259_MASK_REGISTER_MASTER, (UINT8) Mask);
+ IoWrite8 (LEGACY_8259_MASK_REGISTER_SLAVE, (UINT8) (Mask >> 8));
+ IoWrite8 (LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_MASTER, (UINT8) EdgeLevel);
+ IoWrite8 (LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_SLAVE, (UINT8) (EdgeLevel >> 8));
+}
+
+/**
+ A developer supplied function to perform platform specific operations.
+
+ It's a developer supplied function to perform any operations appropriate to a
+ given platform. It's invoked just before passing control to PEI core by SEC
+ core. Platform developer may modify the SecCoreData passed to PEI Core.
+ It returns a platform specific PPI list that platform wishes to pass to PEI core.
+ The Generic SEC core module will merge this list to join the final list passed to
+ PEI core.
+
+ @param[in,out] SecCoreData The same parameter as passing to PEI core. It
+ could be overridden by this function.
+
+ @return The platform specific PPI list to be passed to PEI core or
+ NULL if there is no need of such platform specific PPI list.
+
+**/
+EFI_PEI_PPI_DESCRIPTOR *
+EFIAPI
+SecPlatformMain (
+ IN OUT EFI_SEC_PEI_HAND_OFF *SecCoreData
+ )
+{
+ EFI_PEI_PPI_DESCRIPTOR *PpiList;
+ UINT8 TopOfTemporaryRamPpiIndex;
+ UINT8 *CopyDestinationPointer;
+
+ DEBUG ((DEBUG_INFO, "FSP Wrapper BootFirmwareVolumeBase - 0x%x\n", SecCoreData->BootFirmwareVolumeBase));
+ DEBUG ((DEBUG_INFO, "FSP Wrapper BootFirmwareVolumeSize - 0x%x\n", SecCoreData->BootFirmwareVolumeSize));
+ DEBUG ((DEBUG_INFO, "FSP Wrapper TemporaryRamBase - 0x%x\n", SecCoreData->TemporaryRamBase));
+ DEBUG ((DEBUG_INFO, "FSP Wrapper TemporaryRamSize - 0x%x\n", SecCoreData->TemporaryRamSize));
+ DEBUG ((DEBUG_INFO, "FSP Wrapper PeiTemporaryRamBase - 0x%x\n", SecCoreData->PeiTemporaryRamBase));
+ DEBUG ((DEBUG_INFO, "FSP Wrapper PeiTemporaryRamSize - 0x%x\n", SecCoreData->PeiTemporaryRamSize));
+ DEBUG ((DEBUG_INFO, "FSP Wrapper StackBase - 0x%x\n", SecCoreData->StackBase));
+ DEBUG ((DEBUG_INFO, "FSP Wrapper StackSize - 0x%x\n", SecCoreData->StackSize));
+
+ InitializeApicTimer (0, (UINT32) -1, TRUE, 5);
+
+ //
+ // Set all 8259 interrupts to edge triggered and disabled
+ //
+ Interrupt8259WriteMask (0xFFFF, 0x0000);
+
+ //
+ // Use middle of Heap as temp buffer, it will be copied by caller.
+ // Do not use Stack, because it will cause wrong calculation on stack by PeiCore
+ //
+ PpiList = (VOID *)((UINTN) SecCoreData->PeiTemporaryRamBase + (UINTN) SecCoreData->PeiTemporaryRamSize/2);
+ CopyDestinationPointer = (UINT8 *) PpiList;
+ TopOfTemporaryRamPpiIndex = 0;
+ if ((PcdGet8 (PcdFspModeSelection) == 0) && PcdGetBool (PcdFspDispatchModeUseFspPeiMain)) {
+ //
+ // In Dispatch mode, wrapper should provide PeiCoreFvLocationPpi.
+ //
+ CopyMem (CopyDestinationPointer, mPeiCoreFvLocationPpiList, sizeof (mPeiCoreFvLocationPpiList));
+ TopOfTemporaryRamPpiIndex = 1;
+ CopyDestinationPointer += sizeof (mPeiCoreFvLocationPpiList);
+ }
+ CopyMem (CopyDestinationPointer, mPeiSecPlatformPpi, sizeof (mPeiSecPlatformPpi));
+ //
+ // Patch TopOfTemporaryRamPpi
+ //
+ PpiList[TopOfTemporaryRamPpiIndex].Ppi = (VOID *)((UINTN) SecCoreData->TemporaryRamBase + SecCoreData->TemporaryRamSize);
+
+ return PpiList;
+}
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h
new file mode 100644
index 0000000000..a969120501
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h
@@ -0,0 +1,40 @@
+/** @file
+
+Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __FSPT_CORE_UPD_H__
+#define __FSPT_CORE_UPD_H__
+
+#pragma pack(1)
+
+/** Fsp T Core UPD
+**/
+typedef struct {
+
+/** Offset 0x0020
+**/
+ UINT32 MicrocodeRegionBase;
+
+/** Offset 0x0024
+**/
+ UINT32 MicrocodeRegionSize;
+
+/** Offset 0x0028
+**/
+ UINT32 CodeRegionBase;
+
+/** Offset 0x002C
+**/
+ UINT32 CodeRegionSize;
+
+/** Offset 0x0030
+**/
+ UINT8 Reserved[16];
+} FSPT_CORE_UPD;
+
+#pragma pack()
+
+#endif
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Fsp.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Fsp.h
new file mode 100644
index 0000000000..2acaa373c4
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Fsp.h
@@ -0,0 +1,42 @@
+/** @file
+ Fsp related definitions
+
+Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __FSP_H__
+#define __FSP_H__
+
+//
+// Fv Header
+//
+#define FVH_SIGINATURE_OFFSET 0x28
+#define FVH_SIGINATURE_VALID_VALUE 0x4856465F // valid signature:_FVH
+#define FVH_HEADER_LENGTH_OFFSET 0x30
+#define FVH_EXTHEADER_OFFSET_OFFSET 0x34
+#define FVH_EXTHEADER_SIZE_OFFSET 0x10
+
+//
+// Ffs Header
+//
+#define FSP_HEADER_GUID_DWORD1 0x912740BE
+#define FSP_HEADER_GUID_DWORD2 0x47342284
+#define FSP_HEADER_GUID_DWORD3 0xB08471B9
+#define FSP_HEADER_GUID_DWORD4 0x0C3F3527
+#define FFS_HEADER_SIZE_VALUE 0x18
+
+//
+// Section Header
+//
+#define SECTION_HEADER_TYPE_OFFSET 0x03
+#define RAW_SECTION_HEADER_SIZE_VALUE 0x04
+
+//
+// Fsp Header
+//
+#define FSP_HEADER_IMAGEBASE_OFFSET 0x1C
+#define FSP_HEADER_TEMPRAMINIT_OFFSET 0x30
+
+#endif
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/PeiCoreEntry.nasm b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/PeiCoreEntry.nasm
new file mode 100644
index 0000000000..d6d0b8955f
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/PeiCoreEntry.nasm
@@ -0,0 +1,130 @@
+;------------------------------------------------------------------------------
+;
+; Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; PeiCoreEntry.nasm
+;
+; Abstract:
+;
+; Find and call SecStartup
+;
+;------------------------------------------------------------------------------
+
+SECTION .text
+
+extern ASM_PFX(SecStartup)
+extern ASM_PFX(PlatformInit)
+
+global ASM_PFX(CallPeiCoreEntryPoint)
+ASM_PFX(CallPeiCoreEntryPoint):
+ ;
+ ; Obtain the hob list pointer
+ ;
+ mov eax, [esp+4]
+ ;
+ ; Obtain the stack information
+ ; ECX: start of range
+ ; EDX: end of range
+ ;
+ mov ecx, [esp+8]
+ mov edx, [esp+0xC]
+
+ ;
+ ; Platform init
+ ;
+ pushad
+ push edx
+ push ecx
+ push eax
+ call ASM_PFX(PlatformInit)
+ pop eax
+ pop eax
+ pop eax
+ popad
+
+ ;
+ ; Set stack top pointer
+ ;
+ mov esp, edx
+
+ ;
+ ; Push the hob list pointer
+ ;
+ push eax
+
+ ;
+ ; Save the value
+ ; ECX: start of range
+ ; EDX: end of range
+ ;
+ mov ebp, esp
+ push ecx
+ push edx
+
+ ;
+ ; Push processor count to stack first, then BIST status (AP then BSP)
+ ;
+ mov eax, 1
+ cpuid
+ shr ebx, 16
+ and ebx, 0xFF
+ cmp bl, 1
+ jae PushProcessorCount
+
+ ;
+ ; Some processors report 0 logical processors. Effectively 0 = 1.
+ ; So we fix up the processor count
+ ;
+ inc ebx
+
+PushProcessorCount:
+ push ebx
+
+ ;
+ ; We need to implement a long-term solution for BIST capture. For now, we just copy BSP BIST
+ ; for all processor threads
+ ;
+ xor ecx, ecx
+ mov cl, bl
+PushBist:
+ movd eax, mm0
+ push eax
+ loop PushBist
+
+ ; Save Time-Stamp Counter
+ movd eax, mm5
+ push eax
+
+ movd eax, mm6
+ push eax
+
+ ;
+ ; Pass entry point of the PEI core
+ ;
+ mov edi, 0xFFFFFFE0
+ push DWORD [edi]
+
+ ;
+ ; Pass BFV into the PEI Core
+ ;
+ mov edi, 0xFFFFFFFC
+ push DWORD [edi]
+
+ ;
+ ; Pass stack size into the PEI Core
+ ;
+ mov ecx, [ebp - 4]
+ mov edx, [ebp - 8]
+ push ecx ; RamBase
+
+ sub edx, ecx
+ push edx ; RamSize
+
+ ;
+ ; Pass Control into the PEI Core
+ ;
+ call ASM_PFX(SecStartup)
+
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
new file mode 100644
index 0000000000..9eea3c38b7
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm
@@ -0,0 +1,361 @@
+;------------------------------------------------------------------------------
+;
+; Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+; Module Name:
+;
+; SecEntry.nasm
+;
+; Abstract:
+;
+; This is the code that goes from real-mode to protected mode.
+; It consumes the reset vector, calls TempRamInit API from FSP binary.
+;
+;------------------------------------------------------------------------------
+
+#include "Fsp.h"
+
+SECTION .text
+
+extern ASM_PFX(CallPeiCoreEntryPoint)
+extern ASM_PFX(FsptUpdDataPtr)
+extern ASM_PFX(BoardBeforeTempRamInit)
+; Pcds
+extern ASM_PFX(PcdGet32 (PcdFspTemporaryRamSize))
+extern ASM_PFX(PcdGet32 (PcdFsptBaseAddress))
+
+;----------------------------------------------------------------------------
+;
+; Procedure: _ModuleEntryPoint
+;
+; Input: None
+;
+; Output: None
+;
+; Destroys: Assume all registers
+;
+; Description:
+;
+; Transition to non-paged flat-model protected mode from a
+; hard-coded GDT that provides exactly two descriptors.
+; This is a bare bones transition to protected mode only
+; used for a while in PEI and possibly DXE.
+;
+; After enabling protected mode, a far jump is executed to
+; transfer to PEI using the newly loaded GDT.
+;
+; Return: None
+;
+; MMX Usage:
+; MM0 = BIST State
+; MM5 = Save time-stamp counter value high32bit
+; MM6 = Save time-stamp counter value low32bit.
+;
+;----------------------------------------------------------------------------
+
+BITS 16
+align 4
+global ASM_PFX(_ModuleEntryPoint)
+ASM_PFX(_ModuleEntryPoint):
+ fninit ; clear any pending Floating point exceptions
+ ;
+ ; Store the BIST value in mm0
+ ;
+ movd mm0, eax
+ cli
+
+ ;
+ ; Check INIT# is asserted by port 0xCF9
+ ;
+ mov dx, 0CF9h
+ in al, dx
+ cmp al, 04h
+ jnz NotWarmStart
+
+
+ ;
+ ; @note Issue warm reset, since if CPU only reset is issued not all MSRs are restored to their defaults
+ ;
+ mov dx, 0CF9h
+ mov al, 06h
+ out dx, al
+
+NotWarmStart:
+ ;
+ ; Save time-stamp counter value
+ ; rdtsc load 64bit time-stamp counter to EDX:EAX
+ ;
+ rdtsc
+ movd mm5, edx
+ movd mm6, eax
+
+ ;
+ ; Load the GDT table in GdtDesc
+ ;
+ mov esi, GdtDesc
+ DB 66h
+ lgdt [cs:si]
+
+ ;
+ ; Transition to 16 bit protected mode
+ ;
+ mov eax, cr0 ; Get control register 0
+ or eax, 00000003h ; Set PE bit (bit #0) & MP bit (bit #1)
+ mov cr0, eax ; Activate protected mode
+
+ mov eax, cr4 ; Get control register 4
+ or eax, 00000600h ; Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10)
+ mov cr4, eax
+
+ ;
+ ; Now we're in 16 bit protected mode
+ ; Set up the selectors for 32 bit protected mode entry
+ ;
+ mov ax, SYS_DATA_SEL
+ mov ds, ax
+ mov es, ax
+ mov fs, ax
+ mov gs, ax
+ mov ss, ax
+
+ ;
+ ; Transition to Flat 32 bit protected mode
+ ; The jump to a far pointer causes the transition to 32 bit mode
+ ;
+ mov esi, ProtectedModeEntryLinearAddress
+ jmp dword far [cs:si]
+
+;----------------------------------------------------------------------------
+;
+; Procedure: ProtectedModeEntryPoint
+;
+; Input: None
+;
+; Output: None
+;
+; Destroys: Assume all registers
+;
+; Description:
+;
+; This function handles:
+; Call two basic APIs from FSP binary
+; Initializes stack with some early data (BIST, PEI entry, etc)
+;
+; Return: None
+;
+;----------------------------------------------------------------------------
+
+BITS 32
+align 4
+ProtectedModeEntryPoint:
+ ;
+ ; Early board hooks
+ ;
+ mov esp, BoardBeforeTempRamInitRet
+ jmp ASM_PFX(BoardBeforeTempRamInit)
+
+BoardBeforeTempRamInitRet:
+
+ ; Find the fsp info header
+ mov edi, [ASM_PFX(PcdGet32 (PcdFsptBaseAddress))]
+
+ mov eax, dword [edi + FVH_SIGINATURE_OFFSET]
+ cmp eax, FVH_SIGINATURE_VALID_VALUE
+ jnz FspHeaderNotFound
+
+ xor eax, eax
+ mov ax, word [edi + FVH_EXTHEADER_OFFSET_OFFSET]
+ cmp ax, 0
+ jnz FspFvExtHeaderExist
+
+ xor eax, eax
+ mov ax, word [edi + FVH_HEADER_LENGTH_OFFSET] ; Bypass Fv Header
+ add edi, eax
+ jmp FspCheckFfsHeader
+
+FspFvExtHeaderExist:
+ add edi, eax
+ mov eax, dword [edi + FVH_EXTHEADER_SIZE_OFFSET] ; Bypass Ext Fv Header
+ add edi, eax
+
+ ; Round up to 8 byte alignment
+ mov eax, edi
+ and al, 07h
+ jz FspCheckFfsHeader
+
+ and edi, 0FFFFFFF8h
+ add edi, 08h
+
+FspCheckFfsHeader:
+ ; Check the ffs guid
+ mov eax, dword [edi]
+ cmp eax, FSP_HEADER_GUID_DWORD1
+ jnz FspHeaderNotFound
+
+ mov eax, dword [edi + 4]
+ cmp eax, FSP_HEADER_GUID_DWORD2
+ jnz FspHeaderNotFound
+
+ mov eax, dword [edi + 8]
+ cmp eax, FSP_HEADER_GUID_DWORD3
+ jnz FspHeaderNotFound
+
+ mov eax, dword [edi + 0Ch]
+ cmp eax, FSP_HEADER_GUID_DWORD4
+ jnz FspHeaderNotFound
+
+ add edi, FFS_HEADER_SIZE_VALUE ; Bypass the ffs header
+
+ ; Check the section type as raw section
+ mov al, byte [edi + SECTION_HEADER_TYPE_OFFSET]
+ cmp al, 019h
+ jnz FspHeaderNotFound
+
+ add edi, RAW_SECTION_HEADER_SIZE_VALUE ; Bypass the section header
+ jmp FspHeaderFound
+
+FspHeaderNotFound:
+ jmp $
+
+FspHeaderFound:
+ ; Get the fsp TempRamInit Api address
+ mov eax, dword [edi + FSP_HEADER_IMAGEBASE_OFFSET]
+ add eax, dword [edi + FSP_HEADER_TEMPRAMINIT_OFFSET]
+
+ ; Setup the hardcode stack
+ mov esp, TempRamInitStack
+
+ ; Call the fsp TempRamInit Api
+ jmp eax
+
+TempRamInitDone:
+ cmp eax, 8000000Eh ;Check if EFI_NOT_FOUND returned. Error code for Microcode Update not found.
+ je CallSecFspInit ;If microcode not found, don't hang, but continue.
+
+ cmp eax, 0 ;Check if EFI_SUCCESS retuned.
+ jnz FspApiFailed
+
+ ; ECX: start of range
+ ; EDX: end of range
+CallSecFspInit:
+ sub edx, [ASM_PFX(PcdGet32 (PcdFspTemporaryRamSize))] ; TemporaryRam for FSP
+ xor eax, eax
+ mov esp, edx
+
+ ; Align the stack at DWORD
+ add esp, 3
+ and esp, 0FFFFFFFCh
+
+ push edx
+ push ecx
+ push eax ; zero - no hob list yet
+ call ASM_PFX(CallPeiCoreEntryPoint)
+
+FspApiFailed:
+ jmp $
+
+align 10h
+TempRamInitStack:
+ DD TempRamInitDone
+ DD ASM_PFX(FsptUpdDataPtr); TempRamInitParams
+
+;
+; ROM-based Global-Descriptor Table for the Tiano PEI Phase
+;
+align 16
+global ASM_PFX(BootGdtTable)
+
+;
+; GDT[0]: 0x00: Null entry, never used.
+;
+NULL_SEL EQU $ - GDT_BASE ; Selector [0]
+GDT_BASE:
+ASM_PFX(BootGdtTable):
+ DD 0
+ DD 0
+;
+; Linear data segment descriptor
+;
+LINEAR_SEL EQU $ - GDT_BASE ; Selector [0x8]
+ DW 0FFFFh ; limit 0xFFFFF
+ DW 0 ; base 0
+ DB 0
+ DB 092h ; present, ring 0, data, expand-up, writable
+ DB 0CFh ; page-granular, 32-bit
+ DB 0
+;
+; Linear code segment descriptor
+;
+LINEAR_CODE_SEL EQU $ - GDT_BASE ; Selector [0x10]
+ DW 0FFFFh ; limit 0xFFFFF
+ DW 0 ; base 0
+ DB 0
+ DB 09Bh ; present, ring 0, data, expand-up, not-writable
+ DB 0CFh ; page-granular, 32-bit
+ DB 0
+;
+; System data segment descriptor
+;
+SYS_DATA_SEL EQU $ - GDT_BASE ; Selector [0x18]
+ DW 0FFFFh ; limit 0xFFFFF
+ DW 0 ; base 0
+ DB 0
+ DB 093h ; present, ring 0, data, expand-up, not-writable
+ DB 0CFh ; page-granular, 32-bit
+ DB 0
+
+;
+; System code segment descriptor
+;
+SYS_CODE_SEL EQU $ - GDT_BASE ; Selector [0x20]
+ DW 0FFFFh ; limit 0xFFFFF
+ DW 0 ; base 0
+ DB 0
+ DB 09Ah ; present, ring 0, data, expand-up, writable
+ DB 0CFh ; page-granular, 32-bit
+ DB 0
+;
+; Spare segment descriptor
+;
+SYS16_CODE_SEL EQU $ - GDT_BASE ; Selector [0x28]
+ DW 0FFFFh ; limit 0xFFFFF
+ DW 0 ; base 0
+ DB 0Eh ; Changed from F000 to E000.
+ DB 09Bh ; present, ring 0, code, expand-up, writable
+ DB 00h ; byte-granular, 16-bit
+ DB 0
+;
+; Spare segment descriptor
+;
+SYS16_DATA_SEL EQU $ - GDT_BASE ; Selector [0x30]
+ DW 0FFFFh ; limit 0xFFFF
+ DW 0 ; base 0
+ DB 0
+ DB 093h ; present, ring 0, data, expand-up, not-writable
+ DB 00h ; byte-granular, 16-bit
+ DB 0
+
+;
+; Spare segment descriptor
+;
+SPARE5_SEL EQU $ - GDT_BASE ; Selector [0x38]
+ DW 0 ; limit 0
+ DW 0 ; base 0
+ DB 0
+ DB 0 ; present, ring 0, data, expand-up, writable
+ DB 0 ; page-granular, 32-bit
+ DB 0
+GDT_SIZE EQU $ - GDT_BASE ; Size, in bytes
+
+;
+; GDT Descriptor
+;
+GdtDesc: ; GDT descriptor
+ DW GDT_SIZE - 1 ; GDT limit
+ DD GDT_BASE ; GDT base address
+
+
+ProtectedModeEntryLinearAddress:
+ProtectedModeEntryLinear:
+ DD ProtectedModeEntryPoint ; Offset of our 32 bit code
+ DW LINEAR_CODE_SEL
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Stack.nasm b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Stack.nasm
new file mode 100644
index 0000000000..1396649173
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Stack.nasm
@@ -0,0 +1,72 @@
+;------------------------------------------------------------------------------
+;
+; Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+; Abstract:
+;
+; Switch the stack from temporary memory to permanent memory.
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; VOID
+; EFIAPI
+; SecSwitchStack (
+; UINT32 TemporaryMemoryBase,
+; UINT32 PermanentMemoryBase
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(SecSwitchStack)
+ASM_PFX(SecSwitchStack):
+ ;
+ ; Save three register: eax, ebx, ecx
+ ;
+ push eax
+ push ebx
+ push ecx
+ push edx
+
+ ;
+ ; !!CAUTION!! this function address's is pushed into stack after
+ ; migration of whole temporary memory, so need save it to permanent
+ ; memory at first!
+ ;
+
+ mov ebx, [esp + 20] ; Save the first parameter
+ mov ecx, [esp + 24] ; Save the second parameter
+
+ ;
+ ; Save this function's return address into permanent memory at first.
+ ; Then, Fixup the esp point to permanent memory
+ ;
+ mov eax, esp
+ sub eax, ebx
+ add eax, ecx
+ mov edx, dword [esp] ; copy pushed register's value to permanent memory
+ mov dword [eax], edx
+ mov edx, dword [esp + 4]
+ mov dword [eax + 4], edx
+ mov edx, dword [esp + 8]
+ mov dword [eax + 8], edx
+ mov edx, dword [esp + 12]
+ mov dword [eax + 12], edx
+ mov edx, dword [esp + 16] ; Update this function's return address into permanent memory
+ mov dword [eax + 16], edx
+ mov esp, eax ; From now, esp is pointed to permanent memory
+
+ ;
+ ; Fixup the ebp point to permanent memory
+ ;
+ mov eax, ebp
+ sub eax, ebx
+ add eax, ecx
+ mov ebp, eax ; From now, ebp is pointed to permanent memory
+
+ pop edx
+ pop ecx
+ pop ebx
+ pop eax
+ ret
+
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecFspWrapperPlatformSecLib/PlatformInit.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecFspWrapperPlatformSecLib/PlatformInit.c
new file mode 100644
index 0000000000..486c8c7261
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecFspWrapperPlatformSecLib/PlatformInit.c
@@ -0,0 +1,47 @@
+/** @file
+ Provide platform init function.
+
+Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+#include <PiPei.h>
+#include <Library/DebugLib.h>
+#include <Library/SerialPortLib.h>
+#include <Library/SecBoardInitLib.h>
+#include <Library/TestPointCheckLib.h>
+
+/**
+ Platform initialization.
+
+ @param[in] FspHobList HobList produced by FSP.
+ @param[in] StartOfRange Start of temporary RAM.
+ @param[in] EndOfRange End of temporary RAM.
+**/
+VOID
+EFIAPI
+PlatformInit (
+ IN VOID *FspHobList,
+ IN VOID *StartOfRange,
+ IN VOID *EndOfRange
+ )
+{
+ //
+ // Platform initialization
+ // Enable Serial port here
+ //
+ if (PcdGetBool(PcdSecSerialPortDebugEnable)) {
+ SerialPortInitialize ();
+ }
+
+ DEBUG ((DEBUG_INFO, "PrintPeiCoreEntryPointParam in PlatformInit\n"));
+ DEBUG ((DEBUG_INFO, "FspHobList - 0x%x\n", FspHobList));
+ DEBUG ((DEBUG_INFO, "StartOfRange - 0x%x\n", StartOfRange));
+ DEBUG ((DEBUG_INFO, "EndOfRange - 0x%x\n", EndOfRange));
+
+ BoardAfterTempRamInit ();
+
+ TestPointTempMemoryFunction (StartOfRange, EndOfRange);
+}
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
new file mode 100644
index 0000000000..b17226d43b
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
@@ -0,0 +1,105 @@
+## @file
+# Provide FSP wrapper platform sec related function.
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = SecFspWrapperPlatformSecLib
+ FILE_GUID = 4E1C4F95-90EA-47de-9ACC-B8920189A1F5
+ MODULE_TYPE = SEC
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PlatformSecLib
+
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64
+#
+
+################################################################################
+#
+# Sources Section - list of files that are required for the build to succeed.
+#
+################################################################################
+
+[Sources]
+ FspWrapperPlatformSecLib.c
+ SecRamInitData.c
+ SecPlatformInformation.c
+ SecGetPerformance.c
+ SecTempRamDone.c
+ PlatformInit.c
+ FsptCoreUpd.h
+
+[Sources.IA32]
+ Ia32/SecEntry.nasm
+ Ia32/PeiCoreEntry.nasm
+ Ia32/Stack.nasm
+ Ia32/Fsp.h
+
+################################################################################
+#
+# Package Dependency Section - list of Package files that are required for
+# this module.
+#
+################################################################################
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+ IntelFsp2Pkg/IntelFsp2Pkg.dec
+ IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ CoffeelakeSiliconPkg/SiPkg.dec
+ CoffeeLakeFspBinPkg/CoffeeLakeFspBinPkg.dec
+
+[LibraryClasses]
+ LocalApicLib
+ SerialPortLib
+ FspWrapperPlatformLib
+ FspWrapperApiLib
+ SecBoardInitLib
+ TestPointCheckLib
+ PeiServicesTablePointerLib
+
+[Ppis]
+ gEfiSecPlatformInformationPpiGuid ## CONSUMES
+ gPeiSecPerformancePpiGuid ## CONSUMES
+ gTopOfTemporaryRamPpiGuid ## PRODUCES
+ gEfiPeiFirmwareVolumeInfoPpiGuid ## PRODUCES
+ gFspTempRamExitPpiGuid ## CONSUMES
+ gPlatformInitTempRamExitPpiGuid ## CONSUMES
+
+[Pcd]
+ gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize ## CONSUMES
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress ## CONSUMES
+ gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdSecSerialPortDebugEnable ## CONSUMES
+
+[FixedPcd]
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate ## CONSUMES
+ gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress ## CONSUMES
+ gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize ## CONSUMES
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset ## CONSUMES
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress ## CONSUMES
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize ## CONSUMES
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress ## CONSUMES
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdSerialIoUartNumber ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength ## CONSUMES
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecGetPerformance.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecGetPerformance.c
new file mode 100644
index 0000000000..1e20421239
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecGetPerformance.c
@@ -0,0 +1,89 @@
+/** @file
+ Sample to provide SecGetPerformance function.
+
+Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiPei.h>
+
+#include <Ppi/SecPerformance.h>
+#include <Ppi/TopOfTemporaryRam.h>
+
+#include <Library/BaseMemoryLib.h>
+#include <Library/TimerLib.h>
+#include <Library/DebugLib.h>
+
+/**
+ This interface conveys performance information out of the Security (SEC) phase into PEI.
+
+ This service is published by the SEC phase. The SEC phase handoff has an optional
+ EFI_PEI_PPI_DESCRIPTOR list as its final argument when control is passed from SEC into the
+ PEI Foundation. As such, if the platform supports collecting performance data in SEC,
+ this information is encapsulated into the data structure abstracted by this service.
+ This information is collected for the boot-strap processor (BSP) on IA-32.
+
+ @param[in] PeiServices The pointer to the PEI Services Table.
+ @param[in] This The pointer to this instance of the PEI_SEC_PERFORMANCE_PPI.
+ @param[out] Performance The pointer to performance data collected in SEC phase.
+
+ @retval EFI_SUCCESS The data was successfully returned.
+
+**/
+EFI_STATUS
+EFIAPI
+SecGetPerformance (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN PEI_SEC_PERFORMANCE_PPI *This,
+ OUT FIRMWARE_SEC_PERFORMANCE *Performance
+ )
+{
+ UINT32 Size;
+ UINT32 Count;
+ UINTN TopOfTemporaryRam;
+ UINT64 Ticker;
+ VOID *TopOfTemporaryRamPpi;
+ EFI_STATUS Status;
+
+ DEBUG ((DEBUG_INFO, "SecGetPerformance\n"));
+
+ Status = (*PeiServices)->LocatePpi (
+ PeiServices,
+ &gTopOfTemporaryRamPpiGuid,
+ 0,
+ NULL,
+ (VOID **) &TopOfTemporaryRamPpi
+ );
+ if (EFI_ERROR (Status)) {
+ return EFI_NOT_FOUND;
+ }
+ //
+ // |--------------| <- TopOfTemporaryRam - BL
+ // | List Ptr |
+ // |--------------|
+ // | BL RAM Start |
+ // |--------------|
+ // | BL RAM End |
+ // |--------------|
+ // |Number of BSPs|
+ // |--------------|
+ // | BIST |
+ // |--------------|
+ // | .... |
+ // |--------------|
+ // | TSC[63:32] |
+ // |--------------|
+ // | TSC[31:00] |
+ // |--------------|
+ //
+ TopOfTemporaryRam = (UINTN) TopOfTemporaryRamPpi - sizeof (UINT32);
+ TopOfTemporaryRam -= sizeof (UINT32) * 2;
+ Count = *(UINT32 *)(TopOfTemporaryRam - sizeof (UINT32));
+ Size = Count * sizeof (UINT32);
+
+ Ticker = *(UINT64 *) (TopOfTemporaryRam - sizeof (UINT32) - Size - sizeof (UINT32) * 2);
+ Performance->ResetEnd = GetTimeInNanoSecond (Ticker);
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecPlatformInformation.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecPlatformInformation.c
new file mode 100644
index 0000000000..b0b86ab605
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecPlatformInformation.c
@@ -0,0 +1,78 @@
+/** @file
+ Provide SecPlatformInformation function.
+
+Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiPei.h>
+
+#include <Ppi/SecPlatformInformation.h>
+#include <Ppi/TopOfTemporaryRam.h>
+
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+
+/**
+ This interface conveys state information out of the Security (SEC) phase into PEI.
+
+ @param[in] PeiServices Pointer to the PEI Services Table.
+ @param[in,out] StructureSize Pointer to the variable describing size of the input buffer.
+ @param[out] PlatformInformationRecord Pointer to the EFI_SEC_PLATFORM_INFORMATION_RECORD.
+
+ @retval EFI_SUCCESS The data was successfully returned.
+ @retval EFI_BUFFER_TOO_SMALL The buffer was too small.
+
+**/
+EFI_STATUS
+EFIAPI
+SecPlatformInformation (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN OUT UINT64 *StructureSize,
+ OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord
+ )
+{
+ UINT32 *Bist;
+ UINT32 Size;
+ UINT32 Count;
+ UINTN TopOfTemporaryRam;
+ VOID *TopOfTemporaryRamPpi;
+ EFI_STATUS Status;
+
+ DEBUG ((DEBUG_INFO, "SecPlatformInformation\n"));
+
+ Status = (*PeiServices)->LocatePpi (
+ PeiServices,
+ &gTopOfTemporaryRamPpiGuid,
+ 0,
+ NULL,
+ (VOID **) &TopOfTemporaryRamPpi
+ );
+ if (EFI_ERROR (Status)) {
+ return EFI_NOT_FOUND;
+ }
+
+ //
+ // The entries of BIST information, together with the number of them,
+ // reside in the bottom of stack, left untouched by normal stack operation.
+ // This routine copies the BIST information to the buffer pointed by
+ // PlatformInformationRecord for output.
+ //
+ TopOfTemporaryRam = (UINTN) TopOfTemporaryRamPpi - sizeof (UINT32);
+ TopOfTemporaryRam -= sizeof (UINT32) * 2;
+ Count = *((UINT32 *)(TopOfTemporaryRam - sizeof (UINT32)));
+ Size = Count * sizeof (IA32_HANDOFF_STATUS);
+
+ if ((*StructureSize) < (UINT64) Size) {
+ *StructureSize = Size;
+ return EFI_BUFFER_TOO_SMALL;
+ }
+
+ *StructureSize = Size;
+ Bist = (UINT32 *) (TopOfTemporaryRam - sizeof (UINT32) - Size);
+
+ CopyMem (PlatformInformationRecord, Bist, Size);
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecRamInitData.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecRamInitData.c
new file mode 100644
index 0000000000..8442e5fbff
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecRamInitData.c
@@ -0,0 +1,55 @@
+/** @file
+ Provide TempRamInitParams data.
+
+Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/PcdLib.h>
+#include <FspEas.h>
+#include <FsptUpd.h>
+
+#pragma pack(1)
+
+GLOBAL_REMOVE_IF_UNREFERENCED CONST FSPT_UPD FsptUpdDataPtr = {
+ // FSP_UPD_HEADER
+ {
+ FSPT_UPD_SIGNATURE,
+ 0x00,
+ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00
+ }
+ },
+ // FSPT_CORE_UPD
+ {
+ ((UINT32) FixedPcdGet64 (PcdCpuMicrocodePatchAddress) + FixedPcdGet32 (PcdFlashMicrocodeOffset)),
+ ((UINT32) FixedPcdGet64 (PcdCpuMicrocodePatchRegionSize) - FixedPcdGet32 (PcdFlashMicrocodeOffset)),
+ 0, // Set CodeRegionBase as 0, so that caching will be 4GB-(CodeRegionSize > LLCSize ? LLCSize : CodeRegionSize) will be used.
+ FixedPcdGet32 (PcdFlashCodeCacheSize),
+ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+ }
+ },
+ // FSP_T_CONFIG
+ {
+ FixedPcdGet8 (PcdSerialIoUartDebugEnable),
+ FixedPcdGet8 (PcdSerialIoUartNumber),
+ 0,
+ 0,
+ FixedPcdGet32 (PcdSerialClockRate),
+ FixedPcdGet64 (PcdPciExpressBaseAddress),
+ FixedPcdGet32 (PcdPciExpressRegionLength),
+ { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00
+ }
+ },
+ // UpdTerminator
+ 0x55AA
+};
+#pragma pack()
+
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecTempRamDone.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecTempRamDone.c
new file mode 100644
index 0000000000..65908ef525
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecTempRamDone.c
@@ -0,0 +1,93 @@
+/** @file
+ Provide SecTemporaryRamDone function.
+
+Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiPei.h>
+
+#include <Ppi/TemporaryRamDone.h>
+#include <Ppi/TempRamExitPpi.h>
+#include <Ppi/PlatformInitTempRamExitPpi.h>
+
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugAgentLib.h>
+#include <Library/FspWrapperPlatformLib.h>
+#include <Library/FspWrapperApiLib.h>
+#include <Library/PeiServicesTablePointerLib.h>
+
+/**
+This interface disables temporary memory in SEC Phase.
+**/
+VOID
+EFIAPI
+SecPlatformDisableTemporaryMemory (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ VOID *TempRamExitParam;
+ CONST EFI_PEI_SERVICES **PeiServices;
+ FSP_TEMP_RAM_EXIT_PPI *TempRamExitPpi;
+ PLATFORM_INIT_TEMP_RAM_EXIT_PPI *PlatformInitTempRamExitPpi;
+
+ DEBUG ((DEBUG_INFO, "SecPlatformDisableTemporaryMemory enter\n"));
+ PeiServices = GetPeiServicesTablePointer ();
+ ASSERT (PeiServices != NULL);
+ if (PeiServices == NULL) {
+ return;
+ }
+ ASSERT ((*PeiServices) != NULL);
+ if ((*PeiServices) == NULL) {
+ return;
+ }
+ Status = (*PeiServices)->LocatePpi (
+ PeiServices,
+ &gPlatformInitTempRamExitPpiGuid,
+ 0,
+ NULL,
+ (VOID **) &PlatformInitTempRamExitPpi
+ );
+ ASSERT_EFI_ERROR (Status);
+ if (EFI_ERROR (Status)) {
+ return;
+ }
+
+ Status = PlatformInitTempRamExitPpi->PlatformInitBeforeTempRamExit ();
+ ASSERT_EFI_ERROR (Status);
+
+ if (PcdGet8 (PcdFspModeSelection) == 1) {
+ //
+ // FSP API mode
+ //
+ TempRamExitParam = UpdateTempRamExitParam ();
+ Status = CallTempRamExit (TempRamExitParam);
+ DEBUG ((DEBUG_INFO, "TempRamExit status: 0x%x\n", Status));
+ ASSERT_EFI_ERROR (Status);
+ } else {
+ //
+ // FSP Dispatch mode
+ //
+ Status = (*PeiServices)->LocatePpi (
+ PeiServices,
+ &gFspTempRamExitPpiGuid,
+ 0,
+ NULL,
+ (VOID **) &TempRamExitPpi
+ );
+ ASSERT_EFI_ERROR (Status);
+ if (EFI_ERROR (Status)) {
+ return;
+ }
+ TempRamExitPpi->TempRamExit (NULL);
+ }
+
+ Status = PlatformInitTempRamExitPpi->PlatformInitAfterTempRamExit ();
+ ASSERT_EFI_ERROR (Status);
+
+ return ;
+}
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Include/Fdf/FlashMapInclude.fdf b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Include/Fdf/FlashMapInclude.fdf
new file mode 100644
index 0000000000..41d00ee673
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Include/Fdf/FlashMapInclude.fdf
@@ -0,0 +1,51 @@
+## @file
+# Flash map for the UpXtreme Board.
+#
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+#=================================================================================#
+# 8 M BIOS - for FSP wrapper
+#=================================================================================#
+DEFINE FLASH_BASE = 0xFF800000 #
+DEFINE FLASH_SIZE = 0x00800000 #
+DEFINE FLASH_BLOCK_SIZE = 0x00010000 #
+DEFINE FLASH_NUM_BLOCKS = 0x00000080 #
+#=================================================================================#
+
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageOffset = 0x00000000 # Flash addr (0xFF800000)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageSize = 0x00040000 #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset = 0x00000000 # Flash addr (0xFF800000)
+SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize = 0x0001E000 #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset = 0x0001E000 # Flash addr (0xFF81E000)
+SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize = 0x00002000 #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset = 0x00020000 # Flash addr (0xFF820000)
+SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize = 0x00020000 #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset = 0x00040000 # Flash addr (0xFF840000)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize = 0x00050000 #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset = 0x00090000 # Flash addr (0xFF890000)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize = 0x00070000 #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset = 0x00100000 # Flash addr (0xFF900000)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize = 0x00090000 #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset = 0x00190000 # Flash addr (0xFF990000)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize = 0x00190000 #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset = 0x00320000 # Flash addr (0xFFB20000)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize = 0x00170000 #
+SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset = 0x00490000 # Flash addr (0xFFC90000)
+SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize = 0x000B0000 #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset = 0x00540000 # Flash addr (0xFFD40000)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize = 0x00070000 #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset = 0x005B0000 # Flash addr (0xFFDB0000)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize = 0x000EC000 #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset = 0x0069C000 # Flash addr (0xFFE9C000)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize = 0x00014000 #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryOffset = 0x006B0000 # Flash addr (0xFFEB0000)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemorySize = 0x00010000 #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset = 0x006C0000 # Flash addr (0xFFEC0000)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize = 0x00140000 #
+
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Include/Library/PeiPlatformHookLib.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Include/Library/PeiPlatformHookLib.h
new file mode 100644
index 0000000000..febccdf482
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Include/Library/PeiPlatformHookLib.h
@@ -0,0 +1,131 @@
+/** @file
+ UP Xtreme Platform Hook library.
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_PLATFORM_HOOK_LIB_H_
+#define _PEI_PLATFORM_HOOK_LIB_H_
+
+#include <PlatformInfo.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/GpioLib.h>
+
+// EC Command to provide one byte of debug indication
+#define BSSB_DEBUG_INDICATION 0xAE
+/**
+ Configure EC for specific devices
+
+ @param[in] PchLan - The PchLan of PCH_SETUP variable.
+ @param[in] BootMode - The current boot mode.
+**/
+VOID
+EcInit (
+ IN UINT8 PchLan,
+ IN EFI_BOOT_MODE BootMode
+ );
+
+/**
+ Checks if Premium PMIC present
+
+ @retval TRUE if present
+ @retval FALSE it discrete/other PMIC
+**/
+BOOLEAN
+IsPremiumPmicPresent (
+ VOID
+ );
+
+/**
+ Pmic Programming to supprort LPAL Feature
+
+ @retval NONE
+**/
+VOID
+PremiumPmicDisableSlpS0Voltage (
+ VOID
+ );
+
+/**
+Pmic Programming to supprort LPAL Feature
+ @retval NONE
+**/
+VOID
+PremiumPmicEnableSlpS0Voltage(
+ VOID
+ );
+
+/**
+ Do platform specific programming pre-memory. For example, EC init, Chipset programming
+
+ @retval Status
+**/
+EFI_STATUS
+PlatformSpecificInitPreMem (
+ VOID
+ );
+
+/**
+ Do platform specific programming post-memory.
+
+ @retval Status
+**/
+EFI_STATUS
+PlatformSpecificInit (
+ VOID
+ );
+
+/**
+ Configure GPIO and SIO Before Memory is ready.
+
+ @retval EFI_SUCCESS Operation success.
+**/
+EFI_STATUS
+BoardInitPreMem (
+ VOID
+ );
+
+/**
+ Configure GPIO and SIO
+
+ @retval EFI_SUCCESS Operation success.
+**/
+EFI_STATUS
+BoardInit (
+ VOID
+ );
+
+/**
+Voltage Margining Routine
+
+@retval EFI_SUCCESS Operation success
+**/
+EFI_STATUS
+VoltageMarginingRoutine(
+ VOID
+ );
+
+/**
+ Detect recovery mode
+
+ @retval EFI_SUCCESS System in Recovery Mode
+ @retval EFI_UNSUPPORTED System doesn't support Recovery Mode
+ @retval EFI_NOT_FOUND System is not in Recovery Mode
+**/
+EFI_STATUS
+IsRecoveryMode (
+ VOID
+ );
+
+/**
+ Early board Configuration before Memory is ready.
+
+ @retval EFI_SUCCESS Operation success.
+**/
+EFI_STATUS
+BoardInitEarlyPreMem (
+ VOID
+ );
+
+#endif
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Include/Library/PeiPlatformLib.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Include/Library/PeiPlatformLib.h
new file mode 100644
index 0000000000..2514d2ec44
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Include/Library/PeiPlatformLib.h
@@ -0,0 +1,38 @@
+/** @file
+ UP Xtreme platform library.
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_PLATFORM_LIB_H_
+#define _PEI_PLATFORM_LIB_H_
+
+#define PEI_DEVICE_DISABLED 0
+#define PEI_DEVICE_ENABLED 1
+
+typedef struct {
+ UINT8 Register;
+ UINT32 Value;
+} PCH_GPIO_DEV;
+
+//
+// GPIO Initialization Data Structure
+//
+typedef struct{
+ PCH_GPIO_DEV Use_Sel;
+ PCH_GPIO_DEV Use_Sel2;
+ PCH_GPIO_DEV Use_Sel3;
+ PCH_GPIO_DEV Io_Sel;
+ PCH_GPIO_DEV Io_Sel2;
+ PCH_GPIO_DEV Io_Sel3;
+ PCH_GPIO_DEV Lvl;
+ PCH_GPIO_DEV Lvl2;
+ PCH_GPIO_DEV Lvl3;
+ PCH_GPIO_DEV Inv;
+ PCH_GPIO_DEV Blink;
+ PCH_GPIO_DEV Rst_Sel;
+ PCH_GPIO_DEV Rst_Sel2;
+} GPIO_INIT_STRUCT;
+
+#endif
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Include/PlatformBoardConfig.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Include/PlatformBoardConfig.h
new file mode 100644
index 0000000000..db6024a1e4
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Include/PlatformBoardConfig.h
@@ -0,0 +1,103 @@
+/** @file
+ Header file for UP Xtreme platform board configuration.
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PLATFORM_BOARD_CONFIG_H
+#define _PLATFORM_BOARD_CONFIG_H
+
+#include <ConfigBlock.h>
+#include <PchPolicyCommon.h>
+#include <ConfigBlock/MemoryConfig.h>
+#include <GpioConfig.h>
+#include <TbtBoardInfo.h>
+
+#define IS_ALIGNED(addr, size) (((addr) & (size - 1)) ? 0 : 1)
+#define ALIGN16(size) (IS_ALIGNED(size, 16) ? size : ((size + 16) & 0xFFF0))
+
+#define BOARD_CONFIG_BLOCK_PEI_PREMEM_VERSION 0x00000001
+#define BOARD_CONFIG_BLOCK_PEI_POSTMEM_VERSION 0x00000001
+#define BOARD_CONFIG_BLOCK_DXE_VERSION 0x00000001
+#define BOARD_NO_BATTERY_SUPPORT 0
+#define BOARD_REAL_BATTERY_SUPPORTED BIT0
+#define BOARD_VIRTUAL_BATTERY_SUPPORTED BIT1
+
+#pragma pack(1)
+
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header
+} BOARD_CONFIG_BLOCK;
+
+typedef struct {
+ UINT8 GpioSupport;
+ UINT32 WakeGpioNo;
+ UINT8 HoldRstExpanderNo;
+ UINT32 HoldRstGpioNo;
+ BOOLEAN HoldRstActive;
+ UINT8 PwrEnableExpanderNo;
+ UINT32 PwrEnableGpioNo;
+ BOOLEAN PwrEnableActive;
+} SWITCH_GRAPHIC_GPIO;
+
+typedef struct {
+ UINT8 ClkReqNumber : 4;
+ UINT8 ClkReqSupported : 1;
+ UINT8 DeviceResetPadActiveHigh : 1;
+ UINT32 DeviceResetPad;
+} ROOT_PORT_CLK_INFO;
+
+typedef struct {
+ UINT8 Section;
+ UINT8 Pin;
+} EXPANDER_GPIO_CONFIG;
+
+typedef enum {
+ BoardGpioTypePch,
+ BoardGpioTypeExpander,
+ BoardGpioTypeNotSupported = 0xFF
+} BOARD_GPIO_TYPE;
+
+typedef struct {
+ UINT8 Type;
+ UINT8 Reserved[3]; // alignment for COMMON_GPIO_CONFIG
+ union {
+ UINT32 Pin;
+ EXPANDER_GPIO_CONFIG Expander;
+ } u;
+} BOARD_GPIO_CONFIG;
+
+// Do not change the encoding. It must correspond with PCH_PCIE_CLOCK_USAGE from PCH RC.
+#define NOT_USED 0xFF
+#define FREE_RUNNING 0x80
+#define LAN_CLOCK 0x70
+#define PCIE_PEG 0x40
+#define PCIE_PCH 0x00
+
+typedef struct {
+ UINT32 ClockUsage;
+ UINT32 ClkReqSupported;
+} PCIE_CLOCK_CONFIG;
+
+typedef union {
+ UINT64 Blob;
+ BOARD_GPIO_CONFIG BoardGpioConfig;
+ ROOT_PORT_CLK_INFO Info;
+ PCIE_CLOCK_CONFIG PcieClock;
+} PCD64_BLOB;
+
+typedef union {
+ UINT32 Blob;
+ USB20_AFE Info;
+} PCD32_BLOB;
+
+#ifndef IO_EXPANDER_DISABLED
+#define IO_EXPANDER_DISABLED 0xFF
+#endif
+
+#define SPD_DATA_SIZE 512
+
+#pragma pack()
+
+#endif // _PLATFORM_BOARD_CONFIG_H
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Include/PlatformInfo.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Include/PlatformInfo.h
new file mode 100644
index 0000000000..88564e3733
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Include/PlatformInfo.h
@@ -0,0 +1,42 @@
+/** @file
+ GUID used for Platform Info Data entries in the HOB list.
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PLATFORM_INFO_H_
+#define _PLATFORM_INFO_H_
+
+#pragma pack(1)
+
+///
+/// PCH_GPIO_PAD is equivalent to GPIO_PAD which is defined in GpioConfig.h
+///
+typedef UINT32 PCH_GPIO_PAD; //Copied from GpioConfig.h (need to change it based on include)
+
+typedef struct {
+UINT8 Expander;
+UINT8 Pin;
+UINT16 Reserved; // Reserved for future use
+} IO_EXPANDER_PAD;
+
+typedef union {
+PCH_GPIO_PAD PchGpio;
+IO_EXPANDER_PAD IoExpGpio;
+} GPIO_PAD_CONFIG;
+
+typedef struct {
+UINT8 GpioType; // 0: Disabled (no GPIO support), 1: PCH, 2: I/O Expander
+UINT8 Reserved[3]; // Reserved for future use
+GPIO_PAD_CONFIG GpioData;
+} PACKED_GPIO_CONFIG;
+
+typedef union {
+PACKED_GPIO_CONFIG PackedGpio;
+UINT64 Data64;
+} COMMON_GPIO_CONFIG;
+
+#pragma pack()
+
+#endif
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BaseFuncLib/BaseFuncLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BaseFuncLib/BaseFuncLib.inf
new file mode 100644
index 0000000000..602e8da686
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BaseFuncLib/BaseFuncLib.inf
@@ -0,0 +1,33 @@
+## @file
+# Component information file for Board Functions Library.
+#
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = BaseBoardFuncInitLib
+ FILE_GUID = 7ad17b6c-b9b6-4d88-85c4-7366a2bd12a3
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = NULL|PEIM
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+
+[Packages]
+ WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ CoffeelakeSiliconPkg/SiPkg.dec
+
+[Sources]
+ Gop.c
+
+
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BaseFuncLib/Gop.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BaseFuncLib/Gop.c
new file mode 100644
index 0000000000..e483032944
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BaseFuncLib/Gop.c
@@ -0,0 +1,38 @@
+/** @file
+ Others Board's PCD function hook.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Uefi.h>
+#include <Library/DebugLib.h>
+#include <GopConfigLib.h>
+
+//
+// Null function for nothing GOP VBT update.
+//
+VOID
+EFIAPI
+GopVbtSpecificUpdateNull (
+ IN CHILD_STRUCT **ChildStructPtr
+ )
+{
+ return;
+}
+
+VOID
+EFIAPI
+UpXtremeSpecificUpdate (
+ IN CHILD_STRUCT **ChildStructPtr
+ )
+{
+ ChildStructPtr[1]->DeviceClass = DISPLAY_PORT_ONLY;
+ ChildStructPtr[1]->DVOPort = DISPLAY_PORT_B;
+ ChildStructPtr[2]->DeviceClass = DISPLAY_PORT_HDMI_DVI_COMPATIBLE;
+ ChildStructPtr[2]->DVOPort = DISPLAY_PORT_C;
+ ChildStructPtr[2]->AUX_Channel = AUX_CHANNEL_C;
+ ChildStructPtr[3]->DeviceClass = NO_DEVICE;
+}
+
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BaseGpioCheckConflictLib/BaseGpioCheckConflictLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BaseGpioCheckConflictLib/BaseGpioCheckConflictLib.c
new file mode 100644
index 0000000000..e42bb7cb91
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BaseGpioCheckConflictLib/BaseGpioCheckConflictLib.c
@@ -0,0 +1,137 @@
+/** @file
+ Implementation of BaseGpioCheckConflictLib.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Library/GpioCheckConflictLib.h>
+#include <Uefi/UefiMultiPhase.h>
+#include <Pi/PiBootMode.h>
+#include <Pi/PiHob.h>
+#include <Library/HobLib.h>
+#include <Library/DebugLib.h>
+#include <Private/Library/GpioPrivateLib.h>
+
+/**
+ Check Gpio PadMode conflict and report it.
+
+ @retval none.
+**/
+VOID
+GpioCheckConflict (
+ VOID
+ )
+{
+ EFI_HOB_GUID_TYPE *GpioCheckConflictHob;
+ GPIO_PAD_MODE_INFO *GpioCheckConflictHobData;
+ UINT32 HobDataSize;
+ UINT32 GpioCount;
+ UINT32 GpioIndex;
+ GPIO_CONFIG GpioActualConfig;
+
+ GpioCheckConflictHob = NULL;
+ GpioCheckConflictHobData = NULL;
+
+ DEBUG ((DEBUG_INFO, "GpioCheckConflict Start..\n"));
+
+ //
+ //Use Guid to find HOB.
+ //
+ GpioCheckConflictHob = (EFI_HOB_GUID_TYPE *) GetFirstGuidHob (&gGpioCheckConflictHobGuid);
+ if (GpioCheckConflictHob == NULL) {
+ DEBUG ((DEBUG_INFO, "[Gpio Hob Check] Can't find Gpio Hob.\n"));
+ } else {
+ while (GpioCheckConflictHob != NULL) {
+ //
+ // Find the Data area pointer and Data size from the Hob
+ //
+ GpioCheckConflictHobData = (GPIO_PAD_MODE_INFO *) GET_GUID_HOB_DATA (GpioCheckConflictHob);
+ HobDataSize = GET_GUID_HOB_DATA_SIZE (GpioCheckConflictHob);
+
+ GpioCount = HobDataSize / sizeof (GPIO_PAD_MODE_INFO);
+ DEBUG ((DEBUG_INFO, "[Hob Check] Hob : GpioCount = %d\n", GpioCount));
+
+ //
+ // Probe Gpio entries in Hob and compare which are conflicted
+ //
+ for (GpioIndex = 0; GpioIndex < GpioCount ; GpioIndex++) {
+ GpioGetPadConfig (GpioCheckConflictHobData[GpioIndex].GpioPad, &GpioActualConfig);
+ if (GpioCheckConflictHobData[GpioIndex].GpioPadMode != GpioActualConfig.PadMode) {
+ DEBUG ((DEBUG_ERROR, "[Gpio Check] Identified conflict on pad %a\n", GpioName (GpioCheckConflictHobData[GpioIndex].GpioPad)));
+ }
+ }
+ //
+ // Find next Hob and return the Hob pointer by the specific Hob Guid
+ //
+ GpioCheckConflictHob = GET_NEXT_HOB (GpioCheckConflictHob);
+ GpioCheckConflictHob = GetNextGuidHob (&gGpioCheckConflictHobGuid, GpioCheckConflictHob);
+ }
+
+ DEBUG ((DEBUG_INFO, "GpioCheckConflict End.\n"));
+ }
+
+ return;
+}
+
+/**
+ This libaray will create one Hob for each Gpio config table
+ without PadMode is GpioHardwareDefault
+
+ @param[in] GpioDefinition Point to Platform Gpio table
+ @param[in] GpioTableCount Number of Gpio table entries
+
+ @retval none.
+**/
+VOID
+CreateGpioCheckConflictHob (
+ IN GPIO_INIT_CONFIG *GpioDefinition,
+ IN UINT16 GpioTableCount
+ )
+{
+
+ UINT32 Index;
+ UINT32 GpioIndex;
+ GPIO_PAD_MODE_INFO *GpioCheckConflictHobData;
+ UINT16 GpioCount;
+
+ GpioCount = 0;
+ GpioIndex = 0;
+
+ DEBUG ((DEBUG_INFO, "CreateGpioCheckConflictHob Start \n"));
+
+ for (Index = 0; Index < GpioTableCount ; Index++) {
+ if (GpioDefinition[Index].GpioConfig.PadMode == GpioHardwareDefault) {
+ continue;
+ } else {
+ //
+ // Calculate how big size the Hob Data needs
+ //
+ GpioCount++;
+ }
+ }
+
+ //
+ // Build a HOB tagged with a GUID for identification and returns
+ // the start address of GUID HOB data.
+ //
+ GpioCheckConflictHobData = (GPIO_PAD_MODE_INFO *) BuildGuidHob (&gGpioCheckConflictHobGuid , GpioCount * sizeof (GPIO_PAD_MODE_INFO));
+
+ //
+ // Record Non Default Gpio entries to the Hob
+ //
+ for (Index = 0; Index < GpioTableCount; Index++) {
+ if (GpioDefinition[Index].GpioConfig.PadMode == GpioHardwareDefault) {
+ continue;
+ } else {
+ GpioCheckConflictHobData[GpioIndex].GpioPad = GpioDefinition[Index].GpioPad;
+ GpioCheckConflictHobData[GpioIndex].GpioPadMode = GpioDefinition[Index].GpioConfig.PadMode;
+ GpioIndex++;
+ }
+ }
+
+ DEBUG ((DEBUG_INFO, "CreateGpioCheckConflictHob End \n"));
+ return;
+}
+
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BaseGpioCheckConflictLib/BaseGpioCheckConflictLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BaseGpioCheckConflictLib/BaseGpioCheckConflictLib.inf
new file mode 100644
index 0000000000..24506c3453
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BaseGpioCheckConflictLib/BaseGpioCheckConflictLib.inf
@@ -0,0 +1,35 @@
+## @file
+# Component information file for BaseGpioCheckConflictLib.
+#
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = BaseGpioCheckConflictLib
+ FILE_GUID = C19A848A-F013-4DBF-9C23-F0F74DEA6F14
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = GpioCheckConflictLib
+
+[LibraryClasses]
+ DebugLib
+ HobLib
+ GpioLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec
+ CoffeelakeSiliconPkg/SiPkg.dec
+
+[Sources]
+ BaseGpioCheckConflictLib.c
+
+[Guids]
+ gGpioCheckConflictHobGuid
+
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BaseGpioCheckConflictLibNull/BaseGpioCheckConflictLibNull.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BaseGpioCheckConflictLibNull/BaseGpioCheckConflictLibNull.c
new file mode 100644
index 0000000000..525a9b3e0f
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BaseGpioCheckConflictLibNull/BaseGpioCheckConflictLibNull.c
@@ -0,0 +1,37 @@
+/** @file
+ Implementation of BaseGpioCheckConflicLibNull.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Library/GpioCheckConflictLib.h>
+
+/**
+ Check Gpio PadMode conflict and report it.
+**/
+VOID
+GpioCheckConflict (
+ VOID
+ )
+{
+ return;
+}
+
+/**
+ This libaray will create one Hob for each Gpio config table
+ without PadMode is GpioHardwareDefault
+
+ @param[in] GpioDefinition Point to Platform Gpio table
+ @param[in] GpioTableCount Number of Gpio table entries
+**/
+VOID
+CreateGpioCheckConflictHob (
+ IN GPIO_INIT_CONFIG *GpioDefinition,
+ IN UINT16 GpioTableCount
+ )
+{
+ return;
+}
+
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BaseGpioCheckConflictLibNull/BaseGpioCheckConflictLibNull.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BaseGpioCheckConflictLibNull/BaseGpioCheckConflictLibNull.inf
new file mode 100644
index 0000000000..c00cf0b8af
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BaseGpioCheckConflictLibNull/BaseGpioCheckConflictLibNull.inf
@@ -0,0 +1,32 @@
+## @file
+# Component information file for BaseGpioCheckConflictLib.
+#
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = BaseGpioCheckConflictLibNull
+ FILE_GUID = C19A848A-F013-4DBF-9C23-F0F74DEA6F14
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = GpioCheckConflictLib
+
+[LibraryClasses]
+ DebugLib
+ HobLib
+ GpioLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec
+ CoffeelakeSiliconPkg/SiPkg.dec
+
+[Sources]
+ BaseGpioCheckConflictLibNull.c
+
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BasePlatformHookLib/BasePlatformHookLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BasePlatformHookLib/BasePlatformHookLib.c
new file mode 100644
index 0000000000..119a04b7fd
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BasePlatformHookLib/BasePlatformHookLib.c
@@ -0,0 +1,143 @@
+
+/** @file
+ Platform Hook Library instance for the UpXtreme Board
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Base.h>
+#include <GpioPinsCnlLp.h>
+#include <Library/BaseLib.h>
+#include <Library/GpioLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/PlatformHookLib.h>
+#include <PchAccess.h>
+#include <Uefi/UefiBaseType.h>
+
+#define LCR_OFFSET (FixedPcdGet32 (PcdSerialRegisterStride) * 0x03)
+
+STATIC GPIO_INIT_CONFIG mUartGpioTable[] = {
+ {GPIO_CNL_LP_GPP_C20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_RXD
+ {GPIO_CNL_LP_GPP_C21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//SERIALIO_UART2_TXD
+};
+
+/**
+ Retrieve the I/O or MMIO base address register for the PCI UART device.
+
+ @retval The base address register of the UART device.
+
+**/
+STATIC
+UINTN
+GetSerialRegisterBase (
+ VOID
+ )
+{
+ UINT64 PciAddress;
+ UINT32 BaseAddressBuffer[2];
+ UINT16 Cmd16;
+
+ PciAddress = PCI_SEGMENT_LIB_ADDRESS (
+ DEFAULT_PCI_SEGMENT_NUMBER_PCH,
+ DEFAULT_PCI_BUS_NUMBER_PCH,
+ PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART2,
+ PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART2,
+ 0
+ );
+
+ Cmd16 = PciSegmentRead16 (PciAddress + PCI_VENDOR_ID_OFFSET);
+ if (Cmd16 == 0xFFFF) {
+ //
+ // Device might be hidden, return the fixed serial register base address
+ //
+ return (UINTN) FixedPcdGet32 (PcdSerialRegisterBase);
+ } else {
+ if (PciSegmentRead32 (PciAddress + PCI_COMMAND_OFFSET) & EFI_PCI_COMMAND_MEMORY_SPACE) {
+ BaseAddressBuffer[0] = PciSegmentRead32 (PciAddress + R_SERIAL_IO_CFG_BAR0_LOW) & B_SERIAL_IO_CFG_BAR0_LOW_BAR;
+ BaseAddressBuffer[1] = 0;
+
+ if ((PciSegmentRead32 (PciAddress + PCI_BASE_ADDRESSREG_OFFSET) & 0x6) == 0x4) {
+ BaseAddressBuffer[1] = PciSegmentRead32 (PciAddress + R_SERIAL_IO_CFG_BAR0_HIGH);
+ }
+ return *((UINTN *) (&BaseAddressBuffer[0]));
+ } else {
+ return 0;
+ }
+ }
+}
+
+/**
+ Performs platform specific initialization required for the CPU to access
+ the hardware associated with a SerialPortLib instance. This function does
+ not initialize the serial port hardware itself. Instead, it initializes
+ hardware devices that are required for the CPU to access the serial port
+ hardware. This function may be called more than once.
+
+ @retval RETURN_SUCCESS The platform specific initialization succeeded.
+ @retval RETURN_DEVICE_ERROR The platform specific initialization could not be completed.
+
+**/
+RETURN_STATUS
+EFIAPI
+PlatformHookSerialPortInitialize (
+ VOID
+ )
+{
+ UINT64 PciAddress;
+ UINTN SerialRegisterBase;
+ UINTN SerialRegisterBase1;
+
+ PciAddress = PCI_SEGMENT_LIB_ADDRESS (
+ DEFAULT_PCI_SEGMENT_NUMBER_PCH,
+ DEFAULT_PCI_BUS_NUMBER_PCH,
+ PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART2,
+ PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART2,
+ 0
+ );
+
+ SerialRegisterBase = GetSerialRegisterBase ();
+
+ if (SerialRegisterBase == 0 || SerialRegisterBase == (UINTN) ~0) {
+ return RETURN_DEVICE_ERROR;
+ }
+ SerialRegisterBase1 = SerialRegisterBase + V_SERIAL_IO_CFG_BAR_SIZE;
+
+ if (
+ (MmioRead8 (SerialRegisterBase + LCR_OFFSET) & 0x3F) !=
+ (FixedPcdGet8 (PcdSerialLineControl) & 0x3F)
+ ) {
+ GpioConfigurePads ((sizeof (mUartGpioTable) / sizeof (GPIO_INIT_CONFIG)), mUartGpioTable);
+
+ PciSegmentWrite32 (PciAddress + R_SERIAL_IO_CFG_BAR0_LOW, (UINT32) SerialRegisterBase);
+ PciSegmentWrite32 (PciAddress + R_SERIAL_IO_CFG_BAR1_LOW, (UINT32) SerialRegisterBase1);
+ if (sizeof (UINTN) == sizeof (UINT32)) {
+ PciSegmentWrite32 (PciAddress + R_SERIAL_IO_CFG_BAR0_HIGH, 0x0);
+ PciSegmentWrite32 (PciAddress + R_SERIAL_IO_CFG_BAR1_HIGH, 0x0);
+ } else {
+ PciSegmentWrite32 (PciAddress + R_SERIAL_IO_CFG_BAR0_HIGH, (UINT32) RShiftU64 (SerialRegisterBase, 32));
+ PciSegmentWrite32 (PciAddress + R_SERIAL_IO_CFG_BAR1_HIGH, (UINT32) RShiftU64 (SerialRegisterBase1, 32));
+ }
+ PciSegmentWrite32 (PciAddress + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_BUS_MASTER | EFI_PCI_COMMAND_MEMORY_SPACE);
+ PciSegmentOr32 (PciAddress + R_SERIAL_IO_CFG_D0I3MAXDEVPG, BIT18 | BIT17 | BIT16);
+
+ //
+ // Get controller out of reset
+ //
+ MmioOr32 (SerialRegisterBase + R_SERIAL_IO_MEM_PPR_RESETS,
+ B_SERIAL_IO_MEM_PPR_RESETS_FUNC | B_SERIAL_IO_MEM_PPR_RESETS_APB | B_SERIAL_IO_MEM_PPR_RESETS_IDMA);
+
+ //
+ // Program clock dividers for UARTs
+ //
+ MmioWrite32 (SerialRegisterBase + R_SERIAL_IO_MEM_PPR_CLK,
+ (B_SERIAL_IO_MEM_PPR_CLK_UPDATE | (V_SERIAL_IO_MEM_PPR_CLK_N_DIV << 16) |
+ (V_SERIAL_IO_MEM_PPR_CLK_M_DIV << 1) | B_SERIAL_IO_MEM_PPR_CLK_EN )
+ );
+ }
+
+ return RETURN_SUCCESS;
+}
+
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BasePlatformHookLib/BasePlatformHookLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BasePlatformHookLib/BasePlatformHookLib.inf
new file mode 100644
index 0000000000..b527d90f08
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BasePlatformHookLib/BasePlatformHookLib.inf
@@ -0,0 +1,45 @@
+## @file
+# Platform Hook Library instance for the UpXtreme board.
+#
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = BasePlatformHookLib
+ FILE_GUID = E22ADCC6-ED90-4A90-9837-C8E7FF9E963D
+ VERSION_STRING = 1.0
+ MODULE_TYPE = BASE
+ LIBRARY_CLASS = PlatformHookLib
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+[LibraryClasses]
+ BaseLib
+ GpioLib
+ IoLib
+ PcdLib
+ PciSegmentLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ CoffeelakeSiliconPkg/SiPkg.dec
+ WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec
+
+[Sources]
+ BasePlatformHookLib.c
+
+[FixedPcd]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialLineControl
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.c
new file mode 100644
index 0000000000..57ba4c7a6f
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.c
@@ -0,0 +1,63 @@
+/** @file
+ SMM Board ACPI Enable Library for the UpXtreme Board
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Base.h>
+#include <Uefi.h>
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardAcpiEnableLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+
+EFI_STATUS
+EFIAPI
+UpXtremeBoardEnableAcpi (
+ IN BOOLEAN EnableSci
+ );
+
+EFI_STATUS
+EFIAPI
+UpXtremeBoardDisableAcpi (
+ IN BOOLEAN DisableSci
+ );
+
+EFI_STATUS
+EFIAPI
+SiliconEnableAcpi (
+ IN BOOLEAN EnableSci
+ );
+
+EFI_STATUS
+EFIAPI
+SiliconDisableAcpi (
+ IN BOOLEAN DisableSci
+ );
+
+EFI_STATUS
+EFIAPI
+BoardEnableAcpi (
+ IN BOOLEAN EnableSci
+ )
+{
+ SiliconEnableAcpi (EnableSci);
+ return UpXtremeBoardEnableAcpi (EnableSci);
+}
+
+EFI_STATUS
+EFIAPI
+BoardDisableAcpi (
+ IN BOOLEAN DisableSci
+ )
+{
+ SiliconDisableAcpi (DisableSci);
+ return UpXtremeBoardDisableAcpi (DisableSci);
+}
+
+
+
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf
new file mode 100644
index 0000000000..b1c685711a
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf
@@ -0,0 +1,50 @@
+## @file
+# SMM Board ACPI Enable Library for the UpXtreme Board
+#
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = SmmBoardAcpiEnableLib
+ FILE_GUID = 549E69AE-D3B3-485B-9C17-AF16E20A58AD
+ VERSION_STRING = 1.0
+ MODULE_TYPE = BASE
+ LIBRARY_CLASS = BoardAcpiEnableLib
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+[LibraryClasses]
+ BaseLib
+ IoLib
+ PciLib
+ MmPciLib
+ PchCycleDecodingLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec
+ CoffeelakeSiliconPkg/SiPkg.dec
+
+[Pcd]
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSmcExtSmiBitPosition ## CONSUMES
+
+[Protocols]
+
+[Sources]
+ SmmUpXtremeAcpiEnableLib.c
+ SmmSiliconAcpiEnableLib.c
+ SmmBoardAcpiEnableLib.c
+
+
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c
new file mode 100644
index 0000000000..63881029ad
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c
@@ -0,0 +1,82 @@
+/** @file
+ SMM Multi-Board ACPI Support Library for the UpXtreme Board
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Base.h>
+#include <Uefi.h>
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardAcpiEnableLib.h>
+#include <Library/MultiBoardAcpiSupportLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+
+#include <PlatformBoardId.h>
+
+EFI_STATUS
+EFIAPI
+UpXtremeBoardEnableAcpi (
+ IN BOOLEAN EnableSci
+ );
+
+EFI_STATUS
+EFIAPI
+UpXtremeBoardDisableAcpi (
+ IN BOOLEAN DisableSci
+ );
+
+EFI_STATUS
+EFIAPI
+SiliconEnableAcpi (
+ IN BOOLEAN EnableSci
+ );
+
+EFI_STATUS
+EFIAPI
+SiliconDisableAcpi (
+ IN BOOLEAN DisableSci
+ );
+
+EFI_STATUS
+EFIAPI
+UpXtremeMultiBoardEnableAcpi (
+ IN BOOLEAN EnableSci
+ )
+{
+ SiliconEnableAcpi (EnableSci);
+ return UpXtremeBoardEnableAcpi (EnableSci);
+}
+
+EFI_STATUS
+EFIAPI
+UpXtremeMultiBoardDisableAcpi (
+ IN BOOLEAN DisableSci
+ )
+{
+ SiliconDisableAcpi (DisableSci);
+ return UpXtremeBoardDisableAcpi (DisableSci);
+}
+
+BOARD_ACPI_ENABLE_FUNC mUpXtremeBoardAcpiEnableFunc = {
+ UpXtremeMultiBoardEnableAcpi,
+ UpXtremeMultiBoardDisableAcpi,
+};
+
+EFI_STATUS
+EFIAPI
+SmmUpXtremeMultiBoardAcpiSupportLibConstructor (
+ VOID
+ )
+{
+ if (LibPcdGetSku () == BoardIdUpXtreme) {
+ return RegisterBoardAcpiEnableFunc (&mUpXtremeBoardAcpiEnableFunc);
+ }
+ return EFI_SUCCESS;
+}
+
+
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf
new file mode 100644
index 0000000000..5f5493de77
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf
@@ -0,0 +1,50 @@
+## @file
+# SMM Multi-Board ACPI Support Library for the UpXtreme Board
+#
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = SmmUpXtremeMultiBoardAcpiSupportLib
+ FILE_GUID = 8929A54E-7ED8-4AB3-BEBB-C0367BDBBFF5
+ VERSION_STRING = 1.0
+ MODULE_TYPE = BASE
+ LIBRARY_CLASS = NULL
+ CONSTRUCTOR = SmmUpXtremeMultiBoardAcpiSupportLibConstructor
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+[LibraryClasses]
+ BaseLib
+ IoLib
+ PciLib
+ PmcLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec
+ CoffeelakeSiliconPkg/SiPkg.dec
+
+[Pcd]
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSmcExtSmiBitPosition ## CONSUMES
+
+[Protocols]
+
+[Sources]
+ SmmUpXtremeAcpiEnableLib.c
+ SmmSiliconAcpiEnableLib.c
+ SmmMultiBoardAcpiSupportLib.c
+
+
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c
new file mode 100644
index 0000000000..23b4fe6dc5
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c
@@ -0,0 +1,170 @@
+/** @file
+ SMM Silicon ACPI Enable Library for the UpXtreme Board
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Base.h>
+#include <Uefi.h>
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/BoardAcpiEnableLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <PchAccess.h>
+#include <Library/MmPciLib.h>
+#include <Library/PmcLib.h>
+
+/**
+ Clear Port 80h
+
+ SMI handler to enable ACPI mode
+
+ Dispatched on reads from APM port with value EFI_ACPI_ENABLE_SW_SMI
+
+ Disables the SW SMI Timer.
+ ACPI events are disabled and ACPI event status is cleared.
+ SCI mode is then enabled.
+
+ Clear SLP SMI status
+ Enable SLP SMI
+
+ Disable SW SMI Timer
+
+ Clear all ACPI event status and disable all ACPI events
+
+ Disable PM sources except power button
+ Clear status bits
+
+ Disable GPE0 sources
+ Clear status bits
+
+ Disable GPE1 sources
+ Clear status bits
+
+ Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4)
+
+ Enable SCI
+**/
+EFI_STATUS
+EFIAPI
+SiliconEnableAcpi (
+ IN BOOLEAN EnableSci
+ )
+{
+
+ UINT32 OutputValue;
+ UINT32 SmiEn;
+ UINT32 SmiSts;
+ UINT32 ULKMC;
+ UINTN LpcBaseAddress;
+ UINT16 AcpiBaseAddr;
+ UINT32 Pm1Cnt;
+
+ LpcBaseAddress = PCI_SEGMENT_LIB_ADDRESS(
+ DEFAULT_PCI_SEGMENT_NUMBER_PCH,
+ DEFAULT_PCI_BUS_NUMBER_PCH,
+ PCI_DEVICE_NUMBER_PCH_LPC,
+ PCI_FUNCTION_NUMBER_PCH_LPC,
+ 0
+ );
+ //
+ // Get the ACPI Base Address
+ //
+ AcpiBaseAddr = PmcGetAcpiBase();
+ //
+ // BIOS must also ensure that CF9GR is cleared and locked before handing control to the
+ // OS in order to prevent the host from issuing global resets and resetting ME
+ //
+ // EDK2: To match PCCG current BIOS behavior, do not lock CF9 Global Reset
+ // MmioWrite32 (
+ // PmcBaseAddress + R_PCH_PMC_ETR3),
+ // PmInit);
+
+ //
+ // Clear Port 80h
+ //
+ IoWrite8 (0x80, 0);
+
+ //
+ // Disable SW SMI Timer and clean the status
+ //
+ SmiEn = IoRead32 (AcpiBaseAddr + R_ACPI_IO_SMI_EN);
+ SmiEn &= ~(B_ACPI_IO_SMI_EN_LEGACY_USB2 | B_ACPI_IO_SMI_EN_SWSMI_TMR | B_ACPI_IO_SMI_EN_LEGACY_USB);
+ IoWrite32 (AcpiBaseAddr + R_ACPI_IO_SMI_EN, SmiEn);
+
+ SmiSts = IoRead32 (AcpiBaseAddr + R_ACPI_IO_SMI_STS);
+ SmiSts |= B_ACPI_IO_SMI_EN_LEGACY_USB2 | B_ACPI_IO_SMI_EN_SWSMI_TMR | B_ACPI_IO_SMI_EN_LEGACY_USB;
+ IoWrite32 (AcpiBaseAddr + R_ACPI_IO_SMI_STS, SmiSts);
+
+ //
+ // Disable port 60/64 SMI trap if they are enabled
+ //
+ ULKMC = MmioRead32 (LpcBaseAddress + R_LPC_CFG_ULKMC) & ~(B_LPC_CFG_ULKMC_60REN | B_LPC_CFG_ULKMC_60WEN | B_LPC_CFG_ULKMC_64REN | B_LPC_CFG_ULKMC_64WEN | B_LPC_CFG_ULKMC_A20PASSEN);
+ MmioWrite32 (LpcBaseAddress + R_LPC_CFG_ULKMC, ULKMC);
+
+ //
+ // Disable PM sources except power button
+ //
+ IoWrite16 (AcpiBaseAddr + R_ACPI_IO_PM1_EN, B_ACPI_IO_PM1_EN_PWRBTN);
+
+ //
+ // Clear PM status except Power Button status for RapidStart Resume
+ //
+ IoWrite16 (AcpiBaseAddr + R_ACPI_IO_PM1_STS, 0xFEFF);
+
+ //
+ // Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4)
+ //
+ IoWrite8 (R_RTC_IO_INDEX_ALT, R_RTC_IO_REGD);
+ IoWrite8 (R_RTC_IO_TARGET_ALT, 0x0);
+
+ //
+ // Write ALT_GPI_SMI_EN to disable GPI1 (SMC_EXTSMI#)
+ //
+ OutputValue = IoRead32 (AcpiBaseAddr + 0x38);
+ OutputValue = OutputValue & ~(1 << (UINTN) PcdGet8 (PcdSmcExtSmiBitPosition));
+ IoWrite32 (AcpiBaseAddr + 0x38, OutputValue);
+
+ //
+ // Enable SCI
+ //
+ if (EnableSci) {
+ Pm1Cnt = IoRead32 (AcpiBaseAddr + R_ACPI_IO_PM1_CNT);
+ Pm1Cnt |= B_ACPI_IO_PM1_CNT_SCI_EN;
+ IoWrite32 (AcpiBaseAddr + R_ACPI_IO_PM1_CNT, Pm1Cnt);
+ }
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+SiliconDisableAcpi (
+ IN BOOLEAN DisableSci
+ )
+{
+
+ UINT16 AcpiBaseAddr;
+ UINT32 Pm1Cnt;
+
+ //
+ // Get the ACPI Base Address
+ //
+ AcpiBaseAddr = PmcGetAcpiBase();
+ //
+ // Disable SCI
+ //
+ if (DisableSci) {
+ Pm1Cnt = IoRead32 (AcpiBaseAddr + R_ACPI_IO_PM1_CNT);
+ Pm1Cnt &= ~B_ACPI_IO_PM1_CNT_SCI_EN;
+ IoWrite32 (AcpiBaseAddr + R_ACPI_IO_PM1_CNT, Pm1Cnt);
+ }
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardAcpiLib/SmmUpXtremeAcpiEnableLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardAcpiLib/SmmUpXtremeAcpiEnableLib.c
new file mode 100644
index 0000000000..2b777aab02
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardAcpiLib/SmmUpXtremeAcpiEnableLib.c
@@ -0,0 +1,40 @@
+/** @file
+ SMM UpXtreme ACPI Enable Library
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Base.h>
+#include <Uefi.h>
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardAcpiTableLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+
+#include <PlatformBoardId.h>
+
+EFI_STATUS
+EFIAPI
+UpXtremeBoardEnableAcpi (
+ IN BOOLEAN EnableSci
+ )
+{
+ // enable additional board register
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+UpXtremeBoardDisableAcpi (
+ IN BOOLEAN DisableSci
+ )
+{
+ // enable additional board register
+ return EFI_SUCCESS;
+}
+
+
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/BoardFuncInitPreMem.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/BoardFuncInitPreMem.c
new file mode 100644
index 0000000000..09badef00e
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/BoardFuncInitPreMem.c
@@ -0,0 +1,25 @@
+/** @file
+ Source code for the board configuration init function in Post Memory init phase.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <GopConfigLib.h>
+
+//
+// Null function for nothing GOP VBT update.
+//
+VOID
+GopVbtSpecificUpdateNull (
+ IN CHILD_STRUCT **ChildStructPtr
+ );
+
+//
+// for CFL U DDR4
+//
+VOID
+UpXtremeSpecificUpdate (
+ IN CHILD_STRUCT **ChildStructPtr
+ );
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/BoardInitLib.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/BoardInitLib.h
new file mode 100644
index 0000000000..758cbaa0b6
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/BoardInitLib.h
@@ -0,0 +1,20 @@
+/** @file
+ Header file for board Init function for Post Memory Init phase.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_BOARD_INIT_LIB_H_
+#define _PEI_BOARD_INIT_LIB_H_
+
+#include <Uefi.h>
+#include <Library/BaseLib.h>
+#include <Library/PcdLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/DebugLib.h>
+#include <PlatformBoardId.h>
+
+#endif // _PEI_BOARD_INIT_LIB_H_
+
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/BoardPchInitPreMemLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/BoardPchInitPreMemLib.c
new file mode 100644
index 0000000000..ddeea45175
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/BoardPchInitPreMemLib.c
@@ -0,0 +1,375 @@
+/** @file
+ Source code for the board PCH configuration Pcd init functions for Pre-Memory Init phase.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "UpXtremeInit.h"
+#include <GpioPinsCnlLp.h>
+#include <GpioPinsCnlH.h>
+#include <PlatformBoardConfig.h> // for USB 20 AFE & Root Port Clk Info.
+#include <PlatformBoardId.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/GpioLib.h>
+
+/**
+ Board Root Port Clock Info configuration init function for PEI pre-memory phase.
+
+ @param[in] BoardId An unsigned integrer represent the board id.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+RootPortClkInfoInit (
+ IN UINT16 BoardId
+ )
+{
+ PCD64_BLOB *Clock;
+ UINT32 Index;
+
+ Clock = AllocateZeroPool (16 * sizeof (PCD64_BLOB));
+ ASSERT (Clock != NULL);
+ if (Clock == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+ //
+ // The default clock assignment will be FREE_RUNNING, which corresponds to PchClockUsageUnspecified
+ // This is safe but power-consuming setting. If Platform code doesn't contain port-clock map for a given board,
+ // the clocks will keep on running anyway, allowing PCIe devices to operate. Downside is that clocks will
+ // continue to draw power. To prevent this, remember to provide port-clock map for every board.
+ //
+ for (Index = 0; Index < 16; Index++) {
+ Clock[Index].PcieClock.ClkReqSupported = TRUE;
+ Clock[Index].PcieClock.ClockUsage = FREE_RUNNING;
+ }
+
+ ///
+ /// Assign ClkReq signal to root port. (Base 0)
+ /// For LP, Set 0 - 5
+ /// For H, Set 0 - 15
+ /// Note that if GbE is enabled, ClkReq assigned to GbE will not be available for Root Port.
+ ///
+ switch (BoardId) {
+ // CLKREQ
+ case BoardIdUpXtreme:
+ Clock[0].PcieClock.ClockUsage = FREE_RUNNING;
+ Clock[1].PcieClock.ClockUsage = FREE_RUNNING;
+ Clock[2].PcieClock.ClockUsage = FREE_RUNNING;
+ Clock[3].PcieClock.ClockUsage = FREE_RUNNING;
+ Clock[4].PcieClock.ClockUsage = FREE_RUNNING;
+ Clock[5].PcieClock.ClockUsage = FREE_RUNNING;
+ break;
+
+ default:
+ break;
+ }
+
+ PcdSet64S (PcdPcieClock0, Clock[ 0].Blob);
+ PcdSet64S (PcdPcieClock1, Clock[ 1].Blob);
+ PcdSet64S (PcdPcieClock2, Clock[ 2].Blob);
+ PcdSet64S (PcdPcieClock3, Clock[ 3].Blob);
+ PcdSet64S (PcdPcieClock4, Clock[ 4].Blob);
+ PcdSet64S (PcdPcieClock5, Clock[ 5].Blob);
+ PcdSet64S (PcdPcieClock6, Clock[ 6].Blob);
+ PcdSet64S (PcdPcieClock7, Clock[ 7].Blob);
+ PcdSet64S (PcdPcieClock8, Clock[ 8].Blob);
+ PcdSet64S (PcdPcieClock9, Clock[ 9].Blob);
+ PcdSet64S (PcdPcieClock10, Clock[10].Blob);
+ PcdSet64S (PcdPcieClock11, Clock[11].Blob);
+ PcdSet64S (PcdPcieClock12, Clock[12].Blob);
+ PcdSet64S (PcdPcieClock13, Clock[13].Blob);
+ PcdSet64S (PcdPcieClock14, Clock[14].Blob);
+ PcdSet64S (PcdPcieClock15, Clock[15].Blob);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Board USB related configuration init function for PEI pre-memory phase.
+
+ @param[in] BoardId An unsigned integrer represent the board id.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+UsbConfigInit (
+ IN UINT16 BoardId
+ )
+{
+ PCD32_BLOB *UsbPort20Afe;
+
+ UsbPort20Afe = AllocateZeroPool (PCH_MAX_USB2_PORTS * sizeof (PCD32_BLOB));
+ ASSERT (UsbPort20Afe != NULL);
+ if (UsbPort20Afe == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ //
+ // USB2 AFE settings.
+ //
+ UsbPort20Afe[0].Info.Petxiset = 7;
+ UsbPort20Afe[0].Info.Txiset = 5;
+ UsbPort20Afe[0].Info.Predeemp = 3;
+ UsbPort20Afe[0].Info.Pehalfbit = 0;
+
+ UsbPort20Afe[1].Info.Petxiset = 7;
+ UsbPort20Afe[1].Info.Txiset = 5;
+ UsbPort20Afe[1].Info.Predeemp = 3;
+ UsbPort20Afe[1].Info.Pehalfbit = 0;
+
+ UsbPort20Afe[2].Info.Petxiset = 7;
+ UsbPort20Afe[2].Info.Txiset = 5;
+ UsbPort20Afe[2].Info.Predeemp = 3;
+ UsbPort20Afe[2].Info.Pehalfbit = 0;
+
+ UsbPort20Afe[3].Info.Petxiset = 7;
+ UsbPort20Afe[3].Info.Txiset = 5;
+ UsbPort20Afe[3].Info.Predeemp = 3;
+ UsbPort20Afe[3].Info.Pehalfbit = 0;
+
+ UsbPort20Afe[4].Info.Petxiset = 7;
+ UsbPort20Afe[4].Info.Txiset = 5;
+ UsbPort20Afe[4].Info.Predeemp = 3;
+ UsbPort20Afe[4].Info.Pehalfbit = 0;
+
+ UsbPort20Afe[5].Info.Petxiset = 7;
+ UsbPort20Afe[5].Info.Txiset = 5;
+ UsbPort20Afe[5].Info.Predeemp = 3;
+ UsbPort20Afe[5].Info.Pehalfbit = 0;
+
+ UsbPort20Afe[6].Info.Petxiset = 7;
+ UsbPort20Afe[6].Info.Txiset = 5;
+ UsbPort20Afe[6].Info.Predeemp = 3;
+ UsbPort20Afe[6].Info.Pehalfbit = 0;
+
+ UsbPort20Afe[7].Info.Petxiset = 7;
+ UsbPort20Afe[7].Info.Txiset = 5;
+ UsbPort20Afe[7].Info.Predeemp = 3;
+ UsbPort20Afe[7].Info.Pehalfbit = 0;
+
+ UsbPort20Afe[8].Info.Petxiset = 7;
+ UsbPort20Afe[8].Info.Txiset = 5;
+ UsbPort20Afe[8].Info.Predeemp = 3;
+ UsbPort20Afe[8].Info.Pehalfbit = 0;
+
+ UsbPort20Afe[9].Info.Petxiset = 7;
+ UsbPort20Afe[9].Info.Txiset = 5;
+ UsbPort20Afe[9].Info.Predeemp = 3;
+ UsbPort20Afe[9].Info.Pehalfbit = 0;
+
+ //
+ // USB Port Over Current Pin
+ //
+ PcdSet8S (PcdUsb20OverCurrentPinPort0, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb20OverCurrentPinPort1, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb20OverCurrentPinPort2, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb20OverCurrentPinPort3, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb20OverCurrentPinPort4, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb20OverCurrentPinPort5, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb20OverCurrentPinPort6, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb20OverCurrentPinPort7, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb20OverCurrentPinPort8, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb20OverCurrentPinPort9, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb20OverCurrentPinPort10, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb20OverCurrentPinPort11, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb20OverCurrentPinPort12, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb20OverCurrentPinPort13, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb20OverCurrentPinPort14, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb20OverCurrentPinPort15, UsbOverCurrentPinMax);
+
+ PcdSet8S (PcdUsb30OverCurrentPinPort0, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb30OverCurrentPinPort1, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb30OverCurrentPinPort2, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb30OverCurrentPinPort3, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb30OverCurrentPinPort4, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb30OverCurrentPinPort5, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb30OverCurrentPinPort6, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb30OverCurrentPinPort7, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb30OverCurrentPinPort8, UsbOverCurrentPinMax);
+ PcdSet8S (PcdUsb30OverCurrentPinPort9, UsbOverCurrentPinMax);
+
+ switch (BoardId) {
+ // LP PCH configuration
+ case BoardIdUpXtreme:
+ PcdSet8S (PcdUsb20OverCurrentPinPort0, UsbOverCurrentPin2);
+ PcdSet8S (PcdUsb20OverCurrentPinPort1, UsbOverCurrentPinSkip);
+ PcdSet8S (PcdUsb20OverCurrentPinPort2, UsbOverCurrentPin2);
+ PcdSet8S (PcdUsb20OverCurrentPinPort3, UsbOverCurrentPin2);
+ PcdSet8S (PcdUsb20OverCurrentPinPort4, UsbOverCurrentPin3);
+ PcdSet8S (PcdUsb20OverCurrentPinPort5, UsbOverCurrentPin3);
+ PcdSet8S (PcdUsb20OverCurrentPinPort6, UsbOverCurrentPin3);
+ PcdSet8S (PcdUsb20OverCurrentPinPort7, UsbOverCurrentPin3);
+ PcdSet8S (PcdUsb20OverCurrentPinPort8, UsbOverCurrentPinSkip);
+ PcdSet8S (PcdUsb20OverCurrentPinPort9, UsbOverCurrentPinSkip);
+ PcdSet8S (PcdUsb20OverCurrentPinPort10, UsbOverCurrentPinSkip);
+ PcdSet8S (PcdUsb20OverCurrentPinPort11, UsbOverCurrentPinSkip);
+ PcdSet8S (PcdUsb20OverCurrentPinPort12, UsbOverCurrentPinSkip);
+ PcdSet8S (PcdUsb20OverCurrentPinPort13, UsbOverCurrentPinSkip);
+ PcdSet8S (PcdUsb20OverCurrentPinPort14, UsbOverCurrentPinSkip);
+ PcdSet8S (PcdUsb20OverCurrentPinPort15, UsbOverCurrentPinSkip);
+
+ PcdSet8S (PcdUsb30OverCurrentPinPort0, UsbOverCurrentPin2);
+ PcdSet8S (PcdUsb30OverCurrentPinPort1, UsbOverCurrentPinSkip);
+ PcdSet8S (PcdUsb30OverCurrentPinPort2, UsbOverCurrentPin2);
+ PcdSet8S (PcdUsb30OverCurrentPinPort3, UsbOverCurrentPin2);
+ PcdSet8S (PcdUsb30OverCurrentPinPort4, UsbOverCurrentPinSkip);
+ PcdSet8S (PcdUsb30OverCurrentPinPort5, UsbOverCurrentPinSkip);
+ PcdSet8S (PcdUsb30OverCurrentPinPort6, UsbOverCurrentPinSkip);
+ PcdSet8S (PcdUsb30OverCurrentPinPort7, UsbOverCurrentPinSkip);
+ PcdSet8S (PcdUsb30OverCurrentPinPort8, UsbOverCurrentPinSkip);
+ PcdSet8S (PcdUsb30OverCurrentPinPort9, UsbOverCurrentPinSkip);
+
+ // USB2.0 AFE settings
+ UsbPort20Afe[0].Info.Petxiset = 6;
+ UsbPort20Afe[0].Info.Txiset = 0;
+ UsbPort20Afe[0].Info.Predeemp = 3;
+ UsbPort20Afe[0].Info.Pehalfbit = 0;
+
+ UsbPort20Afe[1].Info.Petxiset = 6;
+ UsbPort20Afe[1].Info.Txiset = 0;
+ UsbPort20Afe[1].Info.Predeemp = 3;
+ UsbPort20Afe[1].Info.Pehalfbit = 0;
+
+ UsbPort20Afe[2].Info.Petxiset = 6;
+ UsbPort20Afe[2].Info.Txiset = 0;
+ UsbPort20Afe[2].Info.Predeemp = 3;
+ UsbPort20Afe[2].Info.Pehalfbit = 0;
+
+ UsbPort20Afe[3].Info.Petxiset = 6;
+ UsbPort20Afe[3].Info.Txiset = 0;
+ UsbPort20Afe[3].Info.Predeemp = 3;
+ UsbPort20Afe[3].Info.Pehalfbit = 0;
+
+ UsbPort20Afe[4].Info.Petxiset = 6;
+ UsbPort20Afe[4].Info.Txiset = 0;
+ UsbPort20Afe[4].Info.Predeemp = 3;
+ UsbPort20Afe[4].Info.Pehalfbit = 0;
+
+ UsbPort20Afe[5].Info.Petxiset = 6;
+ UsbPort20Afe[5].Info.Txiset = 0;
+ UsbPort20Afe[5].Info.Predeemp = 3;
+ UsbPort20Afe[5].Info.Pehalfbit = 0;
+
+ UsbPort20Afe[6].Info.Petxiset = 6;
+ UsbPort20Afe[6].Info.Txiset = 0;
+ UsbPort20Afe[6].Info.Predeemp = 3;
+ UsbPort20Afe[6].Info.Pehalfbit = 0;
+
+ UsbPort20Afe[7].Info.Petxiset = 6;
+ UsbPort20Afe[7].Info.Txiset = 0;
+ UsbPort20Afe[7].Info.Predeemp = 3;
+ UsbPort20Afe[7].Info.Pehalfbit = 0;
+
+ UsbPort20Afe[8].Info.Petxiset = 6;
+ UsbPort20Afe[8].Info.Txiset = 0;
+ UsbPort20Afe[8].Info.Predeemp = 3;
+ UsbPort20Afe[8].Info.Pehalfbit = 0;
+
+ UsbPort20Afe[9].Info.Petxiset = 6;
+ UsbPort20Afe[9].Info.Txiset = 0;
+ UsbPort20Afe[9].Info.Predeemp = 3;
+ UsbPort20Afe[9].Info.Pehalfbit = 0;
+ break;
+ }
+
+ //
+ // Save USB2.0 AFE blobs
+ //
+ PcdSet32S (PcdUsb20Port0Afe, UsbPort20Afe[ 0].Blob);
+ PcdSet32S (PcdUsb20Port1Afe, UsbPort20Afe[ 1].Blob);
+ PcdSet32S (PcdUsb20Port2Afe, UsbPort20Afe[ 2].Blob);
+ PcdSet32S (PcdUsb20Port3Afe, UsbPort20Afe[ 3].Blob);
+ PcdSet32S (PcdUsb20Port4Afe, UsbPort20Afe[ 4].Blob);
+ PcdSet32S (PcdUsb20Port5Afe, UsbPort20Afe[ 5].Blob);
+ PcdSet32S (PcdUsb20Port6Afe, UsbPort20Afe[ 6].Blob);
+ PcdSet32S (PcdUsb20Port7Afe, UsbPort20Afe[ 7].Blob);
+ PcdSet32S (PcdUsb20Port8Afe, UsbPort20Afe[ 8].Blob);
+ PcdSet32S (PcdUsb20Port9Afe, UsbPort20Afe[ 9].Blob);
+ PcdSet32S (PcdUsb20Port10Afe, UsbPort20Afe[10].Blob);
+ PcdSet32S (PcdUsb20Port11Afe, UsbPort20Afe[11].Blob);
+ PcdSet32S (PcdUsb20Port12Afe, UsbPort20Afe[12].Blob);
+ PcdSet32S (PcdUsb20Port13Afe, UsbPort20Afe[13].Blob);
+ PcdSet32S (PcdUsb20Port14Afe, UsbPort20Afe[14].Blob);
+ PcdSet32S (PcdUsb20Port15Afe, UsbPort20Afe[15].Blob);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Board GPIO Group Tier configuration init function for PEI pre-memory phase.
+
+ @param[in] BoardId An unsigned integrer represent the board id.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+GpioGroupTierInit (
+ IN UINT16 BoardId
+ )
+{
+ //
+ // GPIO Group Tier
+ //
+ switch (BoardId) {
+ case BoardIdUpXtreme:
+ PcdSet32S (PcdGpioGroupToGpeDw0, GPIO_CNL_LP_GROUP_GPP_G);
+ PcdSet32S (PcdGpioGroupToGpeDw1, GPIO_CNL_LP_GROUP_SPI);
+ PcdSet32S (PcdGpioGroupToGpeDw2, GPIO_CNL_LP_GROUP_GPP_E);
+ break;
+
+ default:
+ PcdSet32S (PcdGpioGroupToGpeDw0, 0);
+ PcdSet32S (PcdGpioGroupToGpeDw1, 0);
+ PcdSet32S (PcdGpioGroupToGpeDw2, 0);
+ break;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ GPIO init function for PEI pre-memory phase.
+
+ @param[in] BoardId An unsigned integrer represent the board id.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+GpioTablePreMemInit (
+ IN UINT16 BoardId
+ )
+{
+ return EFI_SUCCESS;
+}
+
+/**
+ PmConfig init function for PEI pre-memory phase.
+
+ @param[in] BoardId An unsigned integrer represent the board id.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+PchPmConfigInit (
+ IN UINT16 BoardId
+ )
+{
+ //
+ // Update PmCofig policy: output voltage of VCCPRIMCORE RAIL when SLP_S0# is asserted based on board HW design
+ // 1) Discete VR or Non Premium PMIC: 0.75V (PcdSlpS0Vm075VSupport)
+ // 2) Premium PMIC: runtime control for voltage (PcdSlpS0VmRuntimeControl)
+ // Only applys to board with PCH-LP. Board with Discrete PCH doesn't need this setting.
+ //
+ switch (BoardId) {
+ case BoardIdUpXtreme:
+ PcdSetBoolS (PcdSlpS0VmRuntimeControl, FALSE);
+ PcdSetBoolS (PcdSlpS0Vm070VSupport, FALSE);
+ PcdSetBoolS (PcdSlpS0Vm075VSupport, FALSE);
+ break;
+ }
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/BoardSaConfigPreMem.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/BoardSaConfigPreMem.h
new file mode 100644
index 0000000000..e0ca397139
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/BoardSaConfigPreMem.h
@@ -0,0 +1,79 @@
+/** @file
+ PEI Boards Configurations for PreMem phase.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _BOARD_SA_CONFIG_PRE_MEM_H_
+#define _BOARD_SA_CONFIG_PRE_MEM_H_
+
+#include <ConfigBlock.h>
+#include <ConfigBlock/MemoryConfig.h> // for MRC Configuration
+#include <ConfigBlock/SwitchableGraphicsConfig.h> // for PCIE RTD3 GPIO
+#include <GpioPinsCnlLp.h> // for GPIO definition
+#include <GpioPinsCnlH.h>
+#include <SaAccess.h> // for Root Port number
+#include <PchAccess.h> // for Root Port number
+
+//
+// The following section contains board-specific CMD/CTL/CLK and DQ/DQS mapping, needed for LPDDR3/LPDDR4
+//
+
+//
+// DQByteMap[0] - ClkDQByteMap:
+// If clock is per rank, program to [0xFF, 0xFF]
+// If clock is shared by 2 ranks, program to [0xFF, 0] or [0, 0xFF]
+// If clock is shared by 2 ranks but does not go to all bytes,
+// Entry[i] defines which DQ bytes Group i services
+// DQByteMap[1] - CmdNDQByteMap: Entry[0] is CmdN/CAA and Entry[1] is CmdN/CAB
+// DQByteMap[2] - CmdSDQByteMap: Entry[0] is CmdS/CAA and Entry[1] is CmdS/CAB
+// DQByteMap[3] - CkeDQByteMap : Entry[0] is CKE /CAA and Entry[1] is CKE /CAB
+// For DDR, DQByteMap[3:1] = [0xFF, 0]
+// DQByteMap[4] - CtlDQByteMap : Always program to [0xFF, 0] since we have 1 CTL / rank
+// Variable only exists to make the code easier to use
+// DQByteMap[5] - CmdVDQByteMap: Always program to [0xFF, 0] since we have 1 CA Vref
+// Variable only exists to make the code easier to use
+//
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mDqByteMapUpXtreme[2][6][2] = {
+ // Channel 0:
+ {
+ { 0x0F, 0xF0 }, // CLK0 goes to package 0 - Bytes[3:0], CLK1 goes to package 1 - Bytes[7:4]
+ { 0x00, 0xF0 }, // CmdN does not have CAA, CAB goes to Bytes[7:4]
+ { 0x0F, 0xF0 }, // CmdS CAA goes to Bytes[3:0], CmdS CAB goes to Byte[7:4]
+ { 0x0F, 0x00 }, // CKE CAA goes to Bytes[3:0], CKE does not have CAB
+ { 0xFF, 0x00 }, // CTL (CS) goes to all bytes
+ { 0xFF, 0x00 } // CA Vref is one for all bytes
+ },
+ // Channel 1:
+ {
+ { 0x33, 0xCC }, // CLK0 goes to package 0 - Bytes[3:0], CLK1 goes to package 1 - Bytes[7:4]
+ { 0x00, 0xCC }, // CmdN does not have CAA, CAB goes to Bytes[7:4]
+ { 0x33, 0xCC }, // CmdS CAA goes to Bytes[3:0], CmdS CAB goes to Byte[7:4]
+ { 0x33, 0x00 }, // CKE CAA goes to Bytes[3:0], CKE does not have CAB
+ { 0xFF, 0x00 }, // CTL (CS) goes to all bytes
+ { 0xFF, 0x00 } // CA Vref is one for all bytes
+ }
+};
+
+//
+// DQS byte swizzling between CPU and DRAM
+//
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mDqsMapCpu2DramUpXtreme[2][8] = {
+ { 0, 1, 3, 2, 4, 5, 6, 7 }, // Channel 0
+ { 1, 0, 4, 5, 2, 3, 6, 7 } // Channel 1
+};
+
+//
+// Reference RCOMP resistors on motherboard
+//
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompResistorUpXtreme[SA_MRC_MAX_RCOMP] = { 121, 75, 100 };
+
+//
+// RCOMP target values for RdOdt, WrDS, WrDSCmd, WrDSCtl, WrDSClk
+//
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompTargetUpXtreme[SA_MRC_MAX_RCOMP_TARGETS] = { 60, 26, 20, 20, 26 };
+
+#endif // _BOARD_SA_CONFIG_PRE_MEM_H_
+
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/BoardSaInitPreMemLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/BoardSaInitPreMemLib.c
new file mode 100644
index 0000000000..df57c83e1d
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/BoardSaInitPreMemLib.c
@@ -0,0 +1,298 @@
+/** @file
+ Source code for the board SA configuration Pcd init functions in Pre-Memory init phase.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "BoardSaConfigPreMem.h"
+#include "SaPolicyCommon.h"
+#include "UpXtremeInit.h"
+#include <PlatformBoardConfig.h>
+#include <Library/CpuPlatformLib.h>
+
+//
+// Display DDI settings for UP Xtreme
+//
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mUpXtremeRowDisplayDdiConfig[9] = {
+ DdiPortAEdp, // DDI Port A Config : DdiPortADisabled = Disabled, DdiPortAEdp = eDP, DdiPortAMipiDsi = MIPI DSI
+ DdiHpdEnable, // DDI Port B HPD : DdiHpdDisable = Disable, DdiHpdEnable = Enable HPD
+ DdiHpdEnable, // DDI Port C HPD : DdiHpdDisable = Disable, DdiHpdEnable = Enable HPD
+ DdiHpdEnable, // DDI Port D HPD : DdiHpdDisable = Disable, DdiHpdEnable = Enable HPD
+ DdiHpdEnable, // DDI Port F HPD : DdiHpdDisable = Disable, DdiHpdEnable = Enable HPD
+ DdiDdcEnable, // DDI Port B DDC : DdiDisable = Disable, DdiDdcEnable = Enable DDC
+ DdiDdcEnable, // DDI Port C DDC : DdiDisable = Disable, DdiDdcEnable = Enable DDC
+ DdiDdcEnable, // DDI Port D DDC : DdiDisable = Disable, DdiDdcEnable = Enable DDC
+ DdiDisable // DDI Port F DDC : DdiDisable = Disable, DdiDdcEnable = Enable DDC
+};
+
+/**
+ MRC configuration init function for PEI pre-memory phase.
+
+ @param[in] BoardId An unsigned integer represent the board id.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+SaMiscConfigInit (
+ IN UINT16 BoardId
+ )
+{
+ //
+ // UserBd
+ //
+ switch (BoardId) {
+ case BoardIdUpXtreme:
+ //
+ // Assign UserBd to 5 which is assigned to MrcInputs->BoardType btUser4 for ULT platforms.
+ // This is required to skip Memory voltage programming based on GPIO's in MRC
+ //
+ PcdSet8S (PcdSaMiscUserBd, 5); // MrcBoardType btUser4 for UP Xtreme (ULT/ULX/Modile Halo)
+ break;
+
+ default:
+ // MiscPeiPreMemConfig.UserBd = 0 by default.
+ break;
+ }
+
+ PcdSet16S (PcdSaDdrFreqLimit, 0);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Board Memory Init related configuration init function for PEI pre-memory phase.
+
+ @param[in] BoardId An unsigned integrer represent the board id.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+MrcConfigInit (
+ IN UINT16 BoardId
+ )
+{
+ CPU_FAMILY CpuFamilyId;
+ UINT8 BomId;
+
+ CpuFamilyId = GetCpuFamily();
+
+ if (CpuFamilyId == EnumCpuCflDtHalo) {
+ PcdSetBoolS (PcdDualDimmPerChannelBoardType, TRUE);
+ } else {
+ PcdSetBoolS (PcdDualDimmPerChannelBoardType, FALSE);
+ }
+
+ //
+ // Example policy for DIMM slots implementation boards:
+ // 1. Assign Smbus address of DIMMs and SpdData will be updated later
+ // by reading from DIMM SPD.
+ // 2. No need to apply hardcoded SpdData buffers here for such board.
+ //
+ // Whiskey Lake U RVP has removable DIMM slots.
+ // So assign all Smbus address of DIMMs and leave PcdMrcSpdData set to 0.
+ // Example:
+ // PcdMrcSpdData = 0
+ // PcdMrcSpdDataSize = 0
+ // PcdMrcSpdAddressTable0 = 0xA0
+ // PcdMrcSpdAddressTable1 = 0xA2
+ // PcdMrcSpdAddressTable2 = 0xA4
+ // PcdMrcSpdAddressTable3 = 0xA6
+ //
+ // If a board has soldered down memory. It should use the following settings.
+ // Example:
+ // PcdMrcSpdAddressTable0 = 0
+ // PcdMrcSpdAddressTable1 = 0
+ // PcdMrcSpdAddressTable2 = 0
+ // PcdMrcSpdAddressTable3 = 0
+ // PcdMrcSpdData = static data buffer
+ // PcdMrcSpdDataSize = sizeof (static data buffer)
+ //
+
+ //
+ // SPD Address Table
+ //
+
+ // BOMID [1:0]
+ // 0: 16G A & B CH
+ // 1: 8G A CH
+ // 2: 8G A & B CH
+ // 3: 4G A CH
+ BomId = PcdGet8(PcdBoardBomId);
+ DEBUG ((DEBUG_INFO, "Up Xtreme Bom ID 0x%x\n",BomId));
+
+ if ((BomId & BIT1) == BIT1) {
+ PcdSet32S (PcdMrcSpdData, (UINTN) mUpXtremeSamsungDdr4Spd);
+ PcdSet16S (PcdMrcSpdDataSize, mUpXtremeSamsungDdr4SpdSize);
+ DEBUG ((DEBUG_INFO, "Using Xtreme SPD Samsung Ddr4\n"));
+ } else {
+ PcdSet32S (PcdMrcSpdData, (UINTN) mUpXtremeSkhynixDdr4Spd);
+ PcdSet16S (PcdMrcSpdDataSize, mUpXtremeSkhynixDdr4SpdSize);
+ DEBUG ((DEBUG_INFO, "Using Xtreme SPD Skhynix Ddr4\n"));
+ }
+
+ PcdSet8S (PcdMrcSpdAddressTable0, 0);
+ PcdSet8S (PcdMrcSpdAddressTable1, 0);
+ PcdSet8S (PcdMrcSpdAddressTable2, 0);
+ PcdSet8S (PcdMrcSpdAddressTable3, 0);
+
+ //
+ // DRAM SPD Data & related configuration
+ //
+ PcdSet32S (PcdMrcDqByteMap, (UINTN) mDqByteMapUpXtreme);
+ PcdSet16S (PcdMrcDqByteMapSize, sizeof (mDqByteMapUpXtreme));
+ PcdSet32S (PcdMrcDqsMapCpu2Dram, (UINTN) mDqsMapCpu2DramUpXtreme);
+ PcdSet16S (PcdMrcDqsMapCpu2DramSize, sizeof (mDqsMapCpu2DramUpXtreme));
+
+ switch (BoardId) {
+
+ case BoardIdUpXtreme:
+ PcdSet32S (PcdMrcRcompResistor, (UINTN) RcompResistorUpXtreme);
+ PcdSet32S (PcdMrcRcompTarget, (UINTN) RcompTargetUpXtreme);
+ PcdSetBoolS (PcdMrcDqPinsInterleavedControl, FALSE);
+ PcdSetBoolS (PcdMrcDqPinsInterleaved, FALSE);
+ break;
+
+ default:
+ break;
+ }
+
+ //
+ // CA Vref routing: board-dependent
+ // 0 - VREF_CA goes to both CH_A and CH_B (LPDDR3/DDR3L)
+ // 1 - VREF_CA to CH_A, VREF_DQ_A to CH_B (should not be used)
+ // 2 - VREF_CA to CH_A, VREF_DQ_B to CH_B (DDR4)
+ //
+ switch (BoardId) {
+ case BoardIdUpXtreme:
+ PcdSet8S (PcdMrcCaVrefConfig, 2); // DDR4 boards
+ break;
+
+ default:
+ PcdSet8S (PcdMrcCaVrefConfig, 0); // All DDR3L/LPDDR3/LPDDR4 boards
+ break;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Board SA related GPIO configuration init function for PEI pre-memory phase.
+
+ @param[in] BoardId An unsigned integer represent the board id.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+SaGpioConfigInit (
+ IN UINT16 BoardId
+ )
+{
+ //
+ // Update board's GPIO for PEG slot reset
+ //
+ PcdSetBoolS (PcdPegGpioResetControl, TRUE);
+ PcdSetBoolS (PcdPegGpioResetSupoort, FALSE);
+ PcdSet32S (PcdPeg0ResetGpioPad, 0);
+ PcdSetBoolS (PcdPeg0ResetGpioActive, FALSE);
+ PcdSet32S (PcdPeg3ResetGpioPad, 0);
+ PcdSetBoolS (PcdPeg3ResetGpioActive, FALSE);
+
+ //
+ // PCIE RTD3 GPIO
+ //
+ switch (BoardId) {
+ // todo for UP Xtreme
+ case BoardIdWhiskeyLakeRvp:
+ PcdSet8S(PcdRootPortIndex, 4);
+ PcdSet8S (PcdPcie0GpioSupport, PchGpio);
+ PcdSet32S (PcdPcie0WakeGpioNo, 0);
+ PcdSet8S (PcdPcie0HoldRstExpanderNo, 0);
+ PcdSet32S (PcdPcie0HoldRstGpioNo, GPIO_CNL_LP_GPP_C15);
+ PcdSetBoolS (PcdPcie0HoldRstActive, FALSE);
+ PcdSet8S (PcdPcie0PwrEnableExpanderNo, 0);
+ PcdSet32S (PcdPcie0PwrEnableGpioNo, GPIO_CNL_LP_GPP_C14);
+ PcdSetBoolS (PcdPcie0PwrEnableActive, FALSE);
+
+ PcdSet8S (PcdPcie1GpioSupport, NotSupported);
+ PcdSet32S (PcdPcie1WakeGpioNo, 0);
+ PcdSet8S (PcdPcie1HoldRstExpanderNo, 0);
+ PcdSet32S (PcdPcie1HoldRstGpioNo, 0);
+ PcdSetBoolS (PcdPcie1HoldRstActive, FALSE);
+ PcdSet8S (PcdPcie1PwrEnableExpanderNo, 0);
+ PcdSet32S (PcdPcie1PwrEnableGpioNo, 0);
+ PcdSetBoolS (PcdPcie1PwrEnableActive, FALSE);
+
+ PcdSet8S (PcdPcie2GpioSupport, NotSupported);
+ PcdSet32S (PcdPcie2WakeGpioNo, 0);
+ PcdSet8S (PcdPcie2HoldRstExpanderNo, 0);
+ PcdSet32S (PcdPcie2HoldRstGpioNo, 0);
+ PcdSetBoolS (PcdPcie2HoldRstActive, FALSE);
+ PcdSet8S (PcdPcie2PwrEnableExpanderNo, 0);
+ PcdSet32S (PcdPcie2PwrEnableGpioNo, 0);
+ PcdSetBoolS (PcdPcie2PwrEnableActive, FALSE);
+ break;
+
+ default:
+ PcdSet8S(PcdRootPortIndex, 0xFF);
+ PcdSet8S (PcdPcie0GpioSupport, NotSupported);
+ PcdSet32S (PcdPcie0WakeGpioNo, 0);
+ PcdSet8S (PcdPcie0HoldRstExpanderNo, 0);
+ PcdSet32S (PcdPcie0HoldRstGpioNo, 0);
+ PcdSetBoolS (PcdPcie0HoldRstActive, FALSE);
+ PcdSet8S (PcdPcie0PwrEnableExpanderNo, 0);
+ PcdSet32S (PcdPcie0PwrEnableGpioNo, 0);
+ PcdSetBoolS (PcdPcie0PwrEnableActive, FALSE);
+
+ PcdSet8S (PcdPcie1GpioSupport, NotSupported);
+ PcdSet32S (PcdPcie1WakeGpioNo, 0);
+ PcdSet8S (PcdPcie1HoldRstExpanderNo, 0);
+ PcdSet32S (PcdPcie1HoldRstGpioNo, 0);
+ PcdSetBoolS (PcdPcie1HoldRstActive, FALSE);
+ PcdSet8S (PcdPcie1PwrEnableExpanderNo, 0);
+ PcdSet32S (PcdPcie1PwrEnableGpioNo, 0);
+ PcdSetBoolS (PcdPcie1PwrEnableActive, FALSE);
+
+ PcdSet8S (PcdPcie2GpioSupport, NotSupported);
+ PcdSet32S (PcdPcie2WakeGpioNo, 0);
+ PcdSet8S (PcdPcie2HoldRstExpanderNo, 0);
+ PcdSet32S (PcdPcie2HoldRstGpioNo, 0);
+ PcdSetBoolS (PcdPcie2HoldRstActive, FALSE);
+ PcdSet8S (PcdPcie2PwrEnableExpanderNo, 0);
+ PcdSet32S (PcdPcie2PwrEnableGpioNo, 0);
+ PcdSetBoolS (PcdPcie2PwrEnableActive, FALSE);
+ break;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ SA Display DDI configuration init function for PEI pre-memory phase.
+
+ @param[in] BoardId An unsigned integer represent the board id.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+SaDisplayConfigInit (
+ IN UINT16 BoardId
+ )
+{
+ //
+ // Update Display DDI Config
+ //
+ switch (BoardId) {
+ case BoardIdUpXtreme:
+ PcdSet32S (PcdSaDisplayConfigTable, (UINTN) mUpXtremeRowDisplayDdiConfig);
+ PcdSet16S (PcdSaDisplayConfigTableSize, sizeof (mUpXtremeRowDisplayDdiConfig));
+ break;
+
+ default:
+ break;
+ }
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/GpioTableDefault.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/GpioTableDefault.c
new file mode 100644
index 0000000000..9cc8b50023
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/GpioTableDefault.c
@@ -0,0 +1,213 @@
+/** @file
+ GPIO definition table
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <GpioPinsCnlLp.h>
+#include <Library/GpioLib.h>
+#include <GpioConfig.h>
+
+#define END_OF_GPIO_TABLE 0xFFFFFFFF
+
+//
+// CNL U DRR4 Board GPIO table configuration is used as default
+//
+GPIO_INIT_CONFIG mGpioTableDefault[] =
+{
+// Pmode, GPI_IS, GpioDir, GPIOTxState, RxEvCfg, GPIRoutConfig, PadRstCfg, Term,
+ //{GPIO_CNL_LP_GPP_A0, { GpioPadModeNotUsed, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }},
+ //{GPIO_CNL_LP_GPP_A1, { GpioPadModeNative2, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //eSPI_IO_0
+ //{GPIO_CNL_LP_GPP_A2, { GpioPadModeNative2, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //eSPI_IO_1
+ //{GPIO_CNL_LP_GPP_A3, { GpioPadModeNative2, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //eSPI_IO_2
+ //{GPIO_CNL_LP_GPP_A4, { GpioPadModeNative2, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //eSPI_IO_2
+ //{GPIO_CNL_LP_GPP_A5, { GpioPadModeNative2, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //eSPI_CSB
+ //{GPIO_CNL_LP_GPP_A6, { GpioPadModeNotUsed, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //GPPC_A6_SERIRQ
+ {GPIO_CNL_LP_GPP_A7, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, GpioOutDefault, GpioIntEdge | GpioIntSci, GpioHostDeepReset, GpioTermWpu20K, GpioPadConfigUnlock }}, //SPI_TPM_INT_N
+ //{GPIO_CNL_LP_GPP_A8, { GpioPadModeNotUsed, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }},
+ //(Default HW) {GPIO_CNL_LP_GPP_A9, { GpioPadModeNative2, GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //eSPI_CLK
+ //{GPIO_CNL_LP_GPP_A10, { GpioPadModeNotUsed, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }},
+ {GPIO_CNL_LP_GPP_A11, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel|GpioIntSci, GpioHostDeepReset, GpioTermWpu20K, GpioPadConfigUnlock }}, //WWAN_WAKE_N
+ // (RC control) {GPIO_CNL_LP_GPP_A12, { GpioPadModeNative2, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //SLATEMODE_HALLOUT
+ {GPIO_CNL_LP_GPP_A13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone } }, //DGPU_SEL_SLOT1
+ //(Default HW) {GPIO_CNL_LP_GPP_A14, { GpioPadModeNative2, GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //eSPI_Reset
+ {GPIO_CNL_LP_GPP_A15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //SPKR_PD_N
+ {GPIO_CNL_LP_GPP_A16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //WFCAM_PWREN
+ //(RC control) {GPIO_CNL_LP_GPP_A17, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //SD_PWREN
+ //(RC control) {GPIO_CNL_LP_GPP_A18, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermWpu20K }}, //ACCEL_INT
+ //(RC control) {GPIO_CNL_LP_GPP_A19, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermWpu20K }}, //ALS_INT
+ //(RC control) {GPIO_CNL_LP_GPP_A20, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermWpu20K }}, //HUMAN_PRESENCE_INT
+ //(RC control) {GPIO_CNL_LP_GPP_A21, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermWpu20K }}, //HALL_SENSOR_INT
+ //(RC control) {GPIO_CNL_LP_GPP_A22, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //IVCAM_WAKE
+ //(RC control) {GPIO_CNL_LP_GPP_A23, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermWpu20K }}, //SHARED_INT
+ //(Not used) {GPIO_CNL_LP_GPP_B0, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDefault, GpioTermNone }}, //CORE_VID0
+ //(Not used) {GPIO_CNL_LP_GPP_B1, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDefault, GpioTermNone }}, //CORE_VID0
+ {GPIO_CNL_LP_GPP_B2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone, GpioPadConfigUnlock | GpioOutputStateUnlock } }, //BT_UART_WAKE
+ {GPIO_CNL_LP_GPP_B3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioPlatformReset, GpioTermNone, GpioPadConfigUnlock | GpioOutputStateUnlock }}, //FORCE_PAD_INT
+ {GPIO_CNL_LP_GPP_B4, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone , GpioPadConfigUnlock} }, //BT_DISABLE_N
+ //(RC control) {GPIO_CNL_LP_GPP_B5, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //WWAN_CLK_REQ
+ //(RC control) {GPIO_CNL_LP_GPP_B6, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //PCIE_NAND_CLK_REQ
+ //(RC control) {GPIO_CNL_LP_GPP_B7, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //LAN_CLK_REQ
+ //(RC control) {GPIO_CNL_LP_GPP_B8, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //WLAN_CLK_REQ
+ //(RC control) {GPIO_CNL_LP_GPP_B9, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //PCIE_SLOT1_CLK_REQ
+ //(RC control) {GPIO_CNL_LP_GPP_B10, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //PCIE_SLOT2_CLK_REQ
+ {GPIO_CNL_LP_GPP_B11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone }},
+ //(Default HW) {GPIO_CNL_LP_GPP_B12, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //PM_SLP_S0_N
+ //(Default HW) {GPIO_CNL_LP_GPP_B13, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //PLT_RST_N
+ {GPIO_CNL_LP_GPP_B14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //TCH_PNL_PWR_EN
+ //(CSME Pad) {GPIO_CNL_LP_GPP_B15, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone }}, //NFC_DFU
+ { GPIO_CNL_LP_GPP_B16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioPlatformReset, GpioTermNone, GpioPadConfigUnlock } }, //FPS_INT_N
+ { GPIO_CNL_LP_GPP_B17, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone, GpioPadConfigUnlock} }, //FPS_RESET_N
+ {GPIO_CNL_LP_GPP_B18, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone }}, //TBT_CIO_PWR_EN
+ //(RC control) {GPIO_CNL_LP_GPP_B19, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GSPI1_CS_FPS
+ //(RC control) {GPIO_CNL_LP_GPP_B20, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GSPI1_CLK_FPS
+ //(RC control) {GPIO_CNL_LP_GPP_B21, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GSPI1_MISO_FPS
+ //(RC control) {GPIO_CNL_LP_GPP_B22, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GSPI1_MOSI_FPS
+ {GPIO_CNL_LP_GPP_B23, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioHostDeepReset, GpioTermNone}}, //EC_SLP_S0_CS_N
+ //(RC control) {GPIO_CNL_LP_GPP_C0, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //SMB_CLK
+ //(RC control) {GPIO_CNL_LP_GPP_C1, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //SMB_DATA
+ {GPIO_CNL_LP_GPP_C2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone }}, //WIFI_RF_KILL_N
+ //(CSME Pad) {GPIO_CNL_LP_GPP_C3, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //SML0_CLK
+ //(CSME Pad) {GPIO_CNL_LP_GPP_C4, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //SML0_DATA
+ {GPIO_CNL_LP_GPP_C5, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioHostDeepReset, GpioTermNone, GpioPadConfigUnlock }}, //WIFI_WAKE_N
+ //(Not used) {GPIO_CNL_LP_GPP_C6, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }},
+ //(Not used) {GPIO_CNL_LP_GPP_C7, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }},
+ { GPIO_CNL_LP_GPP_C8, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermWpu20K } }, //CODEC_INT_N
+ { GPIO_CNL_LP_GPP_C9, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntEdge | GpioIntSci, GpioPlatformReset, GpioTermWpu20K, GpioPadConfigUnlock }}, //TBT_CIO_PLUG_EVENT_N
+ {GPIO_CNL_LP_GPP_C10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDefault, GpioPlatformReset, GpioTermNone}}, //TBT_FORCE_PWR
+ {GPIO_CNL_LP_GPP_C11, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioHostDeepReset, GpioTermWpu20K, GpioPadConfigUnlock } }, //IVCAM_WAKE_N
+ {GPIO_CNL_LP_GPP_C12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //PCIE_NAND_RST_N
+ {GPIO_CNL_LP_GPP_C13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //PCIE_NAND_PWREN_N
+ {GPIO_CNL_LP_GPP_C14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //SLOT1_PWREN_N
+ {GPIO_CNL_LP_GPP_C15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //SLOT1_RST_N
+ //(RC control) {GPIO_CNL_LP_GPP_C16, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //I2C0_SDA
+ //(RC control) {GPIO_CNL_LP_GPP_C17, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //I2C0_SCL
+ //(RC control) {GPIO_CNL_LP_GPP_C18, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //I2C1_SDA
+ //(RC control) {GPIO_CNL_LP_GPP_C19, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //I2C1_SCL
+ //(RC control) {GPIO_CNL_LP_GPP_C20, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //UART2_RXD
+ //(RC control) {GPIO_CNL_LP_GPP_C21, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //UART2_TXD
+ //(RC control) {GPIO_CNL_LP_GPP_C22, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //UART2_RTS
+ //(RC control) {GPIO_CNL_LP_GPP_C23, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //UART2_CTS
+ //(CSME Pad) {GPIO_CNL_LP_GPP_D0, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //SPI1_TCH_PNL_CS0_N
+ //(CSME Pad) {GPIO_CNL_LP_GPP_D1, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //SPI1_TCH_PNL_CLK_N
+ //(CSME Pad) {GPIO_CNL_LP_GPP_D2, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //SPI1_TCH_PNL_MISO
+ //(CSME Pad) {GPIO_CNL_LP_GPP_D3, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //SPI1_TCH_PNL_MOSI
+ //(RC control) {GPIO_CNL_LP_GPP_D4, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //IMGCLKOUT
+ //(RC control) {GPIO_CNL_LP_GPP_D5, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //ISH_I2C0_SDA
+ //(RC control) {GPIO_CNL_LP_GPP_D6, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //ISH_I2C0_SCL
+ //(RC control) {GPIO_CNL_LP_GPP_D7, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //ISH_I2C1_SDA
+ //(RC control) {GPIO_CNL_LP_GPP_D8, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //ISH_I2C1_SCL
+ {GPIO_CNL_LP_GPP_D9, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone }}, //TCH_PNL2_RST_N
+ {GPIO_CNL_LP_GPP_D10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntEdge | GpioIntApic, GpioPlatformReset, GpioTermNone, GpioPadConfigUnlock }}, //TCH_PNL2_INT_N
+ {GPIO_CNL_LP_GPP_D11, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv , GpioOutDefault, GpioIntLevel| GpioIntSci, GpioPlatformReset, GpioTermWpu20K, GpioPadConfigUnlock }}, //SLOT1_WAKE_N
+ //(CSME Pad) {GPIO_CNL_LP_GPP_D12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //NFC_RST_N
+ {GPIO_CNL_LP_GPP_D13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDis, GpioResumeReset, GpioTermNone }}, //WWAN_PWREN
+ {GPIO_CNL_LP_GPP_D14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone }}, //TCH_PNL_RST_N
+ //(CSME Pad) {GPIO_CNL_LP_GPP_D15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel|GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //NFC_INT_N
+ {GPIO_CNL_LP_GPP_D16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel|GpioIntSci, GpioHostDeepReset, GpioTermNone, GpioPadConfigUnlock }}, //WIGIG_WAKE_N
+ //(RC control) {GPIO_CNL_LP_GPP_D17, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //DMIC_CLK_1
+ //(RC control) {GPIO_CNL_LP_GPP_D18, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //DMIC_DATA_1
+ //(RC control) {GPIO_CNL_LP_GPP_D19, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //DMIC_CLK_0
+ //(RC control) {GPIO_CNL_LP_GPP_D20, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //DMIC_DATA_0
+ {GPIO_CNL_LP_GPP_D21, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //SPI1_TCH_PNL_IO2
+ {GPIO_CNL_LP_GPP_D22, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //SPI1_TCH_PNL_IO3
+ //(RC control) {GPIO_CNL_LP_GPP_D23, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //SSP_MCLK
+ //(Not used) {GPIO_CNL_LP_GPP_E0, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel|GpioIntSci, GpioPlatformReset, GpioTermWpu20K }}, //Reserved for SATA/PCIE detect
+ //(RC control) {GPIO_CNL_LP_GPP_E1, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel|GpioIntSci, GpioPlatformReset, GpioTermNone }}, //M.2_SSD_DET
+ {GPIO_CNL_LP_GPP_E2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioPlatformReset, GpioTermWpu20K}}, //Reserved for SATA HP val
+ {GPIO_CNL_LP_GPP_E3, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, GpioOutDefault, GpioIntEdge|GpioIntSmi, GpioPlatformReset, GpioTermNone}}, //EC_SMI_N
+ {GPIO_CNL_LP_GPP_E4, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, GpioOutDefault, GpioIntLevel|GpioIntSci, GpioPlatformReset, GpioTermNone, GpioPadConfigUnlock }}, //DGPU_PWROK
+ //(RC control) {GPIO_CNL_LP_GPP_E5, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutDefault, GpioIntLevel|GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //SSD_DEVSLP
+ //(RC control) {GPIO_CNL_LP_GPP_E6, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutDefault, GpioIntLevel|GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //HDD_DEVSLP
+ {GPIO_CNL_LP_GPP_E7, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutDefault, GpioIntEdge|GpioIntDefault, GpioPlatformReset, GpioTermNone, GpioPadConfigUnlock }}, //TCH_PNL_INT_N
+ //(RC control) {GPIO_CNL_LP_GPP_E8, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //SATA_LED_N
+ //(RC control) {GPIO_CNL_LP_GPP_E9, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //BSSB_CLK
+ //(RC control) {GPIO_CNL_LP_GPP_E10, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //BSSB_DI
+ //(RC control) {GPIO_CNL_LP_GPP_E11, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //USB_OC_2
+ //(RC control) {GPIO_CNL_LP_GPP_E12, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //USB_OC_3
+ //(RC control) {GPIO_CNL_LP_GPP_E13, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //DDI1_HPD
+ //(RC control) {GPIO_CNL_LP_GPP_E14, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //DDI2_HPD_EC
+ //(RC control) {GPIO_CNL_LP_GPP_E15, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //DDI3_HPD
+ //(RC control) {GPIO_CNL_LP_GPP_E16, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //DDI4_HPD
+ //(RC control) {GPIO_CNL_LP_GPP_E17, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //EDP_HPD
+ //(RC control) {GPIO_CNL_LP_GPP_E18, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //DDI1_CTRL_CLK
+ //(RC control) {GPIO_CNL_LP_GPP_E19, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //DDI1_CTRL_DATA
+ //(RC control) {GPIO_CNL_LP_GPP_E20, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //DDI2_CTRL_CLK
+ //(RC control) {GPIO_CNL_LP_GPP_E21, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //DDI2_CTRL_DATA
+ //(RC control) {GPIO_CNL_LP_GPP_E22, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //DDI3_CTRL_CLK
+ //(RC control) {GPIO_CNL_LP_GPP_E23, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //DDI3_CTRL_DATA
+ //(Not used){GPIO_CNL_LP_GPP_F0, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GPP_F0_COEX3
+ {GPIO_CNL_LP_GPP_F1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermWpu20K }}, //WWAN_RST_N
+ {GPIO_CNL_LP_GPP_F2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //SATA_HDD_PWREN
+ {GPIO_CNL_LP_GPP_F3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //WF_CLK_EN
+ //(RC control) {GPIO_CNL_LP_GPP_F4, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //CNV_BRI_DT_UART0_RTSB
+ //(RC control) {GPIO_CNL_LP_GPP_F5, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //CNV_BRI_RSP_UART0_RXD
+ //(RC control) {GPIO_CNL_LP_GPP_F6, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //CNV_RGI_DT_UART0_TXD
+ //(RC control) {GPIO_CNL_LP_GPP_F7, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //CNV_RGI_RSP_UART0_CTSB
+ {GPIO_CNL_LP_GPP_F8, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //CNV_MFUART2_RXD
+ {GPIO_CNL_LP_GPP_F9, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //CNV_MFUART2_TXD
+
+ //Also need to assign same GPIO pin to PcdRecoveryModeGpio which will be used at IsRecoveryMode()
+ {GPIO_CNL_LP_GPP_F10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone}}, //BIOS_REC
+
+ //(RC control) {GPIO_CNL_LP_GPP_F11, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GPP_F11_EMMC_CMD
+ //(RC control) {GPIO_CNL_LP_GPP_F12, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GPP_F12_EMMC_DATA0
+ //(RC control) {GPIO_CNL_LP_GPP_F13, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GPP_F13_EMMC_DATA1
+ //(RC control) {GPIO_CNL_LP_GPP_F14, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GPP_F14_EMMC_DATA2
+ //(RC control) {GPIO_CNL_LP_GPP_F15, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GPP_F15_EMMC_DATA3
+ //(RC control) {GPIO_CNL_LP_GPP_F16, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GPP_F16_EMMC_DATA4
+ //(RC control) {GPIO_CNL_LP_GPP_F17, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GPP_F17_EMMC_DATA5
+ //(RC control) {GPIO_CNL_LP_GPP_F18, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GPP_F18_EMMC_DATA6
+ //(RC control) {GPIO_CNL_LP_GPP_F19, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GPP_F19_EMMC_DATA7
+ //(RC control) {GPIO_CNL_LP_GPP_F20, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GPP_F20_EMMC_RCLK
+ //(RC control) {GPIO_CNL_LP_GPP_F21, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GPP_F21_EMMC_CLK
+ //(RC control) {GPIO_CNL_LP_GPP_F22, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GPP_F22_EMMC_RESETB
+ //{GPIO_CNL_LP_GPP_F23, { GpioPadModeNotUsed, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //GPP_F_23
+ //(RC control) {GPIO_CNL_LP_GPP_G0, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNative }}, //GPP_G_0_SD3_CMD
+ //(RC control) {GPIO_CNL_LP_GPP_G1, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNative }}, //GPP_G_1_SD3_D0_SD4_RCLK_P
+ //(RC control) {GPIO_CNL_LP_GPP_G2, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNative }}, //GPP_G_2_SD3_D1_SD4_RCLK_N
+ //(RC control) {GPIO_CNL_LP_GPP_G3, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNative }}, //GPP_G_3_SD3_D2
+ //(RC control) {GPIO_CNL_LP_GPP_G4, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNative }}, //GPP_G_4_SD3_D3
+ {GPIO_CNL_LP_GPP_G5, { GpioHardwareDefault, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermWpu20K }}, //GPP_G_5_SD3_CDB
+ //(Default HW) {GPIO_CNL_LP_GPP_G6, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //GPP_G_6_SD3_CLK
+ {GPIO_CNL_LP_GPP_G7, { GpioHardwareDefault, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermWpd20K }}, //GPP_G_7_SD3_WP
+ //{GPIO_CNL_LP_GPP_H0, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //GPP_H_0_SSP2_SCLK
+ //{GPIO_CNL_LP_GPP_H1, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //GPP_H_1_SSP2_SFRM
+ //{GPIO_CNL_LP_GPP_H2, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //GPP_H_2_SSP2_TXD
+ //{GPIO_CNL_LP_GPP_H3, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermNone }}, //GPP_H_3_SSP2_RXD
+ //(RC control) {GPIO_CNL_LP_GPP_H4, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GPP_H_4_I2C2_SDA
+ //(RC control) {GPIO_CNL_LP_GPP_H5, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GPP_H_5_I2C2_SCL
+ //(RC control) {GPIO_CNL_LP_GPP_H6, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GPP_H_6_I2C3_SDA
+ //(RC control) {GPIO_CNL_LP_GPP_H7, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GPP_H_7_I2C3_SCL
+ //(RC control) {GPIO_CNL_LP_GPP_H8, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GPP_H_8_I2C4_SDA
+ //(RC control) {GPIO_CNL_LP_GPP_H9, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GPP_H_9_I2C4_SCL
+ {GPIO_CNL_LP_GPP_H10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //IVCAM_PWREN
+ {GPIO_CNL_LP_GPP_H11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //IVCAM_RECOVERY
+ {GPIO_CNL_LP_GPP_H12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //IRIS_STROBE
+ {GPIO_CNL_LP_GPP_H13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //IVCAM_MUX_SEL0
+ {GPIO_CNL_LP_GPP_H14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutLow, GpioIntDefault, GpioPlatformReset, GpioTermNone, GpioPadUnlock }}, //UF_CAM_PRIVACY_LED
+ {GPIO_CNL_LP_GPP_H15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //IVCAM_KEY
+ //(Not used) {GPIO_CNL_LP_GPP_H16, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //DDI4_CTRL_CLK
+ //(Not used) {GPIO_CNL_LP_GPP_H17, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //DDI4_CTRL_DATA
+ //(Default HW) {GPIO_CNL_LP_GPP_H18, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //VCCIO_LPM
+ {GPIO_CNL_LP_GPP_H19, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //IVCAM_MUX_SEL1
+ //(RC control) {GPIO_CNL_LP_GPP_H20, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //IMGCLKOUT_WF_CAM
+ //(Not used) {GPIO_CNL_LP_GPP_H21, { GpioPadModeNotUsed, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GPP_H21
+ {GPIO_CNL_LP_GPP_H22, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //WF_CAM_RST
+ //(Not used) {GPIO_CNL_LP_GPP_H23, { GpioPadModeNotUsed, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //GPP_H23
+ //(Default HW) {GPIO_CNL_LP_GPD0, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //PM_BATLOW_N
+ //(Default HW) {GPIO_CNL_LP_GPD1, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //BC_ACOK
+ //(Default HW) {GPIO_CNL_LP_GPD2, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //LAN_WAKE
+ //(Default HW) {GPIO_CNL_LP_GPD3, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //PM_PWRBTN_N
+ //(Default HW) {GPIO_CNL_LP_GPD4, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //PM_SLP_S3_N
+ //(Default HW) {GPIO_CNL_LP_GPD5, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //PM_SLP_S4_N
+ //(Default HW) {GPIO_CNL_LP_GPD6, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //SLP_A_N
+ //{GPIO_CNL_LP_GPD7, { GpioPadModeNotUsed, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //GPD_7
+ //(Default HW) {GPIO_CNL_LP_GPD8, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //SUS_CLK
+ //(Default HW) {GPIO_CNL_LP_GPD9, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //PM_SLP_WLAN_N
+ //(Default HW) {GPIO_CNL_LP_GPD10, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //PM_SLP_S5_N
+ //(Default HW) {GPIO_CNL_LP_GPD11, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //LANPHY_EN
+ {GPIO_CNL_LP_PECI, { GpioHardwareDefault, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermWpd20K }}, // 20K PD for PECI
+};
+UINT16 mGpioTableDefaultSize = sizeof (mGpioTableDefault) / sizeof (GPIO_INIT_CONFIG);
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/GpioTableUpXtreme.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/GpioTableUpXtreme.c
new file mode 100644
index 0000000000..4ce7e7450d
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/GpioTableUpXtreme.c
@@ -0,0 +1,217 @@
+/** @file
+ GPIO definition table for the UP Xtreme
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <GpioPinsCnlLp.h>
+#include <Library/GpioLib.h>
+#include <GpioConfig.h>
+
+GPIO_INIT_CONFIG mGpioTableUpXtreme[] =
+{
+ {GPIO_CNL_LP_GPP_A0, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ {GPIO_CNL_LP_GPP_A1, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNative }},
+ {GPIO_CNL_LP_GPP_A2, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNative }},
+ {GPIO_CNL_LP_GPP_A3, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNative }},
+ {GPIO_CNL_LP_GPP_A4, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNative }},
+ {GPIO_CNL_LP_GPP_A5, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ {GPIO_CNL_LP_GPP_A6, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ {GPIO_CNL_LP_GPP_A7, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ {GPIO_CNL_LP_GPP_A8, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ {GPIO_CNL_LP_GPP_A9, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermWpd20K }},
+ {GPIO_CNL_LP_GPP_A10, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermWpd20K }},
+ {GPIO_CNL_LP_GPP_A11, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ //(RC control) {GPIO_CNL_LP_GPP_A12, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ {GPIO_CNL_LP_GPP_A13, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ {GPIO_CNL_LP_GPP_A14, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ {GPIO_CNL_LP_GPP_A15, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ {GPIO_CNL_LP_GPP_A16, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioPlatformReset, GpioTermWpd20K }},
+ {GPIO_CNL_LP_GPP_A17, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ {GPIO_CNL_LP_GPP_A18, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ {GPIO_CNL_LP_GPP_A19, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ {GPIO_CNL_LP_GPP_A20, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioResumeReset, GpioTermWpu20K }},
+ {GPIO_CNL_LP_GPP_A21, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutHigh, GpioIntDefault | GpioIntEdge, GpioResumeReset, GpioTermWpu20K }},
+ {GPIO_CNL_LP_GPP_A22, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioResumeReset, GpioTermWpu20K }},
+ {GPIO_CNL_LP_GPP_A23, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutHigh, GpioIntDefault | GpioIntEdge, GpioResumeReset, GpioTermWpu20K }},
+
+ {GPIO_CNL_LP_GPP_B0, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ {GPIO_CNL_LP_GPP_B1, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ {GPIO_CNL_LP_GPP_B2, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ {GPIO_CNL_LP_GPP_B3, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ {GPIO_CNL_LP_GPP_B4, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ //(RC control) {GPIO_CNL_LP_GPP_B5, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ //(RC control) {GPIO_CNL_LP_GPP_B6, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ //(RC control) {GPIO_CNL_LP_GPP_B7, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ //(RC control) {GPIO_CNL_LP_GPP_B8, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ //(RC control) {GPIO_CNL_LP_GPP_B9, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ //(RC control) {GPIO_CNL_LP_GPP_B10, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ {GPIO_CNL_LP_GPP_B11, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ {GPIO_CNL_LP_GPP_B12, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ {GPIO_CNL_LP_GPP_B13, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ {GPIO_CNL_LP_GPP_B14, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ {GPIO_CNL_LP_GPP_B15, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ {GPIO_CNL_LP_GPP_B16, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ {GPIO_CNL_LP_GPP_B17, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ {GPIO_CNL_LP_GPP_B18, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ //(RC control) {GPIO_CNL_LP_GPP_B19, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ //(RC control) {GPIO_CNL_LP_GPP_B20, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ //(RC control) {GPIO_CNL_LP_GPP_B21, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ //(RC control) {GPIO_CNL_LP_GPP_B22, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ {GPIO_CNL_LP_GPP_B23, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+
+ //(RC control) {GPIO_CNL_LP_GPP_C0, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ //(RC control) {GPIO_CNL_LP_GPP_C1, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ {GPIO_CNL_LP_GPP_C2, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ //(CSME control) {GPIO_CNL_LP_GPP_C3, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ //(CSME control) {GPIO_CNL_LP_GPP_C4, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ {GPIO_CNL_LP_GPP_C5, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ {GPIO_CNL_LP_GPP_C6, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ {GPIO_CNL_LP_GPP_C7, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ {GPIO_CNL_LP_GPP_C8, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ {GPIO_CNL_LP_GPP_C9, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ {GPIO_CNL_LP_GPP_C10, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ {GPIO_CNL_LP_GPP_C11, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ {GPIO_CNL_LP_GPP_C12, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ {GPIO_CNL_LP_GPP_C13, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ {GPIO_CNL_LP_GPP_C14, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ {GPIO_CNL_LP_GPP_C15, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ //(RC control) {GPIO_CNL_LP_GPP_C16, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ //(RC control) {GPIO_CNL_LP_GPP_C17, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ //(RC control) {GPIO_CNL_LP_GPP_C18, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ //(RC control) {GPIO_CNL_LP_GPP_C19, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ //(RC control) {GPIO_CNL_LP_GPP_C20, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ //(RC control) {GPIO_CNL_LP_GPP_C21, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ //(RC control) {GPIO_CNL_LP_GPP_C22, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ //(RC control) {GPIO_CNL_LP_GPP_C23, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+
+ //(CSME control) {GPIO_CNL_LP_GPP_D0, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ //(CSME control) {GPIO_CNL_LP_GPP_D1, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirNone, GpioOutHigh, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ //(CSME control) {GPIO_CNL_LP_GPP_D2, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ //(CSME control) {GPIO_CNL_LP_GPP_D3, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ //(RC control) {GPIO_CNL_LP_GPP_D4, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutHigh, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermWpu20K }},
+ //(RC control) {GPIO_CNL_LP_GPP_D5, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ //(RC control) {GPIO_CNL_LP_GPP_D6, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ //(RC control) {GPIO_CNL_LP_GPP_D7, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ //(RC control) {GPIO_CNL_LP_GPP_D8, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ {GPIO_CNL_LP_GPP_D9, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ {GPIO_CNL_LP_GPP_D10, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ {GPIO_CNL_LP_GPP_D11, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ {GPIO_CNL_LP_GPP_D12, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ {GPIO_CNL_LP_GPP_D13, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutHigh, GpioIntDefault | GpioIntEdge, GpioResumeReset, GpioTermNone }},
+ {GPIO_CNL_LP_GPP_D14, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ {GPIO_CNL_LP_GPP_D15, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ {GPIO_CNL_LP_GPP_D16, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutHigh, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermWpu20K }},
+ //(RC control) {GPIO_CNL_LP_GPP_D17, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ //(RC control) {GPIO_CNL_LP_GPP_D18, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ //(RC control) {GPIO_CNL_LP_GPP_D19, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ //(RC control) {GPIO_CNL_LP_GPP_D20, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ //(CSME control) {GPIO_CNL_LP_GPP_D21, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ //(CSME control) {GPIO_CNL_LP_GPP_D22, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ //(RC control) {GPIO_CNL_LP_GPP_D23, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+
+ {GPIO_CNL_LP_GPP_E0, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }},
+ //(RC control) {GPIO_CNL_LP_GPP_E1, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //M.2_SSD_DET
+ {GPIO_CNL_LP_GPP_E2, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //Reserved for SATA HP val
+ {GPIO_CNL_LP_GPP_E3, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //EC_SMI_N
+ {GPIO_CNL_LP_GPP_E4, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //DGPU_PWROK
+ //(RC control) {GPIO_CNL_LP_GPP_E5, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //SSD_DEVSLP
+ //(RC control) {GPIO_CNL_LP_GPP_E6, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //HDD_DEVSLP
+ {GPIO_CNL_LP_GPP_E7, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //TCH_PNL_INT_N
+ //(RC control) {GPIO_CNL_LP_GPP_E8, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //SATA_LED_N
+ //(RC control) {GPIO_CNL_LP_GPP_E9, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //BSSB_CLK
+ //(RC control) {GPIO_CNL_LP_GPP_E10, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //BSSB_DI
+ //(RC control) {GPIO_CNL_LP_GPP_E11, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //USB_OC_2
+ //(RC control) {GPIO_CNL_LP_GPP_E12, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //USB_OC_3
+ //(RC control) {GPIO_CNL_LP_GPP_E13, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //DDI1_HPD
+ //(RC control) {GPIO_CNL_LP_GPP_E14, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //DDI2_HPD_EC
+ //(RC control) {GPIO_CNL_LP_GPP_E15, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutHigh, GpioIntDefault | GpioIntEdge, GpioPlatformReset, GpioTermNone }}, //DDI3_HPD
+ //(RC control) {GPIO_CNL_LP_GPP_E16, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //DDI4_HPD
+ //(RC control) {GPIO_CNL_LP_GPP_E17, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //EDP_HPD
+ //(RC control) {GPIO_CNL_LP_GPP_E18, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //DDI1_CTRL_CLK
+ //(RC control) {GPIO_CNL_LP_GPP_E19, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //DDI1_CTRL_DATA
+ //(RC control) {GPIO_CNL_LP_GPP_E20, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //DDI2_CTRL_CLK
+ //(RC control) {GPIO_CNL_LP_GPP_E21, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //DDI2_CTRL_DATA
+ //(RC control) {GPIO_CNL_LP_GPP_E22, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //DDI3_CTRL_CLK
+ //(RC control) {GPIO_CNL_LP_GPP_E23, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //DDI3_CTRL_DATA
+
+ {GPIO_CNL_LP_GPP_F0, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //GPP_F0_COEX3
+ {GPIO_CNL_LP_GPP_F1, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //WWAN_RST_N
+ {GPIO_CNL_LP_GPP_F2, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //SATA_HDD_PWREN
+ {GPIO_CNL_LP_GPP_F3, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //WF_CLK_EN
+ {GPIO_CNL_LP_GPP_F4, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //CNV_BRI_DT_UART0_RTSB
+ {GPIO_CNL_LP_GPP_F5, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //CNV_BRI_RSP_UART0_RXD
+ {GPIO_CNL_LP_GPP_F6, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //CNV_RGI_DT_UART0_TXD
+ {GPIO_CNL_LP_GPP_F7, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //CNV_RGI_RSP_UART0_CTSB
+ {GPIO_CNL_LP_GPP_F8, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //CNV_MFUART2_RXD
+ {GPIO_CNL_LP_GPP_F9, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //CNV_MFUART2_TXD
+ {GPIO_CNL_LP_GPP_F10, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //BIOS_REC
+
+ {GPIO_CNL_LP_GPP_F11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_CMD
+ {GPIO_CNL_LP_GPP_F12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA0
+ {GPIO_CNL_LP_GPP_F13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA1
+ {GPIO_CNL_LP_GPP_F14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA2
+ {GPIO_CNL_LP_GPP_F15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA3
+ {GPIO_CNL_LP_GPP_F16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA4
+ {GPIO_CNL_LP_GPP_F17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA5
+ {GPIO_CNL_LP_GPP_F18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA6
+ {GPIO_CNL_LP_GPP_F19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_DATA7
+ {GPIO_CNL_LP_GPP_F20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_RCLK
+ {GPIO_CNL_LP_GPP_F21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_CLK
+ {GPIO_CNL_LP_GPP_F22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}},//EMMC_RESETB
+
+ //(RC control) {GPIO_CNL_LP_GPP_F23, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //GPP_F_23
+
+ //(RC control) {GPIO_CNL_LP_GPP_G0, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //GPP_G_0_SD3_CMD
+ //(RC control) {GPIO_CNL_LP_GPP_G1, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //GPP_G_1_SD3_D0_SD4_RCLK_P
+ //(RC control) {GPIO_CNL_LP_GPP_G2, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //GPP_G_2_SD3_D1_SD4_RCLK_N
+ //(RC control) {GPIO_CNL_LP_GPP_G3, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //GPP_G_3_SD3_D2
+ //(RC control) {GPIO_CNL_LP_GPP_G4, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //GPP_G_4_SD3_D3
+ {GPIO_CNL_LP_GPP_G5, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //GPP_G_5_SD3_CDB
+ {GPIO_CNL_LP_GPP_G6, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //GPP_G_6_SD3_CLK
+ {GPIO_CNL_LP_GPP_G7, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //GPP_G_7_SD3_WP
+
+ //H0-H3 -> Under GPIO table for GPIO Termination -20K WPU
+ {GPIO_CNL_LP_GPP_H0, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //GPP_H_0_SSP2_SCLK
+ {GPIO_CNL_LP_GPP_H1, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //GPP_H_1_SSP2_SFRM
+ {GPIO_CNL_LP_GPP_H2, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //GPP_H_2_SSP2_TXD
+ {GPIO_CNL_LP_GPP_H3, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //GPP_H_3_SSP2_RXD
+ //(RC control) {GPIO_CNL_LP_GPP_H4, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirin, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //GPP_H_4_I2C2_SDA
+ //(RC control) {GPIO_CNL_LP_GPP_H5, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirin, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //GPP_H_5_I2C2_SCL
+ //(RC control) {GPIO_CNL_LP_GPP_H6, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //GPP_H_6_I2C3_SDA
+ //(RC control) {GPIO_CNL_LP_GPP_H7, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //GPP_H_7_I2C3_SCL
+ //(RC control) {GPIO_CNL_LP_GPP_H8, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //GPP_H_8_I2C4_SDA
+ //(RC control) {GPIO_CNL_LP_GPP_H9, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //GPP_H_9_I2C4_SCL
+ {GPIO_CNL_LP_GPP_H10, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutHigh, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //IVCAM_PWREN
+ {GPIO_CNL_LP_GPP_H11, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutHigh, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //IVCAM_RECOVERY
+ {GPIO_CNL_LP_GPP_H12, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //IRIS_STROBE
+ {GPIO_CNL_LP_GPP_H13, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //IVCAM_MUX_SEL0
+ {GPIO_CNL_LP_GPP_H14, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //UF_CAM_PRIVACY_LED
+ {GPIO_CNL_LP_GPP_H15, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //IVCAM_KEY
+ {GPIO_CNL_LP_GPP_H16, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutHigh, GpioIntDefault | GpioIntEdge, GpioResumeReset, GpioTermNone }}, //DDI4_CTRL_CLK
+ {GPIO_CNL_LP_GPP_H17, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutHigh, GpioIntDefault | GpioIntEdge, GpioResumeReset, GpioTermNone }}, //DDI4_CTRL_DATA
+ {GPIO_CNL_LP_GPP_H18, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirNone, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //VCCIO_LPM
+ {GPIO_CNL_LP_GPP_H19, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //IVCAM_MUX_SEL1
+ //(RC control) {GPIO_CNL_LP_GPP_H20, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //IMGCLKOUT_WF_CAM
+ {GPIO_CNL_LP_GPP_H21, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //GPP_H21
+ {GPIO_CNL_LP_GPP_H22, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //WF_CAM_RST
+ {GPIO_CNL_LP_GPP_H23, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDefault | GpioIntEdge, GpioHostDeepReset, GpioTermNone }}, //GPP_H23
+
+ //(Default HW) {GPIO_CNL_LP_GPD0, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //PM_BATLOW_N
+ //(Default HW) {GPIO_CNL_LP_GPD1, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //BC_ACOK
+ //(Default HW) {GPIO_CNL_LP_GPD2, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //LAN_WAKE
+ //(Default HW) {GPIO_CNL_LP_GPD3, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //PM_PWRBTN_N
+ //(Default HW) {GPIO_CNL_LP_GPD4, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //PM_SLP_S3_N
+ //(Default HW) {GPIO_CNL_LP_GPD5, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //PM_SLP_S4_N
+ //(Default HW) {GPIO_CNL_LP_GPD6, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //SLP_A_N
+ //{GPIO_CNL_LP_GPD7, { GpioPadModeNotUsed, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //GPD_7
+ //(Default HW) {GPIO_CNL_LP_GPD8, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //SUS_CLK
+ //(Default HW) {GPIO_CNL_LP_GPD9, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //PM_SLP_WLAN_N
+ //(Default HW) {GPIO_CNL_LP_GPD10, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //PM_SLP_S5_N
+ //(Default HW) {GPIO_CNL_LP_GPD11, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNone }}, //LANPHY_EN
+
+ {GPIO_CNL_LP_PECI, { GpioHardwareDefault, GpioHostOwnDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermDefault }}, // PECI
+};
+UINT16 mGpioTableUpXtremeSize = sizeof (mGpioTableUpXtreme) / sizeof (GPIO_INIT_CONFIG);
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/PchHdaVerbTables.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/PchHdaVerbTables.h
new file mode 100644
index 0000000000..2e4bef3246
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/PchHdaVerbTables.h
@@ -0,0 +1,3014 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PCH_HDA_VERB_TABLES_H_
+#define _PCH_HDA_VERB_TABLES_H_
+
+#include <Ppi/SiPolicy.h>
+
+HDAUDIO_VERB_TABLE HdaVerbTableDisplayAudio = HDAUDIO_VERB_TABLE_INIT (
+ //
+ // VerbTable: CFL Display Audio Codec
+ // Revision ID = 0xFF
+ // Codec Vendor: 0x8086280B
+ //
+ 0x8086, 0x280B,
+ 0xFF, 0xFF,
+ //
+ // Display Audio Verb Table
+ //
+ // For GEN9, the Vendor Node ID is 08h
+ // Port to be exposed to the inbox driver in the vanilla mode: PORT C - BIT[7:6] = 01b
+ 0x00878140,
+ // Pin Widget 5 - PORT B - Configuration Default: 0x18560010
+ 0x00571C10,
+ 0x00571D00,
+ 0x00571E56,
+ 0x00571F18,
+ // Pin Widget 6 - PORT C - Configuration Default: 0x18560020
+ 0x00671C20,
+ 0x00671D00,
+ 0x00671E56,
+ 0x00671F18,
+ // Pin Widget 7 - PORT D - Configuration Default: 0x18560030
+ 0x00771C30,
+ 0x00771D00,
+ 0x00771E56,
+ 0x00771F18,
+ // Disable the third converter and third Pin (NID 08h)
+ 0x00878140
+);
+
+//
+//codecs verb tables
+//
+HDAUDIO_VERB_TABLE HdaVerbTableAlc700 = HDAUDIO_VERB_TABLE_INIT (
+ //
+ // VerbTable: (Realtek ALC700)
+ // Revision ID = 0xff
+ // Codec Verb Table
+ // Codec Address: CAd value (0/1/2)
+ // Codec Vendor: 0x10EC0700
+ //
+ 0x10EC, 0x0700,
+ 0xFF, 0xFF,
+ //===================================================================================================
+ //
+ // Realtek Semiconductor Corp.
+ //
+ //===================================================================================================
+
+ //Realtek High Definition Audio Configuration - Version : 5.0.3.0
+ //Realtek HD Audio Codec : ALC700
+ //PCI PnP ID : PCI\VEN_8086&DEV_2668&SUBSYS_72708086
+ //HDA Codec PnP ID : HDAUDIO\FUNC_01&VEN_10EC&DEV_0700&SUBSYS_10EC10F2
+ //The number of verb command block : 17
+
+ // NID 0x12 : 0x411111F0
+ // NID 0x13 : 0x40000000
+ // NID 0x14 : 0x411111F0
+ // NID 0x15 : 0x411111F0
+ // NID 0x16 : 0x411111F0
+ // NID 0x17 : 0x90170110
+ // NID 0x18 : 0x411111F0
+ // NID 0x19 : 0x04A11030
+ // NID 0x1A : 0x411111F0
+ // NID 0x1B : 0x411111F0
+ // NID 0x1D : 0x40622005
+ // NID 0x1E : 0x411111F0
+ // NID 0x1F : 0x411111F0
+ // NID 0x21 : 0x04211020
+ // NID 0x29 : 0x411111F0
+
+ //===== HDA Codec Subsystem ID Verb-table =====
+ //HDA Codec Subsystem ID : 0x10EC10F2
+ 0x001720F2,
+ 0x00172110,
+ 0x001722EC,
+ 0x00172310,
+
+ //===== Pin Widget Verb-table =====
+ //Widget node 0x01 :
+ 0x0017FF00,
+ 0x0017FF00,
+ 0x0017FF00,
+ 0x0017FF00,
+ //Pin widget 0x12 - DMIC
+ 0x01271C00,
+ 0x01271D00,
+ 0x01271E00,
+ 0x01271F40,
+ //Pin widget 0x13 - DMIC
+ 0x01371C00,
+ 0x01371D00,
+ 0x01371E00,
+ 0x01371F40,
+ //Pin widget 0x14 - FRONT (Port-D)
+ 0x01471CF0,
+ 0x01471D11,
+ 0x01471E11,
+ 0x01471F41,
+ //Pin widget 0x15 - I2S-OUT
+ 0x01571CF0,
+ 0x01571D11,
+ 0x01571E11,
+ 0x01571F41,
+ //Pin widget 0x16 - LINE3 (Port-B)
+ 0x01671CF0,
+ 0x01671D11,
+ 0x01671E11,
+ 0x01671F41,
+ //Pin widget 0x17 - I2S-OUT
+ 0x01771C10,
+ 0x01771D01,
+ 0x01771E17,
+ 0x01771F90,
+ //Pin widget 0x18 - I2S-IN
+ 0x01871CF0,
+ 0x01871D11,
+ 0x01871E11,
+ 0x01871F41,
+ //Pin widget 0x19 - MIC2 (Port-F)
+ 0x01971C30,
+ 0x01971D10,
+ 0x01971EA1,
+ 0x01971F04,
+ //Pin widget 0x1A - LINE1 (Port-C)
+ 0x01A71CF0,
+ 0x01A71D11,
+ 0x01A71E11,
+ 0x01A71F41,
+ //Pin widget 0x1B - LINE2 (Port-E)
+ 0x01B71CF0,
+ 0x01B71D11,
+ 0x01B71E11,
+ 0x01B71F41,
+ //Pin widget 0x1D - PC-BEEP
+ 0x01D71C05,
+ 0x01D71D20,
+ 0x01D71E62,
+ 0x01D71F40,
+ //Pin widget 0x1E - S/PDIF-OUT
+ 0x01E71CF0,
+ 0x01E71D11,
+ 0x01E71E11,
+ 0x01E71F41,
+ //Pin widget 0x1F - S/PDIF-IN
+ 0x01F71CF0,
+ 0x01F71D11,
+ 0x01F71E11,
+ 0x01F71F41,
+ //Pin widget 0x21 - HP-OUT (Port-I)
+ 0x02171C20,
+ 0x02171D10,
+ 0x02171E21,
+ 0x02171F04,
+ //Pin widget 0x29 - I2S-IN
+ 0x02971CF0,
+ 0x02971D11,
+ 0x02971E11,
+ 0x02971F41,
+ //Widget node 0x20 :
+ 0x02050045,
+ 0x02045289,
+ 0x0205004A,
+ 0x0204201B,
+ //Widget node 0x20 - 1 :
+ 0x05850000,
+ 0x05843888,
+ 0x0205006F,
+ 0x02042C0B,
+
+
+ //Widget node 0X20 for ALC1305 20160603 update
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040000,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040004,
+ 0x02050028,
+ 0x02040600,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003C,
+ 0x02050028,
+ 0x0204FFD0,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040080,
+ 0x02050028,
+ 0x02040080,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040080,
+ 0x02050028,
+ 0x02040880,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003A,
+ 0x02050028,
+ 0x02040DFE,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006A,
+ 0x02050028,
+ 0x0204005D,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006C,
+ 0x02050028,
+ 0x02040442,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040005,
+ 0x02050028,
+ 0x02040880,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040006,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040008,
+ 0x02050028,
+ 0x0204B000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204002E,
+ 0x02050028,
+ 0x02040800,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006A,
+ 0x02050028,
+ 0x020400C3,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006C,
+ 0x02050028,
+ 0x0204D4A0,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006A,
+ 0x02050028,
+ 0x020400CC,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006C,
+ 0x02050028,
+ 0x0204400A,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006A,
+ 0x02050028,
+ 0x020400C1,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006C,
+ 0x02050028,
+ 0x02040320,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040039,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003B,
+ 0x02050028,
+ 0x0204FFFF,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003C,
+ 0x02050028,
+ 0x0204FC20,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003A,
+ 0x02050028,
+ 0x02041DFE,
+ 0x02050029,
+ 0x0204B024,
+ //
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C0,
+ 0x02050028,
+ 0x020401FA,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C1,
+ 0x02050028,
+ 0x0204DE23,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C2,
+ 0x02050028,
+ 0x02041C00,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C3,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C4,
+ 0x02050028,
+ 0x02040200,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C5,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C6,
+ 0x02050028,
+ 0x020403F5,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C7,
+ 0x02050028,
+ 0x0204AF1B,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C8,
+ 0x02050028,
+ 0x02041E0A,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C9,
+ 0x02050028,
+ 0x0204368E,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400CA,
+ 0x02050028,
+ 0x020401FA,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400CB,
+ 0x02050028,
+ 0x0204DE23,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400CC,
+ 0x02050028,
+ 0x02041C00,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400CD,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400CE,
+ 0x02050028,
+ 0x02040200,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400CF,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400D0,
+ 0x02050028,
+ 0x020403F5,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400D1,
+ 0x02050028,
+ 0x0204AF1B,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400D2,
+ 0x02050028,
+ 0x02041E0A,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400D3,
+ 0x02050028,
+ 0x0204368E,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040040,
+ 0x02050028,
+ 0x0204800F,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040062,
+ 0x02050028,
+ 0x02048000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040063,
+ 0x02050028,
+ 0x02044848,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040064,
+ 0x02050028,
+ 0x02040800,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040065,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040066,
+ 0x02050028,
+ 0x02044004,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040067,
+ 0x02050028,
+ 0x02040802,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040068,
+ 0x02050028,
+ 0x0204890F,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040069,
+ 0x02050028,
+ 0x0204E021,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040070,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040071,
+ 0x02050000,
+ 0x02043330,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040072,
+ 0x02050000,
+ 0x02043333,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040073,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040074,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040075,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040076,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040050,
+ 0x02050028,
+ 0x020402EC,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040051,
+ 0x02050028,
+ 0x02044909,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040052,
+ 0x02050028,
+ 0x020440B0,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040046,
+ 0x02050028,
+ 0x0204C22E,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040047,
+ 0x02050028,
+ 0x02040C00,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040048,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040049,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204004A,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204004B,
+ 0x02050028,
+ 0x02041C00,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006A,
+ 0x02050028,
+ 0x02040090,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006C,
+ 0x02050028,
+ 0x0204721F,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204009E,
+ 0x02050028,
+ 0x02040001,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040004,
+ 0x02050028,
+ 0x02040500,
+ 0x02050029,
+ 0x0204B024
+); // HdaVerbTableAlc700
+
+HDAUDIO_VERB_TABLE HdaVerbTableAlc701 = HDAUDIO_VERB_TABLE_INIT (
+ //
+ // VerbTable: (Realtek ALC701)
+ // Revision ID = 0xff
+ // Codec Verb Table
+ // Codec Address: CAd value (0/1/2)
+ // Codec Vendor: 0x10EC0701
+ //
+ 0x10EC, 0x0701,
+ 0xFF, 0xFF,
+ //===================================================================================================
+ //
+ // Realtek Semiconductor Corp.
+ //
+ //===================================================================================================
+
+ //Realtek High Definition Audio Configuration - Version : 5.0.3.0
+ //Realtek HD Audio Codec : ALC701
+ //PCI PnP ID : PCI\VEN_8086&DEV_2668&SUBSYS_72708086
+ //HDA Codec PnP ID : HDAUDIO\FUNC_01&VEN_10EC&DEV_0701&SUBSYS_10EC1124
+ //The number of verb command block : 17
+
+ // NID 0x12 : 0x411111F0
+ // NID 0x13 : 0x40000000
+ // NID 0x14 : 0x411111F0
+ // NID 0x15 : 0x411111F0
+ // NID 0x16 : 0x411111F0
+ // NID 0x17 : 0x90170110
+ // NID 0x18 : 0x411111F0
+ // NID 0x19 : 0x04A11030
+ // NID 0x1A : 0x411111F0
+ // NID 0x1B : 0x411111F0
+ // NID 0x1D : 0x40610041
+ // NID 0x1E : 0x411111F0
+ // NID 0x1F : 0x411111F0
+ // NID 0x21 : 0x04211020
+ // NID 0x29 : 0x411111F0
+
+
+ //===== HDA Codec Subsystem ID Verb-table =====
+ //HDA Codec Subsystem ID : 0x10EC1124
+ 0x00172024,
+ 0x00172111,
+ 0x001722EC,
+ 0x00172310,
+ //===== Pin Widget Verb-table =====
+ //Widget node 0x01 :
+ 0x0017FF00,
+ 0x0017FF00,
+ 0x0017FF00,
+ 0x0017FF00,
+ //Pin widget 0x12 - DMIC
+ 0x01271C00,
+ 0x01271D00,
+ 0x01271E00,
+ 0x01271F40,
+ //Pin widget 0x13 - DMIC
+ 0x01371C00,
+ 0x01371D00,
+ 0x01371E00,
+ 0x01371F40,
+ //Pin widget 0x14 - FRONT (Port-D)
+ 0x01471CF0,
+ 0x01471D11,
+ 0x01471E11,
+ 0x01471F41,
+ //Pin widget 0x15 - I2S-OUT
+ 0x01571CF0,
+ 0x01571D11,
+ 0x01571E11,
+ 0x01571F41,
+ //Pin widget 0x16 - LINE3 (Port-B)
+ 0x01671CF0,
+ 0x01671D11,
+ 0x01671E11,
+ 0x01671F41,
+ //Pin widget 0x17 - I2S-OUT
+ 0x01771C10,
+ 0x01771D01,
+ 0x01771E17,
+ 0x01771F90,
+ //Pin widget 0x18 - I2S-IN
+ 0x01871CF0,
+ 0x01871D11,
+ 0x01871E11,
+ 0x01871F41,
+ //Pin widget 0x19 - MIC2 (Port-F)
+ 0x01971C30,
+ 0x01971D10,
+ 0x01971EA1,
+ 0x01971F04,
+ //Pin widget 0x1A - LINE1 (Port-C)
+ 0x01A71CF0,
+ 0x01A71D11,
+ 0x01A71E11,
+ 0x01A71F41,
+ //Pin widget 0x1B - LINE2 (Port-E)
+ 0x01B71CF0,
+ 0x01B71D11,
+ 0x01B71E11,
+ 0x01B71F41,
+ //Pin widget 0x1D - PC-BEEP
+ 0x01D71C41,
+ 0x01D71D00,
+ 0x01D71E61,
+ 0x01D71F40,
+ //Pin widget 0x1E - S/PDIF-OUT
+ 0x01E71CF0,
+ 0x01E71D11,
+ 0x01E71E11,
+ 0x01E71F41,
+ //Pin widget 0x1F - S/PDIF-IN
+ 0x01F71CF0,
+ 0x01F71D11,
+ 0x01F71E11,
+ 0x01F71F41,
+ //Pin widget 0x21 - HP-OUT (Port-I)
+ 0x02171C20,
+ 0x02171D10,
+ 0x02171E21,
+ 0x02171F04,
+ //Pin widget 0x29 - I2S-IN
+ 0x02971CF0,
+ 0x02971D11,
+ 0x02971E11,
+ 0x02971F41,
+ //Widget node 0x20 :
+ 0x02050045,
+ 0x02045289,
+ 0x0205004A,
+ 0x0204201B,
+ //Widget node 0x20 - 1 :
+ 0x05850000,
+ 0x05843888,
+ 0x0205006F,
+ 0x02042C0B
+); // HdaVerbTableAlc701
+
+HDAUDIO_VERB_TABLE HdaVerbTableAlc274 = HDAUDIO_VERB_TABLE_INIT (
+ //
+ // VerbTable: (Realtek ALC274)
+ // Revision ID = 0xff
+ // Codec Verb Table
+ // Codec Address: CAd value (0/1/2)
+ // Codec Vendor: 0x10EC0274
+ //
+ 0x10EC, 0x0274,
+ 0xFF, 0xFF,
+ //===================================================================================================
+ //
+ // Realtek Semiconductor Corp.
+ //
+ //===================================================================================================
+
+ //Realtek High Definition Audio Configuration - Version : 5.0.3.0
+ //Realtek HD Audio Codec : ALC274
+ //PCI PnP ID : PCI\VEN_8086&DEV_2668&SUBSYS_72708086
+ //HDA Codec PnP ID : HDAUDIO\FUNC_01&VEN_10EC&DEV_0274&SUBSYS_10EC10F6
+ //The number of verb command block : 16
+
+ // NID 0x12 : 0x40000000
+ // NID 0x13 : 0x411111F0
+ // NID 0x14 : 0x411111F0
+ // NID 0x15 : 0x411111F0
+ // NID 0x16 : 0x411111F0
+ // NID 0x17 : 0x411111F0
+ // NID 0x18 : 0x411111F0
+ // NID 0x19 : 0x04A11020
+ // NID 0x1A : 0x411111F0
+ // NID 0x1B : 0x411111F0
+ // NID 0x1D : 0x40451B05
+ // NID 0x1E : 0x411111F0
+ // NID 0x1F : 0x411111F0
+ // NID 0x21 : 0x04211010
+
+
+ //===== HDA Codec Subsystem ID Verb-table =====
+ //,DA Codec Subsystem ID : 0x10EC10F6
+ 0x001720F6,
+ 0x00172110,
+ 0x001722EC,
+ 0x00172310,
+
+ //===== Pin Widget Verb-table =====
+ //Widget node 0x01 :
+ 0x0017FF00,
+ 0x0017FF00,
+ 0x0017FF00,
+ 0x0017FF00,
+ //Pin widget 0x12 - DMIC
+ 0x01271C00,
+ 0x01271D00,
+ 0x01271E00,
+ 0x01271F40,
+ //Pin widget 0x13 - DMIC
+ 0x01371CF0,
+ 0x01371D11,
+ 0x01371E11,
+ 0x01371F41,
+ //Pin widget 0x14 - NPC
+ 0x01471CF0,
+ 0x01471D11,
+ 0x01471E11,
+ 0x01471F41,
+ //Pin widget 0x15 - I2S_OUT2
+ 0x01571CF0,
+ 0x01571D11,
+ 0x01571E11,
+ 0x01571F41,
+ //Pin widget 0x16 - LINE3 (Port-B)
+ 0x01671CF0,
+ 0x01671D11,
+ 0x01671E11,
+ 0x01671F41,
+ //Pin widget 0x17 - I2S_OUT1
+ 0x01771CF0,
+ 0x01771D11,
+ 0x01771E11,
+ 0x01771F41,
+ //Pin widget 0x18 - I2S_IN
+ 0x01871CF0,
+ 0x01871D11,
+ 0x01871E11,
+ 0x01871F41,
+ //Pin widget 0x19 - MIC2 (Port-F)
+ 0x01971C20,
+ 0x01971D10,
+ 0x01971EA1,
+ 0x01971F04,
+ //Pin widget 0x1A - LINE1 (Port-C)
+ 0x01A71CF0,
+ 0x01A71D11,
+ 0x01A71E11,
+ 0x01A71F41,
+ //Pin widget 0x1B - LINE2 (Port-E)
+ 0x01B71CF0,
+ 0x01B71D11,
+ 0x01B71E11,
+ 0x01B71F41,
+ //Pin widget 0x1D - PC-BEEP
+ 0x01D71C05,
+ 0x01D71D1B,
+ 0x01D71E45,
+ 0x01D71F40,
+ //Pin widget 0x1E - S/PDIF-OUT
+ 0x01E71CF0,
+ 0x01E71D11,
+ 0x01E71E11,
+ 0x01E71F41,
+ //Pin widget 0x1F - S/PDIF-IN
+ 0x01F71CF0,
+ 0x01F71D11,
+ 0x01F71E11,
+ 0x01F71F41,
+ //Pin widget 0x21 - HP-OUT (Port-I)
+ 0x02171C10,
+ 0x02171D10,
+ 0x02171E21,
+ 0x02171F04,
+ //Widget node 0x20 :
+ 0x02050045,
+ 0x02045289,
+ 0x0205006F,
+ 0x02042C0B,
+ //Widget node 0x20 - 1 :
+ 0x02050035,
+ 0x02048968,
+ 0x05B50001,
+ 0x05B48540,
+ //Widget node 0x20 - 2 :
+ 0x05850000,
+ 0x05843888,
+ 0x05850000,
+ 0x05843888,
+ //Widget node 0x20 - 3 :
+ 0x0205004A,
+ 0x0204201B,
+ 0x0205004A,
+ 0x0204201B
+); //HdaVerbTableAlc274
+
+//
+// CFL S Audio Codec
+//
+STATIC HDAUDIO_VERB_TABLE CflSHdaVerbTableAlc700 = HDAUDIO_VERB_TABLE_INIT (
+ //
+ // VerbTable: (Realtek ALC700) CFL S RVP
+ // Revision ID = 0xff
+ // Codec Verb Table
+ // Codec Address: CAd value (0/1/2)
+ // Codec Vendor: 0x10EC0700
+ //
+ 0x10EC, 0x0700,
+ 0xFF, 0xFF,
+
+ //===================================================================================================
+ //
+ // Realtek Semiconductor Corp.
+ //
+ //===================================================================================================
+
+ //Realtek High Definition Audio Configuration - Version : 5.0.3.1
+ //Realtek HD Audio Codec : ALC700
+ //PCI PnP ID : PCI\VEN_8086&DEV_2668&SUBSYS_72708086
+ //HDA Codec PnP ID : HDAUDIO\FUNC_01&VEN_10EC&DEV_0700&SUBSYS_10EC112C
+ //The number of verb command block : 17
+
+ // NID 0x12 : 0x90A60130
+ // NID 0x13 : 0x40000000
+ // NID 0x14 : 0x411111F0
+ // NID 0x15 : 0x411111F0
+ // NID 0x16 : 0x03011010
+ // NID 0x17 : 0x90170120
+ // NID 0x18 : 0x411111F0
+ // NID 0x19 : 0x04A1103E
+ // NID 0x1A : 0x411111F0
+ // NID 0x1B : 0x03A11040
+ // NID 0x1D : 0x40600001
+ // NID 0x1E : 0x411111F0
+ // NID 0x1F : 0x411111F0
+ // NID 0x21 : 0x0421102F
+ // NID 0x29 : 0x411111F0
+
+
+ //===== HDA Codec Subsystem ID Verb-table =====
+ //HDA Codec Subsystem ID : 0x10EC112C
+ 0x0017202C,
+ 0x00172111,
+ 0x001722EC,
+ 0x00172310,
+
+
+ //===== Pin Widget Verb-table =====
+ //Widget node 0x01 :
+ 0x0017FF00,
+ 0x0017FF00,
+ 0x0017FF00,
+ 0x0017FF00,
+ //Pin widget 0x12 - DMIC
+ 0x01271C30,
+ 0x01271D01,
+ 0x01271EA6,
+ 0x01271F90,
+ //Pin widget 0x13 - DMIC
+ 0x01371C00,
+ 0x01371D00,
+ 0x01371E00,
+ 0x01371F40,
+ //Pin widget 0x14 - FRONT (Port-D)
+ 0x01471CF0,
+ 0x01471D11,
+ 0x01471E11,
+ 0x01471F41,
+ //Pin widget 0x15 - I2S-OUT
+ 0x01571CF0,
+ 0x01571D11,
+ 0x01571E11,
+ 0x01571F41,
+ //Pin widget 0x16 - LINE3 (Port-B)
+ 0x01671C10,
+ 0x01671D10,
+ 0x01671E01,
+ 0x01671F03,
+ //Pin widget 0x17 - I2S-OUT
+ 0x01771C20,
+ 0x01771D01,
+ 0x01771E17,
+ 0x01771F90,
+ //Pin widget 0x18 - I2S-IN
+ 0x01871CF0,
+ 0x01871D11,
+ 0x01871E11,
+ 0x01871F41,
+ //Pin widget 0x19 - MIC2 (Port-F)
+ 0x01971C3E,
+ 0x01971D10,
+ 0x01971EA1,
+ 0x01971F04,
+ //Pin widget 0x1A - LINE1 (Port-C)
+ 0x01A71CF0,
+ 0x01A71D11,
+ 0x01A71E11,
+ 0x01A71F41,
+ //Pin widget 0x1B - LINE2 (Port-E)
+ 0x01B71C40,
+ 0x01B71D10,
+ 0x01B71EA1,
+ 0x01B71F03,
+ //Pin widget 0x1D - PC-BEEP
+ 0x01D71C01,
+ 0x01D71D00,
+ 0x01D71E60,
+ 0x01D71F40,
+ //Pin widget 0x1E - S/PDIF-OUT
+ 0x01E71CF0,
+ 0x01E71D11,
+ 0x01E71E11,
+ 0x01E71F41,
+ //Pin widget 0x1F - S/PDIF-IN
+ 0x01F71CF0,
+ 0x01F71D11,
+ 0x01F71E11,
+ 0x01F71F41,
+ //Pin widget 0x21 - HP-OUT (Port-I)
+ 0x02171C2F,
+ 0x02171D10,
+ 0x02171E21,
+ 0x02171F04,
+ //Pin widget 0x29 - I2S-IN
+ 0x02971CF0,
+ 0x02971D11,
+ 0x02971E11,
+ 0x02971F41,
+
+ //Widget node 0x20 - 0 FAKE JD unplug
+ 0x02050008,
+ 0x0204A80F,
+ 0x02050008,
+ 0x0204A80F,
+ //Widget node 0x20 - 1 : LINE2-VREFO( MIC2-vrefo-R) base on verb_707h of NID 1Bh , HP-JD gating MIC2-vrefo-L, bypass DAC02 DRE(NID5B bit14)
+ 0x0205006B,
+ 0x02044260,
+ 0x0205006B,
+ 0x02044260,
+ //Widget node 0x20 - 2 : //remove NID 58 realted setting for ALC700
+ 0x05B50010,
+ 0x05B45C1D,
+ 0x0205006F,
+ 0x02040F8B, //Zeek, 0F8Bh
+ //Widget node 0x20 -3 : MIC2-Vrefo-R and MIC2-vrefo-L to independent control
+ 0x02050045,
+ 0x02045089,
+ 0x0205004A,
+ 0x0204201B,
+ //Widget node 0x20 - 4 From JD detect
+ 0x02050008,
+ 0x0204A807,
+ 0x02050008,
+ 0x0204A807,
+ //Widget node 0x20 - 5 Pull high ALC700 GPIO5 for AMP1305 PD pin and enable I2S BCLK first
+ 0x02050090,
+ 0x02040424,
+ 0x00171620,
+ 0x00171720,
+
+ 0x00171520,
+ 0x01770740,
+ 0x01770740,
+ 0x01770740,
+
+
+ //Widget node 0X20 for ALC1305 20181023 update 2W/4ohm to remove ALC1305 EQ setting
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040000,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006A,
+ 0x02050028,
+ 0x020400CF,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006C,
+ 0x02050028,
+ 0x02045548,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003F,
+ 0x02050028,
+ 0x02041000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040004,
+ 0x02050028,
+ 0x02040600,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003C,
+ 0x02050028,
+ 0x0204FFD0,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040080,
+ 0x02050028,
+ 0x02040080,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040080,
+ 0x02050028,
+ 0x02040880,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003A,
+ 0x02050028,
+ 0x02040DFE,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006A,
+ 0x02050028,
+ 0x0204005D,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006C,
+ 0x02050028,
+ 0x02040442,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040005,
+ 0x02050028,
+ 0x02040880,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040006,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040008,
+ 0x02050028,
+ 0x0204B000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204002E,
+ 0x02050028,
+ 0x02040800,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006A,
+ 0x02050028,
+ 0x020400C3,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006C,
+ 0x02050028,
+ 0x0204D4A0,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006A,
+ 0x02050028,
+ 0x020400CC,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006C,
+ 0x02050028,
+ 0x0204400A,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006A,
+ 0x02050028,
+ 0x020400C1,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006C,
+ 0x02050028,
+ 0x02040320,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040039,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003B,
+ 0x02050028,
+ 0x0204FFFF,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003C,
+ 0x02050028,
+ 0x0204FC20,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006A,
+ 0x02050028,
+ 0x02040006,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006C,
+ 0x02050028,
+ 0x020400C0,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003C,
+ 0x02050028,
+ 0x0204FCA0,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003C,
+ 0x02050028,
+ 0x0204FCE0,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003C,
+ 0x02050028,
+ 0x0204FCF0,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040080,
+ 0x02050028,
+ 0x02040080,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040080,
+ 0x02050028,
+ 0x02040880,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040080,
+ 0x02050028,
+ 0x02040880,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003C,
+ 0x02050028,
+ 0x0204FCE0,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003C,
+ 0x02050028,
+ 0x0204FCA0,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003C,
+ 0x02050028,
+ 0x0204FC20,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006A,
+ 0x02050028,
+ 0x02040006,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006C,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040080,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C0,
+ 0x02050028,
+ 0x020401F0,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C1,
+ 0x02050028,
+ 0x0204C1C7,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C2,
+ 0x02050028,
+ 0x02041C00,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C3,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C4,
+ 0x02050028,
+ 0x02040200,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C5,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C6,
+ 0x02050028,
+ 0x020403E1,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C7,
+ 0x02050028,
+ 0x02040F5A,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C8,
+ 0x02050028,
+ 0x02041E1E,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C9,
+ 0x02050028,
+ 0x0204083F,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400CA,
+ 0x02050028,
+ 0x020401F0,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400CB,
+ 0x02050028,
+ 0x0204C1C7,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400CC,
+ 0x02050028,
+ 0x02041C00,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400CD,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400CE,
+ 0x02050028,
+ 0x02040200,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400CF,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400D0,
+ 0x02050028,
+ 0x020403E1,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400D1,
+ 0x02050028,
+ 0x02040F5A,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400D2,
+ 0x02050028,
+ 0x02041E1E,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400D3,
+ 0x02050028,
+ 0x0204083F,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040062,
+ 0x02050028,
+ 0x02048000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040063,
+ 0x02050028,
+ 0x02045F5F,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040064,
+ 0x02050028,
+ 0x02042000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040065,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040066,
+ 0x02050028,
+ 0x02044004,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040067,
+ 0x02050028,
+ 0x02040802,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040068,
+ 0x02050028,
+ 0x0204890F,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040069,
+ 0x02050028,
+ 0x0204E021,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040070,
+ 0x02050028,
+ 0x02048012,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040071,
+ 0x02050028,
+ 0x02043450,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040072,
+ 0x02050028,
+ 0x02040123,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040073,
+ 0x02050028,
+ 0x02044543,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040074,
+ 0x02050028,
+ 0x02042100,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040075,
+ 0x02050028,
+ 0x02044321,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040076,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040050,
+ 0x02050028,
+ 0x02048200,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040051,
+ 0x02050028,
+ 0x02040707,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040052,
+ 0x02050028,
+ 0x02044090,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006A,
+ 0x02050028,
+ 0x02040090,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006C,
+ 0x02050028,
+ 0x0204721F,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040012,
+ 0x02050028,
+ 0x0204DFDF,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204009E,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040004,
+ 0x02050028,
+ 0x02040500,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040060,
+ 0x02050028,
+ 0x02042213,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003A,
+ 0x02050028,
+ 0x02041DFE,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003F,
+ 0x02050028,
+ 0x02043000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040040,
+ 0x02050028,
+ 0x0204000C,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040046,
+ 0x02050028,
+ 0x0204C22E,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204004B,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024
+);
+
+
+//
+// WHL codecs verb tables
+//
+HDAUDIO_VERB_TABLE WhlHdaVerbTableAlc700 = HDAUDIO_VERB_TABLE_INIT (
+ //
+ // VerbTable: (Realtek ALC700) WHL RVP
+ // Revision ID = 0xff
+ // Codec Verb Table for WHL PCH boards
+ // Codec Address: CAd value (0/1/2)
+ // Codec Vendor: 0x10EC0700
+ //
+ 0x10EC, 0x0700,
+ 0xFF, 0xFF,
+ //===================================================================================================
+ //
+ // Realtek Semiconductor Corp.
+ //
+ //===================================================================================================
+
+ //Realtek High Definition Audio Configuration - Version : 5.0.3.1
+ //Realtek HD Audio Codec : ALC700
+ //PCI PnP ID : PCI\VEN_8086&DEV_2668&SUBSYS_72708086
+ //HDA Codec PnP ID : HDAUDIO\FUNC_01&VEN_10EC&DEV_0700&SUBSYS_10EC10F2
+ //The number of verb command block : 17
+
+ // NID 0x12 : 0x411111F0
+ // NID 0x13 : 0x40000000
+ // NID 0x14 : 0x411111F0
+ // NID 0x15 : 0x411111F0
+ // NID 0x16 : 0x411111F0
+ // NID 0x17 : 0x90170110
+ // NID 0x18 : 0x411111F0
+ // NID 0x19 : 0x02A19040
+ // NID 0x1A : 0x411111F0
+ // NID 0x1B : 0x411111F0
+ // NID 0x1D : 0x40638029
+ // NID 0x1E : 0x411111F0
+ // NID 0x1F : 0x411111F0
+ // NID 0x21 : 0x02211020
+ // NID 0x29 : 0x411111F0
+
+ //===== HDA Codec Subsystem ID Verb-table =====
+ //HDA Codec Subsystem ID : 0x10EC10F2
+ 0x001720F2,
+ 0x00172110,
+ 0x001722EC,
+ 0x00172310,
+
+ //===== Pin Widget Verb-table =====
+ //Widget node 0x01 :
+ 0x0017FF00,
+ 0x0017FF00,
+ 0x0017FF00,
+ 0x0017FF00,
+ //Pin widget 0x12 - DMIC
+ 0x01271CF0,
+ 0x01271D11,
+ 0x01271E11,
+ 0x01271F41,
+ //Pin widget 0x13 - DMIC
+ 0x01371C00,
+ 0x01371D00,
+ 0x01371E00,
+ 0x01371F40,
+ //Pin widget 0x14 - FRONT (Port-D)
+ 0x01471CF0,
+ 0x01471D11,
+ 0x01471E11,
+ 0x01471F41,
+ //Pin widget 0x15 - I2S-OUT
+ 0x01571CF0,
+ 0x01571D11,
+ 0x01571E11,
+ 0x01571F41,
+ //Pin widget 0x16 - LINE3 (Port-B)
+ 0x01671CF0,
+ 0x01671D11,
+ 0x01671E11,
+ 0x01671F41,
+ //Pin widget 0x17 - I2S-OUT
+ 0x01771C10,
+ 0x01771D01,
+ 0x01771E17,
+ 0x01771F90,
+ //Pin widget 0x18 - I2S-IN
+ 0x01871CF0,
+ 0x01871D11,
+ 0x01871E11,
+ 0x01871F41,
+ //Pin widget 0x19 - MIC2 (Port-F)
+ 0x01971C40,
+ 0x01971D90,
+ 0x01971EA1,
+ 0x01971F02,
+ //Pin widget 0x1A - LINE1 (Port-C)
+ 0x01A71CF0,
+ 0x01A71D11,
+ 0x01A71E11,
+ 0x01A71F41,
+ //Pin widget 0x1B - LINE2 (Port-E)
+ 0x01B71CF0,
+ 0x01B71D11,
+ 0x01B71E11,
+ 0x01B71F41,
+ //Pin widget 0x1D - PC-BEEP
+ 0x01D71C29,
+ 0x01D71D80,
+ 0x01D71E63,
+ 0x01D71F40,
+ //Pin widget 0x1E - S/PDIF-OUT
+ 0x01E71CF0,
+ 0x01E71D11,
+ 0x01E71E11,
+ 0x01E71F41,
+ //Pin widget 0x1F - S/PDIF-IN
+ 0x01F71CF0,
+ 0x01F71D11,
+ 0x01F71E11,
+ 0x01F71F41,
+ //Pin widget 0x21 - HP-OUT (Port-I)
+ 0x02171C20,
+ 0x02171D10,
+ 0x02171E21,
+ 0x02171F02,
+ //Pin widget 0x29 - I2S-IN
+ 0x02971CF0,
+ 0x02971D11,
+ 0x02971E11,
+ 0x02971F41,
+ //Widget node 0x20 - 0 FAKE JD unplug
+ 0x02050008,
+ 0x0204A80F,
+ 0x02050008,
+ 0x0204A80F,
+
+ //Widget node 0x20 - 1 : //remove NID 58 realted setting for ALC700 bypass DAC02 DRE(NID5B bit14)
+ 0x05B50010,
+ 0x05B45C1D,
+ 0x0205006F,
+ 0x02040F8B, //Zeek, 0F8Bh
+
+ //Widget node 0x20 -2:
+ 0x02050045,
+ 0x02045089,
+ 0x0205004A,
+ 0x0204201B,
+
+ //Widget node 0x20 - 3 From JD detect
+ 0x02050008,
+ 0x0204A807,
+ 0x02050008,
+ 0x0204A807,
+
+ //Widget node 0x20 - 4 Pull high ALC700 GPIO5 for AMP1305 PD pin and enable I2S BCLK first
+ 0x02050090,
+ 0x02040424,
+ 0x00171620,
+ 0x00171720,
+
+ 0x00171520,
+ 0x01770740,
+ 0x01770740,
+ 0x01770740,
+
+ //Widget node 0x20 for ALC1305 20181105 update 2W/4ohm to remove ALC1305 EQ setting and enable ALC1305 silencet detect to prevent I2S noise
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040000,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006A,
+ 0x02050028,
+ 0x020400CF,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006C,
+ 0x02050028,
+ 0x02045548,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003F,
+ 0x02050028,
+ 0x02041000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040004,
+ 0x02050028,
+ 0x02040600,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003C,
+ 0x02050028,
+ 0x0204FFD0,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040080,
+ 0x02050028,
+ 0x02040080,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040080,
+ 0x02050028,
+ 0x02040880,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003A,
+ 0x02050028,
+ 0x02040DFE,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006A,
+ 0x02050028,
+ 0x0204005D,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006C,
+ 0x02050028,
+ 0x02040442,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040005,
+ 0x02050028,
+ 0x02040880,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040006,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040008,
+ 0x02050028,
+ 0x0204B000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204002E,
+ 0x02050028,
+ 0x02040800,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006A,
+ 0x02050028,
+ 0x020400C3,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006C,
+ 0x02050028,
+ 0x0204D4A0,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006A,
+ 0x02050028,
+ 0x020400CC,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006C,
+ 0x02050028,
+ 0x0204400A,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006A,
+ 0x02050028,
+ 0x020400C1,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006C,
+ 0x02050028,
+ 0x02040320,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040039,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003B,
+ 0x02050028,
+ 0x0204FFFF,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003C,
+ 0x02050028,
+ 0x0204FC20,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006A,
+ 0x02050028,
+ 0x02040006,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006C,
+ 0x02050028,
+ 0x020400C0,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003C,
+ 0x02050028,
+ 0x0204FCA0,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003C,
+ 0x02050028,
+ 0x0204FCE0,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003C,
+ 0x02050028,
+ 0x0204FCF0,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040080,
+ 0x02050028,
+ 0x02040080,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040080,
+ 0x02050028,
+ 0x02040880,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040080,
+ 0x02050028,
+ 0x02040880,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003C,
+ 0x02050028,
+ 0x0204FCE0,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003C,
+ 0x02050028,
+ 0x0204FCA0,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003C,
+ 0x02050028,
+ 0x0204FC20,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006A,
+ 0x02050028,
+ 0x02040006,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006C,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040080,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C0,
+ 0x02050028,
+ 0x020401F0,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C1,
+ 0x02050028,
+ 0x0204C1C7,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C2,
+ 0x02050028,
+ 0x02041C00,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C3,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C4,
+ 0x02050028,
+ 0x02040200,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C5,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C6,
+ 0x02050028,
+ 0x020403E1,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C7,
+ 0x02050028,
+ 0x02040F5A,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C8,
+ 0x02050028,
+ 0x02041E1E,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400C9,
+ 0x02050028,
+ 0x0204083F,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400CA,
+ 0x02050028,
+ 0x020401F0,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400CB,
+ 0x02050028,
+ 0x0204C1C7,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400CC,
+ 0x02050028,
+ 0x02041C00,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400CD,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400CE,
+ 0x02050028,
+ 0x02040200,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400CF,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400D0,
+ 0x02050028,
+ 0x020403E1,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400D1,
+ 0x02050028,
+ 0x02040F5A,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400D2,
+ 0x02050028,
+ 0x02041E1E,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x020400D3,
+ 0x02050028,
+ 0x0204083F,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040062,
+ 0x02050028,
+ 0x02048000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040063,
+ 0x02050028,
+ 0x02045F5F,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040064,
+ 0x02050028,
+ 0x02042000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040065,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040066,
+ 0x02050028,
+ 0x02044004,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040067,
+ 0x02050028,
+ 0x02040802,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040068,
+ 0x02050028,
+ 0x0204890F,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040069,
+ 0x02050028,
+ 0x0204E021,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040070,
+ 0x02050028,
+ 0x02048012,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040071,
+ 0x02050028,
+ 0x02043450,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040072,
+ 0x02050028,
+ 0x02040123,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040073,
+ 0x02050028,
+ 0x02044543,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040074,
+ 0x02050028,
+ 0x02042100,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040075,
+ 0x02050028,
+ 0x02044321,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040076,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040050,
+ 0x02050028,
+ 0x02048200,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040051,
+ 0x02050028,
+ 0x02040707,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040052,
+ 0x02050028,
+ 0x02044090,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006A,
+ 0x02050028,
+ 0x02040090,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204006C,
+ 0x02050028,
+ 0x0204721F,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040012,
+ 0x02050028,
+ 0x0204DFDF,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204009E,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040004,
+ 0x02050028,
+ 0x02040500,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040060,
+ 0x02050028,
+ 0x0204E213,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003A,
+ 0x02050028,
+ 0x02041DFE,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204003F,
+ 0x02050028,
+ 0x02043000,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040040,
+ 0x02050028,
+ 0x0204000C,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x02040046,
+ 0x02050028,
+ 0x0204422E,
+ 0x02050029,
+ 0x0204B024,
+
+ 0x02050024,
+ 0x02040010,
+ 0x02050026,
+ 0x0204004B,
+ 0x02050028,
+ 0x02040000,
+ 0x02050029,
+ 0x0204B024
+); // WhlHdaVerbTableAlc700
+
+#endif // _PCH_HDA_VERB_TABLES_H_
+
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/PeiBoardInitPostMemLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/PeiBoardInitPostMemLib.c
new file mode 100644
index 0000000000..d268b216a9
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/PeiBoardInitPostMemLib.c
@@ -0,0 +1,40 @@
+/** @file
+ Platform Hook Library instances
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiPei.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardInitLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+
+EFI_STATUS
+EFIAPI
+UpXtremeBoardInitBeforeSiliconInit (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+BoardInitBeforeSiliconInit (
+ VOID
+ )
+{
+ UpXtremeBoardInitBeforeSiliconInit ();
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+BoardInitAfterSiliconInit (
+ VOID
+ )
+{
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/PeiBoardInitPostMemLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/PeiBoardInitPostMemLib.inf
new file mode 100644
index 0000000000..1565279938
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/PeiBoardInitPostMemLib.inf
@@ -0,0 +1,57 @@
+## @file
+# Component information file for UpXtremeInitLib in PEI post memory phase.
+#
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PeiBoardPostMemInitLib
+ FILE_GUID = 7fcc3900-d38d-419f-826b-72481e8b5509
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = BoardInitLib
+
+[LibraryClasses]
+ BaseLib
+ BaseMemoryLib
+ DebugLib
+ GpioExpanderLib
+ GpioLib
+ HdaVerbTableLib
+ MemoryAllocationLib
+ PcdLib
+ SiliconInitLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ SecurityPkg/SecurityPkg.dec
+ IntelSiliconPkg/IntelSiliconPkg.dec
+ CoffeelakeSiliconPkg/SiPkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec
+
+[Sources]
+ PeiUpXtremeInitPostMemLib.c
+ PeiBoardInitPostMemLib.c
+ GpioTableDefault.c
+ GpioTableUpXtreme.c
+
+[Pcd]
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableSize
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableTouchPanel
+
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTable
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTableSize
+
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardUcmcGpioTable
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardUcmcGpioTableSize
+
+ gEfiSecurityPkgTokenSpaceGuid.PcdTpm2CurrentIrqNum
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/PeiBoardInitPreMemLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/PeiBoardInitPreMemLib.c
new file mode 100644
index 0000000000..d7ad81d4c2
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/PeiBoardInitPreMemLib.c
@@ -0,0 +1,106 @@
+/** @file
+ Platform Hook Library instances
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiPei.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardInitLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+
+EFI_STATUS
+EFIAPI
+UpXtremeBoardDetect (
+ VOID
+ );
+
+EFI_BOOT_MODE
+EFIAPI
+UpXtremeBoardBootModeDetect (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+UpXtremeBoardDebugInit (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+UpXtremeBoardInitBeforeMemoryInit (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+BoardDetect (
+ VOID
+ )
+{
+ UpXtremeBoardDetect ();
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+BoardDebugInit (
+ VOID
+ )
+{
+ UpXtremeBoardDebugInit ();
+ return EFI_SUCCESS;
+}
+
+EFI_BOOT_MODE
+EFIAPI
+BoardBootModeDetect (
+ VOID
+ )
+{
+ return UpXtremeBoardBootModeDetect ();
+}
+
+EFI_STATUS
+EFIAPI
+BoardInitBeforeMemoryInit (
+ VOID
+ )
+{
+ UpXtremeBoardInitBeforeMemoryInit ();
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+BoardInitAfterMemoryInit (
+ VOID
+ )
+{
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+BoardInitBeforeTempRamExit (
+ VOID
+ )
+{
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+BoardInitAfterTempRamExit (
+ VOID
+ )
+{
+ return EFI_SUCCESS;
+}
+
+
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/PeiBoardInitPreMemLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/PeiBoardInitPreMemLib.inf
new file mode 100644
index 0000000000..5166a915a2
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/PeiBoardInitPreMemLib.inf
@@ -0,0 +1,124 @@
+## @file
+# Component information file for PEI UpXtreme Board Init Pre-Mem Library
+#
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PeiBoardInitPreMemLib
+ FILE_GUID = ec3675bc-1470-417d-826e-37378140213d
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = BoardInitLib
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ BaseMemoryLib
+ MemoryAllocationLib
+ PcdLib
+ SiliconInitLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ IntelSiliconPkg/IntelSiliconPkg.dec
+ CoffeelakeSiliconPkg/SiPkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec
+
+[Sources]
+ PeiUpXtremeDetect.c
+ PeiUpXtremeInitPreMemLib.c
+ UpXtremeHsioPtssTables.c
+ PeiBoardInitPreMemLib.c
+
+[Guids]
+ gDebugConfigHobGuid ## CONSUMES
+
+[FixedPcd]
+ gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable
+
+[Pcd]
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioConfigDefaultPort
+
+ # PCH-LP HSIO PTSS Table
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size
+
+ # SA Misc Config
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSaMiscUserBd
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMap
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMapSize
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2Dram
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdData
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdDataSize
+
+ # PEG Reset By GPIO
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0WakeGpioNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstExpanderNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstGpioNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstActive
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableGpioNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableActive
+
+
+ # SPD Address Table
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable0
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable1
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable2
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable3
+
+ # USB 2.0 Port AFE
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port0Afe
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port1Afe
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port2Afe
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port3Afe
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port4Afe
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port5Afe
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port6Afe
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port7Afe
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port8Afe
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port9Afe
+
+ # USB 2.0 Port Over Current Pin
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort0
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort1
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort2
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort3
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort4
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort5
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort6
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort7
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort8
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort9
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort10
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort11
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort12
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort13
+
+ # USB 3.0 Port Over Current Pin
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort0
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort1
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort2
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort3
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort4
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort5
+
+ # Misc
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdIoExpanderPresent
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.c
new file mode 100644
index 0000000000..ddcd8ed15f
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.c
@@ -0,0 +1,41 @@
+/** @file
+ Platform Hook Library instances
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiPei.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardInitLib.h>
+#include <Library/MultiBoardInitSupportLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+
+#include <PlatformBoardId.h>
+
+EFI_STATUS
+EFIAPI
+UpXtremeBoardInitBeforeSiliconInit (
+ VOID
+ );
+
+BOARD_POST_MEM_INIT_FUNC mUpXtremeBoardInitFunc = {
+ UpXtremeBoardInitBeforeSiliconInit,
+ NULL, // BoardInitAfterSiliconInit
+};
+
+EFI_STATUS
+EFIAPI
+PeiUpXtremeMultiBoardInitLibConstructor (
+ VOID
+ )
+{
+ if (LibPcdGetSku () == BoardIdUpXtreme) {
+ return RegisterBoardPostMemInit (&mUpXtremeBoardInitFunc);
+ }
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf
new file mode 100644
index 0000000000..87e9dfde92
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf
@@ -0,0 +1,202 @@
+## @file
+# Component information file for UpXtremeInitLib in PEI post memory phase.
+#
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PeiUpXtremeMultiBoardInitLib
+ FILE_GUID = C7D39F17-E5BA-41D9-8DFE-FF9017499280
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = NULL
+ CONSTRUCTOR = PeiUpXtremeMultiBoardInitLibConstructor
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ BaseMemoryLib
+ MemoryAllocationLib
+ GpioExpanderLib
+ PcdLib
+ MultiBoardInitSupportLib
+ HdaVerbTableLib
+ PeiPlatformHookLib
+ PeiPolicyInitLib
+ PchInfoLib
+ SiliconInitLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ SecurityPkg/SecurityPkg.dec
+ CoffeelakeSiliconPkg/SiPkg.dec
+ IntelSiliconPkg/IntelSiliconPkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec
+
+[Sources]
+ PeiUpXtremeInitPostMemLib.c
+ PeiMultiBoardInitPostMemLib.c
+ GpioTableDefault.c
+ GpioTableUpXtreme.c
+
+[Pcd]
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableSize
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableTouchPanel
+
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTable
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTableSize
+
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardUcmcGpioTable
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardUcmcGpioTableSize
+
+ #===========================================================
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase
+ # Board Init Table List
+
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTablePreMem
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTablePreMemSize
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMem
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMemSize
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreMem
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreMemSize
+
+ # WWAN Full Card Power Off and reset pins
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdWwanFullCardPowerOffGpio
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdWwanBbrstGpio
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdWwanPerstGpio
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdWwanPerstGpioPolarity
+
+ # SA Misc Config
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSaMiscMmioSizeAdjustment
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqPinsInterleavedControl
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqPinsInterleaved
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSaDdrFreqLimit
+
+ # Display DDI
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSaDisplayConfigTable ## PRODUCES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSaDisplayConfigTableSize ## PRODUCES
+
+ # PEG Reset By GPIO
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPegGpioResetControl
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPegGpioResetSupoort
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPeg0ResetGpioPad
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPeg0ResetGpioActive
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPeg3ResetGpioPad
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPeg3ResetGpioActive
+
+ # PCIE RTD3 GPIO
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRootPortDev
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRootPortFunc
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRootPortIndex
+
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0GpioSupport
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1GpioSupport
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1WakeGpioNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1HoldRstExpanderNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1HoldRstGpioNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1HoldRstActive
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1PwrEnableExpanderNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1PwrEnableGpioNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1PwrEnableActive
+
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2GpioSupport
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2WakeGpioNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2HoldRstExpanderNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2HoldRstGpioNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2HoldRstActive
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2PwrEnableExpanderNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2PwrEnableGpioNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2PwrEnableActive
+
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3GpioSupport
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3WakeGpioNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3HoldRstExpanderNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3HoldRstGpioNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3HoldRstActive
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3PwrEnableExpanderNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3PwrEnableGpioNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3PwrEnableActive
+
+ # CA Vref Configuration
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcCaVrefConfig
+
+ # PCIe Clock Info
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock0
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock1
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock2
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock3
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock4
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock5
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock6
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock7
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock8
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock9
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock10
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock11
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock12
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock13
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock14
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock15
+
+ # USB 2.0 Port AFE
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port10Afe
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port11Afe
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port12Afe
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port13Afe
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port14Afe
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port15Afe
+
+ # USB 2.0 Port Over Current Pin
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort14
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort15
+
+ # USB 3.0 Port Over Current Pin
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort6
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort7
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort8
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort9
+
+ # GPIO Group Tier
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw0
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw1
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw2
+
+ # Pch PmConfig Policy
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSlpS0VmRuntimeControl
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSlpS0Vm070VSupport
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSlpS0Vm075VSupport
+
+ # Misc
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPc8374SioKbcPresent
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdOddPowerInitEnable
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdIvCamInitPresent
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRecoveryModeGpio
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMobileDramPresent
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdCpuVboostEnable
+
+
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpdPresent
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardRev
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardBomId
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPlatformType
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDualDimmPerChannelBoardType
+
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable2 ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable2Size ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDebugUsbUartEnable
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMipiCamGpioEnable
+ # TPM interrupt
+ gEfiSecurityPkgTokenSpaceGuid.PcdTpm2CurrentIrqNum
+
+[Guids]
+ gAttemptUsbFirstHotkeyInfoHobGuid ## CONSUMES
+ gCnlPchLpChipsetInitTableDxGuid ## CONSUMES
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.c
new file mode 100644
index 0000000000..18a44ca534
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.c
@@ -0,0 +1,83 @@
+/** @file
+ Platform Hook Library instances
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiPei.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardInitLib.h>
+#include <Library/MultiBoardInitSupportLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+
+#include <PlatformBoardId.h>
+
+EFI_STATUS
+EFIAPI
+UpXtremeBoardDetect (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+UpXtremeMultiBoardDetect (
+ VOID
+ );
+
+EFI_BOOT_MODE
+EFIAPI
+UpXtremeBoardBootModeDetect (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+UpXtremeBoardDebugInit (
+ VOID
+ );
+
+EFI_STATUS
+EFIAPI
+UpXtremeBoardInitBeforeMemoryInit (
+ VOID
+ );
+
+BOARD_DETECT_FUNC mUpXtremeBoardDetectFunc = {
+ UpXtremeMultiBoardDetect
+};
+
+BOARD_PRE_MEM_INIT_FUNC mUpXtremeBoardPreMemInitFunc = {
+ UpXtremeBoardDebugInit,
+ UpXtremeBoardBootModeDetect,
+ UpXtremeBoardInitBeforeMemoryInit,
+ NULL, // BoardInitAfterMemoryInit
+ NULL, // BoardInitBeforeTempRamExit
+ NULL, // BoardInitAfterTempRamExit
+};
+
+EFI_STATUS
+EFIAPI
+UpXtremeMultiBoardDetect (
+ VOID
+ )
+{
+ UpXtremeBoardDetect ();
+ if (LibPcdGetSku () == BoardIdUpXtreme) {
+ RegisterBoardPreMemInit (&mUpXtremeBoardPreMemInitFunc);
+ }
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+PeiUpXtremeMultiBoardInitPreMemLibConstructor (
+ VOID
+ )
+{
+ return RegisterBoardDetect (&mUpXtremeBoardDetectFunc);
+}
+
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf
new file mode 100644
index 0000000000..2903bdacae
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf
@@ -0,0 +1,308 @@
+## @file
+# Component information file for PEI UpXtreme Board Init Pre-Mem Library
+#
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PeiUpXtremeMultiBoardInitPreMemLib
+ FILE_GUID = EA05BD43-136F-45EE-BBBA-27D75817574F
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = NULL
+ CONSTRUCTOR = PeiUpXtremeMultiBoardInitPreMemLibConstructor
+
+[LibraryClasses]
+ BaseLib
+ BaseMemoryLib
+ DebugLib
+ GpioLib
+ MemoryAllocationLib
+ MultiBoardInitSupportLib
+ OcWdtLib
+ PcdLib
+ PchResetLib
+ PeiPlatformHookLib
+ PeiPolicyInitLib
+ PlatformHookLib
+ SiliconInitLib
+ StallPpiLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+ IntelSiliconPkg/IntelSiliconPkg.dec
+ CoffeelakeSiliconPkg/SiPkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec
+
+[Sources]
+ PeiUpXtremeInitPreMemLib.c
+ UpXtremeHsioPtssTables.c
+ UpXtremeSpdTable.c
+ PeiMultiBoardInitPreMemLib.c
+ PeiUpXtremeDetect.c
+ BoardSaInitPreMemLib.c
+ BoardPchInitPreMemLib.c
+ BoardFuncInitPreMem.c
+
+[Ppis]
+ gEfiPeiReadOnlyVariable2PpiGuid
+ gEfiPeiMemoryDiscoveredPpiGuid ## CONSUMES
+ gEfiPeiResetPpiGuid ## PRODUCES
+
+[Guids]
+ gDebugConfigHobGuid ## CONSUMES
+ gPchGeneralPreMemConfigGuid ## CONSUMES
+ gTcoWdtHobGuid ## CONSUMES
+
+[Pcd]
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioConfigDefaultPort
+
+ # PCH-LP HSIO PTSS Table
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size
+
+ # PCH-H HSIO PTSS Table
+ #gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1
+ #gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2
+ #gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size
+ #gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size
+
+ # SA Misc Config
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSaMiscUserBd
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMap
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMapSize
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2Dram
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdData
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdDataSize
+
+ # PEG Reset By GPIO
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0WakeGpioNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstExpanderNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstGpioNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstActive
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableGpioNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableActive
+
+
+ # SPD Address Table
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable0
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable1
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable2
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable3
+
+ # USB 2.0 Port AFE
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port0Afe
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port1Afe
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port2Afe
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port3Afe
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port4Afe
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port5Afe
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port6Afe
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port7Afe
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port8Afe
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port9Afe
+
+ # USB 2.0 Port Over Current Pin
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort0
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort1
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort2
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort3
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort4
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort5
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort6
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort7
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort8
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort9
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort10
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort11
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort12
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort13
+
+ # USB 3.0 Port Over Current Pin
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort0
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort1
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort2
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort3
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort4
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort5
+
+ # Misc
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdIoExpanderPresent
+
+ #===========================================================
+ # Board Init Table List
+
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTablePreMem
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTablePreMemSize
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMem
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMemSize
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreMem
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreMemSize
+
+ # WWAN Full Card Power Off and reset pins
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdWwanFullCardPowerOffGpio
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdWwanBbrstGpio
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdWwanPerstGpio
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdWwanPerstGpioPolarity
+
+ # SA Misc Config
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSaMiscMmioSizeAdjustment
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqPinsInterleavedControl
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqPinsInterleaved
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSaDdrFreqLimit
+
+ # Display DDI
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSaDisplayConfigTable ## PRODUCES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSaDisplayConfigTableSize ## PRODUCES
+
+ # PEG Reset By GPIO
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPegGpioResetControl
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPegGpioResetSupoort
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPeg0ResetGpioPad
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPeg0ResetGpioActive
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPeg3ResetGpioPad
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPeg3ResetGpioActive
+
+ # PCIE RTD3 GPIO
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRootPortDev
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRootPortFunc
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRootPortIndex
+
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0GpioSupport
+
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1GpioSupport
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1WakeGpioNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1HoldRstExpanderNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1HoldRstGpioNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1HoldRstActive
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1PwrEnableExpanderNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1PwrEnableGpioNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1PwrEnableActive
+
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2GpioSupport
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2WakeGpioNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2HoldRstExpanderNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2HoldRstGpioNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2HoldRstActive
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2PwrEnableExpanderNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2PwrEnableGpioNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2PwrEnableActive
+
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3GpioSupport
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3WakeGpioNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3HoldRstExpanderNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3HoldRstGpioNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3HoldRstActive
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3PwrEnableExpanderNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3PwrEnableGpioNo
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3PwrEnableActive
+
+ # CA Vref Configuration
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcCaVrefConfig
+
+ # PCIe Clock Info
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock0
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock1
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock2
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock3
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock4
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock5
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock6
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock7
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock8
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock9
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock10
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock11
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock12
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock13
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock14
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock15
+
+ # USB 2.0 Port AFE
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port10Afe
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port11Afe
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port12Afe
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port13Afe
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port14Afe
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port15Afe
+
+ # USB 2.0 Port Over Current Pin
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort14
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort15
+
+ # USB 3.0 Port Over Current Pin
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort6
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort7
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort8
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort9
+
+ # GPIO Group Tier
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw0
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw1
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw2
+
+ # Pch PmConfig Policy
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSlpS0VmRuntimeControl
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSlpS0Vm070VSupport
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSlpS0Vm075VSupport
+
+ # Misc
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPc8374SioKbcPresent
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdOddPowerInitEnable
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdIvCamInitPresent
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRecoveryModeGpio
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMobileDramPresent
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdCpuVboostEnable
+
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpdPresent
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardRev
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardBomId
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPlatformType
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDualDimmPerChannelBoardType
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength ## CONSUMES
+
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieWwanEnable
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdWwanResetWorkaround ## PRODUCES
+ gSiPkgTokenSpaceGuid.PcdTcoBaseAddress
+
+ gSiPkgTokenSpaceGuid.PcdSerialIoUartEnable ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate ## CONSUMES
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel ## CONSUMES
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemorySize
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize
+ gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
+
+[FixedPcd]
+ gSiPkgTokenSpaceGuid.PcdMchBaseAddress ## CONSUMES
+ gSiPkgTokenSpaceGuid.PcdMchMmioSize ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdDmiBaseAddress ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdDmiMmioSize ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdEpBaseAddress ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdEpMmioSize ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdGdxcBaseAddress ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdGdxcMmioSize ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdApicLocalAddress ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdApicLocalMmioSize ## CONSUMES
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/PeiUpXtremeDetect.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/PeiUpXtremeDetect.c
new file mode 100644
index 0000000000..5860ab364b
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/PeiUpXtremeDetect.c
@@ -0,0 +1,192 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiPei.h>
+#include <SaPolicyCommon.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/IoLib.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PchCycleDecodingLib.h>
+#include <Library/PciLib.h>
+#include <Library/PcdLib.h>
+#include <Library/BaseMemoryLib.h>
+
+#include <Library/PeiSaPolicyLib.h>
+#include <Library/BoardInitLib.h>
+#include <PchAccess.h>
+#include <Library/GpioNativeLib.h>
+#include <Library/GpioLib.h>
+#include <Library/PchPcrLib.h>
+#include <Library/PcdLib.h>
+#include <Library/GpioExpanderLib.h>
+
+
+#include <GpioPinsSklLp.h>
+#include <GpioPinsSklH.h>
+#include <SioRegs.h>
+#include <GpioPinsCnlLp.h>
+#include <CpuRegs.h>
+//#include <CpuDataStruct.h>
+#include <CpuAccess.h>
+#include <Register/Cpuid.h>
+#include "UpXtremeInit.h"
+#include <ConfigBlock.h>
+#include <ConfigBlock/MemoryConfig.h>
+
+
+
+
+CONST UINT32 mUpxGpioBomPad[] = {
+ GPIO_CNL_LP_GPP_C10, // BRD_ID2
+ GPIO_CNL_LP_GPP_C9, // BRD_ID1
+ GPIO_CNL_LP_GPP_C8, // BRD_ID0
+ GPIO_CNL_LP_GPP_A23, // DDR_ID2
+ GPIO_CNL_LP_GPP_A18, // DDR_ID1
+ GPIO_CNL_LP_GPP_C11, // DDR_ID0
+};
+
+CONST GPIO_INIT_CONFIG mUpxBomGpioTemplate = {
+ GPIO_CNL_LP_GPP_C10, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis, GpioHostDeepReset, GpioTermNone}
+};
+
+/**
+ Prints the processor information
+**/
+VOID
+PrintCpuInformation (
+ VOID
+ )
+{
+ UINT32 MaximumExtendedFunction;
+ UINT16 CpuDid;
+ UINT32 CpuFamilyModel;
+ UINT8 CpuStepping;
+ EFI_CPUID_REGISTER Cpuid;
+ //
+ // Array to store brand string from 3 brand string leafs with
+ // 4 32-bit brand string values per leaf and an extra value to
+ // null terminate the string.
+ //
+ UINT32 BrandString[3 * 4 + 1];
+ CHAR8 *AsciiBrandString;
+ CHAR16 *UnicodeBrandString;
+ UINTN Length;
+
+ AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaximumExtendedFunction, NULL, NULL, NULL);
+
+ ZeroMem (&BrandString, sizeof (BrandString));
+ if (CPUID_BRAND_STRING1 <= MaximumExtendedFunction) {
+ AsmCpuid (
+ CPUID_BRAND_STRING1,
+ &BrandString[0],
+ &BrandString[1],
+ &BrandString[2],
+ &BrandString[3]
+ );
+ }
+ if (CPUID_BRAND_STRING2 <= MaximumExtendedFunction) {
+ AsmCpuid (
+ CPUID_BRAND_STRING2,
+ &BrandString[4],
+ &BrandString[5],
+ &BrandString[6],
+ &BrandString[7]
+ );
+ }
+ if (CPUID_BRAND_STRING3 <= MaximumExtendedFunction) {
+ AsmCpuid (
+ CPUID_BRAND_STRING3,
+ &BrandString[8],
+ &BrandString[9],
+ &BrandString[10],
+ &BrandString[11]
+ );
+ }
+
+ //
+ // Skip spaces at the beginning of the brand string
+ //
+ for (AsciiBrandString = (CHAR8 *)BrandString; *AsciiBrandString == ' '; AsciiBrandString++);
+
+ DEBUG ((DEBUG_INFO, "Processor Brand String = %a\n", AsciiBrandString));
+
+ //
+ // Convert ASCII brand string to an allocated Unicode brand string
+ //
+ Length = AsciiStrLen (AsciiBrandString) + 1;
+ UnicodeBrandString = AllocatePool (Length * sizeof (CHAR16));
+ AsciiStrToUnicodeStrS (AsciiBrandString, UnicodeBrandString, Length);
+
+ DEBUG ((DEBUG_INFO, "Processor Unicode Brand String = %s\n", UnicodeBrandString));
+
+ ///
+ /// Read the CPUID & DID information
+ ///
+ AsmCpuid (CPUID_VERSION_INFO, &Cpuid.RegEax, &Cpuid.RegEbx, &Cpuid.RegEcx, &Cpuid.RegEdx);
+ CpuFamilyModel = Cpuid.RegEax & CPUID_FULL_FAMILY_MODEL;
+ CpuStepping = (Cpuid.RegEax & 0xF);
+ CpuDid = PciRead16 (PCI_LIB_ADDRESS (SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, R_SA_MC_DEVICE_ID));
+
+ DEBUG ((DEBUG_ERROR, "CpuFamilyModel 0x%X, CpuStepping 0x%X, CpuDid 0x%X\n", CpuFamilyModel, CpuStepping, CpuDid));
+}
+
+
+EFI_STATUS
+EFIAPI
+UpXtremeBoardDetect (
+ VOID
+ )
+{
+ UINT32 GpioData;
+ GPIO_INIT_CONFIG UpxBomGpioTemplate;
+ UINT8 BomId;
+ UINT8 Index;
+ UINTN NumberOfGpios;
+ EFI_STATUS Status;
+
+ DEBUG ((DEBUG_INFO, "UpXtremeDetectionCallback\n"));
+
+ PrintCpuInformation ();
+
+ if (LibPcdGetSku () != 0) {
+ return EFI_SUCCESS;
+ }
+
+ BomId = 0;
+ NumberOfGpios = ARRAY_SIZE (mUpxGpioBomPad);
+
+ LibPcdSetSku (BoardIdUpXtreme);
+
+ DEBUG ((DEBUG_INFO, "SKU_ID: 0x%x\n", LibPcdGetSku ()));
+ ASSERT (LibPcdGetSku () == BoardIdUpXtreme);
+
+ CopyMem (&UpxBomGpioTemplate, &mUpxBomGpioTemplate, sizeof(UpxBomGpioTemplate));
+
+ // Initialize all GPIO pins to input
+ for (Index = 0; Index < NumberOfGpios; Index++) {
+ UpxBomGpioTemplate.GpioPad = mUpxGpioBomPad[Index];
+ GpioConfigurePads (1, &UpxBomGpioTemplate);
+ }
+
+ // Sample the GPIO pin level
+ for (Index = 0; Index < NumberOfGpios; Index++) {
+ Status = GpioGetInputValue (mUpxGpioBomPad[Index], &GpioData);
+ if (EFI_ERROR(Status)) {
+ break;
+ }
+ BomId = (BomId << 1) + (GpioData & 1);
+ }
+
+ if (Index == NumberOfGpios) {
+ PcdSet8S(PcdBoardBomId, BomId);
+ }
+
+ DEBUG ((DEBUG_INFO, "BOM_ID 0x%x\n", PcdGet8(PcdBoardBomId)));
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/PeiUpXtremeInitPostMemLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/PeiUpXtremeInitPostMemLib.c
new file mode 100644
index 0000000000..65433bc453
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/PeiUpXtremeInitPostMemLib.c
@@ -0,0 +1,416 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiPei.h>
+#include <SaPolicyCommon.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/HdaVerbTableLib.h>
+#include <Library/IoLib.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PchCycleDecodingLib.h>
+#include <Library/PciLib.h>
+#include <Library/PeiSaPolicyLib.h>
+#include <Library/BoardInitLib.h>
+#include <Library/ConfigBlockLib.h>
+#include <PchAccess.h>
+#include <Library/GpioNativeLib.h>
+#include <Library/GpioLib.h>
+#include <GpioPinsSklLp.h>
+#include <GpioPinsSklH.h>
+#include <Library/GpioExpanderLib.h>
+#include <SioRegs.h>
+#include <Library/PchPcrLib.h>
+#include <IoExpander.h>
+#include <AttemptUsbFirst.h>
+#include <PeiPlatformHookLib.h>
+#include <Library/PeiPolicyInitLib.h>
+#include <Library/PchInfoLib.h>
+#include <FirwmareConfigurations.h>
+#include "UpXtremeInit.h"
+
+/**
+GPIO init function for PEI post memory phase.
+
+@param[in] BoardId An unsigned integrer represent the board id.
+
+@retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+BoardGpioInit (
+ IN UINT16 BoardId
+ )
+{
+ //
+ // GPIO Table Init.
+ //
+ switch (BoardId) {
+
+ case BoardIdUpXtreme:
+ PcdSet32S (PcdBoardGpioTable, (UINTN) mGpioTableUpXtreme);
+ PcdSet16S (PcdBoardGpioTableSize, mGpioTableUpXtremeSize);
+ break;
+
+ default:
+ DEBUG ((DEBUG_INFO, "For Unknown Board ID..Use Default GPIO Table...\n"));
+ PcdSet32S (PcdBoardGpioTable, (UINTN) mGpioTableDefault);
+ PcdSet16S (PcdBoardGpioTableSize, mGpioTableDefaultSize);
+ break;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+Touch panel GPIO init function for PEI post memory phase.
+
+@param[in] BoardId An unsigned integrer represent the board id.
+
+@retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+TouchPanelGpioInit (
+ IN UINT16 BoardId
+ )
+{
+ switch (BoardId) {
+ default:
+ PcdSet32S(PcdBoardGpioTableTouchPanel, 0);
+ break;
+ }
+ return EFI_SUCCESS;
+}
+
+/**
+Misc. init function for PEI post memory phase.
+
+@param[in] BoardId An unsigned integrer represent the board id.
+
+@retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+BoardMiscInit (
+ IN UINT16 BoardId
+ )
+{
+ PcdSetBoolS(PcdDebugUsbUartEnable, FALSE);
+
+ switch (BoardId) {
+
+ // todo for UP Xtreme
+ case BoardIdWhiskeyLakeRvp:
+
+ PcdSetBoolS(PcdMipiCamGpioEnable, TRUE);
+ break;
+
+ default:
+ PcdSetBoolS(PcdMipiCamGpioEnable, FALSE);
+ break;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+Security GPIO init function for PEI post memory phase.
+
+@param[in] BoardId An unsigned integrer represent the board id.
+
+@retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+BoardSecurityInit (
+ IN UINT16 BoardId
+ )
+{
+ return EFI_SUCCESS;
+}
+
+/**
+ Board configuration initialization in the post-memory boot phase.
+
+**/
+VOID
+BoardConfigInit (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ UINT16 BoardId;
+
+ BoardId = BoardIdUpXtreme;
+
+ Status = BoardGpioInit (BoardId);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = TouchPanelGpioInit (BoardId);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = HdaVerbTableInit (BoardId);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = BoardMiscInit (BoardId);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = BoardSecurityInit (BoardId);
+ ASSERT_EFI_ERROR (Status);
+}
+
+//@todo Review this functionality and if it is required for WHL SDS
+/**
+Create the HOB for hotkey status for 'Attempt USB First' feature
+
+@retval EFI_SUCCESS HOB Creating successful.
+@retval Others HOB Creating failed.
+**/
+EFI_STATUS
+CreateAttemptUsbFirstHotkeyInfoHob (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ ATTEMPT_USB_FIRST_HOTKEY_INFO AttemptUsbFirstHotkeyInfo;
+
+ Status = EFI_SUCCESS;
+
+ ZeroMem(
+ &AttemptUsbFirstHotkeyInfo,
+ sizeof(AttemptUsbFirstHotkeyInfo)
+ );
+
+ AttemptUsbFirstHotkeyInfo.RevisonId = 0;
+ AttemptUsbFirstHotkeyInfo.HotkeyTriggered = FALSE;
+
+ ///
+ /// Build HOB for Attempt USB First feature
+ ///
+ BuildGuidDataHob(
+ &gAttemptUsbFirstHotkeyInfoHobGuid,
+ &(AttemptUsbFirstHotkeyInfo),
+ sizeof(ATTEMPT_USB_FIRST_HOTKEY_INFO)
+ );
+
+ return Status;
+}
+
+/**
+Search and identify the physical address of a
+file module inside the FW_BINARIES_FV_SIGNED FV
+
+@retval EFI_SUCCESS If address has been found
+@retval Others If address has not been found
+**/
+EFI_STATUS
+FindModuleInFlash2 (
+ IN EFI_FIRMWARE_VOLUME_HEADER *FvHeader,
+ IN EFI_GUID *GuidPtr,
+ IN OUT UINT32 *ModulePtr,
+ IN OUT UINT32 *ModuleSize
+ )
+{
+ EFI_FFS_FILE_HEADER *FfsHeader;
+ EFI_FV_FILE_INFO FileInfo;
+ EFI_PEI_FILE_HANDLE FileHandle;
+ EFI_COMMON_SECTION_HEADER *SectionHeader;
+ VOID *FileBuffer;
+ EFI_STATUS Status;
+
+ FfsHeader = NULL;
+ FileHandle = NULL;
+ SectionHeader = NULL;
+ FileBuffer = NULL;
+
+ while (TRUE) {
+ //
+ // Locate FV_IMAGE file type in the FW_BINARIES_FV_SIGNED firmware volume
+ //
+ Status = PeiServicesFfsFindNextFile(EFI_FV_FILETYPE_FIRMWARE_VOLUME_IMAGE, FvHeader, &FileHandle);
+ if (EFI_ERROR(Status)) {
+ // unable to find FV_IMAGE file in this FV
+ break;
+ }
+
+ FfsHeader = (EFI_FFS_FILE_HEADER*)FileHandle;
+ DEBUG((DEBUG_INFO, "FfsHeader 0x%X:\n", FfsHeader));
+ DEBUG((DEBUG_INFO, " Name = 0x%g\n", &FfsHeader->Name));
+ DEBUG((DEBUG_INFO, " Type = 0x%X\n", FfsHeader->Type));
+ if (IS_FFS_FILE2(FfsHeader)) {
+ DEBUG((DEBUG_INFO, " Size = 0x%X\n", FFS_FILE2_SIZE(FfsHeader)));
+ }
+ else {
+ DEBUG((DEBUG_INFO, " Size = 0x%X\n", FFS_FILE_SIZE(FfsHeader)));
+ }
+
+ //
+ // Locate FW_BINARIES_FV FV_IMAGE Section
+ //
+ Status = PeiServicesFfsFindSectionData(EFI_SECTION_FIRMWARE_VOLUME_IMAGE, FileHandle, &FileBuffer);
+ if (EFI_ERROR(Status)) {
+ // continue to search for the next FV_IMAGE file
+ DEBUG((DEBUG_INFO, "FW_BINARIES_FV section not found. Status = %r\n", Status));
+ continue;
+ }
+
+ SectionHeader = (EFI_COMMON_SECTION_HEADER *)FileBuffer;
+ DEBUG((DEBUG_INFO, "GUIDED SectionHeader 0x%X:\n",
+ (UINT32)(UINT8 *)SectionHeader));
+ if (IS_SECTION2(SectionHeader)) {
+ DEBUG((DEBUG_INFO, " Guid = 0x%g\n",
+ &((EFI_GUID_DEFINED_SECTION2 *)SectionHeader)->SectionDefinitionGuid));
+ DEBUG((DEBUG_INFO, " DataOfset = 0x%X\n",
+ ((EFI_GUID_DEFINED_SECTION2 *)SectionHeader)->DataOffset));
+ }
+ else {
+ DEBUG((DEBUG_INFO, " Guid = 0x%g\n",
+ &((EFI_GUID_DEFINED_SECTION *)SectionHeader)->SectionDefinitionGuid));
+ DEBUG((DEBUG_INFO, " DataOfset = 0x%X\n",
+ ((EFI_GUID_DEFINED_SECTION *)SectionHeader)->DataOffset));
+ }
+ DEBUG((DEBUG_INFO, " Type = 0x%X\n", SectionHeader->Type));
+
+ //
+ // Locate Firmware File System file within Firmware Volume
+ //
+ Status = PeiServicesFfsFindFileByName(GuidPtr, FileBuffer, (VOID **)&FfsHeader);
+ if (EFI_ERROR(Status)) {
+ // continue to search for the next FV_IMAGE file
+ DEBUG((DEBUG_INFO, "Module not found. Status = %r\n", Status));
+ continue;
+ }
+
+ *ModulePtr = (UINT32)((UINT8 *)FfsHeader + sizeof(EFI_FFS_FILE_HEADER));
+
+ //
+ // Get File Information
+ //
+ Status = PeiServicesFfsGetFileInfo(FfsHeader, &FileInfo);
+ if (!EFI_ERROR(Status)) {
+ *ModuleSize = (UINT32)FileInfo.BufferSize;
+ DEBUG((DEBUG_INFO, "Module {0x%g} found at = 0x%X, Size = 0x%X\n",
+ &FfsHeader->Name, *ModulePtr, *ModuleSize));
+ return Status;
+ }
+ }
+
+ return EFI_NOT_FOUND;
+}
+
+/**
+Get the ChipsetInit Binary pointer.
+
+@retval EFI_SUCCESS - ChipsetInit Binary found.
+@retval EFI_NOT_FOUND - ChipsetInit Binary not found.
+**/
+EFI_STATUS
+UpdateChipsetInitPtr (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ PCH_STEPPING PchStep;
+ EFI_FIRMWARE_VOLUME_HEADER *FvHeader;
+ EFI_GUID *ChipsetInitBinaryGuidPtr;
+ SI_POLICY_PPI *SiPolicyPpi;
+ PCH_HSIO_CONFIG *HsioConfig;
+ UINT32 ModuleAddr;
+ UINT32 ModuleSize;
+
+ ModuleAddr = 0;
+ ModuleSize = 0;
+ PchStep = PchStepping();
+
+ Status = PeiServicesLocatePpi(
+ &gSiPolicyPpiGuid,
+ 0,
+ NULL,
+ (VOID **)&SiPolicyPpi
+ );
+ ASSERT_EFI_ERROR(Status);
+
+ Status = GetConfigBlock((VOID *)SiPolicyPpi, &gHsioConfigGuid, (VOID *)&HsioConfig);
+ ASSERT_EFI_ERROR(Status);
+
+ ChipsetInitBinaryGuidPtr = NULL;
+ if (IsPchLp()) {
+ switch (PchStep) {
+ case PCH_D0:
+ case PCH_D1:
+ ChipsetInitBinaryGuidPtr = &gCnlPchLpChipsetInitTableDxGuid;
+ DEBUG((DEBUG_INFO, "Using CnlPchLpChipsetInitTable_Dx table \n"));
+ break;
+ default:
+ return EFI_NOT_FOUND;
+ }
+ }
+ else {
+ return EFI_NOT_FOUND;
+ }
+
+ //
+ // Locate Firmware Volume header
+ //
+ FvHeader = (EFI_FIRMWARE_VOLUME_HEADER *) FixedPcdGet32(PcdFlashFvPostMemoryBase);
+ Status = FindModuleInFlash2(FvHeader, ChipsetInitBinaryGuidPtr, &ModuleAddr, &ModuleSize);
+ //
+ // Get ChipsetInit Binary Pointer
+ //
+ HsioConfig->ChipsetInitBinPtr = ModuleAddr;
+
+ //
+ // Get File Size
+ //
+ HsioConfig->ChipsetInitBinLen = ModuleSize;
+
+ DEBUG((DEBUG_INFO, "ChipsetInit Binary Location: %x\n", HsioConfig->ChipsetInitBinPtr));
+ DEBUG((DEBUG_INFO, "ChipsetInit Binary Size: %x\n", HsioConfig->ChipsetInitBinLen));
+
+ return Status;
+}
+
+/**
+ Configure GPIO and SIO
+
+ @retval EFI_SUCCESS Operation success.
+**/
+EFI_STATUS
+EFIAPI
+UpXtremeBoardInitBeforeSiliconInit (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ UINT8 FwConfig;
+
+ BoardConfigInit();
+ //
+ // Configure GPIO and SIO
+ //
+ Status = BoardInit();
+ ASSERT_EFI_ERROR(Status);
+
+ FwConfig = FwConfigProduction;
+ PeiPolicyInit(FwConfig);
+
+ //
+ // Create USB Boot First hotkey information HOB
+ //
+ CreateAttemptUsbFirstHotkeyInfoHob();
+
+ //
+ // Initializing Platform Specific Programming
+ //
+ Status = PlatformSpecificInit();
+ ASSERT_EFI_ERROR(Status);
+
+ //
+ // Update ChipsetInitPtr
+ //
+ Status = UpdateChipsetInitPtr();
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/PeiUpXtremeInitPreMemLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/PeiUpXtremeInitPreMemLib.c
new file mode 100644
index 0000000000..0d55078943
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/PeiUpXtremeInitPreMemLib.c
@@ -0,0 +1,659 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiPei.h>
+#include <SaPolicyCommon.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/IoLib.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PchCycleDecodingLib.h>
+#include <Library/PciLib.h>
+#include <Library/PcdLib.h>
+#include <Library/BaseMemoryLib.h>
+
+#include <Library/PeiSaPolicyLib.h>
+#include <Library/BoardInitLib.h>
+#include <PchAccess.h>
+#include <Library/GpioNativeLib.h>
+#include <Library/GpioLib.h>
+#include <GpioPinsSklLp.h>
+#include <GpioPinsSklH.h>
+#include <Library/GpioExpanderLib.h>
+#include <SioRegs.h>
+#include <Library/PchPcrLib.h>
+
+#include "UpXtremeInit.h"
+#include <ConfigBlock.h>
+#include <Setup.h>
+#include <ConfigBlock/MemoryConfig.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/PchPcrLib.h>
+#include <Library/PchInfoLib.h>
+#include <Register/PchRegsPcr.h>
+#include <Library/PchResetLib.h>
+#include <Register/PchRegsLpc.h>
+#include <Library/StallPpiLib.h>
+#include <Library/PeiPolicyInitLib.h>
+#include <Ppi/Reset.h>
+#include <PlatformBoardConfig.h>
+#include <GpioPinsCnlLp.h>
+#include <Library/PmcLib.h>
+#include <Library/PciSegmentLib.h>
+#include <PeiPlatformHookLib.h>
+#include <FirwmareConfigurations.h>
+#include <Guid/TcoWdtHob.h>
+#include <Library/OcWdtLib.h>
+#include <CpuRegs.h>
+#include <Library/BaseLib.h>
+
+///
+/// Reset Generator I/O Port
+///
+#define RESET_GENERATOR_PORT 0xCF9
+
+
+#define MSR_CACHE_VARIABLE_MTRR_BASE 0x00000200
+#define CACHE_WRITEPROTECTED 5
+
+typedef struct {
+ EFI_PHYSICAL_ADDRESS BaseAddress;
+ UINT64 Length;
+} MEMORY_MAP;
+
+GLOBAL_REMOVE_IF_UNREFERENCED MEMORY_MAP MmioMap[] = {
+ { FixedPcdGet64(PcdApicLocalAddress), FixedPcdGet32(PcdApicLocalMmioSize) },
+ { FixedPcdGet64(PcdMchBaseAddress), FixedPcdGet32(PcdMchMmioSize) },
+ { FixedPcdGet64(PcdDmiBaseAddress), FixedPcdGet32(PcdDmiMmioSize) },
+ { FixedPcdGet64(PcdEpBaseAddress), FixedPcdGet32(PcdEpMmioSize) },
+ { FixedPcdGet64(PcdGdxcBaseAddress), FixedPcdGet32(PcdGdxcMmioSize) }
+};
+
+EFI_STATUS
+MrcConfigInit(
+ IN UINT16 BoardId
+);
+
+EFI_STATUS
+SaGpioConfigInit(
+ IN UINT16 BoardId
+);
+
+EFI_STATUS
+ SaMiscConfigInit(
+IN UINT16 BoardId
+);
+
+EFI_STATUS
+ RootPortClkInfoInit(
+IN UINT16 BoardId
+);
+
+EFI_STATUS
+ UsbConfigInit(
+IN UINT16 BoardId
+);
+
+EFI_STATUS
+GpioGroupTierInit(
+ IN UINT16 BoardId
+);
+
+EFI_STATUS
+GpioTablePreMemInit(
+ IN UINT16 BoardId
+);
+
+EFI_STATUS
+PchPmConfigInit(
+ IN UINT16 BoardId
+);
+
+EFI_STATUS
+SaDisplayConfigInit(
+ IN UINT16 BoardId
+);
+
+EFI_STATUS
+EFIAPI
+PlatformInitPreMemCallBack(
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+);
+
+EFI_STATUS
+EFIAPI
+MemoryDiscoveredPpiNotify(
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+);
+
+EFI_STATUS
+EFIAPI
+PchReset(
+ IN CONST EFI_PEI_SERVICES **PeiServices
+);
+
+static EFI_PEI_RESET_PPI mResetPpi = {
+ PchReset
+};
+
+static EFI_PEI_PPI_DESCRIPTOR mPreMemPpiList[] = {
+ {
+ (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gEfiPeiResetPpiGuid,
+ &mResetPpi
+ }
+};
+
+static EFI_PEI_NOTIFY_DESCRIPTOR mPreMemNotifyList = {
+ (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gEfiPeiReadOnlyVariable2PpiGuid,
+ (EFI_PEIM_NOTIFY_ENTRY_POINT)PlatformInitPreMemCallBack
+};
+
+static EFI_PEI_NOTIFY_DESCRIPTOR mMemDiscoveredNotifyList = {
+ (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gEfiPeiMemoryDiscoveredPpiGuid,
+ (EFI_PEIM_NOTIFY_ENTRY_POINT)MemoryDiscoveredPpiNotify
+};
+
+/**
+Board misc init function for PEI pre-memory phase.
+
+@param[in] BoardId An unsigned integer represent the board id.
+
+@retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+BoardMiscInitPreMem(
+ IN UINT16 BoardId
+ )
+{
+ //
+ // Configure WWAN Full Card Power Off and reset pins
+ //
+ switch (BoardId) {
+ // todo for UP Xtreme
+ case BoardIdWhiskeyLakeRvp:
+ //
+ // According to board default settings, GPP_D16 is used to enable/disable modem
+ // power. An alternative way to contol modem power is to toggle FCP_OFF via GPP_D13
+ // but board rework is required.
+ //
+ PcdSet32S (PcdWwanFullCardPowerOffGpio, GPIO_CNL_LP_GPP_D16);
+ PcdSet32S (PcdWwanBbrstGpio, GPIO_CNL_LP_GPP_F1);
+ PcdSet32S (PcdWwanPerstGpio, GPIO_CNL_LP_GPP_E15);
+ PcdSet8S (PcdWwanPerstGpioPolarity, 1);
+ break;
+
+ default:
+ break;
+ }
+
+ //
+ // Pc8374SioKbc Present
+ //
+ PcdSetBoolS (PcdPc8374SioKbcPresent, FALSE);
+
+ return EFI_SUCCESS;
+}
+
+//@todo it should be moved to Si Pkg.
+/**
+Early Platform PCH initialization
+**/
+VOID
+EarlyPlatformPchInit(
+ VOID
+)
+{
+ UINT8 Data8;
+ UINT16 Data16;
+ UINT8 TcoRebootHappened;
+ TCO_WDT_HOB *TcoWdtHobPtr;
+ EFI_STATUS Status;
+
+ ///
+ /// Halt the TCO timer
+ ///
+ Data16 = IoRead16 (PcdGet16 (PcdTcoBaseAddress) + R_TCO_IO_TCO1_CNT);
+ Data16 |= B_TCO_IO_TCO1_CNT_TMR_HLT;
+ IoWrite16 (PcdGet16 (PcdTcoBaseAddress) + R_TCO_IO_TCO1_CNT, Data16);
+
+ ///
+ /// Read the Second TO status bit
+ ///
+ Data8 = IoRead8 (PcdGet16 (PcdTcoBaseAddress) + R_TCO_IO_TCO2_STS);
+ if ((Data8 & B_TCO_IO_TCO2_STS_SECOND_TO) == B_TCO_IO_TCO2_STS_SECOND_TO) {
+ TcoRebootHappened = 1;
+ DEBUG ((DEBUG_INFO, "PlatformInitPreMem - TCO Second TO status bit is set. This might be a TCO reboot\n"));
+ }
+ else {
+ TcoRebootHappened = 0;
+ }
+
+ ///
+ /// Create HOB
+ ///
+ Status = PeiServicesCreateHob (EFI_HOB_TYPE_GUID_EXTENSION, sizeof (TCO_WDT_HOB), (VOID **) &TcoWdtHobPtr);
+ if (!EFI_ERROR (Status)) {
+ TcoWdtHobPtr->Header.Name = gTcoWdtHobGuid;
+ TcoWdtHobPtr->TcoRebootHappened = TcoRebootHappened;
+ }
+
+ ///
+ /// Clear the Second TO status bit
+ ///
+ IoWrite8 (PcdGet16(PcdTcoBaseAddress) + R_TCO_IO_TCO2_STS, B_TCO_IO_TCO2_STS_SECOND_TO);
+}
+
+/**
+ Board configuration initialization in the pre-memory boot phase.
+
+**/
+VOID
+BoardConfigInitPreMem (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ UINT16 BoardId;
+
+ BoardId = BoardIdUpXtreme;
+
+ Status = MrcConfigInit (BoardId);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = SaGpioConfigInit (BoardId);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = SaMiscConfigInit (BoardId);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = RootPortClkInfoInit (BoardId);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = UsbConfigInit (BoardId);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = GpioGroupTierInit (BoardId);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = GpioTablePreMemInit (BoardId);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = PchPmConfigInit (BoardId);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = BoardMiscInitPreMem (BoardId);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = SaDisplayConfigInit (BoardId);
+ ASSERT_EFI_ERROR (Status);
+}
+
+/**
+This function handles PlatformInit task after PeiReadOnlyVariable2 PPI produced
+
+@param[in] PeiServices Pointer to PEI Services Table.
+@param[in] NotifyDesc Pointer to the descriptor for the Notification event that
+ caused this function to execute.
+@param[in] Ppi Pointer to the PPI data associated with this function.
+
+@retval EFI_SUCCESS The function completes successfully
+@retval others
+**/
+EFI_STATUS
+EFIAPI
+PlatformInitPreMemCallBack(
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+)
+{
+ EFI_STATUS Status;
+ UINT16 ABase;
+ UINT8 FwConfig;
+
+ //
+ // Init Board Config Pcd.
+ //
+ BoardConfigInitPreMem ();
+
+ FwConfig = FwConfigProduction;
+ PcdSetBoolS (PcdPcieWwanEnable, FALSE);
+ PcdSetBoolS (PcdWwanResetWorkaround, FALSE);
+
+ //
+ // Early Board Configuration before memory is ready.
+ //
+ Status = BoardInitEarlyPreMem ();
+ ASSERT_EFI_ERROR (Status);
+
+ ///
+ /// If there was unexpected reset but no WDT expiration and no resume from S3/S4,
+ /// clear unexpected reset status and enforce expiration. This is to inform Firmware
+ /// which has no access to unexpected reset status bit, that something went wrong.
+ ///
+ OcWdtResetCheck ();
+
+ Status = OcWdtInit ();
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Initialize Intel PEI Platform Policy
+ //
+ PeiPolicyInitPreMem (FwConfig);
+
+ ///
+ /// Configure GPIO and SIO
+ ///
+ Status = BoardInitPreMem ();
+ ASSERT_EFI_ERROR (Status);
+
+ ABase = PmcGetAcpiBase ();
+
+ ///
+ /// Clear all pending SMI. On S3 clear power button enable so it will not generate an SMI.
+ ///
+ IoWrite16 (ABase + R_ACPI_IO_PM1_EN, 0);
+ IoWrite32 (ABase + R_ACPI_IO_GPE0_EN_127_96, 0);
+
+ ///
+ /// Install Pre Memory PPIs
+ ///
+ Status = PeiServicesInstallPpi (&mPreMemPpiList[0]);
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
+/**
+Provide hard reset PPI service.
+To generate full hard reset, write 0x0E to PCH RESET_GENERATOR_PORT (0xCF9).
+
+@param[in] PeiServices General purpose services available to every PEIM.
+
+@retval Not return System reset occured.
+@retval EFI_DEVICE_ERROR Device error, could not reset the system.
+**/
+EFI_STATUS
+EFIAPI
+PchReset(
+ IN CONST EFI_PEI_SERVICES **PeiServices
+)
+{
+ DEBUG ((DEBUG_INFO, "Perform Cold Reset\n"));
+ IoWrite8 (RESET_GENERATOR_PORT, 0x0E);
+
+ CpuDeadLoop ();
+
+ ///
+ /// System reset occured, should never reach at this line.
+ ///
+ ASSERT_EFI_ERROR (EFI_DEVICE_ERROR);
+
+ return EFI_DEVICE_ERROR;
+}
+
+/**
+Install Firmware Volume Hob's once there is main memory
+
+@param[in] PeiServices General purpose services available to every PEIM.
+@param[in] NotifyDescriptor Notify that this module published.
+@param[in] Ppi PPI that was installed.
+
+@retval EFI_SUCCESS The function completed successfully.
+**/
+EFI_STATUS
+EFIAPI
+MemoryDiscoveredPpiNotify(
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,
+ IN VOID *Ppi
+)
+{
+ EFI_STATUS Status;
+ EFI_BOOT_MODE BootMode;
+ UINTN Index;
+ UINT8 PhysicalAddressBits;
+ UINT32 RegEax;
+ MEMORY_MAP PcieMmioMap;
+
+ Index = 0;
+
+ Status = PeiServicesGetBootMode (&BootMode);
+ ASSERT_EFI_ERROR (Status);
+
+ AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
+ if (RegEax >= 0x80000008) {
+ AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
+ PhysicalAddressBits = (UINT8) RegEax;
+ }
+ else {
+ PhysicalAddressBits = 36;
+ }
+
+ ///
+ /// Create a CPU hand-off information
+ ///
+ BuildCpuHob (PhysicalAddressBits, 16);
+
+ ///
+ /// Build Memory Mapped IO Resource which is used to build E820 Table in LegacyBios.
+ ///
+ PcieMmioMap.BaseAddress = FixedPcdGet64 (PcdPciExpressBaseAddress);
+ PcieMmioMap.Length = PcdGet32 (PcdPciExpressRegionLength);
+
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_MEMORY_MAPPED_IO,
+ (EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
+ PcieMmioMap.BaseAddress,
+ PcieMmioMap.Length
+ );
+ BuildMemoryAllocationHob (
+ PcieMmioMap.BaseAddress,
+ PcieMmioMap.Length,
+ EfiMemoryMappedIO
+ );
+ for (Index = 0; Index < sizeof (MmioMap) / (sizeof (MEMORY_MAP)); Index++) {
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_MEMORY_MAPPED_IO,
+ (EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
+ MmioMap[Index].BaseAddress,
+ MmioMap[Index].Length
+ );
+ BuildMemoryAllocationHob (
+ MmioMap[Index].BaseAddress,
+ MmioMap[Index].Length,
+ EfiMemoryMappedIO
+ );
+ }
+
+ //
+ // Report resource HOB for flash FV
+ //
+ BuildResourceDescriptorHob (
+ EFI_RESOURCE_MEMORY_MAPPED_IO,
+ (EFI_RESOURCE_ATTRIBUTE_PRESENT |
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
+ (UINTN) FixedPcdGet32 (PcdFlashAreaBaseAddress),
+ (UINTN) FixedPcdGet32 (PcdFlashAreaSize)
+ );
+ BuildMemoryAllocationHob (
+ (UINTN) FixedPcdGet32 (PcdFlashAreaBaseAddress),
+ (UINTN) FixedPcdGet32 (PcdFlashAreaSize),
+ EfiMemoryMappedIO
+ );
+
+ BuildFvHob (
+ (UINTN) FixedPcdGet32 (PcdFlashAreaBaseAddress),
+ (UINTN) FixedPcdGet32 (PcdFlashAreaSize)
+ );
+
+ return Status;
+}
+
+
+/**
+ Increases the code cache size
+**/
+VOID
+EFIAPI
+EnlargeCodeCacheRegion (
+ VOID
+ )
+{
+ UINT32 MsrIndex;
+ UINT32 NewCodeCacheSize;
+ UINT32 AdjustedSize;
+ UINT64 MaskLen;
+
+ //
+ // MTRR is patched to enable a larger code cache to avoid performance penalty.
+ //
+ NewCodeCacheSize = PcdGet32 (PcdFlashFvPreMemorySize) + PcdGet32 (PcdFlashFvAdvancedPreMemorySize) + \
+ PcdGet32 (PcdFlashFvFspTSize) + PcdGet32 (PcdFlashFvFspMSize) + \
+ PcdGet32 (PcdFlashFvFspSSize) + PcdGet32 (PcdFlashMicrocodeFvSize);
+
+ MaskLen = (AsmReadMsr64 (MSR_CACHE_VARIABLE_MTRR_BASE + 1) | (SIZE_4GB - 1)) + 1;
+ MsrIndex = MSR_CACHE_VARIABLE_MTRR_BASE + 1 * 2;
+ AdjustedSize = GetPowerOfTwo32 (NewCodeCacheSize);
+ if (NewCodeCacheSize > AdjustedSize) {
+ AdjustedSize <<= 1;
+ }
+
+ AsmWriteMsr64 (MsrIndex, (SIZE_4GB - AdjustedSize) | CACHE_WRITEPROTECTED);
+ AsmWriteMsr64 (MsrIndex + 1, (MaskLen - AdjustedSize) | B_CACHE_MTRR_VALID);
+}
+
+/**
+ Board configuration init function for PEI pre-memory phase.
+
+ @retval EFI_SUCCESS The function completed successfully.
+ @retval EFI_INVALID_PARAMETER The parameter is NULL.
+**/
+EFI_STATUS
+EFIAPI
+UpXtremeInitPreMem (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+
+ ///
+ /// Install Stall PPI
+ ///
+ Status = InstallStallPpi ();
+ ASSERT_EFI_ERROR (Status);
+
+ ///@todo it should be moved to Si Pkg.
+ ///
+ /// Do Early PCH init
+ ///
+ EarlyPlatformPchInit ();
+
+ //
+ // Install PCH RESET PPI and EFI RESET2 PeiService
+ //
+ Status = PchInitializeReset ();
+ ASSERT_EFI_ERROR (Status);
+
+ EnlargeCodeCacheRegion ();
+
+ ///
+ /// Performing PlatformInitPreMemCallBack after PeiReadOnlyVariable2 PPI produced
+ ///
+ Status = PeiServicesNotifyPpi (&mPreMemNotifyList);
+
+ ///
+ /// After code reorangized, memorycallback will run because the PPI is already
+ /// installed when code run to here, it is supposed that the InstallEfiMemory is
+ /// done before.
+ ///
+ Status = PeiServicesNotifyPpi (&mMemDiscoveredNotifyList);
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Configure GPIO and SIO before memory ready
+
+ @retval EFI_SUCCESS Operation success.
+**/
+EFI_STATUS
+EFIAPI
+UpXtremeBoardInitBeforeMemoryInit (
+ VOID
+ )
+{
+ UpXtremeInitPreMem ();
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+UpXtremeBoardDebugInit (
+ VOID
+ )
+{
+ // Serial port initialization is performed in the PlatformHookSerialPortInitialize ()
+ // function invoked by SerialPortInitialize () in SerialPortLib
+DEBUG_CODE_BEGIN();
+ DEBUG_CONFIG_DATA_HOB *DebugConfigDataHob;
+
+ DebugConfigDataHob = BuildGuidHob (&gDebugConfigHobGuid, sizeof (DEBUG_CONFIG_DATA_HOB));
+ ASSERT (DebugConfigDataHob != NULL);
+ if (DebugConfigDataHob == NULL) {
+ DEBUG ((DEBUG_ERROR, "Build Debug Config Hob failed!\n"));
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ switch (PcdGet32 (PcdSerialBaudRate)) {
+ case 9600:
+ DebugConfigDataHob->SerialDebugBaudRate = 3;
+ break;
+ case 19200:
+ DebugConfigDataHob->SerialDebugBaudRate = 4;
+ break;
+ case 57600:
+ DebugConfigDataHob->SerialDebugBaudRate = 6;
+ break;
+ default:
+ DebugConfigDataHob->SerialDebugBaudRate = 7;
+ }
+ DebugConfigDataHob->SerialDebug = 0x3;
+ DebugConfigDataHob->RamDebugInterface = 0;
+ DebugConfigDataHob->UartDebugInterface = 0;
+ DebugConfigDataHob->Usb3DebugInterface = 0;
+ DebugConfigDataHob->SerialIoDebugInterface = (FeaturePcdGet (PcdSerialIoUartEnable)) ? 1 : 0;
+ DebugConfigDataHob->TraceHubDebugInterface = 0;
+
+DEBUG_CODE_END();
+
+ return EFI_SUCCESS;
+}
+
+EFI_BOOT_MODE
+EFIAPI
+UpXtremeBoardBootModeDetect (
+ VOID
+ )
+{
+ return BOOT_WITH_FULL_CONFIGURATION;
+}
+
+
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/UpXtremeHsioPtssTables.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/UpXtremeHsioPtssTables.c
new file mode 100644
index 0000000000..7e1320a5ac
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/UpXtremeHsioPtssTables.c
@@ -0,0 +1,32 @@
+/** @file
+ UpXtreme HSIO PTSS H File
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _UPEXTREME_HSIO_PTSS_H_
+#define _UPEXTREME_HSIO_PTSS_H_
+
+#include <PchHsioPtssTables.h>
+
+#ifndef HSIO_PTSS_TABLE_SIZE
+#define HSIO_PTSS_TABLE_SIZE(A) A##_Size = sizeof (A) / sizeof (HSIO_PTSS_TABLES)
+#endif
+
+//BoardId UpXtreme
+HSIO_PTSS_TABLES PchLpHsioPtss_Cx_UpXtreme[] = {
+ {{14, 0, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, 0}
+};
+
+UINT16 PchLpHsioPtss_Cx_UpXtreme_Size = sizeof(PchLpHsioPtss_Cx_UpXtreme) / sizeof(HSIO_PTSS_TABLES);
+
+HSIO_PTSS_TABLES PchLpHsioPtss_Bx_UpXtreme[] = {
+ {{14, 0, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, 0},
+};
+
+UINT16 PchLpHsioPtss_Bx_UpXtreme_Size = sizeof(PchLpHsioPtss_Bx_UpXtreme) / sizeof(HSIO_PTSS_TABLES);
+
+#endif // _UPEXTREME_HSIO_PTSS_H_
+
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/UpXtremeInit.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/UpXtremeInit.h
new file mode 100644
index 0000000000..75333c492c
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/UpXtremeInit.h
@@ -0,0 +1,44 @@
+/** @file
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _UP_XTREME_INIT_H_
+#define _UP_XTREME_INIT_H_
+
+#include <Uefi.h>
+#include <IoExpander.h>
+#include <PlatformBoardId.h>
+#include <Library/BaseLib.h>
+#include <Library/PcdLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/DebugLib.h>
+#include <Library/GpioLib.h>
+#include <Ppi/SiPolicy.h>
+#include <PchHsioPtssTables.h>
+
+extern const UINT8 mUpXtremeSamsungDdr4Spd[];
+extern const UINT16 mUpXtremeSamsungDdr4SpdSize;
+extern const UINT8 mUpXtremeSkhynixDdr4Spd[];
+extern const UINT16 mUpXtremeSkhynixDdr4SpdSize;
+
+extern HSIO_PTSS_TABLES PchLpHsioPtss_Bx_UpXtreme[];
+extern UINT16 PchLpHsioPtss_Bx_UpXtreme_Size;
+extern HSIO_PTSS_TABLES PchLpHsioPtss_Cx_UpXtreme[];
+extern UINT16 PchLpHsioPtss_Cx_UpXtreme_Size;
+
+extern GPIO_INIT_CONFIG mGpioTableWhlUDdr4PreMem[];
+extern UINT16 mGpioTableWhlUDdr4PreMemSize;
+extern GPIO_INIT_CONFIG mGpioTableWhlUDdr4WwanOnEarlyPreMem[];
+extern UINT16 mGpioTableWhlUDdr4WwanOnEarlyPreMemSize;
+extern GPIO_INIT_CONFIG mGpioTableWhlUDdr4WwanOffEarlyPreMem[];
+extern UINT16 mGpioTableWhlUDdr4WwanOffEarlyPreMemSize;
+
+extern GPIO_INIT_CONFIG mGpioTableUpXtreme[];
+extern UINT16 mGpioTableUpXtremeSize;
+extern GPIO_INIT_CONFIG mGpioTableDefault[];
+extern UINT16 mGpioTableDefaultSize;
+
+#endif // _UP_XTREME_INIT_H_
+
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/UpXtremeSpdTable.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/UpXtremeSpdTable.c
new file mode 100644
index 0000000000..85f29bd59d
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/BoardInitLib/UpXtremeSpdTable.c
@@ -0,0 +1,86 @@
+/** @file
+ UpXtreme Serial Presence Data (SPD)
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _UPXTREME_SPD_TABLE_H_
+#define _UPXTREME_SPD_TABLE_H_
+
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mUpXtremeSkhynixDdr4Spd[] = {
+ 0x23, 0x11, 0x0C, 0x03, 0x85, 0x21, 0x00, 0x08, 0x00, 0x60, 0x00, 0x03, 0x01, 0x03, 0x00, 0x00,
+ 0x00, 0x00, 0x07, 0x0D, 0xF8, 0x0F, 0x00, 0x00, 0x6E, 0x6E, 0x6E, 0x11, 0x00, 0x6E, 0xF0, 0x0A,
+ 0x20, 0x08, 0x00, 0x05, 0x00, 0xA8, 0x1B, 0x28, 0x28, 0x00, 0x78, 0x00, 0x14, 0x3C, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x16, 0x36, 0x0B, 0x35,
+ 0x16, 0x36, 0x0B, 0x35, 0x00, 0x00, 0x16, 0x36, 0x0B, 0x35, 0x16, 0x36, 0x0B, 0x35, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x9C, 0xB5, 0x00, 0x00, 0x00, 0x00, 0xE7, 0xD6, 0x89, 0x02,
+ 0x0F, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xE2,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x80, 0xAD, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x4D, 0x41, 0x41, 0x35, 0x31, 0x53,
+ 0x36, 0x41, 0x4D, 0x52, 0x36, 0x4E, 0x2D, 0x55, 0x48, 0x20, 0x20, 0x20, 0x20, 0x00, 0x80, 0xAD,
+ 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xDD, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 mUpXtremeSkhynixDdr4SpdSize = sizeof (mUpXtremeSkhynixDdr4Spd);
+
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mUpXtremeSamsungDdr4Spd[] = {
+ 0x23, 0x11, 0x0C, 0x03, 0x45, 0x21, 0x00, 0x08, 0x00, 0x60, 0x00, 0x03, 0x02, 0x03, 0x80, 0x00,
+ 0x00, 0x00, 0x07, 0x0D, 0xF8, 0x0F, 0x00, 0x00, 0x6E, 0x6E, 0x6E, 0x11, 0x00, 0x6E, 0xF0, 0x0A,
+ 0x20, 0x08, 0x00, 0x05, 0x00, 0xF0, 0x2B, 0x34, 0x28, 0x00, 0x78, 0x00, 0x14, 0x3C, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x16, 0x36, 0x0B, 0x35,
+ 0x16, 0x36, 0x0B, 0x35, 0x00, 0x00, 0x16, 0x36, 0x0B, 0x35, 0x16, 0x36, 0x0B, 0x35, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x9C, 0xB5, 0x00, 0x00, 0x00, 0x00, 0xE7, 0xD6, 0xB8, 0x4A,
+ 0x0F, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xE2,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x08, 0xF7, 0x4B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x44, 0x34, 0x53, 0x53, 0x31, 0x32, 0x31,
+ 0x36, 0x31, 0x53, 0x48, 0x32, 0x34, 0x41, 0x2D, 0x42, 0x20, 0x20, 0x20, 0x20, 0x00, 0x80, 0xCE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 mUpXtremeSamsungDdr4SpdSize = sizeof (mUpXtremeSamsungDdr4Spd);
+
+#endif
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/DxePolicyBoardConfigLib/DxePolicyBoardConfig.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/DxePolicyBoardConfigLib/DxePolicyBoardConfig.h
new file mode 100644
index 0000000000..c420873002
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/DxePolicyBoardConfigLib/DxePolicyBoardConfig.h
@@ -0,0 +1,19 @@
+/** @file
+ Header file for DxePolicyBoardConfig library instance.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _DXE_POLICY_BOARD_CONFIG_H_
+#define _DXE_POLICY_BOARD_CONFIG_H_
+
+#include <PiDxe.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/DxePolicyBoardConfigLib.h>
+
+
+#endif
+
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/DxePolicyBoardConfigLib/DxePolicyBoardConfigLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/DxePolicyBoardConfigLib/DxePolicyBoardConfigLib.inf
new file mode 100644
index 0000000000..8d414102ee
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/DxePolicyBoardConfigLib/DxePolicyBoardConfigLib.inf
@@ -0,0 +1,45 @@
+## @file
+# Module Information file for DxePolicyBoardConfigLib Library
+#
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = DxePolicyBoardConfigLib
+ FILE_GUID = 17836E9F-7188-4640-80A3-B4441585FFE9
+ VERSION_STRING = 1.0
+ MODULE_TYPE = DXE_DRIVER
+ LIBRARY_CLASS = DxePolicyUpdateLib|DXE_DRIVER
+
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+[Sources]
+ DxeSaPolicyBoardConfig.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ IntelSiliconPkg/IntelSiliconPkg.dec
+ CoffeelakeSiliconPkg/SiPkg.dec
+ WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec
+
+[LibraryClasses]
+ UefiBootServicesTableLib
+ UefiRuntimeServicesTableLib
+ BaseLib
+ BaseMemoryLib
+ PcdLib
+ DebugLib
+ HobLib
+ ConfigBlockLib
+
+[Guids]
+ gMemoryDxeConfigGuid ## CONSUMES
+
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/DxePolicyBoardConfigLib/DxeSaPolicyBoardConfig.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/DxePolicyBoardConfigLib/DxeSaPolicyBoardConfig.c
new file mode 100644
index 0000000000..78edbab5ad
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/DxePolicyBoardConfigLib/DxeSaPolicyBoardConfig.c
@@ -0,0 +1,36 @@
+/** @file
+ Intel DXE SA Policy update by board configuration
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "DxePolicyBoardConfig.h"
+#include <Library/ConfigBlockLib.h>
+
+/**
+ This function performs DXE SA Policy update by board configuration.
+
+ @param[in, out] DxeSaPolicy DXE SA Policy
+
+ @retval EFI_SUCCESS The SI Policy is successfully updated.
+ @retval Others The SI Policy is not successfully updated.
+**/
+EFI_STATUS
+EFIAPI
+UpdateDxeSaPolicyBoardConfig (
+ IN OUT SA_POLICY_PROTOCOL *DxeSaPolicy
+ )
+{
+ EFI_STATUS Status;
+ MEMORY_DXE_CONFIG *MemoryDxeConfig;
+
+ DEBUG((DEBUG_INFO, "Updating SA Policy by board config in DXE\n"));
+
+ Status = GetConfigBlock ((VOID *)DxeSaPolicy, &gMemoryDxeConfigGuid, (VOID *)&MemoryDxeConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPlatformHookLib/PeiPlatformHookLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPlatformHookLib/PeiPlatformHookLib.c
new file mode 100644
index 0000000000..9b14c2457b
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPlatformHookLib/PeiPlatformHookLib.c
@@ -0,0 +1,298 @@
+/** @file
+ PEI Library Functions. Initialize GPIOs
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiPei.h>
+#include <PeiPlatformHookLib.h>
+#include <SaPolicyCommon.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/IoLib.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <Library/TimerLib.h>
+#include <Library/PchCycleDecodingLib.h>
+#include <Library/PeiPlatformLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/PmcLib.h>
+#include <Library/PeiSaPolicyLib.h>
+#include <PchAccess.h>
+#include <Library/CpuPlatformLib.h>
+#include <Library/GpioNativeLib.h>
+#include <Library/GpioLib.h>
+#include <GpioPinsCnlLp.h>
+#include <GpioPinsCnlH.h>
+#include <Library/PchInfoLib.h>
+#include <Library/CnviLib.h>
+#include <SioRegs.h>
+#include <PlatformBoardConfig.h>
+#include <Library/PchPcrLib.h>
+#include <Library/GpioCheckConflictLib.h>
+
+#define SIO_RUNTIME_REG_BASE_ADDRESS 0x0680
+
+#define RECOVERY_MODE_GPIO_PIN 0 // Platform specific @todo use PCD
+
+#define MANUFACTURE_MODE_GPIO_PIN 0 // Platform specific @todo use PCD
+
+/**
+ Configures GPIO
+
+ @param[in] GpioTable Point to Platform Gpio table
+ @param[in] GpioTableCount Number of Gpio table entries
+
+**/
+VOID
+ConfigureGpio (
+ IN GPIO_INIT_CONFIG *GpioDefinition,
+ IN UINT16 GpioTableCount
+ )
+{
+ DEBUG ((DEBUG_INFO, "ConfigureGpio() Start\n"));
+
+ CreateGpioCheckConflictHob (GpioDefinition, GpioTableCount);
+
+ GpioConfigurePads (GpioTableCount, GpioDefinition);
+
+ DEBUG ((DEBUG_INFO, "ConfigureGpio() End\n"));
+}
+
+/**
+ Configure GPIO group GPE tier.
+
+ @retval none.
+**/
+VOID
+GpioGroupTierInitHook(
+ VOID
+ )
+{
+ DEBUG ((DEBUG_INFO, "GpioGroupTierInitHook Start\n"));
+
+ if (PcdGet32 (PcdGpioGroupToGpeDw0)) {
+ GpioSetGroupToGpeDwX (PcdGet32 (PcdGpioGroupToGpeDw0),
+ PcdGet32 (PcdGpioGroupToGpeDw1),
+ PcdGet32 (PcdGpioGroupToGpeDw2));
+ }
+ DEBUG ((DEBUG_INFO, "GpioGroupTierInitHook End\n"));
+}
+
+/**
+ Configure single GPIO pad for touchpanel interrupt
+**/
+VOID
+TouchpanelGpioInit (
+ VOID
+ )
+{
+ GPIO_INIT_CONFIG* TouchpanelPad;
+ GPIO_PAD_OWN PadOwnVal;
+
+ PadOwnVal = 0;
+ TouchpanelPad = (VOID *) (UINTN) PcdGet32 (PcdBoardGpioTableTouchPanel);
+ if (TouchpanelPad != NULL) {
+ GpioGetPadOwnership (TouchpanelPad->GpioPad, &PadOwnVal);
+ if (PadOwnVal == GpioPadOwnHost) {
+ GpioConfigurePads (1, TouchpanelPad);
+ }
+ }
+}
+
+/**
+ Configure GPIO Before Memory is not ready.
+
+**/
+VOID
+GpioInitPreMem (
+ VOID
+ )
+{
+ if (PcdGet32 (PcdBoardGpioTablePreMem) != 0 && PcdGet16 (PcdBoardGpioTablePreMemSize) != 0) {
+ ConfigureGpio ((VOID *) (UINTN) PcdGet32 (PcdBoardGpioTablePreMem), (UINTN) PcdGet16 (PcdBoardGpioTablePreMemSize));
+ }
+}
+
+/**
+ Basic GPIO configuration before memory is ready
+
+**/
+VOID
+GpioInitEarlyPreMem (
+ VOID
+ )
+{
+ GPIO_CONFIG BbrstConfig;
+ UINT32 WwanBbrstGpio;
+
+ WwanBbrstGpio = PcdGet32 (PcdWwanBbrstGpio);
+
+ if (WwanBbrstGpio) {
+ //
+ // BIOS needs to put modem in OFF state for the two scenarios below.
+ // 1. Modem RESET# is not asserted via PLTRST# in the previous sleep state
+ // 2. Modem is disabled via setup option
+ //
+ GpioGetPadConfig (WwanBbrstGpio, &BbrstConfig);
+ if ((PcdGetBool (PcdPcieWwanEnable) == FALSE) ||
+ (PcdGetBool (PcdWwanResetWorkaround) == TRUE &&
+ BbrstConfig.Direction == GpioDirOut &&
+ BbrstConfig.OutputState == GpioOutHigh)) {
+ //
+ // Assert FULL_CARD_POWER_OFF#, RESET# and PERST# GPIOs
+ //
+ if (PcdGet32 (PcdBoardGpioTableWwanOffEarlyPreMem) != 0 && PcdGet16 (PcdBoardGpioTableWwanOffEarlyPreMemSize) != 0) {
+ ConfigureGpio ((VOID *) (UINTN) PcdGet32 (PcdBoardGpioTableWwanOffEarlyPreMem), (UINTN) PcdGet16 (PcdBoardGpioTableWwanOffEarlyPreMemSize));
+ }
+ if (PcdGetBool (PcdPcieWwanEnable) == TRUE && PcdGetBool (PcdWwanResetWorkaround) == TRUE) {
+ MicroSecondDelay (1 * 1000); // Delay by 1ms
+ }
+ }
+
+ //
+ // Turn ON modem power and de-assert RESET# and PERST# GPIOs
+ //
+ if (PcdGetBool (PcdPcieWwanEnable) == TRUE) {
+ if (PcdGet32 (PcdBoardGpioTableWwanOnEarlyPreMem) != 0 && PcdGet16 (PcdBoardGpioTableWwanOnEarlyPreMemSize) != 0) {
+ ConfigureGpio ((VOID *) (UINTN) PcdGet32 (PcdBoardGpioTableWwanOnEarlyPreMem), (UINTN) PcdGet16 (PcdBoardGpioTableWwanOnEarlyPreMemSize));
+ }
+ }
+ }
+}
+
+/**
+ Configure GPIO
+
+**/
+VOID
+GpioInit (
+ VOID
+ )
+{
+ ConfigureGpio ((VOID *) (UINTN) PcdGet32 (PcdBoardGpioTable), (UINTN) PcdGet16 (PcdBoardGpioTableSize));
+
+ if (PcdGet32 (PcdBoardGpioTable2)) {
+ ConfigureGpio ((VOID *) (UINTN) PcdGet32 (PcdBoardGpioTable2), (UINTN) PcdGet16 (PcdBoardGpioTable2Size));
+ }
+
+ TouchpanelGpioInit ();
+
+ //
+ // Lock pads after initializing platform GPIO.
+ // Pads which were requested to be unlocked during configuration
+ // will not be locked.
+ //
+ GpioLockPads ();
+
+ return;
+}
+
+/**
+ Configure Super IO
+
+**/
+VOID
+SioInit (
+ VOID
+ )
+{
+ //
+ // Program and Enable Default Super IO Configuration Port Addresses and range
+ //
+ PchLpcGenIoRangeSet (PcdGet16 (PcdLpcSioConfigDefaultPort) & (~0xF), 0x10);
+
+ PchLpcGenIoRangeSet (SIO_RUNTIME_REG_BASE_ADDRESS & (~0x7F), 0x10);
+
+ return;
+}
+
+/**
+ Configure GPIO and SIO before memory ready
+
+ @retval EFI_SUCCESS Operation success.
+**/
+EFI_STATUS
+BoardInitPreMem (
+ VOID
+ )
+{
+ //
+ // Obtain Platform Info from HOB.
+ //
+ GpioInitPreMem ();
+ GpioGroupTierInitHook ();
+ SioInit ();
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Configure GPIO and SIO
+
+ @retval EFI_SUCCESS Operation success.
+**/
+EFI_STATUS
+BoardInit (
+ VOID
+ )
+{
+
+ GpioInit ();
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Do platform specific programming post-memory.
+
+ @retval EFI_SUCCESS The function completed successfully.
+**/
+
+EFI_STATUS
+PlatformSpecificInit (
+ VOID
+ )
+{
+ GPIO_CONFIG GpioConfig;
+
+ if (IsCnlPch ()) {
+
+ //
+ // Tristate unused pins by audio link mode.
+ //
+ ZeroMem(&GpioConfig, sizeof(GPIO_CONFIG));
+ GpioConfig.PadMode = GpioPadModeGpio;
+ GpioConfig.HostSoftPadOwn = GpioHostOwnGpio;
+ GpioConfig.Direction = GpioDirNone;
+ GpioConfig.OutputState = GpioOutDefault;
+ GpioConfig.InterruptConfig = GpioIntDis;
+ GpioConfig.PowerConfig = GpioPlatformReset;
+ GpioConfig.ElectricalConfig = GpioTermNone;
+
+ GpioSetPadConfig (GPIO_CNL_LP_SSP1_SFRM, &GpioConfig);
+ GpioSetPadConfig (GPIO_CNL_LP_SSP1_TXD, &GpioConfig);
+
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Early Board Configuration before memory is ready
+
+ @retval EFI_SUCCESS Operation success.
+**/
+EFI_STATUS
+BoardInitEarlyPreMem (
+ VOID
+ )
+{
+ GpioInitEarlyPreMem ();
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPlatformHookLib/PeiPlatformHookLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPlatformHookLib/PeiPlatformHookLib.inf
new file mode 100644
index 0000000000..04349d9469
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPlatformHookLib/PeiPlatformHookLib.inf
@@ -0,0 +1,95 @@
+## @file
+#
+# Copyright (c) 2020 Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = PeiPlatformHookLib
+ FILE_GUID = AD901798-B0DA-4B20-B90C-283F886E76D0
+ VERSION_STRING = 1.0
+ MODULE_TYPE = PEIM
+ LIBRARY_CLASS = PeiPlatformHookLib|PEIM PEI_CORE SEC
+
+[LibraryClasses]
+ DebugLib
+ BaseMemoryLib
+ IoLib
+ HobLib
+ PcdLib
+ TimerLib
+ PchCycleDecodingLib
+ GpioLib
+ CpuPlatformLib
+ PeiServicesLib
+ ConfigBlockLib
+ PeiSaPolicyLib
+ GpioExpanderLib
+ PmcLib
+ PchPcrLib
+ PciSegmentLib
+ GpioCheckConflictLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ IntelSiliconPkg/IntelSiliconPkg.dec
+ CoffeelakeSiliconPkg/SiPkg.dec
+ WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec
+
+[Pcd]
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioConfigDefaultPort ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSioBaseAddress ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdIoExpanderPresent ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDebugUsbUartEnable ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMipiCamGpioEnable ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableSize ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable2 ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable2Size ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTable ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTableSize ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTable2 ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTable2Size ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableTouchPanel ## CONSUMES
+
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTablePreMem
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTablePreMemSize
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMem
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMemSize
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreMem
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreMemSize
+
+ # GPIO Group Tier
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw0 ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw1 ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw2 ## CONSUMES
+
+ # Misc
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdIoExpanderPresent ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPc8374SioKbcPresent ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdOddPowerInitEnable ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdIvCamInitPresent ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRecoveryModeGpio ## CONSUMES
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdCpuVboostEnable ## CONSUMES
+
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdWwanBbrstGpio
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieWwanEnable
+ gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdWwanResetWorkaround
+
+[Sources]
+ PeiPlatformHookLib.c
+
+[Ppis]
+ gEfiPeiReadOnlyVariable2PpiGuid ## CONSUMES
+ gSiPolicyPpiGuid ## CONSUMES
+
+[Guids]
+ gSaDataHobGuid ## CONSUMES
+ gEfiGlobalVariableGuid ## CONSUMES
+ gGpioCheckConflictHobGuid ## CONSUMES
+
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoardConfigLib/PeiCpuPolicyBoardConfig.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoardConfigLib/PeiCpuPolicyBoardConfig.c
new file mode 100644
index 0000000000..d1d1920823
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoardConfigLib/PeiCpuPolicyBoardConfig.c
@@ -0,0 +1,49 @@
+/** @file
+ Intel PEI CPU Policy update by board configuration
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiPolicyBoardConfig.h"
+#include <Library/ConfigBlockLib.h>
+
+/**
+ This function performs PEI CPU Policy update by board configuration.
+
+ @param[in, out] SiPolicy The SI Policy PPI instance
+
+ @retval EFI_SUCCESS The SI Policy is successfully updated.
+ @retval Others The SI Policy is not successfully updated.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiCpuPolicyBoardConfig (
+ IN OUT SI_POLICY_PPI *SiPolicyPpi
+ )
+{
+ EFI_STATUS Status;
+ SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig;
+ SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi;
+ CPU_CONFIG *CpuConfig;
+
+ DEBUG((DEBUG_INFO, "Updating CPU Policy by board config in Post Mem\n"));
+
+ Status = PeiServicesLocatePpi(
+ &gSiPreMemPolicyPpiGuid,
+ 0,
+ NULL,
+ (VOID **)&SiPreMemPolicyPpi
+ );
+ ASSERT_EFI_ERROR(Status);
+
+ Status = GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gSaMiscPeiPreMemConfigGuid, (VOID *) &MiscPeiPreMemConfig);
+ ASSERT_EFI_ERROR(Status);
+
+ Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuConfigGuid, (VOID *) &CpuConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoardConfigLib/PeiCpuPolicyBoardConfigPreMem.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoardConfigLib/PeiCpuPolicyBoardConfigPreMem.c
new file mode 100644
index 0000000000..2b80a268e6
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoardConfigLib/PeiCpuPolicyBoardConfigPreMem.c
@@ -0,0 +1,29 @@
+/** @file
+ Intel PEI CPU Pre-Memory Policy update by board configuration
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiPolicyBoardConfig.h"
+#include <Library/ConfigBlockLib.h>
+
+/**
+ This function performs PEI CPU Pre-Memory Policy update by board configuration.
+
+ @param[in, out] SiPolicy The SI PreMem Policy PPI instance
+
+ @retval EFI_SUCCESS The SI Policy is successfully updated.
+ @retval Others The SI Policy is not successfully updated.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiCpuPolicyBoardConfigPreMem (
+ IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi
+ )
+{
+
+ return EFI_SUCCESS;
+}
+
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoardConfigLib/PeiMePolicyBoardConfig.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoardConfigLib/PeiMePolicyBoardConfig.c
new file mode 100644
index 0000000000..cff2b03ca9
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoardConfigLib/PeiMePolicyBoardConfig.c
@@ -0,0 +1,36 @@
+/** @file
+ Intel PEI ME Policy update by board configuration
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiPolicyBoardConfig.h"
+#include <Library/ConfigBlockLib.h>
+
+/**
+ This function performs PEI ME Policy update by board configuration.
+
+ @param[in, out] SiPolicy The SI Policy PPI instance
+
+ @retval EFI_SUCCESS The SI Policy is successfully updated.
+ @retval Others The SI Policy is not successfully updated.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiMePolicyBoardConfig (
+ IN OUT SI_POLICY_PPI *SiPolicyPpi
+ )
+{
+ EFI_STATUS Status;
+ ME_PEI_CONFIG *MePeiConfig;
+
+ DEBUG((DEBUG_INFO, "Updating ME Policy by board config in Post Mem\n"));
+
+ Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gMePeiConfigGuid, (VOID *) &MePeiConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoardConfigLib/PeiMePolicyBoardConfigPreMem.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoardConfigLib/PeiMePolicyBoardConfigPreMem.c
new file mode 100644
index 0000000000..610b6b8cb5
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoardConfigLib/PeiMePolicyBoardConfigPreMem.c
@@ -0,0 +1,37 @@
+/** @file
+ Intel PEI ME Pre-Memory Policy update by board configuration
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiPolicyBoardConfig.h"
+#include <Library/ConfigBlockLib.h>
+
+/**
+ This function performs PEI ME Pre-Memory Policy update by board configuration.
+
+ @param[in, out] SiPolicy The SI PreMem Policy PPI instance
+
+ @retval EFI_SUCCESS The SI Policy is successfully updated.
+ @retval Others The SI Policy is not successfully updated.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiMePolicyBoardConfigPreMem (
+ IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi
+ )
+{
+ EFI_STATUS Status;
+ ME_PEI_PREMEM_CONFIG *MePeiPreMemConfig;
+
+ DEBUG((DEBUG_INFO, "Updating ME Policy by board config in Pre Mem\n"));
+
+ Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gMePeiPreMemConfigGuid, (VOID *) &MePeiPreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
+
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoardConfigLib/PeiPchPolicyBoardConfig.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoardConfigLib/PeiPchPolicyBoardConfig.c
new file mode 100644
index 0000000000..a3b3a63eec
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoardConfigLib/PeiPchPolicyBoardConfig.c
@@ -0,0 +1,36 @@
+/** @file
+ Intel PEI PCH Policy update by board configuration
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiPolicyBoardConfig.h"
+#include <Library/ConfigBlockLib.h>
+
+/**
+ This function performs PEI PCH Policy update by board configuration.
+
+ @param[in, out] SiPolicy The SI Policy PPI instance
+
+ @retval EFI_SUCCESS The SI Policy is successfully updated.
+ @retval Others The SI Policy is not successfully updated.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiPchPolicyBoardConfig (
+ IN OUT SI_POLICY_PPI *SiPolicyPpi
+ )
+{
+ EFI_STATUS Status;
+ PCH_GENERAL_CONFIG *PchGeneralConfig;
+
+ DEBUG((DEBUG_INFO, "Updating PCH Policy by board config in Post Mem\n"));
+
+ Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gPchGeneralConfigGuid, (VOID *) &PchGeneralConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoardConfigLib/PeiPchPolicyBoardConfigPreMem.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoardConfigLib/PeiPchPolicyBoardConfigPreMem.c
new file mode 100644
index 0000000000..01bb75525b
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoardConfigLib/PeiPchPolicyBoardConfigPreMem.c
@@ -0,0 +1,37 @@
+/** @file
+ Intel PEI PCH Pre-Memory Policy update by board configuration
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiPolicyBoardConfig.h"
+#include <Library/ConfigBlockLib.h>
+
+/**
+ This function performs PEI PCH Pre-Memory Policy update by board configuration.
+
+ @param[in, out] SiPolicy The SI PreMem Policy PPI instance
+
+ @retval EFI_SUCCESS The SI Policy is successfully updated.
+ @retval Others The SI Policy is not successfully updated.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiPchPolicyBoardConfigPreMem (
+ IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi
+ )
+{
+ EFI_STATUS Status;
+ PCH_GENERAL_PREMEM_CONFIG *PchGeneralPreMemConfig;
+
+ DEBUG((DEBUG_INFO, "Updating PCH Policy by board config in Pre Mem\n"));
+
+ Status = GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gPchGeneralPreMemConfigGuid, (VOID *) &PchGeneralPreMemConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
+
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoardConfigLib/PeiPolicyBoardConfig.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoardConfigLib/PeiPolicyBoardConfig.h
new file mode 100644
index 0000000000..64f6c67639
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoardConfigLib/PeiPolicyBoardConfig.h
@@ -0,0 +1,22 @@
+/** @file
+ Header file for PeiPolicyBoardConfig library instance.
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_POLICY_BOARD_CONFIG_H_
+#define _PEI_POLICY_BOARD_CONFIG_H_
+
+#include <PiPei.h>
+#include <ConfigBlock/MePeiConfig.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/PeiPolicyBoardConfigLib.h>
+#include <Library/IoLib.h>
+#include <Library/BaseMemoryLib.h>
+
+#endif
+
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoardConfigLib/PeiPolicyBoardConfigLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoardConfigLib/PeiPolicyBoardConfigLib.inf
new file mode 100644
index 0000000000..aaf0abbf04
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoardConfigLib/PeiPolicyBoardConfigLib.inf
@@ -0,0 +1,71 @@
+## @file
+# Module Information file for PeiPolicyBoardConfigLib Library
+#
+#
+# Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = PeiPolicyBoardConfigLib
+ FILE_GUID = B1E959E3-9DCA-4D6F-938C-420C3BF5D820
+ VERSION_STRING = 1.0
+ MODULE_TYPE = PEIM
+ LIBRARY_CLASS = PeiPolicyBoardConfigLib|PEIM PEI_CORE SEC
+
+[Sources]
+ PeiCpuPolicyBoardConfigPreMem.c
+ PeiCpuPolicyBoardConfig.c
+ PeiMePolicyBoardConfigPreMem.c
+ PeiMePolicyBoardConfig.c
+ PeiPchPolicyBoardConfigPreMem.c
+ PeiPchPolicyBoardConfig.c
+ PeiSaPolicyBoardConfigPreMem.c
+ PeiSaPolicyBoardConfig.c
+ PeiSiPolicyBoardConfig.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ SecurityPkg/SecurityPkg.dec
+ IntelSiliconPkg/IntelSiliconPkg.dec
+ CoffeelakeSiliconPkg/SiPkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec
+
+[LibraryClasses]
+ PcdLib
+ DebugLib
+ HobLib
+ ConfigBlockLib
+ IoLib
+ BaseCryptLib
+ BaseMemoryLib
+
+[Guids]
+ gCpuSecurityPreMemConfigGuid ## CONSUMES
+ gMePeiPreMemConfigGuid ## CONSUMES
+ gPchGeneralPreMemConfigGuid ## CONSUMES
+ gSaMiscPeiPreMemConfigGuid ## CONSUMES
+ gCpuConfigGuid ## CONSUMES
+ gPchGeneralConfigGuid ## CONSUMES
+ gEfiTpmDeviceInstanceTpm20DtpmGuid
+ gEfiTpmDeviceInstanceTpm12Guid
+
+[Ppis]
+ gEfiPeiReadOnlyVariable2PpiGuid ## CONSUMES
+
+[Pcd]
+ gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdDmiBaseAddress ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdEpBaseAddress ## CONSUMES
+ gPlatformModuleTokenSpaceGuid.PcdEdramBaseAddress ## CONSUMES
+ gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid ## CONSUMES
+
+[FixedPcd]
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize ## CONSUMES
+
+
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoardConfigLib/PeiSaPolicyBoardConfig.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoardConfigLib/PeiSaPolicyBoardConfig.c
new file mode 100644
index 0000000000..a8f6860bd0
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoardConfigLib/PeiSaPolicyBoardConfig.c
@@ -0,0 +1,36 @@
+/** @file
+ Intel PEI SA Policy update by board configuration
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiPolicyBoardConfig.h"
+#include <Library/ConfigBlockLib.h>
+
+/**
+ This function performs PEI SA Policy update by board configuration.
+
+ @param[in, out] SiPolicy The SI Policy PPI instance
+
+ @retval EFI_SUCCESS The SI Policy is successfully updated.
+ @retval Others The SI Policy is not successfully updated.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiSaPolicyBoardConfig (
+ IN OUT SI_POLICY_PPI *SiPolicyPpi
+ )
+{
+ EFI_STATUS Status;
+ GRAPHICS_PEI_CONFIG *GtConfig;
+
+ DEBUG((DEBUG_INFO, "Updating SA Policy by board config in Post Mem\n"));
+
+ Status = GetConfigBlock ((VOID *) SiPolicyPpi, &gGraphicsPeiConfigGuid, (VOID *)&GtConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoardConfigLib/PeiSaPolicyBoardConfigPreMem.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoardConfigLib/PeiSaPolicyBoardConfigPreMem.c
new file mode 100644
index 0000000000..c1c6915b10
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoardConfigLib/PeiSaPolicyBoardConfigPreMem.c
@@ -0,0 +1,30 @@
+/** @file
+ Intel PEI SA Pre-Memory Policy update by board configuration
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiPolicyBoardConfig.h"
+#include <ConfigBlock/SaMiscPeiPreMemConfig.h>
+#include <Library/ConfigBlockLib.h>
+
+/**
+ This function performs PEI SA Pre-Memory Policy update by board configuration.
+
+ @param[in, out] SiPolicy The SI PreMem Policy PPI instance
+
+ @retval EFI_SUCCESS The SI Policy is successfully updated.
+ @retval Others The SI Policy is not successfully updated.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiSaPolicyBoardConfigPreMem (
+ IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi
+ )
+{
+ return EFI_SUCCESS;
+}
+
+
diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoardConfigLib/PeiSiPolicyBoardConfig.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoardConfigLib/PeiSiPolicyBoardConfig.c
new file mode 100644
index 0000000000..e8dd2b9609
--- /dev/null
+++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/UpXtreme/Library/PeiPolicyBoardConfigLib/PeiSiPolicyBoardConfig.c
@@ -0,0 +1,27 @@
+/** @file
+ Intel PEI SA Policy update by board configuration
+
+
+ Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiPolicyBoardConfig.h"
+
+/**
+ This function performs PEI SI Policy update by board configuration.
+
+ @param[in, out] SiPolicy The SI Policy PPI instance
+
+ @retval EFI_SUCCESS The SI Policy is successfully updated.
+ @retval Others The SI Policy is not successfully updated.
+**/
+EFI_STATUS
+EFIAPI
+UpdatePeiSiPolicyBoardConfig (
+ IN OUT SI_POLICY_PPI *SiPolicyPpi
+ )
+{
+ return EFI_SUCCESS;
+}
+
--
2.19.1.windows.1
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