Re: [edk2-platforms][PATCH V2 2/7] Platform/ARM/Morello: Add support for PciHostBridgeLib

["Sami Mujawar" <sami.mujawar@arm.com>]

Hi Chandni,

This patch looks good to me.

Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

Regards,

Sami Mujawar

On 01/04/2021, 15:36, "Chandni Cherukuri" <chandni.cherukuri@arm.com> wrote:

    Morello FVP platform supports a PCIe root complex.
    This patch implements PciHostBridgeLib to support PCIe.

    Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
    ---
     Platform/ARM/Morello/Library/PciHostBridgeLib/PciHostBridgeLibFvp.inf |  48 ++++++
     Platform/ARM/Morello/Library/PciHostBridgeLib/PciHostBridgeLibFvp.c   | 180 ++++++++++++++++++++
     2 files changed, 228 insertions(+)

    diff --git a/Platform/ARM/Morello/Library/PciHostBridgeLib/PciHostBridgeLibFvp.inf b/Platform/ARM/Morello/Library/PciHostBridgeLib/PciHostBridgeLibFvp.inf
    new file mode 100644
    index 000000000000..1d6c5b01d13d
    --- /dev/null
    +++ b/Platform/ARM/Morello/Library/PciHostBridgeLib/PciHostBridgeLibFvp.inf
    @@ -0,0 +1,48 @@
    +## @file
    +#  PCI Host Bridge Library instance for ARM Morello FVP platform.
    +#
    +#  Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
    +#
    +#  SPDX-License-Identifier: BSD-2-Clause-Patent
    +#
    +##
    +
    +[Defines]
    +  INF_VERSION                    = 0x0001001B
    +  BASE_NAME                      = PciHostBridgeLib
    +  FILE_GUID                      = 6879CEAD-DC94-42EB-895C-096D36B8083C
    +  MODULE_TYPE                    = DXE_DRIVER
    +  VERSION_STRING                 = 1.0
    +  LIBRARY_CLASS                  = PciHostBridgeLib|DXE_DRIVER
    +
    +#
    +# The following information is for reference only and not required by the build
    +# tools.
    +#
    +#  VALID_ARCHITECTURES           = AARCH64
    +#
    +
    +[Sources]
    +  PciHostBridgeLibFvp.c
    +
    +[Packages]
    +  ArmPkg/ArmPkg.dec
    +  MdeModulePkg/MdeModulePkg.dec
    +  MdePkg/MdePkg.dec
    +  Platform/ARM/Morello/MorelloPlatform.dec
    +
    +[FixedPcd]
    +  gArmMorelloTokenSpaceGuid.PcdPciBusMax
    +  gArmMorelloTokenSpaceGuid.PcdPciBusMin
    +  gArmMorelloTokenSpaceGuid.PcdPciIoBase
    +  gArmMorelloTokenSpaceGuid.PcdPciIoSize
    +  gArmMorelloTokenSpaceGuid.PcdPciMmio32Base
    +  gArmMorelloTokenSpaceGuid.PcdPciMmio32Size
    +  gArmMorelloTokenSpaceGuid.PcdPciMmio64Base
    +  gArmMorelloTokenSpaceGuid.PcdPciMmio64Size
    +
    +[Protocols]
    +  gEfiCpuIo2ProtocolGuid          ## CONSUMES
    +
    +[Depex]
    +  gEfiCpuIo2ProtocolGuid
    diff --git a/Platform/ARM/Morello/Library/PciHostBridgeLib/PciHostBridgeLibFvp.c b/Platform/ARM/Morello/Library/PciHostBridgeLib/PciHostBridgeLibFvp.c
    new file mode 100644
    index 000000000000..042cbbdca202
    --- /dev/null
    +++ b/Platform/ARM/Morello/Library/PciHostBridgeLib/PciHostBridgeLibFvp.c
    @@ -0,0 +1,180 @@
    +/** @file
    +  PCI Host Bridge Library instance for ARM Morello FVP platform.
    +
    +  Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
    +
    +  SPDX-License-Identifier: BSD-2-Clause-Patent
    +**/
    +
    +#include <Library/DebugLib.h>
    +#include <Library/DevicePathLib.h>
    +#include <Library/PciHostBridgeLib.h>
    +#include <Protocol/PciHostBridgeResourceAllocation.h>
    +
    +#define ROOT_COMPLEX_NUM 1
    +
    +GLOBAL_REMOVE_IF_UNREFERENCED
    +STATIC CHAR16 CONST * CONST mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = {
    +  L"Mem", L"I/O", L"Bus"
    +};
    +
    +#pragma pack(1)
    +typedef struct {
    +  ACPI_HID_DEVICE_PATH     AcpiDevicePath;
    +  EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
    +} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;
    +#pragma pack ()
    +
    +STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[ROOT_COMPLEX_NUM] = {
    +  {
    +    {
    +      {
    +        ACPI_DEVICE_PATH,
    +        ACPI_DP,
    +        {
    +          (UINT8)sizeof (ACPI_HID_DEVICE_PATH),
    +          (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
    +        }
    +      },
    +      EISA_PNP_ID(0x0A08),
    +      0
    +    },
    +    {
    +      END_DEVICE_PATH_TYPE,
    +      END_ENTIRE_DEVICE_PATH_SUBTYPE,
    +      {
    +        END_DEVICE_PATH_LENGTH,
    +        0
    +      }
    +    }
    +  },
    +};
    +
    +STATIC PCI_ROOT_BRIDGE mPciRootBridge[ROOT_COMPLEX_NUM] = {
    +  {
    +    0,                                              // Segment
    +    0,                                              // Supports
    +    0,                                              // Attributes
    +    TRUE,                                           // DmaAbove4G
    +    FALSE,                                          // NoExtendedConfigSpace
    +    FALSE,                                          // ResourceAssigned
    +    EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM |          // AllocationAttributes
    +    EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
    +    {
    +      // Bus
    +      FixedPcdGet32 (PcdPciBusMin),
    +      FixedPcdGet32 (PcdPciBusMax)
    +    }, {
    +      // Io
    +      FixedPcdGet64 (PcdPciIoBase),
    +      FixedPcdGet64 (PcdPciIoBase) + FixedPcdGet64 (PcdPciIoSize) - 1
    +    }, {
    +      // Mem
    +      FixedPcdGet32 (PcdPciMmio32Base),
    +      FixedPcdGet32 (PcdPciMmio32Base) + FixedPcdGet32 (PcdPciMmio32Size) - 1
    +    }, {
    +      // MemAbove4G
    +      FixedPcdGet64 (PcdPciMmio64Base),
    +      FixedPcdGet64 (PcdPciMmio64Base) + FixedPcdGet64 (PcdPciMmio64Size) - 1
    +    }, {
    +      // PMem
    +      MAX_UINT64,
    +      0
    +    }, {
    +      // PMemAbove4G
    +      MAX_UINT64,
    +      0
    +    },
    +    (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[0]
    +  },
    +};
    +
    +/**
    +  Return all the root bridge instances in an array.
    +
    +  @param Count  Return the count of root bridge instances.
    +
    +  @return All the root bridge instances in an array.
    +          The array should be passed into PciHostBridgeFreeRootBridges()
    +          when it's not used.
    +**/
    +PCI_ROOT_BRIDGE *
    +EFIAPI
    +PciHostBridgeGetRootBridges (
    +  UINTN *Count
    +  )
    +{
    +  *Count = ARRAY_SIZE (mPciRootBridge);
    +  return mPciRootBridge;
    +}
    +
    +/**
    +  Free the root bridge instances array returned from PciHostBridgeGetRootBridges().
    +
    +  @param Bridges The root bridge instances array.
    +  @param Count   The count of the array.
    +**/
    +VOID
    +EFIAPI
    +PciHostBridgeFreeRootBridges (
    +  PCI_ROOT_BRIDGE *Bridges,
    +  UINTN           Count
    +  )
    +{
    +}
    +
    +/**
    +  Inform the platform that the resource conflict happens.
    +
    +  @param HostBridgeHandle Handle of the Host Bridge.
    +  @param Configuration    Pointer to PCI I/O and PCI memory resource
    +                          descriptors. The Configuration contains the resources
    +                          for all the root bridges. The resource for each root
    +                          bridge is terminated with END descriptor and an
    +                          additional END is appended indicating the end of the
    +                          entire resources. The resource descriptor field
    +                          values follow the description in
    +                          EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
    +                          .SubmitResources().
    +**/
    +VOID
    +EFIAPI
    +PciHostBridgeResourceConflict (
    +  EFI_HANDLE                        HostBridgeHandle,
    +  VOID                              *Configuration
    +  )
    +{
    +  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
    +  UINTN                             RootBridgeIndex;
    +  DEBUG ((DEBUG_ERROR, "PciHostBridge: Resource conflict happens!\n"));
    +
    +  RootBridgeIndex = 0;
    +  Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;
    +  while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) {
    +    DEBUG ((DEBUG_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++));
    +    for (; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) {
    +      ASSERT (Descriptor->ResType <
    +              (ARRAY_SIZE (mPciHostBridgeLibAcpiAddressSpaceTypeStr))
    +              );
    +      DEBUG ((DEBUG_ERROR, "%s: Length/Alignment = 0x%lx / 0x%lx\n",
    +              mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType],
    +              Descriptor->AddrLen, Descriptor->AddrRangeMax
    +              ));
    +      if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {
    +        DEBUG ((DEBUG_ERROR, "Granularity/SpecificFlag = %ld / %02x%s\n",
    +                Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag,
    +                ((Descriptor->SpecificFlag &
    +                  EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE
    +                  ) != 0) ? L" (Prefetchable)" : L""
    +                ));
    +      }
    +    }
    +    //
    +    // Skip the END descriptor for root bridge
    +    //
    +    ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR);
    +    Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)(
    +                   (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1
    +                   );
    +  }
    +}
    -- 
    2.17.1