From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) (using TLSv1 with cipher CAMELLIA256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id EBA5681CEB for ; Mon, 31 Oct 2016 19:25:43 -0700 (PDT) Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga103.jf.intel.com with ESMTP; 31 Oct 2016 19:25:45 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.31,577,1473145200"; d="scan'208";a="26304047" Received: from fmsmsx103.amr.corp.intel.com ([10.18.124.201]) by orsmga004.jf.intel.com with ESMTP; 31 Oct 2016 19:25:44 -0700 Received: from shsmsx101.ccr.corp.intel.com (10.239.4.153) by FMSMSX103.amr.corp.intel.com (10.18.124.201) with Microsoft SMTP Server (TLS) id 14.3.248.2; Mon, 31 Oct 2016 19:25:44 -0700 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.206]) by SHSMSX101.ccr.corp.intel.com ([169.254.1.104]) with mapi id 14.03.0248.002; Tue, 1 Nov 2016 10:25:42 +0800 From: "Fan, Jeff" To: Leo Duran , "edk2-devel@lists.01.org" CC: "Gao, Liming" , "lersek@redhat.com" , "Kinney, Michael D" Thread-Topic: [PATCH] UefiCpuPkg: Move GetProcessorLocation() to LocalApicLib library Thread-Index: AQHSM68Mrm3MzSyKcUylvP5I1q4giqDDYpIg Date: Tue, 1 Nov 2016 02:25:41 +0000 Message-ID: <542CF652F8836A4AB8DBFAAD40ED192A4A2BC512@shsmsx102.ccr.corp.intel.com> References: <1477942977-25242-1-git-send-email-leo.duran@amd.com> In-Reply-To: <1477942977-25242-1-git-send-email-leo.duran@amd.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiNjZiMzg0M2UtOTM5OC00MzQ0LTgxMzQtN2JkZmVmZjUxMjdiIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE1LjkuNi42IiwiVHJ1c3RlZExhYmVsSGFzaCI6Ilwvc2QxNUdaVDk1TjdcL3ZnWXV6bkZCZVFaM2xZQ1FxcFNuQm9ENk5NS3hcL009In0= x-ctpclassification: CTP_IC x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH] UefiCpuPkg: Move GetProcessorLocation() to LocalApicLib library X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 01 Nov 2016 02:25:44 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Leo, I just recognized GetProcessorLocation() is too generic name and used by ot= her library or modules to return Processor location from MP services. For example, the old Galileo-board-software-package used the same API to re= turn Processor Location. To avoid changing other library/modules, I suggest to use one specific name= in Local APIC Library, for example GetProcessorLocationByApicId (). I will create the patch to do this renaming. Thanks! Jeff -----Original Message----- From: Leo Duran [mailto:leo.duran@amd.com]=20 Sent: Tuesday, November 01, 2016 3:43 AM To: edk2-devel@lists.01.org Cc: Gao, Liming; lersek@redhat.com; Fan, Jeff; Kinney, Michael D; Leo Duran Subject: [PATCH] UefiCpuPkg: Move GetProcessorLocation() to LocalApicLib li= brary 1) Remove SmmGetProcessorLocation() from PiSmmCpuDxeSmm driver. 2) Remove ExtractProcessorLocation() from MpInitLib library. 3) Add GetProcessorLocation() to BaseXApicLib and BaseXApicX2ApicLib. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leo Duran --- UefiCpuPkg/Include/Library/LocalApicLib.h | 20 +++ UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c | 146 +++++++++++++++++= ++++ .../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c | 146 +++++++++++++++++= ++++ UefiCpuPkg/Library/MpInitLib/MpLib.c | 133 +----------------= -- UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c | 126 +----------------= - 5 files changed, 324 insertions(+), 247 deletions(-) diff --git a/UefiCpuPkg/Include/Library/LocalApicLib.h b/UefiCpuPkg/Include= /Library/LocalApicLib.h index cd4e613..179409e 100644 --- a/UefiCpuPkg/Include/Library/LocalApicLib.h +++ b/UefiCpuPkg/Include/Library/LocalApicLib.h @@ -410,6 +410,26 @@ GetApicMsiValue ( IN BOOLEAN LevelTriggered, IN BOOLEAN AssertionLevel ); + +/** + Get Package ID/Core ID/Thread ID of a processor. + + The algorithm assumes the target system has symmetry across physical =20 + package boundaries with respect to the number of logical processors =20 + per package, number of cores per package. + + @param[in] InitialApicId Initial APIC ID of the target logical process= or. + @param[out] Package Returns the processor package ID. + @param[out] Core Returns the processor core ID. + @param[out] Thread Returns the processor thread ID. +**/ +VOID +GetProcessorLocation( + IN UINT32 InitialApicId, + OUT UINT32 *Package OPTIONAL, + OUT UINT32 *Core OPTIONAL, + OUT UINT32 *Thread OPTIONAL + ); =20 #endif =20 diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c b/UefiCpuPkg/Li= brary/BaseXApicLib/BaseXApicLib.c index 8d0fb02..f32d287 100644 --- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c +++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c @@ -941,3 +941,149 @@ GetApicMsiValue ( } return MsiData.Uint64; } + +/** + Get Package ID/Core ID/Thread ID of a processor. + + The algorithm assumes the target system has symmetry across physical =20 + package boundaries with respect to the number of logical processors =20 + per package, number of cores per package. + + @param[in] InitialApicId Initial APIC ID of the target logical process= or. + @param[out] Package Returns the processor package ID. + @param[out] Core Returns the processor core ID. + @param[out] Thread Returns the processor thread ID. +**/ +VOID +GetProcessorLocation( + IN UINT32 InitialApicId, + OUT UINT32 *Package OPTIONAL, + OUT UINT32 *Core OPTIONAL, + OUT UINT32 *Thread OPTIONAL + ) +{ + BOOLEAN TopologyLeafSupported; + UINTN ThreadBits; + UINTN CoreBits; + CPUID_VERSION_INFO_EBX VersionInfoEbx; + CPUID_VERSION_INFO_EDX VersionInfoEdx; + CPUID_CACHE_PARAMS_EAX CacheParamsEax; + CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax; + CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx; + CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx; + UINT32 MaxCpuIdIndex; + UINT32 SubIndex; + UINTN LevelType; + UINT32 MaxLogicProcessorsPerPackage; + UINT32 MaxCoresPerPackage; + + // + // Check if the processor is capable of supporting more than one logical= processor. + // + AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL,=20 + &VersionInfoEdx.Uint32); if (VersionInfoEdx.Bits.HTT =3D=3D 0) { + if (Thread !=3D NULL) { + *Thread =3D 0; + } + if (Core !=3D NULL) { + *Core =3D 0; + } + if (Package !=3D NULL) { + *Package =3D 0; + } + return; + } + + ThreadBits =3D 0; + CoreBits =3D 0; + + // + // Assume three-level mapping of APIC ID: Package:Core:SMT. + // + TopologyLeafSupported =3D FALSE; + + // + // Get the max index of basic CPUID + // + AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL); + + // + // If the extended topology enumeration leaf is available, it // is=20 + the preferred mechanism for enumerating topology. + // + if (MaxCpuIdIndex >=3D CPUID_EXTENDED_TOPOLOGY) { + AsmCpuidEx( + CPUID_EXTENDED_TOPOLOGY, + 0, + &ExtendedTopologyEax.Uint32, + &ExtendedTopologyEbx.Uint32, + &ExtendedTopologyEcx.Uint32, + NULL + ); + // + // If CPUID.(EAX=3D0BH, ECX=3D0H):EBX returns zero and maximum input v= alue for + // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is= not + // supported on that processor. + // + if (ExtendedTopologyEbx.Uint32 !=3D 0) { + TopologyLeafSupported =3D TRUE; + + // + // Sub-leaf index 0 (ECX=3D 0 as input) provides enumeration paramet= ers to extract + // the SMT sub-field of x2APIC ID. + // + LevelType =3D ExtendedTopologyEcx.Bits.LevelType; + ASSERT(LevelType =3D=3D CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT); + ThreadBits =3D ExtendedTopologyEax.Bits.ApicIdShift; + + // + // Software must not assume any "level type" encoding + // value to be related to any sub-leaf index, except sub-leaf 0. + // + SubIndex =3D 1; + do { + AsmCpuidEx( + CPUID_EXTENDED_TOPOLOGY, + SubIndex, + &ExtendedTopologyEax.Uint32, + NULL, + &ExtendedTopologyEcx.Uint32, + NULL + ); + LevelType =3D ExtendedTopologyEcx.Bits.LevelType; + if (LevelType =3D=3D CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) { + CoreBits =3D ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits; + break; + } + SubIndex++; + } while (LevelType !=3D CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID); + } + } + + if (!TopologyLeafSupported) { + AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL)= ; + MaxLogicProcessorsPerPackage =3D VersionInfoEbx.Bits.MaximumAddressabl= eIdsForLogicalProcessors; + if (MaxCpuIdIndex >=3D CPUID_CACHE_PARAMS) { + AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL= , NULL); + MaxCoresPerPackage =3D CacheParamsEax.Bits.MaximumAddressableIdsForL= ogicalProcessors + 1; + } + else { + // + // Must be a single-core processor. + // + MaxCoresPerPackage =3D 1; + } + + ThreadBits =3D (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / Max= CoresPerPackage - 1) + 1); + CoreBits =3D (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); } + + if (Thread !=3D NULL) { + *Thread =3D InitialApicId & ((1 << ThreadBits) - 1); + } + if (Core !=3D NULL) { + *Core =3D (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1); + } + if (Package !=3D NULL) { + *Package =3D (InitialApicId >> (ThreadBits + CoreBits)); + } +} diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c b/U= efiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c index 4c42696..a34a272 100644 --- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c +++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c @@ -1036,3 +1036,149 @@ GetApicMsiValue ( } return MsiData.Uint64; } + +/** + Get Package ID/Core ID/Thread ID of a processor. + + The algorithm assumes the target system has symmetry across physical =20 + package boundaries with respect to the number of logical processors =20 + per package, number of cores per package. + + @param[in] InitialApicId Initial APIC ID of the target logical process= or. + @param[out] Package Returns the processor package ID. + @param[out] Core Returns the processor core ID. + @param[out] Thread Returns the processor thread ID. +**/ +VOID +GetProcessorLocation( + IN UINT32 InitialApicId, + OUT UINT32 *Package OPTIONAL, + OUT UINT32 *Core OPTIONAL, + OUT UINT32 *Thread OPTIONAL + ) +{ + BOOLEAN TopologyLeafSupported; + UINTN ThreadBits; + UINTN CoreBits; + CPUID_VERSION_INFO_EBX VersionInfoEbx; + CPUID_VERSION_INFO_EDX VersionInfoEdx; + CPUID_CACHE_PARAMS_EAX CacheParamsEax; + CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax; + CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx; + CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx; + UINT32 MaxCpuIdIndex; + UINT32 SubIndex; + UINTN LevelType; + UINT32 MaxLogicProcessorsPerPackage; + UINT32 MaxCoresPerPackage; + + // + // Check if the processor is capable of supporting more than one logical= processor. + // + AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL,=20 + &VersionInfoEdx.Uint32); if (VersionInfoEdx.Bits.HTT =3D=3D 0) { + if (Thread !=3D NULL) { + *Thread =3D 0; + } + if (Core !=3D NULL) { + *Core =3D 0; + } + if (Package !=3D NULL) { + *Package =3D 0; + } + return; + } + + ThreadBits =3D 0; + CoreBits =3D 0; + + // + // Assume three-level mapping of APIC ID: Package:Core:SMT. + // + TopologyLeafSupported =3D FALSE; + + // + // Get the max index of basic CPUID + // + AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL); + + // + // If the extended topology enumeration leaf is available, it // is=20 + the preferred mechanism for enumerating topology. + // + if (MaxCpuIdIndex >=3D CPUID_EXTENDED_TOPOLOGY) { + AsmCpuidEx( + CPUID_EXTENDED_TOPOLOGY, + 0, + &ExtendedTopologyEax.Uint32, + &ExtendedTopologyEbx.Uint32, + &ExtendedTopologyEcx.Uint32, + NULL + ); + // + // If CPUID.(EAX=3D0BH, ECX=3D0H):EBX returns zero and maximum input v= alue for + // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is= not + // supported on that processor. + // + if (ExtendedTopologyEbx.Uint32 !=3D 0) { + TopologyLeafSupported =3D TRUE; + + // + // Sub-leaf index 0 (ECX=3D 0 as input) provides enumeration paramet= ers to extract + // the SMT sub-field of x2APIC ID. + // + LevelType =3D ExtendedTopologyEcx.Bits.LevelType; + ASSERT(LevelType =3D=3D CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT); + ThreadBits =3D ExtendedTopologyEax.Bits.ApicIdShift; + + // + // Software must not assume any "level type" encoding + // value to be related to any sub-leaf index, except sub-leaf 0. + // + SubIndex =3D 1; + do { + AsmCpuidEx( + CPUID_EXTENDED_TOPOLOGY, + SubIndex, + &ExtendedTopologyEax.Uint32, + NULL, + &ExtendedTopologyEcx.Uint32, + NULL + ); + LevelType =3D ExtendedTopologyEcx.Bits.LevelType; + if (LevelType =3D=3D CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) { + CoreBits =3D ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits; + break; + } + SubIndex++; + } while (LevelType !=3D CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID); + } + } + + if (!TopologyLeafSupported) { + AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL)= ; + MaxLogicProcessorsPerPackage =3D VersionInfoEbx.Bits.MaximumAddressabl= eIdsForLogicalProcessors; + if (MaxCpuIdIndex >=3D CPUID_CACHE_PARAMS) { + AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL= , NULL); + MaxCoresPerPackage =3D CacheParamsEax.Bits.MaximumAddressableIdsForL= ogicalProcessors + 1; + } + else { + // + // Must be a single-core processor. + // + MaxCoresPerPackage =3D 1; + } + + ThreadBits =3D (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / Max= CoresPerPackage - 1) + 1); + CoreBits =3D (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); } + + if (Thread !=3D NULL) { + *Thread =3D InitialApicId & ((1 << ThreadBits) - 1); + } + if (Core !=3D NULL) { + *Core =3D (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1); + } + if (Package !=3D NULL) { + *Package =3D (InitialApicId >> (ThreadBits + CoreBits)); + } +} diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpIn= itLib/MpLib.c index c3fe721..e48ff6a 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c @@ -58,132 +58,6 @@ IsBspExecuteDisableEnabled ( } =20 /** - Get CPU Package/Core/Thread location information. - - @param[in] InitialApicId CPU APIC ID - @param[out] Location Pointer to CPU location information -**/ -VOID -ExtractProcessorLocation ( - IN UINT32 InitialApicId, - OUT EFI_CPU_PHYSICAL_LOCATION *Location - ) -{ - BOOLEAN TopologyLeafSupported; - UINTN ThreadBits; - UINTN CoreBits; - CPUID_VERSION_INFO_EBX VersionInfoEbx; - CPUID_VERSION_INFO_EDX VersionInfoEdx; - CPUID_CACHE_PARAMS_EAX CacheParamsEax; - CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax; - CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx; - CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx; - UINT32 MaxCpuIdIndex; - UINT32 SubIndex; - UINTN LevelType; - UINT32 MaxLogicProcessorsPerPackage; - UINT32 MaxCoresPerPackage; - - // - // Check if the processor is capable of supporting more than one logical= processor. - // - AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32); - if (VersionInfoEdx.Bits.HTT =3D=3D 0) { - Location->Thread =3D 0; - Location->Core =3D 0; - Location->Package =3D 0; - return; - } - - ThreadBits =3D 0; - CoreBits =3D 0; - - // - // Assume three-level mapping of APIC ID: Package:Core:SMT. - // - - TopologyLeafSupported =3D FALSE; - // - // Get the max index of basic CPUID - // - AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL); - - // - // If the extended topology enumeration leaf is available, it - // is the preferred mechanism for enumerating topology. - // - if (MaxCpuIdIndex >=3D CPUID_EXTENDED_TOPOLOGY) { - AsmCpuidEx ( - CPUID_EXTENDED_TOPOLOGY, - 0, - &ExtendedTopologyEax.Uint32, - &ExtendedTopologyEbx.Uint32, - &ExtendedTopologyEcx.Uint32, - NULL - ); - // - // If CPUID.(EAX=3D0BH, ECX=3D0H):EBX returns zero and maximum input v= alue for - // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is= not - // supported on that processor. - // - if (ExtendedTopologyEbx.Uint32 !=3D 0) { - TopologyLeafSupported =3D TRUE; - - // - // Sub-leaf index 0 (ECX=3D 0 as input) provides enumeration paramet= ers to extract - // the SMT sub-field of x2APIC ID. - // - LevelType =3D ExtendedTopologyEcx.Bits.LevelType; - ASSERT (LevelType =3D=3D CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT); - ThreadBits =3D ExtendedTopologyEax.Bits.ApicIdShift; - - // - // Software must not assume any "level type" encoding - // value to be related to any sub-leaf index, except sub-leaf 0. - // - SubIndex =3D 1; - do { - AsmCpuidEx ( - CPUID_EXTENDED_TOPOLOGY, - SubIndex, - &ExtendedTopologyEax.Uint32, - NULL, - &ExtendedTopologyEcx.Uint32, - NULL - ); - LevelType =3D ExtendedTopologyEcx.Bits.LevelType; - if (LevelType =3D=3D CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) { - CoreBits =3D ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits; - break; - } - SubIndex++; - } while (LevelType !=3D CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID); - } - } - - if (!TopologyLeafSupported) { - AsmCpuid (CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL= ); - MaxLogicProcessorsPerPackage =3D VersionInfoEbx.Bits.MaximumAddressabl= eIdsForLogicalProcessors; - if (MaxCpuIdIndex >=3D CPUID_CACHE_PARAMS) { - AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NUL= L, NULL); - MaxCoresPerPackage =3D CacheParamsEax.Bits.MaximumAddressableIdsForL= ogicalProcessors + 1; - } else { - // - // Must be a single-core processor. - // - MaxCoresPerPackage =3D 1; - } - - ThreadBits =3D (UINTN) (HighBitSet32 (MaxLogicProcessorsPerPackage / M= axCoresPerPackage - 1) + 1); - CoreBits =3D (UINTN) (HighBitSet32 (MaxCoresPerPackage - 1) + 1); - } - - Location->Thread =3D InitialApicId & ((1 << ThreadBits) - 1); - Location->Core =3D (InitialApicId >> ThreadBits) & ((1 << CoreBits) -= 1); - Location->Package =3D (InitialApicId >> (ThreadBits + CoreBits)); -} - -/** Worker function for SwitchBSP(). =20 Worker function for SwitchBSP(), assigned to the AP which is intended @@= -1451,7 +1325,12 @@ MpInitLibGetProcessorInfo ( // // Get processor location information // - ExtractProcessorLocation (CpuMpData->CpuData[ProcessorNumber].ApicId, &P= rocessorInfoBuffer->Location); + GetProcessorLocation ( + CpuMpData->CpuData[ProcessorNumber].ApicId, + &ProcessorInfoBuffer->Location.Package, + &ProcessorInfoBuffer->Location.Core, + &ProcessorInfoBuffer->Location.Thread + ); =20 if (HealthData !=3D NULL) { HealthData->Uint32 =3D CpuMpData->CpuData[ProcessorNumber].Health; diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c b/UefiCpuPkg/PiSmmCpuDx= eSmm/CpuService.c index 40f2a17..f377a36 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c @@ -27,125 +27,6 @@ EFI_SMM_CPU_SERVICE_PROTOCOL mSmmCpuService =3D { }; =20 /** - Get Package ID/Core ID/Thread ID of a processor. - - APIC ID must be an initial APIC ID. - - The algorithm below assumes the target system has symmetry across physic= al package boundaries - with respect to the number of logical processors per package, number of = cores per package. - - @param ApicId APIC ID of the target logical processor. - @param Location Returns the processor location information. -**/ -VOID -SmmGetProcessorLocation ( - IN UINT32 ApicId, - OUT EFI_CPU_PHYSICAL_LOCATION *Location - ) -{ - UINTN ThreadBits; - UINTN CoreBits; - UINT32 RegEax; - UINT32 RegEbx; - UINT32 RegEcx; - UINT32 RegEdx; - UINT32 MaxCpuIdIndex; - UINT32 SubIndex; - UINTN LevelType; - UINT32 MaxLogicProcessorsPerPackage; - UINT32 MaxCoresPerPackage; - BOOLEAN TopologyLeafSupported; - - ASSERT (Location !=3D NULL); - - ThreadBits =3D 0; - CoreBits =3D 0; - TopologyLeafSupported =3D FALSE; - - // - // Check if the processor is capable of supporting more than one logical= processor. - // - AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &RegEdx); - ASSERT ((RegEdx & BIT28) !=3D 0); - - // - // Assume three-level mapping of APIC ID: Package:Core:SMT. - // - - // - // Get the max index of basic CPUID - // - AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL); - - // - // If the extended topology enumeration leaf is available, it - // is the preferred mechanism for enumerating topology. - // - if (MaxCpuIdIndex >=3D CPUID_EXTENDED_TOPOLOGY) { - AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 0, &RegEax, &RegEbx, &RegEcx, NUL= L); - // - // If CPUID.(EAX=3D0BH, ECX=3D0H):EBX returns zero and maximum input v= alue for - // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is= not - // supported on that processor. - // - if ((RegEbx & 0xffff) !=3D 0) { - TopologyLeafSupported =3D TRUE; - - // - // Sub-leaf index 0 (ECX=3D 0 as input) provides enumeration paramet= ers to extract - // the SMT sub-field of x2APIC ID. - // - LevelType =3D (RegEcx >> 8) & 0xff; - ASSERT (LevelType =3D=3D CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT); - if ((RegEbx & 0xffff) > 1 ) { - ThreadBits =3D RegEax & 0x1f; - } else { - // - // HT is not supported - // - ThreadBits =3D 0; - } - - // - // Software must not assume any "level type" encoding - // value to be related to any sub-leaf index, except sub-leaf 0. - // - SubIndex =3D 1; - do { - AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, SubIndex, &RegEax, NULL, &Reg= Ecx, NULL); - LevelType =3D (RegEcx >> 8) & 0xff; - if (LevelType =3D=3D CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) { - CoreBits =3D (RegEax & 0x1f) - ThreadBits; - break; - } - SubIndex++; - } while (LevelType !=3D CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID); - } - } - - if (!TopologyLeafSupported) { - AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL); - MaxLogicProcessorsPerPackage =3D (RegEbx >> 16) & 0xff; - if (MaxCpuIdIndex >=3D CPUID_CACHE_PARAMS) { - AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &RegEax, NULL, NULL, NULL); - MaxCoresPerPackage =3D (RegEax >> 26) + 1; - } else { - // - // Must be a single-core processor. - // - MaxCoresPerPackage =3D 1; - } - - ThreadBits =3D (UINTN) (HighBitSet32 (MaxLogicProcessorsPerPackage / M= axCoresPerPackage - 1) + 1); - CoreBits =3D (UINTN) (HighBitSet32 (MaxCoresPerPackage - 1) + 1); - } - - Location->Thread =3D ApicId & ~((-1) << ThreadBits); - Location->Core =3D (ApicId >> ThreadBits) & ~((-1) << CoreBits); - Location->Package =3D (ApicId >> (ThreadBits+ CoreBits)); -} - -/** Gets processor information on the requested processor at the instant thi= s call is made. =20 @param[in] This A pointer to the EFI_SMM_CPU_SERVICE_PR= OTOCOL instance. @@ -280,7 +161,12 @@ SmmAddProcessor ( gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId =3D=3D INVALID_AP= IC_ID) { gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId =3D ProcessorId; gSmmCpuPrivate->ProcessorInfo[Index].StatusFlag =3D 0; - SmmGetProcessorLocation ((UINT32)ProcessorId, &gSmmCpuPrivate->Proce= ssorInfo[Index].Location); + GetProcessorLocation ( + (UINT32)ProcessorId, + &gSmmCpuPrivate->ProcessorInfo[Index].Location.Package, + &gSmmCpuPrivate->ProcessorInfo[Index].Location.Core, + &gSmmCpuPrivate->ProcessorInfo[Index].Location.Thread + ); =20 *ProcessorNumber =3D Index; gSmmCpuPrivate->Operation[Index] =3D SmmCpuAdd; -- 1.9.1