From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9670481EA5 for ; Fri, 11 Nov 2016 04:38:13 -0800 (PST) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga103.jf.intel.com with ESMTP; 11 Nov 2016 04:38:17 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.31,621,1473145200"; d="scan'208";a="1058263424" Received: from fmsmsx107.amr.corp.intel.com ([10.18.124.205]) by orsmga001.jf.intel.com with ESMTP; 11 Nov 2016 04:38:17 -0800 Received: from fmsmsx124.amr.corp.intel.com (10.18.125.39) by fmsmsx107.amr.corp.intel.com (10.18.124.205) with Microsoft SMTP Server (TLS) id 14.3.248.2; Fri, 11 Nov 2016 04:38:16 -0800 Received: from shsmsx151.ccr.corp.intel.com (10.239.6.50) by fmsmsx124.amr.corp.intel.com (10.18.125.39) with Microsoft SMTP Server (TLS) id 14.3.248.2; Fri, 11 Nov 2016 04:38:16 -0800 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.239]) by SHSMSX151.ccr.corp.intel.com ([169.254.3.96]) with mapi id 14.03.0248.002; Fri, 11 Nov 2016 20:38:12 +0800 From: "Fan, Jeff" To: Laszlo Ersek , "Yao, Jiewen" , "edk2-devel@lists.01.org" CC: "Tian, Feng" , "Kinney, Michael D" , Paolo Bonzini , "Zeng, Star" Thread-Topic: [edk2] [PATCH V3 0/6] Enable SMM page level protection. Thread-Index: AQHSO/o3yjH/vKbUyEWBCLbqnqd9SqDS+VMAgAA2RICAAId00A== Date: Fri, 11 Nov 2016 12:38:12 +0000 Message-ID: <542CF652F8836A4AB8DBFAAD40ED192A4A2DAC96@shsmsx102.ccr.corp.intel.com> References: <1478854859-11096-1-git-send-email-jiewen.yao@intel.com> <74D8A39837DF1E4DA445A8C0B3885C50386CF501@shsmsx102.ccr.corp.intel.com> In-Reply-To: Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiYmNiOGU4ZDMtMGYwNy00ODRmLWFhZjAtN2VjMmM0OTE0ZWVmIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE1LjkuNi42IiwiVHJ1c3RlZExhYmVsSGFzaCI6IlMwM1FcL0JONzZGbVpjZ1M4SnZVanNyZ2V0QWwyWGNzR3NrWFhpd0RPSXBBPSJ9 x-ctpclassification: CTP_IC x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH V3 0/6] Enable SMM page level protection. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 11 Nov 2016 12:38:13 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Laszlo, NX support and fix in SmiEntry.asm is new code for UefiCpuPkg. So, that mea= ns we still have other unknown problem on S3 boot issue. Jeff -----Original Message----- From: Laszlo Ersek [mailto:lersek@redhat.com]=20 Sent: Friday, November 11, 2016 8:26 PM To: Yao, Jiewen; edk2-devel@lists.01.org; Fan, Jeff Cc: Tian, Feng; Kinney, Michael D; Paolo Bonzini; Zeng, Star Subject: Re: [edk2] [PATCH V3 0/6] Enable SMM page level protection. Jiewen, Jeff, On 11/11/16 10:12, Yao, Jiewen wrote: > HI Laszlo > I fixed the IA32 boot issue in this patch Thank you. Jiewen, I'd like to request the following: - Please separate the fix for the incorrect parameter passing to SmiRendezvous() out to a separate patch. It is my understanding that the issue exists already in the master branch. Is that right? If it is, then the fix should not be tied to the SMM page level protection feature. - Please give that patch to Jeff. Jeff, can you please repost your series [edk2] [PATCH v2 0/3] Put AP into safe hlt-loop code on S3 path to edk2-devel, as v3, with Jiewen's patch from above included, as patch#4? = Because, I would like to see a patch series that addresses all known S3 iss= ues that we've uncovered in this investigation. The first three patches should fix BZ#216, yes. The last (4th) patch, from Jiewen, is unrelated to that BZ indeed, but it n= onetheless addresses an existent issue in PiSmmCpuDxeSmm that can be hit du= ring S3. My goal is to apply that series (the first 3 patches from Jeff, and the fou= rth patch from Jiewen), and to test it as one unit. I'd like to see if thos= e changes fix the infrequent, but still triggerable issues with S3+SMM, for both Ia32 and Ia32X64. If everything works fine, then that series should be committed. After that, I'd like to test Jiewen's v4 series for the SMM page level prot= ection, separately. In other words, first we should fix the existent bugs that Jiewen's SMM pag= e level protection feature only amplifies (but doesn't introduce) on QEMU/K= VM + OVMF. Once the known bugs are fixed, I'll be glad to test the new feat= ure. Would this work for you guys? Thank you, Laszlo > with DEBUG message update you suggested. >=20 > My unit test failed before. Now it can pass. > I validated on a real IA32 and Windows OVMF with and without XD. >=20 >=20 > For QEMU installation, it is still on progress. > We have setup a Fedora 24 host, download QEMU, and install it. > But we are still struggling to make QEMU boot on Fedora. > Your step by step is great. There is still some minor place we stuck in d= ue to my ignorance. > My goal is still to setup an environment like yours for our validation or= issue reproduce. > It just need take some time, more than I expected. sign... >=20 > Thank you > Yao Jiewen >=20 >> -----Original Message----- >> From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf=20 >> Of Jiewen Yao >> Sent: Friday, November 11, 2016 5:01 PM >> To: edk2-devel@lists.01.org >> Cc: Tian, Feng ; Kinney, Michael D=20 >> ; Paolo Bonzini ;=20 >> Laszlo Ersek ; Fan, Jeff ;=20 >> Zeng, Star >> Subject: [edk2] [PATCH V3 0/6] Enable SMM page level protection. >> >> >> =3D=3D=3D=3D below is V3 description =3D=3D=3D=3D >> 1) PiSmmCpu: Fix CpuIndex corruption issue due to stack malposition. >> (Many thanks to Laszlo Ersek for catching it.) >> 2) PiSmmCpu: Add ASSERT for CpuIndex check. >> 3) PiSmmCpu: Use DEBUG_VERBOSE for page table update. >> 4) PiSmmCpu: Do not report DEBUG message for Ap non present when=20 >> PcdCpuSmmSyncMode=3D=3D1 (Relex mode). >> 5) PiSmmCpu: Do not report DEBUG message for AP removed when=20 >> PcdCpuHotPlugSupport=3D=3DTRUE. >> >> Tested combination: >> 1) XD disabled >> 2) XD enabled in SMM and disabled in non-SMM. >> 3) XD enabled in SMM and enabled in non-SMM. >> >> =3D=3D=3D=3D below is V2 description =3D=3D=3D=3D >> 1) PiSmmCpu: resolve OVMF multiple processors boot hang issue. >> 2) PiSmmCpu: Add debug info on StartupAp() fails. >> 3) PiSmmCpu: Add ASSERT for AllocatePages(). >> 4) PiSmmCpu: Add protection detail in commit message. >> 5) UefiCpuPkg.dsc: Add page table footprint info in commit message. >> >> =3D=3D=3D=3D below is V1 description =3D=3D=3D=3D >> This series patch enables SMM page level protection. >> Features are: >> 1) PiSmmCore reports SMM PE image code/data information in=20 >> EdkiiPiSmmMemoryAttributeTable, if the SMM image is page aligned. >> 2) PiSmmCpu consumes EdkiiPiSmmMemoryAttributeTable and set XD for=20 >> data page and RO for code page. >> 3) PiSmmCpu enables Static Paging for X64 according to=20 >> PcdCpuSmmStaticPageTable. If it is true, 1G paging for above 4G is=20 >> used as long as it is supported. >> 4) PiSmmCpu sets importance data structure to be read only, such as=20 >> Gdt, Idt, SmmEntrypoint, and PageTable itself. >> >> tested platform: >> 1) Intel internal platform (X64). >> 2) EDKII Quark IA32 >> 3) EDKII Vlv2 X64 >> 4) EDKII OVMF IA32 and IA32X64. (with -smp 8) >> >> Cc: Jeff Fan >> Cc: Feng Tian >> Cc: Star Zeng >> Cc: Michael D Kinney >> Cc: Laszlo Ersek >> Cc: Paolo Bonzini >> Contributed-under: TianoCore Contribution Agreement 1.0 >> Signed-off-by: Jiewen Yao >> >> Jiewen Yao (6): >> MdeModulePkg/Include: Add PiSmmMemoryAttributesTable.h >> MdeModulePkg/dec: Add gEdkiiPiSmmMemoryAttributesTableGuid. >> MdeModulePkg/PiSmmCore: Add MemoryAttributes support. >> UefiCpuPkg/dec: Add PcdCpuSmmStaticPageTable. >> UefiCpuPkg/PiSmmCpuDxeSmm: Add paging protection. >> QuarkPlatformPkg/dsc: enable Smm paging protection. >> >> MdeModulePkg/Core/PiSmmCore/Dispatcher.c | 66 + >> MdeModulePkg/Core/PiSmmCore/MemoryAttributesTable.c | 1509 >> ++++++++++++++++++++ >> MdeModulePkg/Core/PiSmmCore/Page.c | 775 >> +++++++++- >> MdeModulePkg/Core/PiSmmCore/PiSmmCore.c | 40 >> + >> MdeModulePkg/Core/PiSmmCore/PiSmmCore.h | 91 >> ++ >> MdeModulePkg/Core/PiSmmCore/PiSmmCore.inf | 2 >> + >> MdeModulePkg/Core/PiSmmCore/Pool.c | 16 >> + >> MdeModulePkg/Include/Guid/PiSmmMemoryAttributesTable.h | 51 + >> MdeModulePkg/MdeModulePkg.dec | >> 3 + >> QuarkPlatformPkg/Quark.dsc | 6 + >> UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c | 71 >> +- >> UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S | 75 >> +- >> UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm | 75 >> +- >> UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm | 79 >> +- >> UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiException.S | 226 >> +-- >> UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiException.asm | 36 >> +- >> UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiException.nasm | 36 >> +- >> UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmFuncsArch.c | 37 >> +- >> UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmProfileArch.c | 4 >> +- >> UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 135 >> +- >> UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | >> 144 +- >> UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | >> 156 +- >> UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf | >> 5 +- >> UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | >> 871 +++++++++++ >> UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c | 39 >> +- >> UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.h | 15 >> +- >> UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 274 >> +++- >> UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S | 59 >> +- >> UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm | 62 >> +- >> UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm | 69 >> +- >> UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiException.S | 250 >> +--- >> UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiException.asm | 35 >> +- >> UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiException.nasm | 31 >> +- >> UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c | 30 >> +- >> UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.c | 7 >> +- >> UefiCpuPkg/UefiCpuPkg.dec | 8 + >> 36 files changed, 4585 insertions(+), 803 deletions(-) create mode=20 >> 100644 MdeModulePkg/Core/PiSmmCore/MemoryAttributesTable.c >> create mode 100644 >> MdeModulePkg/Include/Guid/PiSmmMemoryAttributesTable.h >> create mode 100644 >> UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c >> >> -- >> 2.7.4.windows.1 >> >> _______________________________________________ >> edk2-devel mailing list >> edk2-devel@lists.01.org >> https://lists.01.org/mailman/listinfo/edk2-devel > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel >=20