From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 66FD181E40 for ; Mon, 21 Nov 2016 23:20:45 -0800 (PST) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga105.jf.intel.com with ESMTP; 21 Nov 2016 23:20:45 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.31,531,1473145200"; d="scan'208";a="789371028" Received: from fmsmsx105.amr.corp.intel.com ([10.18.124.203]) by FMSMGA003.fm.intel.com with ESMTP; 21 Nov 2016 23:20:45 -0800 Received: from shsmsx104.ccr.corp.intel.com (10.239.4.70) by FMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP Server (TLS) id 14.3.248.2; Mon, 21 Nov 2016 23:20:44 -0800 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.239]) by SHSMSX104.ccr.corp.intel.com ([169.254.5.142]) with mapi id 14.03.0248.002; Tue, 22 Nov 2016 15:20:42 +0800 From: "Fan, Jeff" To: Laszlo Ersek , edk2-devel-01 CC: "Justen, Jordan L" , "Kinney, Michael D" , Paolo Bonzini Thread-Topic: [PATCH v2 1/4] UefiCpuPkg/PiSmmCpuDxeSmm: dynamic PcdCpuSmmApSyncTimeout, PcdCpuSmmSyncMode Thread-Index: AQHSQaMWBlz1RzTdNUasalKqHaTy+6Dknl9A Date: Tue, 22 Nov 2016 07:20:42 +0000 Message-ID: <542CF652F8836A4AB8DBFAAD40ED192A4A2E475A@shsmsx102.ccr.corp.intel.com> References: <20161118135249.26018-1-lersek@redhat.com> <20161118135249.26018-2-lersek@redhat.com> In-Reply-To: <20161118135249.26018-2-lersek@redhat.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiMTM1MTkxZmMtYzA5Ni00Mzk1LTk4ZTgtOGZjMTVmNzA5ZWI5IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE1LjkuNi42IiwiVHJ1c3RlZExhYmVsSGFzaCI6IktDVlVzQlRWV3c2Q085bjRpclRwZjZuamRGK1czdnljMEo1eVNPTTllNW89In0= x-ctpclassification: CTP_IC x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH v2 1/4] UefiCpuPkg/PiSmmCpuDxeSmm: dynamic PcdCpuSmmApSyncTimeout, PcdCpuSmmSyncMode X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 22 Nov 2016 07:20:45 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Jeff Fan -----Original Message----- From: Laszlo Ersek [mailto:lersek@redhat.com]=20 Sent: Friday, November 18, 2016 9:53 PM To: edk2-devel-01 Cc: Fan, Jeff; Justen, Jordan L; Kinney, Michael D; Paolo Bonzini Subject: [PATCH v2 1/4] UefiCpuPkg/PiSmmCpuDxeSmm: dynamic PcdCpuSmmApSyncT= imeout, PcdCpuSmmSyncMode Move the declaration of these PCDs from the [PcdsFixedAtBuild, PcdsPatchableInModule] section of "UefiCpuPkg/UefiCpuPkg.dec" to the [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx] section. Their types, default values, and token values remain unchanged. Only UefiCpuPkg/PiSmmCpuDxeSmm consumes these PCDs, specifically on the cal= l stack of its entry point function, and it turns them into static or dynam= ically allocated data in SMRAM: PiCpuSmmEntry() [PiSmmCpuDxeSmm.c] InitializeSmmTimer() [SyncTimer.c] PcdCpuSmmApSyncTimeout -> mTimeoutTicker InitializeMpServiceData() [MpService.c] InitializeMpSyncData() [MpService.c] PcdCpuSmmSyncMode -> mSmmMpSyncData->EffectiveSyncMode However, there's another call path to fetching "PcdCpuSmmSyncMode", namely SmmInitHandler() [PiSmmCpuDxeSmm.c] InitializeMpSyncData() [MpService.c] PcdCpuSmmSyncMode -> mSmmMpSyncData->EffectiveSyncMode and this path is exercised during S3 resume (as stated by the comment in SmmInitHandler() too, "Initialize private data during S3 resume"). While we can call the PCD protocol (via PcdLib) for fetching dynamic PCDs i= n the entry point function, we cannot do that at S3 resume. Therefore pre-f= etch PcdCpuSmmSyncMode into a new global variable (which lives in SMRAM) in InitializeMpServiceData(), just before calling InitializeMpSyncDa= ta(). This way InitializeMpSyncData() can retrieve the stashed PCD value fr= om SMRAM, regardless of the boot mode. Cc: Jeff Fan Cc: Jordan Justen Cc: Michael Kinney Cc: Paolo Bonzini Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3D230 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek --- Notes: v2: - new in v2 UefiCpuPkg/UefiCpuPkg.dec | 20 ++++++++++---------- UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 4 +++- 2 files changed, 13 insertions(+), 11 deletions(-) diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec index 89= 779c447d50..ca560398bbef 100644 --- a/UefiCpuPkg/UefiCpuPkg.dec +++ b/UefiCpuPkg/UefiCpuPkg.dec @@ -156,10 +156,6 @@ [PcdsFixedAtBuild, PcdsPatchableInModule] # @Prompt Processor stack size in SMM. gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x2000|UINT32|0x32132105 =20 - ## Specifies timeout value in microseconds for the BSP in SMM to wait fo= r all APs to come into SMM. - # @Prompt AP synchronization timeout value in SMM. - gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|1000000|UINT64|0x321321= 04 - ## Indicates if SMM Code Access Check is enabled. # If enabled, the SMM handler cannot execute the code outside SMM regio= ns. # This PCD is suggested to TRUE in production image.

@@ -168,12= +164,6 @@ [PcdsFixedAtBuild, PcdsPatchableInModule] # @Prompt SMM Code Access Check. gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable|TRUE|BOOLEAN|0x= 60000013 =20 - ## Indicates the CPU synchronization method used when processing an SMI. - # 0x00 - Traditional CPU synchronization method.
- # 0x01 - Relaxed CPU synchronization method.
- # @Prompt SMM CPU Synchronization Method. - gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmSyncMode|0x00|UINT8|0x60000014 - ## Specifies the number of variable MTRRs reserved for OS use. The defau= lt number of # MTRRs reserved for OS use is 2. # @Prompt Number of reserved variable MTRRs. @@ -214,6 +204,16 @@ [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic,= PcdsDynamicEx] # @Prompt Use static page table for all memory in SMM. gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStaticPageTable|TRUE|BOOLEAN|0x321321= 0D =20 + ## Specifies timeout value in microseconds for the BSP in SMM to wait fo= r all APs to come into SMM. + # @Prompt AP synchronization timeout value in SMM. + =20 + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|1000000|UINT64|0x3213 + 2104 + + ## Indicates the CPU synchronization method used when processing an SMI. + # 0x00 - Traditional CPU synchronization method.
+ # 0x01 - Relaxed CPU synchronization method.
+ # @Prompt SMM CPU Synchronization Method. + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmSyncMode|0x00|UINT8|0x60000014 + [PcdsDynamic, PcdsDynamicEx] ## Contains the pointer to a CPU S3 data buffer of structure ACPI_CPU_DA= TA. # @Prompt The pointer to a CPU S3 data buffer. diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c b/UefiCpuPkg/PiSmmCpuDxe= Smm/MpService.c index 9b8db90ff6ed..cfbf59e8f2ca 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c @@ -24,6 +24,7 @@ UINTN mSmmMpSyncDat= aSize; SMM_CPU_SEMAPHORES mSmmCpuSemaphores; UINTN mSemaphoreSize; SPIN_LOCK *mPFLock =3D NULL; +SMM_CPU_SYNC_MODE mCpuSmmSyncMode; =20 /** Performs an atomic compare exchange operation to get semaphore. @@ -1338,7 +1339,7 @@ InitializeMpSyncData ( // mSmmMpSyncData->BspIndex =3D (UINT32)-1; } - mSmmMpSyncData->EffectiveSyncMode =3D (SMM_CPU_SYNC_MODE) PcdGet8 (Pcd= CpuSmmSyncMode); + mSmmMpSyncData->EffectiveSyncMode =3D mCpuSmmSyncMode; =20 mSmmMpSyncData->Counter =3D mSmmCpuSemaphores.SemaphoreGlobal.Co= unter; mSmmMpSyncData->InsideSmm =3D mSmmCpuSemaphores.SemaphoreGlobal.In= sideSmm; @@ -1392,6 +1393,7 @@ InitializeMpServiceData ( (sizeof (SMM_CPU_DATA_BLOCK) + sizeof (BOOLEAN)) * = gSmmCpuPrivate->SmmCoreEntryContext.NumberOfCpus; mSmmMpSyncData =3D (SMM_DISPATCHER_MP_SYNC_DATA*) AllocatePages (EFI_SIZ= E_TO_PAGES (mSmmMpSyncDataSize)); ASSERT (mSmmMpSyncData !=3D NULL); + mCpuSmmSyncMode =3D (SMM_CPU_SYNC_MODE)PcdGet8 (PcdCpuSmmSyncMode); InitializeMpSyncData (); =20 // -- 2.9.2