From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id AF3C181F15 for ; Wed, 30 Nov 2016 22:48:23 -0800 (PST) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga101.fm.intel.com with ESMTP; 30 Nov 2016 22:48:22 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.33,723,1477983600"; d="scan'208";a="907481374" Received: from fmsmsx105.amr.corp.intel.com ([10.18.124.203]) by orsmga003.jf.intel.com with ESMTP; 30 Nov 2016 22:48:21 -0800 Received: from fmsmsx114.amr.corp.intel.com (10.18.116.8) by FMSMSX105.amr.corp.intel.com (10.18.124.203) with Microsoft SMTP Server (TLS) id 14.3.248.2; Wed, 30 Nov 2016 22:48:21 -0800 Received: from shsmsx103.ccr.corp.intel.com (10.239.4.69) by FMSMSX114.amr.corp.intel.com (10.18.116.8) with Microsoft SMTP Server (TLS) id 14.3.248.2; Wed, 30 Nov 2016 22:48:21 -0800 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.239]) by SHSMSX103.ccr.corp.intel.com ([169.254.4.96]) with mapi id 14.03.0248.002; Thu, 1 Dec 2016 14:48:19 +0800 From: "Fan, Jeff" To: "Kinney, Michael D" , "edk2-devel@lists.01.org" CC: "Yao, Jiewen" , "Tian, Feng" Thread-Topic: [Patch] UefiCpuPkg/Include: Add VMX MSR register structures Thread-Index: AQHSStt/tqYSeLzWHEarN/7AY4WTeqDyqBEQ Date: Thu, 1 Dec 2016 06:48:19 +0000 Message-ID: <542CF652F8836A4AB8DBFAAD40ED192A4A2ED5EC@shsmsx102.ccr.corp.intel.com> References: <1480490960-16120-1-git-send-email-michael.d.kinney@intel.com> In-Reply-To: <1480490960-16120-1-git-send-email-michael.d.kinney@intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiMmFlNzY2MjUtNDRhNC00YTQ2LWExZjItYWNjMjlhOWRmMTE5IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE1LjkuNi42IiwiVHJ1c3RlZExhYmVsSGFzaCI6IklDa3h3Ymw3SVhFRlJmejhPQTNNT1N1TWprdzU0MGs0RGYrcDJyTHhETWc9In0= x-ctpclassification: CTP_IC x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [Patch] UefiCpuPkg/Include: Add VMX MSR register structures X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 01 Dec 2016 06:48:24 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Jeff Fan -----Original Message----- From: Kinney, Michael D=20 Sent: Wednesday, November 30, 2016 3:29 PM To: edk2-devel@lists.01.org Cc: Yao, Jiewen; Fan, Jeff; Tian, Feng Subject: [Patch] UefiCpuPkg/Include: Add VMX MSR register structures Add MSR_IA32_VMX_BASIC_REGISTER and IA32_VMX_MISC_REGISTER structures with the bit fields for these two MSRs. Also add MSEG_HEADER structure whose base address is in the MsegBase field of MS= R_IA32_SMM_MONITOR_CTL_REGISTER. Cc: Jiewen Yao Cc: Jeff Fan Cc: Feng Tian Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney --- UefiCpuPkg/Include/Register/ArchitecturalMsr.h | 224 +++++++++++++++++++++= +++- 1 file changed, 219 insertions(+), 5 deletions(-) diff --git a/UefiCpuPkg/Include/Register/ArchitecturalMsr.h b/UefiCpuPkg/In= clude/Register/ArchitecturalMsr.h index 7de1c4b..a7a221d 100644 --- a/UefiCpuPkg/Include/Register/ArchitecturalMsr.h +++ b/UefiCpuPkg/Include/Register/ArchitecturalMsr.h @@ -19,6 +19,14 @@ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume = 3, December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-1. =20 + @par Specification Reference: + Intel(R) 64 and IA-32 Architectures Software Developer's Manual,=20 + Volume 3, December 2015, Appendix A VMX Capability Reporting Facility, S= ection A.1. + + @par Specification Reference: + Intel(R) 64 and IA-32 Architectures Software Developer's Manual,=20 + Volume 3, December 2015, Appendix A VMX Capability Reporting Facility, S= ection A.6. + **/ =20 #ifndef __ARCHITECTURAL_MSR_H__ @@ -411,7 +419,7 @@ typedef union { =20 =20 /** - SMM Monitor Configuration (R/W). If CPUID.01H: ECX[5]=3D1. CPUID.01H: EC= X[6] =3D + SMM Monitor Configuration (R/W). If CPUID.01H: ECX[5]=3D1 or CPUID.01H:= =20 + ECX[6] =3D 1. =20 @param ECX MSR_IA32_SMM_MONITOR_CTL (0x0000009B) @@ -471,6 +479,25 @@ = typedef union { UINT64 Uint64; } MSR_IA32_SMM_MONITOR_CTL_REGISTER; =20 +/** + MSEG header that is located at the physical address specified by the=20 +MsegBase + field of #MSR_IA32_SMM_MONITOR_CTL_REGISTER. +**/ +typedef struct { + UINT32 MsegHeaderRevision; + UINT32 MonitorFeatures; + UINT32 GdtrLimit; + UINT32 GdtrBaseOffset; + UINT32 CsSelector; + UINT32 EipOffset; + UINT32 EspOffset; + UINT32 Cr3Offset; + // + // Pad header so total size is 2KB + // + UINT8 Reserved[SIZE_2KB - 8 * sizeof (UINT32)]; +} MSEG_HEADER; + =20 /** Base address of the logical processor's SMRAM image (RO, SMM only). If @= @ -3681,14 +3708,119 @@ typedef union { =20 Example usage @code - UINT64 Msr; + MSR_IA32_VMX_BASIC_REGISTER Msr; =20 - Msr =3D AsmReadMsr64 (MSR_IA32_VMX_BASIC); + Msr.Uint64 =3D AsmReadMsr64 (MSR_IA32_VMX_BASIC); @endcode @note MSR_IA32_VMX_BASIC is defined as IA32_VMX_BASIC in SDM. **/ #define MSR_IA32_VMX_BASIC 0x00000480 =20 +/** + MSR information returned for MSR index #MSR_IA32_VMX_BASIC **/=20 +typedef union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 30:0] VMCS revision identifier used by the processor. Proce= ssors + /// that use the same VMCS revision identifier use the same size for V= MCS + /// regions (see subsequent item on bits 44:32). + /// + /// @note Earlier versions of this manual specified that the VMCS revi= sion + /// identifier was a 32-bit field in bits 31:0 of this MSR. For all + /// processors produced prior to this change, bit 31 of this MSR was r= ead + /// as 0. + /// + UINT32 VmcsRevisonId:31; + UINT32 MustBeZero:1; + /// + /// [Bit 44:32] Reports the number of bytes that software should alloc= ate + /// for the VMXON region and any VMCS region. It is a value greater t= han + /// 0 and at most 4096(bit 44 is set if and only if bits 43:32 are cle= ar). + /// + UINT32 VmcsSize:13; + UINT32 Reserved1:3; + /// + /// [Bit 48] Indicates the width of the physical addresses that may be= used + /// for the VMXON region, each VMCS, and data structures referenced by + /// pointers in a VMCS (I/O bitmaps, virtual-APIC page, MSR areas for = VMX + /// transitions). If the bit is 0, these addresses are limited to the + /// processor's physical-address width. If the bit is 1, these addres= ses + /// are limited to 32 bits. This bit is always 0 for processors that + /// support Intel 64 architecture. + /// + /// @note On processors that support Intel 64 architecture, the pointe= r + /// must not set bits beyond the processor's physical address width. + /// + UINT32 VmcsAddressWidth:1; + /// + /// [Bit 49] If bit 49 is read as 1, the logical processor supports th= e + /// dual-monitor treatment of system-management interrupts and + /// system-management mode. See Section 34.15 for details of this trea= tment. + /// + UINT32 DualMonitor:1; + /// + /// [Bit 53:50] report the memory type that should be used for the VMC= S, + /// for data structures referenced by pointers in the VMCS (I/O bitmap= s, + /// virtual-APIC page, MSR areas for VMX transitions), and for the MSE= G + /// header. If software needs to access these data structures (e.g., t= o + /// modify the contents of the MSR bitmaps), it can configure the pagi= ng + /// structures to map them into the linear-address space. If it does s= o, + /// it should establish mappings that use the memory type reported bit= s + /// 53:50 in this MSR. + /// + /// As of this writing, all processors that support VMX operation indi= cate + /// the write-back type. + /// + /// If software needs to access these data structures (e.g., to modify + /// the contents of the MSR bitmaps), it can configure the paging + /// structures to map them into the linear-address space. If it does s= o, + /// it should establish mappings that use the memory type reported in = this + /// MSR. + /// + /// @note Alternatively, software may map any of these regions or + /// structures with the UC memory type. (This may be necessary for the= MSEG + /// header.) Doing so is discouraged unless necessary as it will cause= the + /// performance of software accesses to those structures to suffer. + /// + /// + UINT32 MemoryType:4; + /// + /// [Bit 54] If bit 54 is read as 1, the logical processor reports + /// information in the VM-exit instruction-information field on VM exi= ts + /// due to execution of the INS and OUTS instructions. This reporting = is + /// done only if this bit is read as 1. + /// + UINT32 InsOutsReporting:1; + /// + /// [Bit 55] Bit 55 is read as 1 if any VMX controls that default to 1= may + /// be cleared to 0. See Appendix A.2 for details. It also reports sup= port + /// for the VMX capability MSRs IA32_VMX_TRUE_PINBASED_CTLS, + /// IA32_VMX_TRUE_PROCBASED_CTLS, IA32_VMX_TRUE_EXIT_CTLS, and + /// IA32_VMX_TRUE_ENTRY_CTLS. See Appendix A.3.1, Appendix A.3.2, + /// Appendix A.4, and Appendix A.5 for details. + /// + UINT32 VmxControls:1; + UINT32 Reserved2:8; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} MSR_IA32_VMX_BASIC_REGISTER; + +/// +/// @{ Define value for bit field=20 +MSR_IA32_VMX_BASIC_REGISTER.MemoryType +/// +#define MSR_IA32_VMX_BASIC_REGISTER_MEMORY_TYPE_UNCACHEABLE 0x00 +#define MSR_IA32_VMX_BASIC_REGISTER_MEMORY_TYPE_WRITE_BACK 0x06 +/// +/// @} +/// + =20 /** Capability Reporting Register of Pinbased VM-execution Controls (R/O) Se= e @@ -3777,14 +3909,96 @@ typedef union { =20 Example usage @code - UINT64 Msr; + IA32_VMX_MISC_REGISTER Msr; =20 - Msr =3D AsmReadMsr64 (MSR_IA32_VMX_MISC); + Msr.Uint64 =3D AsmReadMsr64 (MSR_IA32_VMX_MISC); @endcode @note MSR_IA32_VMX_MISC is defined as IA32_VMX_MISC in SDM. **/ #define MSR_IA32_VMX_MISC 0x00000485 =20 +/** + MSR information returned for MSR index #IA32_VMX_MISC **/ typedef=20 +union { + /// + /// Individual bit fields + /// + struct { + /// + /// [Bits 4:0] Reports a value X that specifies the relationship betwe= en the + /// rate of the VMX-preemption timer and that of the timestamp counter= (TSC). + /// Specifically, the VMX-preemption timer (if it is active) counts do= wn by + /// 1 every time bit X in the TSC changes due to a TSC increment. + /// + UINT32 VmxTimerRatio:5; + /// + /// [Bit 5] If bit 5 is read as 1, VM exits store the value of IA32_EF= ER.LMA + /// into the "IA-32e mode guest" VM-entry control;see Section 27.2 for= more + /// details. This bit is read as 1 on any logical processor that suppo= rts + /// the 1-setting of the "unrestricted guest" VM-execution control. + /// + UINT32 VmExitEferLma:1; + /// + /// [Bit 6] reports (if set) the support for activity state 1 (HLT). + /// + UINT32 HltActivityStateSupported:1; + /// + /// [Bit 7] reports (if set) the support for activity state 2 (shutdow= n). + /// + UINT32 ShutdownActivityStateSupported:1; + /// + /// [Bit 8] reports (if set) the support for activity state 3 (wait-fo= r-SIPI). + /// + UINT32 WaitForSipiActivityStateSupported:1; + UINT32 Reserved1:6; + /// + /// [Bit 15] If read as 1, the RDMSR instruction can be used in system= - + /// management mode (SMM) to read the IA32_SMBASE MSR (MSR address 9EH= ). + /// See Section 34.15.6.4. + /// + UINT32 SmBaseMsrSupported:1; + /// + /// [Bits 24:16] Indicate the number of CR3-target values supported by= the + /// processor. This number is a value between 0 and 256, inclusive (bi= t 24 + /// is set if and only if bits 23:16 are clear). + /// + UINT32 NumberOfCr3TargetValues:9; + /// + /// [Bit 27:25] Bits 27:25 is used to compute the recommended maximum + /// number of MSRs that should appear in the VM-exit MSR-store list, t= he + /// VM-exit MSR-load list, or the VM-entry MSR-load list. Specifically= , if + /// the value bits 27:25 of IA32_VMX_MISC is N, then 512 * (N + 1) is = the + /// recommended maximum number of MSRs to be included in each list. If= the + /// limit is exceeded, undefined processor behavior may result (includ= ing a + /// machine check during the VMX transition). + /// + UINT32 MsrStoreListMaximum:3; + /// + /// [Bit 28] If read as 1, bit 2 of the IA32_SMM_MONITOR_CTL can be se= t + /// to 1. VMXOFF unblocks SMIs unless IA32_SMM_MONITOR_CTL[bit 2] is 1 + /// (see Section 34.14.4). + /// + UINT32 BlockSmiSupported:1; + /// + /// [Bit 29] read as 1, software can use VMWRITE to write to any suppo= rted + /// field in the VMCS; otherwise, VMWRITE cannot be used to modify VM-= exit + /// information fields. + /// + UINT32 VmWriteSupported:1; + UINT32 Reserved2:2; + /// + /// [Bits 63:32] Reports the 32-bit MSEG revision identifier used by t= he + /// processor. + /// + UINT32 MsegRevisionIdentifier:32; + } Bits; + /// + /// All bit fields as a 64-bit value + /// + UINT64 Uint64; +} IA32_VMX_MISC_REGISTER; + =20 /** Capability Reporting Register of CR0 Bits Fixed to 0 (R/O) See Appendix = A.7, -- 2.6.3.windows.1