From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 92E2F81D79 for ; Sun, 15 Jan 2017 16:49:28 -0800 (PST) Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga101.fm.intel.com with ESMTP; 15 Jan 2017 16:49:28 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.33,236,1477983600"; d="scan'208";a="213714934" Received: from fmsmsx103.amr.corp.intel.com ([10.18.124.201]) by fmsmga004.fm.intel.com with ESMTP; 15 Jan 2017 16:49:28 -0800 Received: from fmsmsx154.amr.corp.intel.com (10.18.116.70) by FMSMSX103.amr.corp.intel.com (10.18.124.201) with Microsoft SMTP Server (TLS) id 14.3.248.2; Sun, 15 Jan 2017 16:49:28 -0800 Received: from shsmsx103.ccr.corp.intel.com (10.239.4.69) by FMSMSX154.amr.corp.intel.com (10.18.116.70) with Microsoft SMTP Server (TLS) id 14.3.248.2; Sun, 15 Jan 2017 16:49:28 -0800 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.88]) by SHSMSX103.ccr.corp.intel.com ([10.239.4.69]) with mapi id 14.03.0248.002; Mon, 16 Jan 2017 08:49:26 +0800 From: "Fan, Jeff" To: Leo Duran , "edk2-devel@lists.01.org" CC: "Gao, Liming" , "Kinney, Michael D" , "Justen, Jordan L" , "lersek@redhat.com" , "brijesh.singh@amd.com" Thread-Topic: [PATCH v3 03/10] UefiCpuPkg: Modify CpuIoPei to support new IoLib library Thread-Index: AQHSbdki6SvfZXdlWEuJhfteyus6mKE6R/FQ Date: Mon, 16 Jan 2017 00:49:25 +0000 Message-ID: <542CF652F8836A4AB8DBFAAD40ED192A4C516FF0@shsmsx102.ccr.corp.intel.com> References: <1484338200-31337-1-git-send-email-leo.duran@amd.com> <1484338200-31337-4-git-send-email-leo.duran@amd.com> In-Reply-To: <1484338200-31337-4-git-send-email-leo.duran@amd.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiMTc3YWNiNTEtOTA3OS00ZTM4LWI3NDgtM2Y4OTYxODJjMWI4IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE1LjkuNi42IiwiVHJ1c3RlZExhYmVsSGFzaCI6IlEzS0FUdHhVZG8zc1FORlV0TllacmVDVVlxaDFIQzhmZjNvXC9lU3VzUE1FPSJ9 x-ctpclassification: CTP_IC x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH v3 03/10] UefiCpuPkg: Modify CpuIoPei to support new IoLib library X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Jan 2017 00:49:28 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Jeff Fan -----Original Message----- From: Leo Duran [mailto:leo.duran@amd.com]=20 Sent: Saturday, January 14, 2017 4:10 AM To: edk2-devel@lists.01.org Cc: Gao, Liming; Kinney, Michael D; Fan, Jeff; Justen, Jordan L; lersek@red= hat.com; brijesh.singh@amd.com; Leo Duran Subject: [PATCH v3 03/10] UefiCpuPkg: Modify CpuIoPei to support new IoLib = library The IO_PPI supports Fifo types by invoking the Fifo routines in the new Bas= eIoLibIntrinsic (IoLib class) library. Cc: Jeff Fan Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Brijesh Singh Signed-off-by: Leo Duran --- UefiCpuPkg/CpuIoPei/CpuIoPei.c | 52 ++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 52 insertions(+) diff --git a/UefiCpuPkg/CpuIoPei/CpuIoPei.c b/UefiCpuPkg/CpuIoPei/CpuIoPei.= c index 3c5c8a7..b6d538b 100644 --- a/UefiCpuPkg/CpuIoPei/CpuIoPei.c +++ b/UefiCpuPkg/CpuIoPei/CpuIoPei.c @@ -2,6 +2,8 @@ Produces the CPU I/O PPI. =20 Copyright (c) 2009 - 2012, Intel Corporation. All rights reserved.
+Copyright (c) 2017, AMD Incorporated. All rights reserved.
+ This program and the accompanying materials =20 are licensed and made available under the terms and conditions of the BSD = License =20 which accompanies this distribution. The full text of the license may be = found at =20 @@ -375,6 +377,31 @@ CpuIoServiceRead ( InStride =3D mInStride[Width]; OutStride =3D mOutStride[Width]; OperationWidth =3D (EFI_PEI_CPU_IO_PPI_WIDTH) (Width & 0x03); + + // + // Fifo operations supported for (mInStride[Width] =3D=3D 0) // if=20 + (InStride =3D=3D 0) { + switch (OperationWidth) { + case EfiPeiCpuIoWidthUint8: + IoReadFifo8 ((UINTN)Address, Count, Buffer); + return EFI_SUCCESS; + case EfiPeiCpuIoWidthUint16: + IoReadFifo16 ((UINTN)Address, Count, Buffer); + return EFI_SUCCESS; + case EfiPeiCpuIoWidthUint32: + IoReadFifo32 ((UINTN)Address, Count, Buffer); + return EFI_SUCCESS; + default: + // + // The CpuIoCheckParameter call above will ensure that this + // path is not taken. + // + ASSERT (FALSE); + break; + } + } + Aligned =3D (BOOLEAN)(((UINTN)Buffer & (mInStride[OperationWidth] - 1)) = =3D=3D 0x00); for (Uint8Buffer =3D Buffer; Count > 0; Address +=3D InStride, Uint8Buff= er +=3D OutStride, Count--) { if (OperationWidth =3D=3D EfiPeiCpuIoWidthUint8) { @@ -447,6 +474,31 @= @ CpuIoServiceWrite ( InStride =3D mInStride[Width]; OutStride =3D mOutStride[Width]; OperationWidth =3D (EFI_PEI_CPU_IO_PPI_WIDTH) (Width & 0x03); + + // + // Fifo operations supported for (mInStride[Width] =3D=3D 0) // if=20 + (InStride =3D=3D 0) { + switch (OperationWidth) { + case EfiPeiCpuIoWidthUint8: + IoWriteFifo8 ((UINTN)Address, Count, Buffer); + return EFI_SUCCESS; + case EfiPeiCpuIoWidthUint16: + IoWriteFifo16 ((UINTN)Address, Count, Buffer); + return EFI_SUCCESS; + case EfiPeiCpuIoWidthUint32: + IoWriteFifo32 ((UINTN)Address, Count, Buffer); + return EFI_SUCCESS; + default: + // + // The CpuIoCheckParameter call above will ensure that this + // path is not taken. + // + ASSERT (FALSE); + break; + } + } + Aligned =3D (BOOLEAN)(((UINTN)Buffer & (mInStride[OperationWidth] - 1)) = =3D=3D 0x00); for (Uint8Buffer =3D (UINT8 *)Buffer; Count > 0; Address +=3D InStride, = Uint8Buffer +=3D OutStride, Count--) { if (OperationWidth =3D=3D EfiPeiCpuIoWidthUint8) { -- 1.9.1