From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id D6F8981D79 for ; Sun, 15 Jan 2017 16:54:33 -0800 (PST) Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga104.fm.intel.com with ESMTP; 15 Jan 2017 16:54:33 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.33,236,1477983600"; d="scan'208";a="213716214" Received: from fmsmsx104.amr.corp.intel.com ([10.18.124.202]) by fmsmga004.fm.intel.com with ESMTP; 15 Jan 2017 16:54:33 -0800 Received: from fmsmsx124.amr.corp.intel.com (10.18.125.39) by fmsmsx104.amr.corp.intel.com (10.18.124.202) with Microsoft SMTP Server (TLS) id 14.3.248.2; Sun, 15 Jan 2017 16:54:33 -0800 Received: from shsmsx101.ccr.corp.intel.com (10.239.4.153) by fmsmsx124.amr.corp.intel.com (10.18.125.39) with Microsoft SMTP Server (TLS) id 14.3.248.2; Sun, 15 Jan 2017 16:54:33 -0800 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.88]) by SHSMSX101.ccr.corp.intel.com ([169.254.1.177]) with mapi id 14.03.0248.002; Mon, 16 Jan 2017 08:54:31 +0800 From: "Fan, Jeff" To: Leo Duran , "edk2-devel@lists.01.org" CC: "Gao, Liming" , "Kinney, Michael D" , "Justen, Jordan L" , "lersek@redhat.com" , "brijesh.singh@amd.com" Thread-Topic: [PATCH v3 09/10] IntelFrameworkPkg/DxeIoLibCpuIo: Add new Fifo routines in IoLib class Thread-Index: AQHSbdklrnrixJcitEmuKvyE0nWdu6E6SnaA Date: Mon, 16 Jan 2017 00:54:30 +0000 Message-ID: <542CF652F8836A4AB8DBFAAD40ED192A4C51706F@shsmsx102.ccr.corp.intel.com> References: <1484338200-31337-1-git-send-email-leo.duran@amd.com> <1484338200-31337-10-git-send-email-leo.duran@amd.com> In-Reply-To: <1484338200-31337-10-git-send-email-leo.duran@amd.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiODI5ZjJjMGYtY2ZkNi00MWNlLTg2NGYtOWRjYjY5MmY0MDJlIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE1LjkuNi42IiwiVHJ1c3RlZExhYmVsSGFzaCI6Iks5MXhHR29DNFM5WGVPTW5Ma3ZGM3l1NGlEZ2U2RFJwVzZvVldcLzZjNUFFPSJ9 x-ctpclassification: CTP_IC x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH v3 09/10] IntelFrameworkPkg/DxeIoLibCpuIo: Add new Fifo routines in IoLib class X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Jan 2017 00:54:34 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Jeff Fan -----Original Message----- From: Leo Duran [mailto:leo.duran@amd.com]=20 Sent: Saturday, January 14, 2017 4:10 AM To: edk2-devel@lists.01.org Cc: Gao, Liming; Kinney, Michael D; Fan, Jeff; Justen, Jordan L; lersek@red= hat.com; brijesh.singh@amd.com; Leo Duran Subject: [PATCH v3 09/10] IntelFrameworkPkg/DxeIoLibCpuIo: Add new Fifo rou= tines in IoLib class Cc: Michael D Kinney Cc: Jeff Fan Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Brijesh Singh Signed-off-by: Leo Duran --- .../Library/DxeIoLibCpuIo/DxeCpuIoLibInternal.h | 70 +++++- IntelFrameworkPkg/Library/DxeIoLibCpuIo/IoLib.c | 248 +++++++++++++++++= ++++ 2 files changed, 311 insertions(+), 7 deletions(-) diff --git a/IntelFrameworkPkg/Library/DxeIoLibCpuIo/DxeCpuIoLibInternal.h = b/IntelFrameworkPkg/Library/DxeIoLibCpuIo/DxeCpuIoLibInternal.h index 66c73fe..c15bca8 100644 --- a/IntelFrameworkPkg/Library/DxeIoLibCpuIo/DxeCpuIoLibInternal.h +++ b/IntelFrameworkPkg/Library/DxeIoLibCpuIo/DxeCpuIoLibInternal.h @@ -5,6 +5,8 @@ all source code of this library instance. =20 Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
+ Copyright (c) 2017, AMD Incorporated. All rights reserved.
+ This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -35,8 +37,10 @@ Reads registers in the EFI CPU I/O space. =20 Reads the I/O port specified by Port with registers width specified by W= idth. - The read value is returned. If such operations are not supported, then A= SSERT(). + The read value is returned. + This function must guarantee that all I/O read and write operations are = serialized. + If such operations are not supported, then ASSERT(). =20 @param Port The base address of the I/O operation. The caller is responsible for aligning the Address= if required. @@ -48,16 +52,18 @@ UINT64 EFIAPI IoReadWorker ( - IN UINTN Port, - IN EFI_CPU_IO_PROTOCOL_WIDTH Width + IN UINTN Port, + IN EFI_CPU_IO_PROTOCOL_WIDTH Width ); =20 /** Writes registers in the EFI CPU I/O space. =20 Writes the I/O port specified by Port with registers width and value spe= cified by Width - and Data respectively. Data is returned. If such operations are not sup= ported, then ASSERT(). + and Data respectively. Data is returned. + This function must guarantee that all I/O read and write operations are = serialized. + If such operations are not supported, then ASSERT(). =20 @param Port The base address of the I/O operation. The caller is responsible for aligning the Address= if required. @@ -70,9 +76,59 @@ IoReadWorker ( UINT64 EFIAPI IoWriteWorker ( - IN UINTN Port, - IN EFI_CPU_IO_PROTOCOL_WIDTH Width, - IN UINT64 Data + IN UINTN Port, + IN EFI_CPU_IO_PROTOCOL_WIDTH Width, + IN UINT64 Data + ); + +/** + Reads registers in the EFI CPU I/O space. + + Reads the I/O port specified by Port with registers width specified by W= idth. + The port is read Count times, and the read data is stored in the provide= d Buffer. + + This function must guarantee that all I/O read and write operations are = serialized. + If such operations are not supported, then ASSERT(). + + @param Port The base address of the I/O operation. + The caller is responsible for aligning the Address= if required. + @param Width The width of the I/O operation. + @param Count The number of times to read I/O port. + @param Buffer The buffer to store the read data into. + +**/ +VOID +EFIAPI +IoReadFifoWorker ( + IN UINTN Port, + IN EFI_CPU_IO_PROTOCOL_WIDTH Width, + IN UINTN Count, + IN VOID *Buffer + ); + +/** + Writes registers in the EFI CPU I/O space. + + Writes the I/O port specified by Port with registers width specified by = Width. + The port is written Count times, and the write data is retrieved from th= e provided Buffer. + + This function must guarantee that all I/O read and write operations are = serialized. + If such operations are not supported, then ASSERT(). + + @param Port The base address of the I/O operation. + The caller is responsible for aligning the Address= if required. + @param Width The width of the I/O operation. + @param Count The number of times to write I/O port. + @param Buffer The buffer to store the read data into. + +**/ +VOID +EFIAPI +IoWriteFifoWorker ( + IN UINTN Port, + IN EFI_CPU_IO_PROTOCOL_WIDTH Width, + IN UINTN Count, + IN VOID *Buffer ); =20 /** diff --git a/IntelFrameworkPkg/Library/DxeIoLibCpuIo/IoLib.c b/IntelFramewo= rkPkg/Library/DxeIoLibCpuIo/IoLib.c index c1c48d5..1dbc362 100644 --- a/IntelFrameworkPkg/Library/DxeIoLibCpuIo/IoLib.c +++ b/IntelFrameworkPkg/Library/DxeIoLibCpuIo/IoLib.c @@ -4,6 +4,8 @@ are based on EFI_CPU_IO_PROTOCOL. =20 Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
+ Copyright (c) 2017, AMD Incorporated. All rights reserved.
+ This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -113,6 +115,68 @@ IoWriteWorker ( } =20 /** + Reads registers in the EFI CPU I/O space. + + Reads the I/O port specified by Port with registers width specified by W= idth. + The port is read Count times, and the read data is stored in the provide= d Buffer. + + This function must guarantee that all I/O read and write operations are = serialized. + If such operations are not supported, then ASSERT(). + + @param Port The base address of the I/O operation. + The caller is responsible for aligning the Address= if required. + @param Width The width of the I/O operation. + @param Count The number of times to read I/O port. + @param Buffer The buffer to store the read data into. + +**/ +VOID +EFIAPI +IoReadFifoWorker ( + IN UINTN Port, + IN EFI_CPU_IO_PROTOCOL_WIDTH Width, + IN UINTN Count, + IN VOID *Buffer + ) +{ + EFI_STATUS Status; + + Status =3D mCpuIo->Io.Read (mCpuIo, Width, Port, Count, Buffer); + ASSERT_EFI_ERROR (Status); +} + +/** + Writes registers in the EFI CPU I/O space. + + Writes the I/O port specified by Port with registers width specified by = Width. + The port is written Count times, and the write data is retrieved from th= e provided Buffer. + + This function must guarantee that all I/O read and write operations are = serialized. + If such operations are not supported, then ASSERT(). + + @param Port The base address of the I/O operation. + The caller is responsible for aligning the Address= if required. + @param Width The width of the I/O operation. + @param Count The number of times to write I/O port. + @param Buffer The buffer to store the read data into. + +**/ +VOID +EFIAPI +IoWriteFifoWorker ( + IN UINTN Port, + IN EFI_CPU_IO_PROTOCOL_WIDTH Width, + IN UINTN Count, + IN VOID *Buffer + ) +{ + EFI_STATUS Status; + + Status =3D mCpuIo->Io.Write (mCpuIo, Width, Port, Count, Buffer); + ASSERT_EFI_ERROR (Status); +} + +/** Reads memory-mapped registers in the EFI system memory space. =20 Reads the MMIO registers specified by Address with registers width speci= fied by Width. @@ -402,6 +466,190 @@ IoWrite64 ( } =20 /** + Reads an 8-bit I/O port fifo into a block of memory. + + Reads the 8-bit I/O fifo port specified by Port. + The port is read Count times, and the read data is stored in the=20 + provided Buffer. + + This function must guarantee that all I/O read and write operations=20 + are serialized. + + If 8-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to read. + @param Count The number of times to read I/O port. + @param Buffer The buffer to store the read data into. + +**/ +VOID +EFIAPI +IoReadFifo8 ( + IN UINTN Port, + IN UINTN Count, + OUT VOID *Buffer + ) +{ + IoReadFifoWorker (Port, EfiCpuIoWidthFifoUint8, Count, Buffer); } + +/** + Writes a block of memory into an 8-bit I/O port fifo. + + Writes the 8-bit I/O fifo port specified by Port. + The port is written Count times, and the write data is retrieved=20 + from the provided Buffer. + + This function must guarantee that all I/O write and write operations=20 + are serialized. + + If 8-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to write. + @param Count The number of times to write I/O port. + @param Buffer The buffer to retrieve the write data from. + +**/ +VOID +EFIAPI +IoWriteFifo8 ( + IN UINTN Port, + IN UINTN Count, + IN VOID *Buffer + ) +{ + IoWriteFifoWorker (Port, EfiCpuIoWidthFifoUint8, Count, Buffer); } + +/** + Reads a 16-bit I/O port fifo into a block of memory. + + Reads the 16-bit I/O fifo port specified by Port. + The port is read Count times, and the read data is stored in the=20 + provided Buffer. + + This function must guarantee that all I/O read and write operations=20 + are serialized. + + If 16-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to read. + @param Count The number of times to read I/O port. + @param Buffer The buffer to store the read data into. + +**/ +VOID +EFIAPI +IoReadFifo16 ( + IN UINTN Port, + IN UINTN Count, + OUT VOID *Buffer + ) +{ + // + // Make sure Port is aligned on a 16-bit boundary. + // + ASSERT ((Port & 1) =3D=3D 0); + IoReadFifoWorker (Port, EfiCpuIoWidthFifoUint16, Count, Buffer); } + +/** + Writes a block of memory into a 16-bit I/O port fifo. + + Writes the 16-bit I/O fifo port specified by Port. + The port is written Count times, and the write data is retrieved=20 + from the provided Buffer. + + This function must guarantee that all I/O write and write operations=20 + are serialized. + + If 16-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to write. + @param Count The number of times to write I/O port. + @param Buffer The buffer to retrieve the write data from. + +**/ +VOID +EFIAPI +IoWriteFifo16 ( + IN UINTN Port, + IN UINTN Count, + IN VOID *Buffer + ) +{ + // + // Make sure Port is aligned on a 16-bit boundary. + // + ASSERT ((Port & 1) =3D=3D 0); + IoWriteFifoWorker (Port, EfiCpuIoWidthFifoUint16, Count, Buffer); } + +/** + Reads a 32-bit I/O port fifo into a block of memory. + + Reads the 32-bit I/O fifo port specified by Port. + The port is read Count times, and the read data is stored in the=20 + provided Buffer. + + This function must guarantee that all I/O read and write operations=20 + are serialized. + + If 32-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to read. + @param Count The number of times to read I/O port. + @param Buffer The buffer to store the read data into. + +**/ +VOID +EFIAPI +IoReadFifo32 ( + IN UINTN Port, + IN UINTN Count, + OUT VOID *Buffer + ) +{ + // + // Make sure Port is aligned on a 32-bit boundary. + // + ASSERT ((Port & 3) =3D=3D 0); + IoReadFifoWorker (Port, EfiCpuIoWidthFifoUint32, Count, Buffer); } + +/** + Writes a block of memory into a 32-bit I/O port fifo. + + Writes the 32-bit I/O fifo port specified by Port. + The port is written Count times, and the write data is retrieved=20 + from the provided Buffer. + + This function must guarantee that all I/O write and write operations=20 + are serialized. + + If 32-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to write. + @param Count The number of times to write I/O port. + @param Buffer The buffer to retrieve the write data from. + +**/ +VOID +EFIAPI +IoWriteFifo32 ( + IN UINTN Port, + IN UINTN Count, + IN VOID *Buffer + ) +{ + // + // Make sure Port is aligned on a 32-bit boundary. + // + ASSERT ((Port & 3) =3D=3D 0); + IoWriteFifoWorker (Port, EfiCpuIoWidthFifoUint32, Count, Buffer); } + +/** Reads an 8-bit MMIO register. =20 Reads the 8-bit MMIO register specified by Address. The 8-bit read value= is -- 1.9.1