From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 2386281F5F for ; Thu, 9 Feb 2017 23:10:42 -0800 (PST) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga105.fm.intel.com with ESMTP; 09 Feb 2017 23:10:41 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.35,139,1484035200"; d="scan'208";a="42410671" Received: from fmsmsx103.amr.corp.intel.com ([10.18.124.201]) by orsmga002.jf.intel.com with ESMTP; 09 Feb 2017 23:10:41 -0800 Received: from fmsmsx125.amr.corp.intel.com (10.18.125.40) by FMSMSX103.amr.corp.intel.com (10.18.124.201) with Microsoft SMTP Server (TLS) id 14.3.248.2; Thu, 9 Feb 2017 23:10:39 -0800 Received: from shsmsx101.ccr.corp.intel.com (10.239.4.153) by FMSMSX125.amr.corp.intel.com (10.18.125.40) with Microsoft SMTP Server (TLS) id 14.3.248.2; Thu, 9 Feb 2017 23:10:39 -0800 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.88]) by SHSMSX101.ccr.corp.intel.com ([169.254.1.177]) with mapi id 14.03.0248.002; Fri, 10 Feb 2017 15:10:37 +0800 From: "Fan, Jeff" To: "Duran, Leo" , "edk2-devel@ml01.01.org" CC: "Tian, Feng" , "Zeng, Star" , Laszlo Ersek , "Singh, Brijesh" Thread-Topic: [PATCH 3/3] UefiCpuPkg/Universal/Acpi/S3Resume2Pei: Add support for PCD PcdPteMemoryEncryptionAddressOrMask Thread-Index: AQHSglA1ohnEirmfrE6b0SgtQ7JZuKFhgu6g//+eVICAALAWwA== Date: Fri, 10 Feb 2017 07:10:37 +0000 Message-ID: <542CF652F8836A4AB8DBFAAD40ED192A4C533C03@shsmsx102.ccr.corp.intel.com> References: <1486588386-2146-1-git-send-email-leo.duran@amd.com> <1486588386-2146-4-git-send-email-leo.duran@amd.com> <542CF652F8836A4AB8DBFAAD40ED192A4C5334DB@shsmsx102.ccr.corp.intel.com> In-Reply-To: Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiMDYwZThjNTctMmJjOS00MTIwLTkyZWYtNTk5OWMxMmJhYzA2IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE1LjkuNi42IiwiVHJ1c3RlZExhYmVsSGFzaCI6InJ0SDRqbG5XejAwMjluYkdJSEtUR0FOYkwrWTNrSzFaQjNUVVJGXC9SOENvPSJ9 x-ctpclassification: CTP_IC x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH 3/3] UefiCpuPkg/Universal/Acpi/S3Resume2Pei: Add support for PCD PcdPteMemoryEncryptionAddressOrMask X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 10 Feb 2017 07:10:42 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Leo, If this PCD is only to patch address, could you make sure the other fields = not to be updated in case the platform set the other fields in PCD. PageTable setup in DxeIpl is in boot service data range. If this feature is= only supported in POST phase, that's enough. Thanks! Jeff -----Original Message----- From: Duran, Leo [mailto:leo.duran@amd.com]=20 Sent: Friday, February 10, 2017 12:28 PM To: Fan, Jeff; edk2-devel@ml01.01.org Cc: Tian, Feng; Zeng, Star; Laszlo Ersek; Singh, Brijesh Subject: RE: [PATCH 3/3] UefiCpuPkg/Universal/Acpi/S3Resume2Pei: Add suppor= t for PCD PcdPteMemoryEncryptionAddressOrMask Hi Jeff, The new PCD is intended to be OR'ed with the address (upper bits). Leo. > -----Original Message----- > From: Fan, Jeff [mailto:jeff.fan@intel.com] > Sent: Thursday, February 09, 2017 8:23 PM > To: Duran, Leo ; edk2-devel@ml01.01.org > Cc: Tian, Feng ; Zeng, Star=20 > ; Laszlo Ersek ; Singh,=20 > Brijesh > Subject: RE: [PATCH 3/3] UefiCpuPkg/Universal/Acpi/S3Resume2Pei: Add=20 > support for PCD PcdPteMemoryEncryptionAddressOrMask >=20 > Hi Leo, >=20 > I want to understand your usage model. What fields are you going to=20 > update in below Page Table Entry by the new PCD? >=20 > typedef union { > struct { > UINT64 Present:1; // 0 =3D Not present in memory, 1 = =3D Present in > memory > UINT64 ReadWrite:1; // 0 =3D Read-Only, 1=3D Read/Write > UINT64 UserSupervisor:1; // 0 =3D Supervisor, 1=3DUser > UINT64 WriteThrough:1; // 0 =3D Write-Back caching, 1=3DWr= ite-Through > caching > UINT64 CacheDisabled:1; // 0 =3D Cached, 1=3DNon-Cached > UINT64 Accessed:1; // 0 =3D Not accessed, 1 =3D Access= ed (set by CPU) > UINT64 Dirty:1; // 0 =3D Not Dirty, 1 =3D written b= y processor on access > to page > UINT64 MustBe1:1; // Must be 1 > UINT64 Global:1; // 0 =3D Not global page, 1 =3D glo= bal page TLB not > cleared on CR3 write > UINT64 Available:3; // Available for use by system soft= ware > UINT64 PAT:1; // > UINT64 MustBeZero:8; // Must be zero; > UINT64 PageTableBaseAddress:31; // Page Table Base Address > UINT64 AvabilableHigh:11; // Available for use by system soft= ware > UINT64 Nx:1; // 0 =3D Execute Code, 1 =3D No Cod= e Execution > } Bits; > UINT64 Uint64; > } PAGE_TABLE_ENTRY; >=20 > I did not see any updating in SMM. Is it un-necessary? Is this feature=20 > working on POST phase or OS runtime phase? >=20 > Thanks! > Jeff >=20 > -----Original Message----- > From: Leo Duran [mailto:leo.duran@amd.com] > Sent: Thursday, February 09, 2017 5:13 AM > To: edk2-devel@ml01.01.org > Cc: Leo Duran; Fan, Jeff; Tian, Feng; Zeng, Star; Laszlo Ersek;=20 > Brijesh Singh > Subject: [PATCH 3/3] UefiCpuPkg/Universal/Acpi/S3Resume2Pei: Add=20 > support for PCD PcdPteMemoryEncryptionAddressOrMask >=20 > This PCD holds the address mask for page table entries when memory=20 > encryption is enabled on AMD processors supporting the Secure=20 > Encrypted Virtualization (SEV) feature. >=20 > The mask is applied when page tables are created (S3Resume.c). >=20 > CC: Jeff Fan > Cc: Feng Tian > Cc: Star Zeng > Cc: Laszlo Ersek > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Brijesh Singh > Signed-off-by: Leo Duran > --- > UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c | 9 +++++---- > UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf | 2 ++ > 2 files changed, 7 insertions(+), 4 deletions(-) >=20 > diff --git a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c > b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c > index d306fba..ee1e2cd 100644 > --- a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c > +++ b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c > @@ -5,6 +5,7 @@ > control is passed to OS waking up handler. >=20 > Copyright (c) 2006 - 2016, Intel Corporation. All rights=20 > reserved.
> + Copyright (c) 2017, AMD Incorporated. All rights reserved.
>=20 > This program and the accompanying materials > are licensed and made available under the terms and conditions @@=20 > -696,7 > +697,7 @@ RestoreS3PageTables ( > // > // Make a PML4 Entry > // > - PageMapLevel4Entry->Uint64 =3D > (UINT64)(UINTN)PageDirectoryPointerEntry; > + PageMapLevel4Entry->Uint64 =3D > + (UINT64)(UINTN)PageDirectoryPointerEntry | PcdGet64=20 > + (PcdPteMemoryEncryptionAddressOrMask); > PageMapLevel4Entry->Bits.ReadWrite =3D 1; > PageMapLevel4Entry->Bits.Present =3D 1; >=20 > @@ -707,7 +708,7 @@ RestoreS3PageTables ( > // > // Fill in the Page Directory entries > // > - PageDirectory1GEntry->Uint64 =3D (UINT64)PageAddress; > + PageDirectory1GEntry->Uint64 =3D (UINT64)PageAddress |=20 > + PcdGet64 (PcdPteMemoryEncryptionAddressOrMask); > PageDirectory1GEntry->Bits.ReadWrite =3D 1; > PageDirectory1GEntry->Bits.Present =3D 1; > PageDirectory1GEntry->Bits.MustBe1 =3D 1; @@ -724,7 +725,7 @@= =20 > RestoreS3PageTables ( > // > // Fill in a Page Directory Pointer Entries > // > - PageDirectoryPointerEntry->Uint64 =3D > (UINT64)(UINTN)PageDirectoryEntry; > + PageDirectoryPointerEntry->Uint64 =3D=20 > + (UINT64)(UINTN)PageDirectoryEntry | PcdGet64=20 > + (PcdPteMemoryEncryptionAddressOrMask); > PageDirectoryPointerEntry->Bits.ReadWrite =3D 1; > PageDirectoryPointerEntry->Bits.Present =3D 1; >=20 > @@ -732,7 +733,7 @@ RestoreS3PageTables ( > // > // Fill in the Page Directory entries > // > - PageDirectoryEntry->Uint64 =3D (UINT64)PageAddress; > + PageDirectoryEntry->Uint64 =3D (UINT64)PageAddress |=20 > + PcdGet64 (PcdPteMemoryEncryptionAddressOrMask); > PageDirectoryEntry->Bits.ReadWrite =3D 1; > PageDirectoryEntry->Bits.Present =3D 1; > PageDirectoryEntry->Bits.MustBe1 =3D 1; diff --git=20 > a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf > b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf > index 73aeca3..d514523 100644 > --- a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf > +++ b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf > @@ -6,6 +6,7 @@ > # control is passed to OS waking up handler. > # > # Copyright (c) 2010 - 2014, Intel Corporation. All rights=20 > reserved.
> +# Copyright (c) 2017, AMD Incorporated. All rights reserved.
> # > # This program and the accompanying materials are # licensed and=20 > made available under the terms and conditions of the BSD License @@=20 > -91,6 +92,7 @@ [FeaturePcd] >=20 > [Pcd] > gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable ##=20 > SOMETIMES_CONSUMES > + > gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrM > ask ## CONSUMES >=20 > [Depex] > TRUE > -- > 1.9.1